ZaANational Semiconductor NM27C040 General Description The NM27C040 is a high performance, 4,194,304-bit Electri- cally Programmable UV Erasable Read Only Memory. It is organized as 512K words of 8 bits each. Its pin-compatibility with byte-wide JEDEC EPROMs enables upgrades through 8 Mbit EPROMs. The Dont Care feature on Vpp during read operations allows memory expansions from 1M to 8 Mbits with no printed circuit board changes. The NM27C040 provides microprocessor-based systems extensive storage capacity for targe portions of operating system and application software. Its 120 ns access time provides high speed operation with high-performance CPUs. The NM27C040 offers a single chip solution for the code storage requirements of 100% firmware-based equipment. Frequently used software routines are quickly executed from EPROM storage, greatly enhancing system utility. 4,194,304-Bit (512K x 8) High Performance CMOS EPROM January 1994 The NM27C040 is manufactured using Nationals advanced CMOS AMG EPROM technology. Features w High performance CMOS 120 ns access time @ Simplified upgrade path Vpp is a Don't Care during normal read operation @ Manufacturers identification code m JEDEC standard pin configuration 32-pin DIP 32-pin PLCC 32-pin TSOP Block Diagram Vvog O GND O> \pp O> OE OUTPUT ENABLE, CHIP ENABLE, AND CE/PGM PROGRAM LOGIC ro Y DECODER AO-A18 ADDRESS INPUTS Xx DECODER TRI-STATE is a AMGTN is a trademark of WSI, Inc. of Nationai [ Ge DATA OUTPUTS 00 - 07 oO oF OUTPUT BUFFERS Y GATING 4,194,304-BIT CELL MATRIX TL/D/10836-1 1994 National Semiconductor Corporation TL/D/10836 | RARD-B20M24/Printed in U. S.A. WOUdg SOW) aouews0ji9g UBIH (8 X WZLS) Ha-POE P61 b OVOOZZINNConnection Diagrams DIP 27C080 270020 27C010 NM27C040 27C010 270020 27C080 A19 XX/Vpp_ | XX/Vpp Net bv. V Vv, Voc Ai6 A16 A16 6C]2 31418 xx/ BOM xx/ BGM A18 Ai5 A15 A15 mscq3 309 417 XX Al7 A17 Ai2 Al2 A12 acs 214 A14 A14 A14 A7 A7 A7 awds5 23 M3 A13 A13 A13 A6 A6 AG asC]6 27048 A8 A8 A8 AS A5 AS sq 2649 AQ AQ AQ A4 A4 A4 mCjs C) 25a11 Al1 Al1 A11 A3 A3 A3 sds 240 OE OE OE/Vpp A2 A2 A2 wei 230410 A10 A10 A10 Al Al Al adn 2D EPA CE CE CE/PGM AO AO AO ociiz 21510, O7 07 07 Oo Oo Qo 0,413 200, O6 O6 O6 O; 0; O; o,qs 19f0, Os Os Os Og Oo O2 0,415 180, O4 O4 O4 GND GND GND onoddis 17F0, Og Oz O3 TL/D/10836-2 Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C040 pin. Commercial Temperature Range (0C to + 70C) Extended Temperature Range ( 40C to + 85C) Voc = 5V 410% Voc = 5V +10% Parameter/Order Number Access Time (ns) Parameter/Order Number Access Time (ns) NM27C040 Q, V, T 120 120 NM27C040 QE, VE, TE 150 150 NM27C040 Q, V, T 150 150 NM27C040 QE, VE, TE 170 170 NM27C040 Q, V, T 170 170 NM27C040 QE, VE, TE 200 200 NM27C040 Q, V, T 200 200 Military Temperature Range ( 55C to + 125C) Package Types: NM27C040 Q, V, T XXX Vec = 5V + 10% Q = Quartz-Windowed Ceramic DIP Parameter/Order Number Access Time (ns) y = eed NM27C040 QM 150 150 All packages conform to the JEDEC standard. NM27C040 QM 200 200 e All versions are guaranteed to function for slower speeds. Pin Names AO-A18 Addresses CE/PGM Chip Enable/Program OE Output Enable 00-07 Outputs XX Dont Care (During Read)Absolute Maximum Ratings (note 1) Operating Range If Military/Aerospace specified devices are required, Range Temperature Voc | Tolerance please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Commercial | 0C to + 70C +5V +10% Storage Temperature 65C to + 150C Industrial 40C to + 85C +5V +10% All Input Voltages except A9 with Military 55Cto + 125C | +5V +10% Respect to Ground 0.6V to +7V Vpp and AQ with Respect to Ground 0.6V to +14V Vcc Supply Voltage with Respect to Ground 0.6V to +7V ESD Protection >2000V All Output Voltages with Respect to Ground Voc + 10V to GND 0.6V Read Operation DC Electrical Characteristics over operating range with Vpp = Vcc Symbol Parameter Test Conditions Min Max Units VIL Input Low Level -0.5 0.8 v Vin Input High Level 2.0 Veco + 1 v VoL Output Low Voltage lo, = 2.1mA 0.4 v VoH Output High Voltage lon = 2.5mA 3.5 Vv Ispy Voc Standby Current (CMOS) | CE = Voc + 0.3V 100 pA Ispe Voc Standby Current CE = Vin 1 mA ioc Vec Active Current CE = OF = Vi,VO=O0mA | f= 5MHz 30 mA Ipp Vpp Supply Current Vep = Voc 10 pA Vpp Vpp Read Voltage Voc 0.4 Voc v a Input Load Current Vin = 5.5V or GND -1 1 pA ILo Output Leakage Current Vout = 5.5V or GND -10 10 pA AC Electrical Characteristics over operating range with Vpp = Voc 120 150 170 200 Symbol Parameter Units Min Max Min Max Min Max Min Max tacc Address to Output Delay 120 150 170 200 tce CE to Output Delay 120 150 170 200 toe OE to Output Delay 50 50 50 50 toe Output Disable to ns 4 (Note 2) Output Float 3 36 s 88 tou Output Hold from Addresses (Note 2) CE or OE, Whichever 0) 0 0 0 Occurred FirstCapacitance 1, = + 25C, f = 1 MHz (Note 2) Symbol Parameter Conditions Typ Max Units Cin Input Capacitance Vin = OV 9 15 pF Cout Output Capacitance Vout = 0V t2 15 pF AC Test Conditions Output Load 1 TTL Gate and Timing Measurement Reference Level (Note 10) C_ = 100 pF (Note 8) Inputs 0.8V and 2V Input Rise and Fall Times <5ns Outputs 0.8V and 2V Input Pulse Levels 0.45V to 2.4V AC Waveforms (notes 6, 7, and 9) ADDRESSES ADDRESSES VALID 4 ed top | NOTES 4, 5. tor NOTES 4, 5. ANAS Slee ML NOTE 3. 2.0V Hi-Z OUTPUT 0.8V VALID OUTPUT i tl tacc It le (NOTE 3) OH TL/D/10836-4 Note 1: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: This parameter is only sampled and is not 100% tested. Note 3: OE may be delayed up to tacc ~ tog after the falling edge of CE without impacting tacc. Note 4: The tpr and tof compare level is determined as follows: High to TRI-STATE, the measured Voy; (DC) 0.10V; Low to TRI-STATE, the measured Vo 1 (DC) + 0.10V. Note 5: TRISTATE may be attained using OE or CE. Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 .F ceramic capacitor be used on every device between Voc and GND. Note 7: The outputs must be restricted to Voc + 1.0V to avoid latch-up and device damage. Note 8: 1 TTL Gate: Io, = 1.6 mA, lo = 400 pA. ,: 100 pF includes fixture capacitance. Note 9: Vpp may be connected to Voc except during programming. Note 10: Inputs and outputs can undershoot to 2.0V for 20 ns Max.Programming Waveform (note 3) PROGRAM PROGRAM VERIFY ADORESSES ADDRESS N 2v DATA DATA IN STABLE CE/PGM Oey OE o.av TL/D/10836-5Programming Characteristics (notes 1, 2,3 & 4) Symbol Parameter Conditions Min Typ Max Units tas Address Setup Time 1 Ss toes OE Setup Time 1 ps tos Data Setup Time 1 ps typs Vpp Setup Time 1 ps tvcs Voc Setup Time 1 BS taH Address Hold Time 0 BS toH Data Hold Time 1 ps tor Output Enable to Output Float Delay CE/PGM = X 0 60 ns tpw Program Pulse Width 95 100 105 ps toe Data Valid from OE CE/PGM = X 100 ns Ipp Vpp Supply Current during CE/PGM = Vi, 30 mA Programming Pulse loc Voc Supply Current 30 mA Ta Temperature Ambient 20 26 30 C Voc Power Supply Voltage 6.0 6.25 6.5 Vv Vpp Programming Supply Voltage 12.5 12.75 13.0 tER Input Rise, Fall Time 5 ns VIL Input Low Voltage -0.1 0.0 0.45 v ViH Input High Voltage 2.4 4.0 v tin Input Timing Reference Voltage 0.8 2.0 v tout Output Timing Reference Voltage 0.8 2.0 v Note 1: Nationals standard product warranty applies only to devices programmed to specifications described herein. Note 2: Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a board with voltage applied to Vpp or Vcc. Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 4F capacitor is required across Vpp, Voc to GND to suppress spurious voltage transients which may damage the device. Note 4: Programming and program verify are tested with the fast Progam Algorithm, at typical power supply voltages and timings. Note 5: During power up the CE/PGM pin must be brought high (> Vj) either coincident with or before power is applied to Vpp.Fast Programming Algorithm Flow Chart ADDR = FIRST LOCATION Vog = 6.25 Vpp = 12.75 PROGRAM ONE 100 ys PULSE INCREMENT X DEVICE FAILED INCREMENT ADDR Voc = Vpp = 5.0V 5% DEVICE FAILED DEVICE PASSED TL/D/10836-6 FIGURE 1Functional Description DEVICE OPERATION The six modes of operation of the EPROM are listed in Ta- ble |. It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are Voc and Vpp. The Vpp power supply must be at 12.75V during the three programming modes, and must be at 5V in the other three modes. The Voc power supply must be at 6.25V dur- ing the three programming modes, and at 5V in the other three modes. Read Mode The EPROM has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE/PGM) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tacc) is equal to the delay from CE to output (tog). Data is available at the outputs tog after the falling edge of OE, assuming that CE/PGM has been low and addresses have been stable for at least tacc- toe: Standby Mode The EPROM has a standby mode which reduces the active power dissipation by over 99%, from of 65 mW to 0.55 mW. The EPROM is placed in the standby mode by applying a CMOS high signal to the CE/PGM input. When in standby mode, the outputs are in a high impedance state, indepen- dent of the OE input. Output Disable The EPRON is placed in output disable by applying a TTL high signal to the OE input. When in output disable all cir- cuitry is enabled, except the outputs are in a high imped- ance state (TRI-STATE). Output OR-Typing Because the EPROM is usually used in larger memory ar- rays, National has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control function allows for: a) the lowest possible memory power dissipation, and b) complete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recom- mended that CE/PGM be decoded and used as the primary device selecting function, while OE be made a common connection to all devices in the array and connected to the READ tine from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. Programming CAUTION: Exceeding 14V on pin 1 (Vpp) will damage the EPROM. Initially, and after each erasure, all bits of the EPROM are in the 1s state. Data is introduced by selectively program- ming 0s into the desired bit locations. Although only 0s will be programmed, both 1's and 0s can be pre- sented in the data word. The only way to change a 0 toa 41 is by ultraviolet light erasure. The EPROM is in the programming mode when the Vpp power supply is at 12.75V and OE is at Vy. It is required that at least a 0.1 uF capacitor be placed across Vpp, Vcc to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. When the address and data are stable, an active low, TTL program pulse is applied to the CE/PGM input. A program pulse must be applied at each address location to be pro- grammed. The EPROM is programmed with the Fast Pro- gramming Algorithm shown in Figure 7. Each Address is programmed with a series of 100 ys pulses until it verifies good, up to a maximum of 25 pulses. Most memory cells will program with a single 100 ys pulse. The EPROM must not be programmed with a DC signal ap- plied to the CE/PGM input. Programming multiple EPROM in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the parallel EPROM may be connected together when they are pro- grammed with the same data. A low level TTL pulse applied to the CE/PGM input programs the paralleled EPROM. Note: Some programmer manufacturers, due to equipment limitation, may Offer interactive program Algorithm (shown in Figure 2. Program Inhibit Programming multiple EPROMs in parallel with different data is also easily accomplished. Except for CE/PGM all like inputs (including OE) of the parallel EPROMs may be common. A TTL low level program pulse applied to an EPROM's CE/PGM input with Vpp at 12.75V will program that EPROM. A TTL high tevel CE/PGM input inhibits the other EPROMs from being programmed. Program Verify A verify should be performed on the programmed. bits to determine whether they were correctly programmed. The verify may be performed with Vpp at 12.75V. Vpp must be at Voc, except during programming and program verify. AFTER PROGRAMMING Opaque labels should be placed over the EPROM window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the genera- tion of photo currents. MANUFACTURERS IDENTIFICATION CODE The EPROM has a manufacturers identification code to aid in programming. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then automatically calls up the specific programming algo- rithm for the part. This automatic programming control is only possible with programmers which have the capability of reading the code. The Manufacturer's Identification code, shown in Table Il, specifically identifies the manufacturer and device type. The code for NM27C040 is 8F08, where 8F" designates that it is made by National Semiconductor, and 08 designates a 4 Megabit (612K x 8) part. The code is accessed by applying 12V +0.5V to address pin AQ. Addresses A1-A8, A10-A18, and all control pins are held at V\_. Address pin AO is held at Vi_ for the manu-Functional Description (Continued) facturers code, and held at Viy for the device code. The code is read on the eight data pins, OgO7. Proper code access is only guaranteed at 25C +5C. ERASURE CHARACTERISTICS The erasure characteristics of the device are such that era- sure begins to occur when exposed to light with wave- lengths shorter than approximately 4000 Angstroms (A). tt should be noted that sunlight and certain types of fluores- cent lamps have wavelengths in the 3000A-4000A range. The recommended erasure procedure for the EPROM is ex- posure to short wave ultraviolet light which has a wave- length of 2537A. The integrated dose (i.e., UV intensity X exposure time) for erasure should be minimum of 15W-sec/cm2. The EPROM should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure. An erasure system should be calibrated periodically. The distance from lamp to device should be maintained at one inch. The erasure time increase as the square of the dis- tance from the lamp. (If distance is doubled the erasure time increases by factor of 4.) Lamps lose intensity as they age. Mode Selection When a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make cer- tain full erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, compo- nents, and even system designs have been erroneously suspected when incomplete erasure was the problem. SYSTEM CONSIDERATION The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, Icc, has three segments that are of interest to the system de- signer: the standby current level, the active current level, and the transient current peaks that are produced by volt- age transitions on input pins. The magnitude of these tran- sient current peaks is dependent of the output capacitance loading of the device. The associated Vcc transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that at least a 0.1 F ceramic capacitor be used on every device between Vcc and GND. This should be a high frequency capacitor of low inherent inductance. In addition, at least a 4.7 F bulk electrolytic capacitor should be used between Vcc and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The pur- pose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces. The modes of operation of the NM27C040 are listed in Table |. A single 5V power supply is required in the read mode. All inputs are TTL levels except for Vpp and AQ for device signature. TABLE I. Modes Selection Pins CE/PGM OE Vpp Vec Outputs Mode Read VIL Vit x 5.0V Dout (Note 1) Output Disable xX Vin x 5.0V High Z Standby VIH xX xX 5.0V High Z Programming Vit Vin 12.75V 6.25V Din Program Verify xX VIL 12.75V 6.25V Dout Program Inhibit Vin ViH 12.75V 6.25V High Z Note 1: X can be Vi, or Vy TABLE Ii. Manufacturers Identification Code Pins AO | A9 | 07 | 06 (12) | (26) | (21) | (20) 05 | 04 | 03 | 02 | 01 | 00 | Hex (19) | (18) | (17) | (15) | (14) | (13) | Data Manufacturer Code | Vi_ | 12V] 1 0 0 0 1 1 1 1 8F Device Code Vin | 12V] 0 0 0 0 1 0 0 0 08Physical Dimensions inches (mitimeters) 1.660 MAX 32 17 AAA AAA AAs I ] R0.025 | \ ) - - + V - ~ 0.585 WAX t \ \ Se J LILAC TILL Cayts RARARARA LAT 1 R 0.030-0.055 UV WINDOW SIZE AND CONFIGURATION DETERMINED BY DEVICE SIZE. >| f+ 0.050-0.060 9.010 MAX 0.590-0.620 Le 9.005 MIN GLASS SEALANT TYP 1 | t 0.225 max Te HY r] 0.175 WAX 0.125 MIN 0.015-0.060 80" Nae 0. 08 a. 012 P TYP 0,090-0.110 860-940 TYP 0.150 MIN TYP Tre 0.685 +0. as] 0.060 | 0.060-0.100 TYP 9.01570.021 45240 (REV. 0} 32-Lead EPROM Ceramic Dual-in-Line Package (Q) Order Number NM27C040QXXX NS Package Number J32AQ 10Physical Dimensions inches (millimeters) (Continued) BASE J PLANE r 0.015 r > [* [0.38] MIN TYP 0.485-0.495, [12.32-12.57] [# [raion Of) 0.449-0.453 [11.40-11,51] | 00 + [aa070.01 Oe]-=O] (1143) ON L 0.106-0.112 0.000-0.010 | 2] [2.69-2.84] [0.00-0.25] [=0-] 0.023-0.029 POLISHED OPTIONAL . 7p so 10.58-0.74] I 5 29 a 0.549-0.553 q 0 [13.94- 14.05] o 0 44 Hy 0.541-0.545 d O [13.74-13.84] * tee 0.585-0.595 q H [14.86-15.11] q 0 q Hi 3 4 n {0.050 OU TOUUoTI 14 20 I Lo sec vera a $0070. OLD $ | 0.007(0.18] [a|F-6 0.123-0.140 [3.12-3.56] 9 0:118-0.129 (3.00-3.28] [+ [rea Op [eereO| 0.042-0.048 45X Ty 07-1.22] 8 0.025 (0.64) MIN 0.006-0.012 -| _ 0.026-0.032 [0.15-0.30] [0.66-0.81] 0.019-0.025 [eco OppareS] (48-084 ae 0.490-0.530 {12.45-13.46] ( tio 18] ) an =+ 0.013-0.021 (0.33-0.53] 0.078-0.095 TYP [1.98-2.44] 32-Lead PLCC Package (V) Order Number NM27CO40VXXX NS Package Number VA32A el te 9.008 yay =C= 0.020 y [0.13] 9 9100 0.004{0. 10] (o.51) | ft [0.254] 1 0.045 _] [1.14] 0.030-0.040 [0.76-1.02] 0.025 y [0.54] MN DETAIL A TYPICAL 0.021-0.027 ae ROTATED 90 bs 0.065-0.071 + [1.65-1.80] [__0.053-0.059 [1.35- 1.50] 0.031-0.037 i [0.79-0.94] 0.027-0.033 [0.69-0.84] SECTION B-8 VASA (REV a) TYPICAL WNM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM . . . Lit # 112239- Physical Dimensions inches (millimeters) (Continued) 39-004 | 20.0 40.2 | tr 95 - 1,06 = = SO SS SS = "Ee SS ny oS > 4 > = [assem > > 16 0.15-0.25 TYP ele o.150 20.008 (LEADFRAME THICKNESS) I 18.440.1 | [ = + \ fai Tw F\ Ale-10 SEE DETAIL A 1.27 MAX \ 99-50 32-Lead TSOP Package Order Number NM27CO40TXXX NS Package Number MBH32A 0.4-0.6 DETAIL A TYPICAL 0-0.25 WBHSZA (REV B) LIFE SUPPORT POLICY NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. 40453 National Semiconductor National National Nationa! National Semiconductores National Semiconductor Corporation GmbH Japan Ltd. Kong Ltd. Do Brazil Ltda. (Australia) Pty, Ltd. 2900 Semiconductor Drive Industriestrasse 10 Sanseido Bldg. 5F 13th Floor, Straight Block Av. Brig. Faria Lima, 1409 16 Business Park Dr. P.O. Box 58090 D-82256 Firstenfeldbruck 4-15-3 Nishi Shinjuku Ocean Centre, Canton Rd. 6 Andar Notting Hill, VIC 3168 Santa Clara, CA 95052-8090. ermany Shinjuku-Ku, Tsimshatsui, Kowloon Cep-01451, Paulistano, Australia Tel: 1{800) 272-9959 Tel: (0-81-41) 103-0 Tokyo 160, Japan Hong Kong Sao Paulo, SP, Brazil Tal: (3) 558-9999 TWX: (810) 339-9240 Telex: 527649 Tel: 3-3298-7001 Tel: (852) 737-1600 Tel: (55-11) 212-5066 Fax: (3) 558-9998 Fax: (0-81-41) 10-35-06 FAX: 3-3299-7000 Telex: 51292 NSHKL Fax: (852) 736-9960 Telex: 391-1131931 NSBR BA Fax: (65-41) 212-1184 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications, /x