AP2142A/ AP2152A
Document number: DS32191 Rev. 3 - 2 4 of 16
www.diodes.com March 2013
© Diodes Incorporated
AP2142A/ AP2152A
Electrical Characteristics (@TA = +25°C, VIN = +5.0V, unless otherwise specified.)
Symbol Parameter Test Conditions (Note 5) Min Typ Max Unit
VUVLO Input UVLO 1.6 2.0 2.4 V
ISHDN Input Shutdown Current Disabled, IOUT = 0 0.1 1 µA
IQ Input Quiescent Current, Dual Enabled, IOUT = 0 115 180 µA
ILEAK Input Leakage Current Disabled, OUT grounded 1 µA
IREV Reverse Leakage Current Disabled, VIN = 0V, VOUT = 5V, IREV at VIN 0.01 0.1 µA
RDS(ON) Switch On-Resistance
VIN = 5V, IOUT = 0.5A,
TA = +25°C
SO-8 90 110
m
MSOP-8EP,
U-DFN3030-8 85 105
VIN = 5V, IOUT = 0.5A, -40°C TA +85°C 135
VIN = 3.3V, IOUT = 0.5A,
TA = +25°C
SO-8 110 130
MSOP-8EP,
U-DFN3030-8 105 125
VIN = 3.3V, IOUT = 0.5A, -40°C TA +85°C 170
ILIMIT Over-Load Current Limit VIN = 5V, VOUT = 4V, CL = 4.7µF -40°C TA +85°C 0.55 0.7 0.85 A
ILIMIT_G Ganged Over-Load Current Limit VIN = 5V, VOUT = 4V, OUT1 &
OUT2 tied together, CL = 4.7µF -40°C TA +85°C 1.1 1.4 1.7 A
ITrig Current Limiting Trigger Threshold Output Current Slew rate (<100A/s), CL = 4.7µF 1.0 A
ITrig_G Ganged Current Limiting Trigger
Threshold OUT1 & OUT2 tied together, Output Current Slew rate
(<100A/s), CL = 4.7µF 1.0 A
IOS Short-Circuit Current per Channel OUTx connected to ground, device enabled into short
circuit, CL = 4.7µF 0.7 A
IOS_G Ganged Short-Circuit Current OUT1 & OUT2 connected to ground, device enabled into
short-circuit, CL = 4.7µF 1.1 1.4 1.7 A
TSHORT Short-Circuit Response Time VOUT = 0V to IOUT = ILIMIT (output shorted to ground) 2 µs
VIL EN Input Logic Low Voltage VIN = 2.7V to 5.5V 0.8 V
VIH EN Input Logic High Voltage VIN = 2.7V to 5.5V 2 V
ISINK EN Input Leakage VEN = 0V to 5.5V 1 µA
ILEAK-O Output Leakage Current Disabled, VOUT = 0V 0.5 1 µA
TR Output Turn-On Rise Time CL = 1µF, RLOAD = 10 0.6 1.5 ms
TF Output Turn-Off Fall Time CL = 1µF, RLOAD = 10 0.05 0.3 ms
TD(ON) Output Turn-On Delay Time CL = 100µF, RLOAD = 10 0.2 0.5 ms
TD(OFF) Output Turn-Off Delay Time CL = 100µF, RLOAD = 10 0.1 0.3 ms
RFLG FLG Output FET On-Resistance IFLG = 10mA 20 40
IFOH FLG Off Current VFLG = 5V 0.01 1 µA
TBlank FLG Blanking Time CL =4.7µF 4 7 15 ms
RDIS Discharge Resistance (Note 6) VIN = 5V, disabled, IOUT =1mA 100
TSHDN Thermal Shutdown Threshold Enabled, RLOAD =1k 140 C
THYS Thermal Shutdown Hysteresis 25 C
JA Thermal Resistance Junction-to-Ambient SO-8 (Note 7) 115 °C/W
MSOP-8EP (Note 8) 75
U-DFN3030-8 (Note 8) 60
Notes: 5. Pulse-testing techniques maintain junction temperature clo se to ambient temperature; thermal effects must be taken into account separately.
6. The discharge function is active when the device is disabled (when enable is de-asserted or during power-up / power-down when VIN < VUVLO). The
discharge function offers a resistive discharge path for the external storage capacitor for limited time.
7. Test condition for SO-8: Device mounted on FR-4 substrate PCB with minimum recommended pad layout.
8. Test condition for MSOP-8EP and U-DFN3030-8: Device mounted on 2” x 2” FR-4 substrate PCB, 2oz copper, with minimum recommended pad on top
layer and thermal vias to bottom layer ground plane.