M24512-MW6T - STMicroelectronics

1/18June 2002

M24512

512 Kbit Serial I²C Bus EEPROM

■Two Wire I2C Serial Interface

Supports 400 kHz Protocol

■Single Supply Voltage:

– 4.5V to 5.5V for M24512

– 2.5V to 5.5V for M24512-W

– 1.8V to 3.6V for M24512-S

■Write Control Input

■BYTE and PAGE WRITE (up to 128 Bytes)

■RANDOM and SEQ UEN TIAL READ Modes

■Self-Tim ed P ro gr a m ming Cycle

■Automatic Addres s Incrementing

■Enhanced E SD/La tch-Up Behavior

■More than 100,000 Erase/Write Cycles

■More than 40 Year Data Retention

DESCRIPTION

These I2C-compatible electrically erasable

programmable memory (EEPROM) devices are

organised as 64Kx8 bits, and operate down to

2.5 V (for the -W version), and down to 1.8 V (for

the -S v ersion).

These devices are compatible with the I2C

memory protocol. This is a two wire serial interface

that us es a bi-directional data bus and serial c lock.

The devices carry a built-in 4-bit Device Type

Identifier code (1010) in accordance with the I2C

bus def i nition.

Figure 1. Logic Diagram

AI02275

SDA

VCC

M24512

SCL

VSS

E0-E2

Table 1. Signal Names

E0, E1, E2 Chip Enable

SDA Serial Data

SCL Serial Clock

WC Write Control

VCC Supply Volta ge

VSS Ground

PDIP8 (BN)

0.25 mm frame

LGA8 (LA)

LGA

SO8 (MW)

200 mil width

M24512

2/18

Figure 2A. DIP Connections

Figure 2B. LGA Connections

SDAVSS SCL

WCE1

E0 VCC

AI02276

M24512

SDAVSS SCL

E0 VCC

AI03791

M24512

Figure 2C. SO8 Connections

AI04035

5SDAVSS SCL

WCE1

E0 VCC

M24512

Table 2. Absolute Maximum Ratings 1

Note: 1. Exc ept for t he rating “Operating Temperatu re Range”, s tr esses a bove th ose lis ted in the Tabl e “Abs ol ute Maximum Ratings” m ay

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality

documents.

2. I PC/JEDE C J- S T D- 02 0A

3. JEDEC Std J ESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

Symbol Parameter Value Unit

TAAmbient Operating Temperature –40 to 125 °C

TSTG Storage Temperature –65 to 150 °C

TLEAD Lead Temperature during Soldering PDIP: 10 seconds

SO: 20 seconds (max) 2260

235 °C

VIO Input or Output range –0.6 to 6.5 V

VCC Supply Voltage –0.3 to 6.5 V

VESD Electrostatic Discharge Voltage (Human Body model) 34000 V

3/18

M24512

The device behaves as a sl ave in the I2C protocol,

with all memory operations synchronized by the

serial clock. Read and Write operations are

initiated by a Start condition, generated by the bus

master. The Start condition is followed by a Device

Select Code and RW bit (as described in Table 3),

terminated by an acknow ledge bit.

When writing data to the memory, the device

inserts an acknowledge bit during the 9th bit time ,

following the bus master’s 8-bit transmission.

When data is read by the bus master, the bus

master acknowledg es the receipt of the data byte

in the same way. Data transfers are terminated by

a Stop condition after an Ack for Write, and after a

NoAck for Read.

Power On Reset: VCC Lock-Out Write Pr otect

In order to prevent data corruption and inadvertent

Write operations during Power-up, a Power On

Reset (POR) circuit is included. The in ternal reset

is held active until VCC has reached the POR

threshold value, and all opera tions are disabled –

the device will not respond to any command. In the

same way, when VCC drops from the operating

voltage, below the POR threshold value, all

operations are disabled and the device will not

respond to any comma nd. A stab le a nd vali d VCC

must be applied before applying any logic si gnal.

SIGNAL DESCRIPTION

Serial Clo ck (SCL)

This input signal is u sed to strobe all data in and

out of the device. In applications where this signal

is used by slave devices to synchronize the bus to

a slower clock, the bus master must have an open

drain output, and a pull-up resistor must be

connected from Serial Clock (SCL) to VCC. (Figure

3 indicates how the value of the pull-up resistor

can be calculated). In most applications, though,

this method of synchronization is not employed,

and so the pull-up resistor is not necessary,

provided that the bus master has a push-pull

(rather than open drain) output.

Serial Data (SDA)

This bi-directional signal is used t o t ransfer data in

or out of the device. It is an open drai n output that

may be wi re-OR’ed with ot her op en drai n or open

collector signals on the bus. A pull up resistor mus t

be connected from Serial Data (SDA) to VCC.

(Figure 3 indicates how the value of the pull-up

resistor can be calculated).

Chip Enable (E0, E1, E2)

These input signals are used to set the value that

is to be looked f or on the three least significant bits

(b3, b2, b1) of the 7-bit Device Select Code. These

inputs must be tied to VCC or VSS, to establish the

Device Select Code. When unconnected, the Chip

Enable (E2, E 1, E 0) sign als are internally read as

VIL (see Tables 7 and 8).

Write Control (WC)

This input signal is usef ul for protecting t he entire

contents of the memory from inadvertent write

operations. Write operations are disabled to the

entire memory array when Write Control (WC) is

driven High. When unconnected, the signal is

internally read as VIL, and Write operations are

allowed.

When Write Control (WC) is driven High, Device

Select and Address bytes are acknowledged,

Data bytes are not acknowledged.

Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus

AI01665

VCC

CBUS

SDA

MASTER

SCL CBUS

100

CBUS (pF)

Maximum RP value (kΩ)

10 1000

fc = 400kHz

fc = 100kHz

M24512

4/18

DEVICE OPERATION

The device supports the I2C protocol. This is

summarized in Figure 4. Any device that sends

data on to the bus is defined to be a transmitter,

and any device that reads the data to be a

receiver. The device that controls the data transfer

is known as the bus master, and the other as the

slave device. A data t ransfer can only be initiated

by the bus master, which will also provide the

serial clock for synchronization. The M24512

device is always a slave in all communi cati on.

Start Condition

Start is identified by a falling edge of Serial Data

(SDA) while Serial Clock (SCL) is stable in the

High state. A Start condition must precede any

data transfer command. The device continuously

monitors (exc ept duri n g a Writ e cycle) Se rial Data

(SDA) and Serial Clock (S CL) for a Start condition,

and will not re spond unles s one is given.

Stop Condition

Stop is identified by a rising edge of Serial Data

(SDA) while Serial Clock (SCL) is stable and

driven High. A Stop condition terminates

communication between the device and the bus

master. A Read command that is followed by

NoAck can be followed by a Stop condition to force

the device into the Stand-by mode. A Stop

condition at the end of a Write command triggers

th e int er n a l EEPROM Writ e cycle.

Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a

successful byte transfer. The bus transmitter,

whether it be bus master or sl ave device, rel eases

Serial Data (SDA) after sending eight bits of data.

During the 9th clock pulse period, the receiver pulls

Serial Data (SDA) Low to acknowl edge the receipt

of the eight data bits.

Figure 4. I2C Bus Protocol

SCL

SDA

SCL

SDA

START

Condition

SDA

Input SDA

Change

AI00792B

STOP

Condition

123 789

MSB ACK

START

Condition

SCL 123 789

MSB ACK

STOP

Condition

5/18

M24512

Data Input

During data input, the device samples Serial Data

(SDA) on the rising edge of Serial Clock (SCL).

For correct device operation, Serial Data (SDA)

must be stable during the rising edge of Serial

Clock (SCL), and the Serial Data (SDA) signal

must change

only

when Serial Clock (SCL) is

driven Low.

Memory Addressing

To start communication between the bus master

and the slave device, the bus maste r must initiate

a Start condition. Following this, the bus master

sends the Device Select Code, shown in Table 3

(on Serial Data (SDA), most significant bit f i rst).

The Device Select Code consists of a 4-bit Device

Type Identifier, and a 3-bit Chip Enable “Add re ss”

(E2, E1, E0). To address t he memory array, the 4-

bit Device T ype Identi fier is 1010b.

Up to eight memory devices can be c onnect ed on

a single I 2C bus. Eac h one is given a uniq ue 3-bit

code on the Chip Enable (E0, E1, E2) inputs.

When the Device Select Code is received on

Serial Data (SDA), the device only responds if the

Chip Enable Addres s i s the same as the v alue on

the Chip Enable (E0, E1, E2) inputs.

The 8th bit is the Read/Write bit (RW). This bit is

set to 1 for Read and 0 for Write operations.

If a match occurs on the Device Select code, the

corresponding device gives an acknowledgment

on Serial Data (SD A) du ring the 9th bit time. If the

device does not match the Device Select code, it

deselects itself from the bus, and goes into Stand-

by mode.

Write Operations

Following a Start condition the b us master sends

a Device Select Code with the RW bi t re set t o 0.

The device acknowledges t his, as shown in Figure

6, and waits for two address bytes. The device

responds to each address byte with an

acknowledge bit, and then waits for the data byte.

Writing to the memory may be inhibited if Write

Control (WC) is d riven High. Any Writ e instruction

with Write Control (WC) driven High (during a

period of time from the Start condition until the end

of the two address bytes) will not modify the

memory contents, and the accompanying data

bytes are

not

acknowledged, as shown in Figure 5.

Each data byte in the memory has a 16-bit (two

byte wide) address. The Most Significant Byte

(Table 4) is sent first, followed by the Least

Significant By te (Ta ble 5). Bits b 15 to b0 form t he

address of the byte in memory.

When th e bus mast er generate s a S top con dition

immediat ely after the Ack bi t (in t he “10th bit” time

slot), either at the end of a Byte Write or a Page

Write, the internal memory Write cycle is triggered.

Table 3. Device Select Code 1

No te : 1 . The m ost significant bit, b7, is sent firs t .

Device Type Identifier Chip Enable Address RW

b7 b6 b5 b4 b3 b2 b1 b0

Device Select Code 1 0 1 0 E2 E1 E 0 RW

Table 4. Mos t Significant Byte

Table 5. Least Significant Byte

b15 b14 b13 b12 b11 b10 b9 b8

b7 b6 b5 b4 b3 b2 b1 b0

Table 6. Operating Modes

No te: 1 . X = VIH or VIL.

Mode RW bit WC 1 Bytes Initial Sequence

Current Address Read 1 X 1 START, Device Select, RW = 1

Random Address Read 0X1

START, Device Select, RW = 0, Address

1 X reSTART, Device Select, RW = 1

Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read

Byte Write 0 VIL 1 START, Device Select, RW = 0

Page Write 0 VIL ≤ 128 START, Device Select, RW = 0

M24512

6/18

Figu re 5. Wri t e Mode Sequences w ith W C =1 (data writ e inhibi ted)

STOP

START

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

START

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

DATA IN 2

AI01120C

PAGE WRITE

(cont'd)

WC (cont'd)

STOP

DATA IN N

ACK ACK ACK NO ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK NO ACK

A Stop condition at any other time slot does not

trigger the internal Write cycle.

During the internal Write cycle, Seria l Da ta (SDA)

is disabled internally, and the device does not

respond to any requests.

Byte Write

After the Device Select code and the address

bytes, the bus master s ends one dat a byte. If the

addressed location is Write-protected, by Write

Control (WC) being driven High, the device replies

with NoAck, and the location is not modified. If,

instead, the addressed location is not Write-

protected, the device replies with Ack. The bus

master terminates the transfer by generating a

Stop condi tion, as shown in Figure 6.

Page Write

The Page Wr ite mode allows up to 128 bytes to be

written in a single Write cycle, provided that they

are all located in the same ’row’ in the memory:

that is, the most significant memory address bits

(b15-b7) are the same. If more bytes are sent than

will fit u p t o the end of the r ow, a c ondit ion know n

as ‘roll-over’ occurs. This should be avoided, as

data starts to become overwritten in an

implement ation depend ent way.

The bus mas ter sends from 1 to 128 bytes of data,

each of which is acknowledged by the device if

Write Cont rol (WC) is Low. If Write Control (WC) is

High, the contents of the addressed memory

location are not modified, and each data byte is

followed by a NoAck. After each byte is

transferred, the internal byte address counter (the

7 least significant address bits only) is

incremented. The tr ansfer is terminated by the bus

master generating a Stop condition.

Minimizing System Delays by Polli ng On ACK

During the internal Write cycle, the device

disconnects its elf fr om the bus, and writ es a copy

of the data from its internal latches to the memory

7/18

M24512

Figu re 6. Wri t e Mode Sequences w ith W C =0 (data writ e enab led)

STOP

START

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

START

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

DATA IN 2

AI01106B

PAGE WRITE

(cont'd)

WC (cont'd)

STOP

DATA IN N

ACK

R/W

ACK ACK ACK

ACK ACK ACK ACK

R/W

ACKACK

cells. The maximum Write time (tw) is shown in

Table 9, but the typical time is shorter. To make

use of t his, a polling sequence can be used by the

bus master .

The sequenc e, as shown in Figure 7, is:

– Initial condition: a Write cycl e is i n progress.

– Step 1: the b us m as ter issues a S tart c ondi tion

followed by a Device Select Code (the first byte

of the new instruction).

– Step 2: if the device is busy with the internal

Write cy cle, no Ack will be returned and t he bus

master goes back to Step 1. If the device has

terminated the internal Write cycle, it responds

with an Ack, indicating that the device is ready

to receive t he second part of the instr uction (the

first byte of this instruction having been sent

during Step 1).

Read Operation s

Read operations are performed independently of

the state of the Write Cont rol (WC) signal.

Random Address Read

A dummy Write is performed to load the address

into the address counter (as shown in Figure 8) but

without

sending a Stop condition. Then, the bus

master sends anot her Start condition, and repeat s

the Device Sel ect Code, with t he RW bit set to 1.

The device acknowledges this, and outputs the

contents of the addressed byte. The bus master

must

not

acknowledge the byte, and terminates

the transfer wi th a Stop condition.

Current Address Read

The device has an internal address counter which

is incremented each time a byte is read. For the

Current Address Read operation, following a Start

condition, the bus master only sends a Device

Select Code with the RW bit set to 1. The device

acknowledges this, and outputs the byte

M24512

8/18

counter ‘rolls-over’, and the device continues to

output data from memory address 00h.

Acknowledge in Read Mode

For all Read commands, the device waits, after

each byte read, f or an acknowle dgm ent during the

9th bit time. If the bus master does not drive Serial

Data (SDA) Low during this time, the device

terminates the data transfer and switches to its

Stand-by mode.

addressed by the internal address counter. The

counter is then incremented. The bus master

terminates the transfer with a Stop condition, as

shown in Figure 8,

without

acknowledging the

byte.

Sequenti al Re ad

This operation can be used after a Current

Address Read or a Random Address Read. The

bus master

does

acknowledge the data byte

output, and sends addition al clock pulses so that

the device continues to output the next byte in

sequence. To terminate the stream of bytes, the

bus master must

not

acknowledge the last byte,

and

must

generate a Stop condition, as shown in

Figure 8.

The output data comes from consecutive

addresses, with the internal address counter

automatical ly i ncremen ted af ter each byte output.

After the last memory address, the address

Figu re 7. Wri t e C yc le Pol l in g Fl owchart us i n g ACK

WRITE Cycle

in Progress

AI01847C

Operation is

Addressing the

Memory

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

YES

YESNO

ReSTART

STOP

DATA for the

WRITE Operation DEVICE SELECT

with RW = 1

Send Address

and Receive ACK

First byte of instruction

with RW = 0 already

decoded by the device

YESNO START

Condition

Continue the

WRITE Operation Continue the

Random READ Operation

9/18

M24512

Figure 8. Read Mode Sequ ences

No te : 1 . The seven most significant bits of t he Device Select Code of a Ra ndom Read (in the 1 st and 4th by tes) mu st be id ent ical.

START

DEV SEL * BYTE ADDR BYTE ADDR

START

DEV SEL DATA OUT 1

AI01105C

DATA OUT N

STOP

START

CURRENT

ADDRESS

READ DEV SEL DATA OUT

RANDOM

ADDRESS

READ

STOP

START

DEV SEL * DATA OUT

SEQUENTIAL

CURRENT

READ

STOP

DATA OUT N

START

DEV SEL * BYTE ADDR BYTE ADDR

SEQUENTIAL

RANDOM

READ

START

DEV SEL * DATA OUT 1

STOP

ACK

R/W

NO ACK

ACK

R/W

ACK ACK ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK

ACK ACK ACK

R/W

ACK ACK

R/W

ACK NO ACK

M24512

10/18

Table 7. DC Characteristics

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.5 to 5.5 V)

(TA = 0 to 70 °C or –20 to 85 °C; VCC = 1.8 to 3.6 V)

Not e: 1. This is preliminary data.

Table 8. Input Parameters 1 (TA = 25 °C, f = 4 00 kHz)

Not e: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min. Max. Unit

ILI Input Leakage Current

(SCL, SDA) VIN = VSS or VCC ± 2 µA

ILI Input Leakage Current

(E2, E1, E0, WC)VIN = VSS ± 5 µA

ILO Output Leakage Current VOUT = VSS or VCC, SDA in Hi-Z ± 2 µA

ICC Supply Current

VCC=5V, fc=400kHz (rise/fall time < 30ns) 2mA

-W series: VCC =2.5 V, fc=400kHz (rise/fall time < 30ns) 1mA

-S series: VCC =1.8 V, fc=400kHz (rise/fall time < 30ns) 0.81mA

ICC1 Supply Current

(Stand-by)

VIN = VSS or VCC , VCC = 5 V 10 µA

-W series: VIN = VSS or VCC , VCC = 2.5 V 2 µA

-S series: VIN = VSS or VCC , VCC = 1.8 V 11µA

VIL Input Low Voltage – 0.3 0.3VCC V

VIH Input High Volta ge 0.7VCC VCC+1 V

VOL Output Low

Voltage

IOL = 3 mA, VCC = 5 V 0.4 V

-W series: IOL = 2.1 mA, VCC = 2.5 V 0.4 V

-S series: IOL = 0.15 mA, VCC = 1.8 V 0.21V

Symbol Parameter Test Condition Min. Max. Unit

CIN Input Capa citanc e (SDA) 8 pF

CIN Input Capacitance (other pins) 6 pF

ZLInput Impedance (E2, E1, E0, WC)V

IN ≤ VIL 50 300 kΩ

ZHInput Impedance (E2, E1, E0, WC) VIN ≥ VIH 500 kΩ

tNS Pulse width ignored

(Input Filter on SCL and SDA) Single glitch 200 ns

11/18

M24512

Table 9. AC Characteristics

No te : 1 . For a reSTA RT conditi on, or fo l l owing a Wr i te cycle .

2. Sam p l ed onl y, n ot 100% teste d.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

4. Thi s i s preli m i nary data.

Symbol Alt. Parameter

M24512

Unit

VCC=4.5 to 5.5 V

TA=0 to 70°C or

–40 to 85°C

VCC=2.5 to 5.5 V

TA=0 to 70°C or

–40 to 85°C

VCC=1.8 to 3.6 V

TA=0 to 70°C or

–20 to 85°C4

Min Max Min Max Min Max

tCH1CH2 tRClock Rise Time 300 300 300 ns

tCL1CL2 tFClock Fall Time 300 300 300 ns

tDH1DH2 2tRSDA Rise Time 20 300 20 300 20 300 ns

tDL1DL2 2tFSDA Fall Time 20 300 20 300 20 300 ns

tCHDX 1tSU:STA Clock High to Input Transition 600 600 600 ns

tCHCL tHIGH Clock Pulse Width High 600 600 600 ns

tDLCL tHD:STA Input Low to Clock Low (START) 600 600 600 ns

tCLDX tHD:DAT Clock Low to Input Transition 0 0 0 µs

tCLCH tLOW Clock Pulse Width Low 1.3 1.3 1.3 µs

tDXCX tSU:DAT Input Transition to Clock

Transition 100 100 100 ns

tCHDH tSU:STO Clock High to Input High (STOP) 600 600 600 ns

tDHDL tBUF Input High to Input Low (Bus

Free) 1.3 1.3 1.3 µs

tCLQV 3tAA Clock Low to Data Out Valid 200 900 200 900 200 900 ns

tCLQX tDH Data Out Hold Time After Clock

Low 200 200 200 ns

fCfSCL Clock Frequency 400 400 400 kHz

tWtWR Write Time 10 10 10 ms

Table 10. A C Measurem en t Condition s

Input Rise and Fall Times ≤ 50 ns

Input Pulse Voltages 0.2VCC to 0.8VCC

Input and Output Timing

Reference Voltages 0.3VCC to 0.7VCC

Figu re 9. AC Measurement C ondition s

AI00825

0.8VCC

0.2VCC

0.7VCC

0.3VCC

M24512

12/18

Figure 10. AC Waveforms

SCL

SDA In

SCL

SDA Out

SCL

SDA In

tCHCL

tDLCL

tCHDX

START

Condition

tCLCH

tDXCXtCLDX

SDA

Input

SDA

Change tCHDH tDHDL

STOP

Condition

Data Valid

tCLQV tCLQX

tCHDH

STOP

Condition

tCHDX

START

Condition

Write Cycle

AI00795C

START

Condition

13/18

M24512

Table 11. Ordering Information Scheme

No te: 1. The -S vers i on (VCC range 1.8 V to 3.6 V) onl y availa bl e i n t emperature ranges 5.

Example: M24512 – W MW 6 T

Memory Capacity Option

512 512 Kbit (64K x 8) T Tape and Reel Packing

Operating Voltage

blank 4.5 V to 5.5 V

W 2.5 V to 5.5 V

S11.8 V to 3.6 V

Package Temperature Range

BN PDIP8 (0.25 mm frame) 5 –20 °C to 85 °C

MW SO8 (200 mil width) 6 –40 °C to 85 °C

LA LGA8 (Land Grid Array)

ORDERING INFORMATION

Devices are shipped from the factory with the

memory c ontent set at all 1s (F Fh).

The notation used for the device number is as

shown in Table 11. For a list of available options

(speed, package, etc.) or for f urt her information on

any aspect of this device, please contact your

nearest ST Sales Office.

M24512

14/18

PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Packag e Outline

Note: 1. Drawing is not to scale.

PDIP-B

PDIP8 – 8 pin Plastic DIP, 0. 25mm lead frame, P ackage Mechanical Dat a

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 5.33 0.210

A1 0.38 0.015

A2 3.30 2.92 4.95 0.130 0.115 0.195

b 0.46 0.36 0.56 0.018 0.014 0.022

b2 1.52 1.14 1.78 0.060 0.045 0.070

c 0.25 0.20 0.36 0.010 0.008 0.014

D 9.27 9.02 10.16 0.365 0.355 0.400

E 7.87 7.62 8.26 0.310 0.300 0.325

E1 6.35 6.10 7.11 0.250 0.240 0.280

e 2.54 – – 0.100 – –

eA 7.62 – – 0.300 – –

eB 10.92 0.430

L 3.30 2.92 3.81 0.130 0.115 0.150

15/18

M24512

SO8 wide – 8 lead Pl astic Smal l Outline, 200 mils body wi dth

Not e: Drawing is not to scale.

SO-b

LA1 α

SO8 wide – 8 lead Pl astic Smal l Outline, 200 mils body wi dth

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 2.03 0.080

A1 0.10 0.25 0.004 0.010

A2 1.78 0.070

B 0.35 0.45 0.014 0.018

C 0.20 – – 0.008 – –

D 5.15 5.35 0.203 0.211

E 5.20 5.40 0.205 0.213

e 1.27 – – 0.050 – –

H 7.70 8.10 0.303 0.319

L 0.50 0.80 0.020 0.031

α0° 10° 0° 10°

N8 8

CP 0.10 0.004

M24512

16/18

LGA8 - 8 lead Land Grid Array

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.040 0.940 1.140 0.0409 0.0370 0.0449

A1 0.340 0.300 0.380 0.0134 0.0118 0.0150

A2 0.700 0.640 0.760 0.0276 0.0252 0.0299

D 8.000 7.900 8.100 0.3150 0.3110 0.3189

D1 0.100 – – 0.0039 – –

E 5.000 4.900 5.100 0.1969 0.1929 0.2008

E1 1.270 – – 0.0500 – –

E2 3.810 – – 0.1500 – –

E3 0.390 – – 0.0154 – –

k 0.100 – – 0.0039 – –

T1 0.410 – – 0.0161 – –

T2 0.670 – – 0.0264 – –

T3 0.970 – – 0.0382 – –

ddd 0.100 – – 0.0039 – –

LGA8 - 8 lead Land Grid Array

Note: 1. Drawing is not to scale.

LGA-Z01B

CONTACT 1

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M24512

Revision History

Date Rev. Description of Revision

29-Jan-2001 1.1

Lead Soldering Temperature in the Absolute Maximum Ratings table amended

Write Cycle Polling Flow Chart using ACK illustration updated

LGA8 and SO8(wide) packages added

References to PSDIP8 changed to PDIP8, and Package Mechanical data updated

10-Apr-2001 1.2 LGA8 Package Mechanical data and illustration updated

SO16 package removed

16-Jul-2001 1.3 LGA8 Package given the designator “LA”

02-Oct-2001 1.4 LGA8 Package mechanical data updated

13-Dec-2001 1.5 Document becomes Preliminary Data

Test conditions for ILI, ILO, ZL and ZH made more precise

VIL and VIH values unified. tNS value changed

12-Jun-2001 1.6 Document becomes Full Datasheet

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