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© 1990, 1993, 1995
MOS INTEGRATED CIRCUIT
µ
PD431000A
1M-BIT CMOS STATIC RAM
128K-WORD BY 8-BIT
DATA SHEET
Document No. M11657EJBV0DS00 (11th edition)
Date Published April 2002 NS CP (K)
Printed in Japan
The mark ★ shows major revised points.
Description
The
µ
PD431000A is a high speed, low power, and 1,048,576 bits (131,072 words by 8 bits) CMOS static RAM.
The
µ
PD431000A has two chip enable pins (/CE1, CE2) to extend the capacity. And battery backup is available. In
addition to this, A and B versions are low voltage operations.
The
µ
PD431000A is packed in 32-pin PLASTIC DIP, 32-pin PLASTIC SOP and 32-pin PLASTIC TSOP (I) (8 × 13.4
mm) and (8 × 20 mm).
Features
• 131,072 words by 8 bits organization
• Fast access time: 70, 85, 100, 120, 150 ns (MAX.)
• Low voltage operation (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V)
• Operating ambient temperature: TA = 0 to 70 °C
• Low VCC data retention: 2.0 V (MIN.)
• Output Enable input for easy application
• Two Chip Enable inputs: /CE1, CE2
Part number Access time Operating supply Operating ambient Supply current
ns (MAX.) voltage temperature At operating At standby At data retention
V °C mA (MAX.)
µ
A (MAX.)
µ
A (MAX.) Note1
µ
PD431000A-xxL 70, 85 4.5 to 5.5 0 to 70 70 100 15
µ
PD431000A-xxLL 20 3
µ
PD431000A-Axx 70 Note2, 100 3.0 to 5.5 35 Note3 13 Note5
µ
PD431000A-Bxx 70 Note2, 100, 120, 150 2.7 to 5.5 30 Note4 11 Note6
Notes 1. TA ≤ 40 °C
2. VCC = 4.5 to 5.5 V
3. 70 mA (VCC > 3.6 V)
4. 70 mA (VCC > 3.3 V)
5. 20
µ
A (VCC > 3.6 V)
6. 20
µ
A (VCC > 3.3 V)
Data Sheet M11657EJBV0DS
2
µ
PD431000A
Ordering Information
Part number Package Access time Operating supply Operating ambient Remark
ns (MAX.) voltage temperature
V°C
µ
PD431000ACZ-70L 32-pin PLASTIC DIP 70 4.5 to 5.5 0 to 70 L version
µ
PD431000ACZ-85L (15.24mm (600)) 85
µ
PD431000ACZ-70LL 70 LL version
µ
PD431000ACZ-85LL 85
µ
PD431000AGW-70L 32-pin PLASTIC SOP 70 4.5 to 5.5 L version
µ
PD431000AGW-85L (13.34 mm (525)) 85
µ
PD431000AGW-70LL 70 LL version
µ
PD431000AGW-85LL 85
µ
PD431000AGW-A10 100 3.0 to 5.5 A version
µ
PD431000AGW-B12 120 2.7 to 5.5 B version
µ
PD431000AGW-B15 150
µ
PD431000AGZ-85L-KJH 32-pin PLASTIC TSOP(I) 85 4.5 to 5.5 L version
µ
PD431000AGZ-70LL-KJH (8x20) (Normal bent) 70 LL version
µ
PD431000AGZ-85LL-KJH 85
µ
PD431000AGZ-B10-KJH 100 2.7 to 5.5 B version
µ
PD431000AGZ-B15-KJH 150
µ
PD431000AGZ-70LL-KKH 32-pin PLASTIC TSOP(I) 70 4.5 to 5.5 LL version
µ
PD431000AGZ-B15-KKH (8x20) (Reverse bent) 150 2.7 to 5.5 B version
µ
PD431000AGU-B10-9JH 32-pin PLASTIC TSOP(I) 100 2.7 to 5.5 B version
µ
PD431000AGU-B12-9JH (8x13.4) (Normal bent) 120
µ
PD431000AGU-B15-9JH 150
µ
PD431000AGU-B10-9KH 32-pin PLASTIC TSOP(I) 100
(8x13.4) (Reverse bent)
Data Sheet M11657EJBV0DS 3
µ
PD431000A
Pin Configurations (Marking Side)
/xxx indicates active low signal.
32-pin PLASTIC DIP (15.24 mm (600))
[
µ
µµ
µ
PD431000ACZ-xxL]
[
µ
µµ
µ
PD431000ACZ-xxLL]
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
V
CC
A15
CE2
/WE
A13
A8
A9
A11
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0 - A16 : Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CE1, CE2 : Chip Enable 1, 2
/WE : Write Enable
/OE : Output Enable
VCC : Power supply
GND : Ground
NC : No connection
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M11657EJBV0DS
4
µ
PD431000A
32-pin PLASTIC SOP (13.34 mm (525))
[
µ
µµ
µ
PD431000AGW-xxL]
[
µ
µµ
µ
PD431000AGW-xxLL]
[
µ
µµ
µ
PD431000AGW-Axx]
[
µ
µµ
µ
PD431000AGW-Bxx]
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
V
CC
A15
CE2
/WE
A13
A8
A9
A11
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0 - A16 : Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CE1, CE2 : Chip Enable 1, 2
/WE : Write Enable
/OE : Output Enable
VCC : Power supply
GND : Ground
NC : No connection
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M11657EJBV0DS 5
µ
PD431000A
32-pin PLASTIC TSOP(I) (8x20) (Normal bent)
[
µ
µµ
µ
PD431000AGZ-xxL-KJH]
[
µ
µµ
µ
PD431000AGZ-xxLL-KJH]
[
µ
µµ
µ
PD431000AGZ-Bxx-KJH]
A11
A9
A8
A13
/WE
CE2
A15
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32-pin PLASTIC TSOP(I) (8x20) (Reverse bent)
[
µ
µµ
µ
PD431000AGZ-xxLL-KKH]
[
µ
µµ
µ
PD431000AGZ-Bxx-KKH]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
A11
A9
A8
A13
/WE
CE2
A15
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
A0 - A16 : Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CE1, CE2 : Chip Enable 1, 2
/WE : Write Enable
/OE : Output Enable
VCC : Power supply
GND : Ground
NC : No connection
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M11657EJBV0DS
6
µ
PD431000A
32-pin PLASTIC TSOP(I) (8x13.4) (Normal bent)
[
µ
µµ
µ
PD431000AGU-Bxx-9JH]
A11
A9
A8
A13
/WE
CE2
A15
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32-pin PLASTIC TSOP(I) (8x13.4) (Reverse bent)
[
µ
µµ
µ
PD431000AGU-Bxx-9KH]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
A11
A9
A8
A13
/WE
CE2
A15
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
A0 - A16 : Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CE1, CE2 : Chip Enable 1, 2
/WE : Write Enable
/OE : Output Enable
VCC : Power supply
GND : Ground
NC : No connection
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M11657EJBV0DS 7
µ
PD431000A
Block Diagram
Address buffer
Address
buffer Row
decoder Memory cell array
1,048,576 bits
Input data
controller
A0
A16
Sense amplifier /
Switching circuit
Column decoder
/CE1
/WE
/OE
CE2
Output data
controller
VCC
GND
I/O1
I/O8
Truth Table
/CE1 CE2 /OE /WE Mode I/O Supply current
H×××Not selected High impedance ISB
×L××
L H H H Output disable ICCA
L H L H Read DOUT
LH×LWrite DIN
Remark × : VIH or VIL
Data Sheet M11657EJBV0DS
8
µ
PD431000A
Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Supply voltage VCC –0.5 Note to +7.0 V
Input / Output voltage VT–0.5 Note to VCC + 0.5 V
Operating ambient temperature TA0 to 70 °C
Storage temperature Tstg –55 to +125 °C
Note –3.0 V (MIN.) (Pulse width: 30 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol Condition
µ
PD431000A-xxL
µ
PD431000A-Axx
µ
PD431000A-Bxx Unit
µ
PD431000A-xxLL
MIN. MAX. MIN. MAX. MIN. MAX.
Supply voltage VCC 4.5 5.5 3.0 5.5 2.7 5.5 V
High level input voltage VIH 2.2 VCC+0.5 2.2 VCC+0.5 2.2 VCC+0.5 V
Low level input voltage VIL –0.3 Note +0.8 –0.3 Note +0.5 –0.3 Note +0.5 V
Operating ambient temperature TA070070070°C
Note –3.0 V (MIN.) (Pulse width: 30 ns)
Capacitance (TA = 25 °
°°
°C, f = 1 MHz)
Parameter Symbol Test conditions MIN. TYP. MAX. Unit
Input capacitance CIN VIN = 0 V 6 pF
Input / Output capacitance CI/O VI/O = 0 V 10 pF
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These parameters are not 100% tested.
Data Sheet M11657EJBV0DS 9
µ
PD431000A
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
Parameter Symbol Test condition
µ
PD431000A-xxL
µ
PD431000A-xxLL
µ
PD431000A-Axx Unit
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX.
Input leakage ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0 –1.0 +1.0
µ
A
current
I/O leakage ILO VI/O = 0 V to VCC, –1.0 +1.0 –1.0 +1.0 –1.0 +1.0
µ
A
current /CE1 = VIH or CE2 = VIL
or /WE = VIL or /OE = VIH
Operating ICCA1 /CE1 = VIL, CE2 = VIH, 4070 4070 4070mA
supply current II/O = 0 mA
Minimum cycle time VCC ≤ 3.6 V – – 35
ICCA2 /CE1 = VIL, CE2 = VIH, II/O = 0 mA,151515
Cycle time = ∞VCC ≤ 3.6 V – – 8
ICCA3 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, 10 10 10
Cycle time = 1
µ
s, II/O = 0 mA,
VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V
VCC ≤ 3.6 V – – 8
Standby ISB /CE1 = VIH or CE2 = VIL 333mA
supply current VCC ≤ 3.6 V – – 2
ISB1 /CE1 ≥ VCC − 0.2 V, 2 100 1 20 1 20
µ
A
CE2 ≥ VCC − 0.2 V VCC ≤ 3.6 V – – 0.5 13
ISB2 CE2 ≤ 0.2 V 2 100 1 20 1 20
VCC ≤ 3.6 V – – – – 0.5 13
High level VOH1 IOH = –1.0 mA, VCC ≥ 4.5 V 2.4 2.4 2.4 V
output voltage IOH = –0.5 mA – – 2.4
VOH2 IOH = –0.02 mA – – VCC–0.1
Low level VOL1 IOL = 2.1 mA, VCC ≥ 4.5 V 0.4 0.4 0.4 V
output voltage IOL = 1.0 mA – – 0.4
VOL2 IOL = 0.02 mA – – 0.1
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless product classification.
Data Sheet M11657EJBV0DS
10
µ
PD431000A
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)
Parameter Symbol Test condition
µ
PD431000A-Bxx Unit
MIN. TYP. MAX.
Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0
µ
A
I/O leakage current ILO VI/O = 0 V to VCC, /CE1 = VIH or CE2 = VIL –1.0 +1.0
µ
A
or /WE = VIL or /OE = VIH
Operating supply current ICCA1 /CE1 = VIL, CE2 = VIH, II/O = 0 mA 40 70 mA
Minimum cycle time VCC ≤ 3.3 V 30
ICCA2 /CE1 = VIL, CE2 = VIH, II/O = 0 mA, 15
Cycle time = ∞VCC ≤ 3.3 V 7
ICCA3 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, 10
Cycle time = 1
µ
s, II/O = 0 mA,
VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V VCC ≤ 3.3 V 7
Standby supply current ISB /CE1 = VIH or CE2 = VIL 3mA
VCC ≤ 3.3 V 2
ISB1 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V 1 20
µ
A
VCC ≤ 3.3 V 0.5 11
ISB2 CE2 ≤ 0.2 V 1 20
VCC ≤ 3.3 V 0.5 11
High level output voltage VOH1 IOH = –1.0 mA, VCC ≥ 4.5 V 2.4 V
IOH = –0.5 mA 2.4
VOH2 IOH = –0.02 mA VCC–0.1
Low level output voltage VOL1 IOL = 2.1 mA, VCC ≥ 4.5 V 0.4 V
IOL = 1.0 mA 0.4
VOL2 IOL = 0.02 mA 0.1
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless product classification.
Data Sheet M11657EJBV0DS 11
µ
PD431000A
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[
µ
µµ
µ
PD431000A-70L,
µ
µµ
µ
PD431000A-85L,
µ
µµ
µ
PD431000A-70LL,
µ
µµ
µ
PD431000A-85LL]
Input Waveform (Rise and Fall Time ≤
≤≤
≤ 5 ns)
Test points1.5 V 1.5 V
2.2 V
0.8 V
Output Waveform
Test points1.5 V 1.5 V
Output Load
AC characteristics should be measured with the following output load conditions.
Figure 1 Figure 2
(tAA, tCO1, tCO2, tOE, tOH)(t
LZ1, tLZ2, tOLZ, tHZ1, tHZ2, tOHZ, tWHZ, tOW)
+5 V
I/O (Output)
1.8 kΩ
5 pF
C
L
990 Ω
+5 V
I/O (Output)
1.8 kΩ
100 pF
C
L
990 Ω
Remark CL includes capacitance of the probe and jig, and stray capacitance.
[
µ
µµ
µ
PD431000A-A10,
µ
µµ
µ
PD431000A-B10,
µ
µµ
µ
PD431000A-B12,
µ
µµ
µ
PD431000A-B15]
Input Waveform (Rise and Fall Time ≤
≤≤
≤ 5 ns)
Test points1.5 V 1.5 V
2.2 V
0.5 V
Output Waveform
Test points1.5 V 1.5 V
Output Load
AC characteristics should be measured with the following output load conditions.
Part number Output load condition
tAA, tCO1, tCO2, tOE, tOH tLZ1, tLZ2, tOLZ, tHZ1, tHZ2, tOHZ, tWHZ, tOW
µ
PD431000A-A10,
µ
PD431000A-B10,
µ
PD431000A-B12 1TTL + 50 pF 1TTL + 5 pF
µ
PD431000A-B15 1TTL + 100 pF 1TTL + 5 pF
Data Sheet M11657EJBV0DS
12
µ
PD431000A
Read Cycle (1/2)
Parameter Symbol VCC ≥ 4.5 V VCC ≥ 3.0 V Unit Condition
µ
PD431000A-70
µ
PD431000A-85
µ
PD431000A-A10
µ
PD431000A-Axx
µ
PD431000A-Bxx
MIN. MAX. MIN. MAX. MIN. MAX.
Read cycle time tRC 70 85 100 ns
Address access time tAA 70 85 100 ns Note
/CE1 access time tCO1 70 85 100 ns
CE2 access time tCO2 70 85 100 ns
/OE to output valid tOE 35 45 50 ns
Output hold from address change tOH 10 10 10 ns
/CE1 to output in low impedance tLZ1 10 10 10 ns
CE2 to output in low impedance tLZ2 10 10 10 ns
/OE to output in low impedance tOLZ 555ns
/CE1 to output in high impedance tHZ1 25 30 35 ns
CE2 to output in high impedance tHZ2 25 30 35 ns
/OE to output in high impedance tOHZ 25 30 35 ns
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
Read Cycle (2/2)
Parameter Symbol VCC ≥ 2.7 V Unit Condition
µ
PD431000A-B10
µ
PD431000A-B12
µ
PD431000A-B15
MIN. MAX. MIN. MAX. MIN. MAX.
Read cycle time tRC 100 120 150 ns
Address access time tAA 100 120 150 ns Note
/CE1 access time tCO1 100 120 150 ns
CE2 access time tCO2 100 120 150 ns
/OE to output valid tOE 50 60 70 ns
Output hold from address change tOH 10 10 10 ns
/CE1 to output in low impedance tLZ1 10 10 10 ns
CE2 to output in low impedance tLZ2 10 10 10 ns
/OE to output in low impedance tOLZ 555ns
/CE1 to output in high impedance tHZ1 35 40 50 ns
CE2 to output in high impedance tHZ2 35 40 50 ns
/OE to output in high impedance tOHZ 35 40 50 ns
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
Data Sheet M11657EJBV0DS 13
µ
PD431000A
Read Cycle Timing Chart
t
HZ2
t
RC
t
OH
t
HZ1
t
LZ2
t
CO2
t
LZ1
t
CO1
t
AA
High impedance Data out
CE2 (Input)
/CE1 (Input)
Address (Input)
I/O (Output)
t
OLZ
t
OE
t
OHZ
/OE (Input)
Remark In read cycle, /WE should be fixed to high level.
Data Sheet M11657EJBV0DS
14
µ
PD431000A
Write Cycle (1/2)
Parameter Symbol VCC ≥ 4.5 V VCC ≥ 3.0 V Unit Condition
`
µ
PD431000A-70
µ
PD431000A-85
µ
PD431000A-A10
µ
PD431000A-Axx
µ
PD431000A-Bxx
MIN. MAX. MIN. MAX. MIN. MAX.
Write cycle time tWC 70 85 100 ns
/CE1 to end of write tCW1 55 70 80 ns
CE2 to end of write tCW2 55 70 80 ns
Address valid to end of write tAW 55 70 80 ns
Address setup time tAS 000ns
Write pulse width tWP 50 60 60 ns
Write recovery time tWR 550ns
Data valid to end of write tDW 35 35 60 ns
Data hold time tDH 000ns
/WE to output in high impedance tWHZ 25 30 35 ns Note
Output active from end of write tOW 555ns
Note See the output load.
Remark These AC characteristics are in common regardless package types.
Write Cycle (2/2)
Parameter Symbol VCC ≥ 2.7 V Unit Condition
µ
PD431000A-B10
µ
PD431000A-B12
µ
PD431000A-B15
MIN. MAX. MIN. MAX. MIN. MAX.
Write cycle time tWC 100 120 150 ns
/CE1 to end of write tCW1 80 100 120 ns
CE2 to end of write tCW2 80 100 120 ns
Address valid to end of write tAW 80 100 120 ns
Address setup time tAS 000ns
Write pulse width tWP 60 85 100 ns
Write recovery time tWR 000ns
Data valid to end of write tDW 60 60 80 ns
Data hold time tDH 000ns
/WE to output in high impedance tWHZ 35 40 50 ns Note
Output active from end of write tOW 555ns
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
Data Sheet M11657EJBV0DS 15
µ
PD431000A
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
t
CW1
t
WHZ
t
DW
t
DH
t
OW
Indefinite data out High
impe-
dance
High
impe-
dance
Data in Indefinite data out
Address (Input)
/CE1 (Input)
I/O (Input / Output)
CE2 (Input)
t
CW2
t
AW
t
WP
t
AS
t
WR
/WE (Input)
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.
2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2
changes to high level at the same time or after the change of /WE to low level, the I/O pins will
remain high impedance state.
3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
Data Sheet M11657EJBV0DS
16
µ
PD431000A
Write Cycle Timing Chart 2 (/CE1 Controlled)
tWC
tAS tCW1
tDW tDH
Data in
High impedance
Address (Input)
/CE1 (Input)
I/O (Input) High
impedance
CE2 (Input)
tCW2
tAW tWP tWR
/WE (Input)
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.
Data Sheet M11657EJBV0DS 17
µ
PD431000A
Write Cycle Timing Chart 3 (CE2 Controlled)
t
WC
t
AS
t
CW2
t
DW
t
DH
Data in
High impedance
Address (Input)
CE2 (Input)
I/O (Input) High
impedance
/CE1 (Input)
t
CW1
t
AW
t
WP
t
WR
/WE (Input)
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.
Data Sheet M11657EJBV0DS
18
µ
PD431000A
Low VCC Data Retention Characteristics (TA = 0 to 70 °
°°
°C)
Parameter Symbol Test Condition
µ
PD431000A-xxL
µ
PD431000A-xxLL Unit
µ
PD431000A-Axx
µ
PD431000A-Bxx
MIN. TYP. MAX. MIN. TYP. MAX.
Data retention VCCDR1 /CE1 ≥ VCC − 0.2 V, 2.0 5.5 2.0 5.5 V
supply voltage CE2 ≥ VCC − 0.2 V
VCCDR2 CE2 ≤ 0.2 V 2.0 5.5 2.0 5.5
Data retention ICCDR1 VCC = 3.0 V, /CE1 ≥ VCC − 0.2 V, 1 50 Note1 0.5 10 Note2
µ
A
supply current CE2 ≥ VCC − 0.2 V
ICCDR2 VCC = 3.0 V, CE2 ≤ 0.2 V 1 50 Note1 0.5 10 Note2
Chip deselection tCDR 00ns
to data retention
mode
Operation tR55ms
recovery time
Notes 1. 15
µ
A (TA ≤ 40 °C)
2. 3
µ
A (TA ≤ 40 °C)
Data Sheet M11657EJBV0DS 19
µ
PD431000A
Data Retention Timing Chart
(1) /CE1 Controlled
V
IH
(MIN.)
V
CCDR
(MIN.)
V
IL
(MAX.)
V
CC
/CE1
/CE1 ≥ V
CC
– 0.2 V
GND
4.5 V
Note
t
CDR
Data retention mode t
R
Note A version : 3.0 V, B version : 2.7 V
Remark On the data retention mode by controlling /CE1, the input level of CE2 must be CE2 ≥ VCC − 0.2 V or CE2
≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state.
(2) CE2 Controlled
V
IH
(MIN.)
V
CCDR
(MIN.)
V
IL
(MAX.)
V
CC
CE2
CE2 ≤ 0.2 V
GND
4.5 V
Note
t
CDR
Data retention mode t
R
Note A version : 3.0 V, B version : 2.7 V
Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE, /OE) can be in
high impedance state.
Data Sheet M11657EJBV0DS
20
µ
PD431000A
Package Drawings
32-PIN PLASTIC DIP (15.24mm(600))
NOTES
1. Each lead centerline is located within 0.25 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A 40.64 MAX.
B 1.27 MAX.
C 2.54 (T.P.)
D 0.50±0.10
F 1.1 MIN.
G 3.2±0.3
J 5.08 MAX.
K 15.24 (T.P.)
M 0.25
N 0.25
H 0.51 MIN.
I 4.31 MAX.
L 13.2+0.10
−0.05
2. Item "K" to center of leads when formed parallel.
P32C-100-600A-2
R 0 - 15°
P 0.9 MIN.
32 17
116
NB
I
MR
M
C
D
F
H
G
A
JK
L
P
Data Sheet M11657EJBV0DS 21
µ
PD431000A
32 17
116
S
32-PIN PLASTIC SOP (13.34 mm (525))
NOTE
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
C0.78 MAX.
B20.61 MAX.
A
1.27 (T.P.)
E 0.15±0.05
F 2.95 MAX.
G 2.7
H 14.1±0.3
I11.3
J1.4±0.2
D 0.40+0.10
−0.05
M0.12
N0.10
L 0.8±0.2
K 0.20+0.10
−0.05
P3°+7°
−3°
P32GW-50-525A-1
K
L
G
P
DM
B
J
detail of lead end
SN
A
H
I
M
F
E
C
Data Sheet M11657EJBV0DS
22
µ
PD431000A
NOTES
32-PIN PLASTIC TSOP(I) (8x20)
ITEM MILLIMETERS
A
B
C
E
I
8.0±0.1
0.5 (T.P.)
0.1±0.05
0.45 MAX.
K
1.2 MAX.
18.4±0.1
0.145±0.05
F
0.10M
D 0.22±0.05
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
R
L
0.97±0.08G
L 0.5
0.10N
P 20.0±0.2
Q3°+5°
−3°
0.25R
S32GZ-50-KJH1-2
S 0.60±0.15
J 0.8±0.2
G
F
ES
Q
detail of lead end
1
16
32
17
SN
SC
DM
M
B
A
P
K
I J
Data Sheet M11657EJBV0DS 23
µ
PD431000A
NOTES
32-PIN PLASTIC TSOP(I) (8x20)
ITEM MILLIMETERS
A
B
C
E
I
8.0±0.1
0.5 (T.P.)
0.1±0.05
0.45 MAX.
K
1.2 MAX.
18.4±0.1
0.145±0.05
F
0.10M
D 0.22±0.05
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
C
R
DM
M
G
0.97±0.08G
L 0.5
0.10N
P 20.0±0.2
Q3°+5°
−3°
0.25R
S32GZ-50-KKH1-2
S 0.60±0.15
J 0.8±0.2
B
F
E
Q
S
L
detail of lead end
1
16
32
17
S
A
SN
K
I
P
J
Data Sheet M11657EJBV0DS
24
µ
PD431000A
32-PIN PLASTIC TSOP(I) (8x13.4)
NOTES
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
P32GU-50-9JH-2
B 0.45 MAX.
C 0.5 (T.P.)
detail of lead end
A 8.0±0.1
H 12.4±0.2
B
T
D 0.22±0.05
G 1.0±0.05
I 11.8±0.1
J 0.8±0.2
K
L 0.5
M 0.08
N 0.08
Q 0.1±0.05
P 13.4±0.2
S 1.2 MAX.
R3°
T 0.25
U 0.6±0.15
+5°
−3°
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
M
U
L
R
Q
S
DM
C
G
J
0.145+0.025
−0.015
1
16
32
17
S
SN
K
H
P
IA
Data Sheet M11657EJBV0DS 25
µ
PD431000A
+0.025
−0.015
32-PIN PLASTIC TSOP(I) (8x13.4)
NOTES
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
P32GU-50-9KH-2
B 0.45 MAX.
C 0.5 (T.P.)
detail of lead end
A 8.0±0.1
H 12.4±0.2
T
D 0.22±0.05
G 1.0±0.05
I 11.8±0.1
J 0.8±0.2
K
L 0.5
M 0.08
N 0.08
Q 0.1±0.05
P 13.4±0.2
S 1.2 MAX.
R3°
T 0.25
U 0.6±0.15
+5°
−3°
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
U
L
R
Q
S
0.145
1
16
32
17
SN
S
B
M
DM
C
G
A
K
H
P
IJ
Data Sheet M11657EJBV0DS
26
µ
PD431000A
Recommended Soldering Conditions
The following conditions must be met when soldering conditions of the
µ
PD431000A.
For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL”
(C10535E).
Please consult with our sales offices in case other soldering process is used, or in case soldering is done under
different conditions.
Types of Surface Mount Device
µ
PD431000AGW-xxL : 32-pin PLASTIC SOP (13.34 mm (525))
µ
PD431000AGW-xxLL : 32-pin PLASTIC SOP (13.34 mm (525))
µ
PD431000AGW-Axx : 32-pin PLASTIC SOP (13.34 mm (525))
µ
PD431000AGW-Bxx : 32-pin PLASTIC SOP (13.34 mm (525))
µ
PD431000AGZ-xxL-KJH : 32-pin PLASTIC TSOP(I) (8x20) (Normal bent)
µ
PD431000AGZ-xxLL-KJH : 32-pin PLASTIC TSOP(I) (8x20) (Normal bent)
µ
PD431000AGZ-xxLL-KKH : 32-pin PLASTIC TSOP(I) (8x20) (Reverse bent)
µ
PD431000AGZ-Bxx-KJH : 32-pin PLASTIC TSOP(I) (8x20) (Normal bent)
µ
PD431000AGZ-Bxx-KKH : 32-pin PLASTIC TSOP(I) (8x20) (Reverse bent)
µ
PD431000AGU-Bxx-9JH : 32-pin PLASTIC TSOP(I) (8x13.4) (Normal bent)
µ
PD431000AGU-Bxx-9KH : 32-pin PLASTIC TSOP(I) (8x13.4) (Reverse bent)
Please consult with our sales offices.
Types of Through Hole Mount Device
µ
PD431000ACZ-xxL: 32-pin PLASTIC DIP (15.24 mm (600))
µ
PD431000ACZ-xxLL: 32-pin PLASTIC DIP (15.24 mm (600))
Soldering process Soldering conditions
Wave soldering (Only to leads) Solder temperature: 260 °C or below, Flow time: 10 seconds or below
Partial heating method Pin temperature : 300 °C or below, Time: 3 seconds or below (Per one lead)
Caution Do not jet molten solder on the surface of package.
Data Sheet M11657EJBV0DS 27
µ
PD431000A
Revision History
Edition/ Page Type of Location Description
Date This Previous revision (Previous edition -> This edition)
edition edition
11th edition/ Throughout Throughout Addition Part number
µ
PD431000AGZ-B10-KJH
April 2002
µ
PD431000AGU-B10-9JH
µ
PD431000AGU-B10-9KH
p. 2, 6, 25, 26 p. 2, 6, 25 Addition Package 32-pin PLASTIC TSOP(I) (8x13.4) (Reverse bent)
Data Sheet M11657EJBV0DS
28
µ
PD431000A
[MEMO]
Data Sheet M11657EJBV0DS 29
µ
PD431000A
[MEMO]
Data Sheet M11657EJBV0DS
30
µ
PD431000A
[MEMO]
Data Sheet M11657EJBV0DS 31
µ
PD431000A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
µ
PD431000A
M8E 00. 4
The information in this document is current as of April, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
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patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
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Customers must check the quality grade of each semiconductor product before using it in a particular
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and industrial robots
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systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
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