TC74HC1G0AP/AF TC74HC161AP/AF/AFN TC74HC162AP/AF TC74HC163AP/AF/AFN SYNGHnONOUS PRESETTABLE TEe74H Ae AE TC74HCIGIAP/AE/AFN BIN TC74HCIOZAP/AE IIAP/AF/AFN BINARY,SYNCHRONOUS mi oO > 4 R a eZAP/ TC74HCIGIAP/ The TC74HC160A, 161A, 162A and 163A are high speed CMOS SYNCHRONOUS PRESETTABLE COUNTERs fabricated with silicon gate CMOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The 74HC160A/162A are BCD decade counters and the TC74HC161A/163A are 4 bit binary counters. The CLOCK input is active on the rising edge. Both LOAD and CLEAR inputs are active on low logic level. Presetting of all four [C's is synchronous to the rising edge of CLOCK. The clear function of the TC74HC162A/163A is synchro nous to CLOCK, while the TC74HC160A/161A are cleared asynchronously. Two enable inputs (ENP and ENT) and CARRY OUTPUT are provided to enable easy cascading of counters, which facilitates easy implementation of n-bit counters without using external gates. All inputs are equipped with protection circuits against 1 F (SOP 16P300) 1 P(DIP16-P-300A) i 1 FN(SOL 16-P- 150) PIN ASSIGNMENT static discharge or transient excess voltage. ai WS FEATURES. 8 & CLEAR! [] 16 Vec ; CLock2f] Fis CARRY . High Speed seeds ance see ese ceseneteetesseoune f wax=63MH2(typ. Jat Vec =5V OUTPUT * Low Power Dissipation --------- Ioc=4u A(Max. at Ta=25C 8 114 * High Noise Immunity o-+-+-++ VxiH =VML =28% Voc(Min.) pata | 84[) 130 | our- * Output Drive Capability ---.------ 10 LSTTL Loads IN} cst] M12Q | PUTS Symmetrical Output Impedance ---| Igy 1 =Ig, =4mA(Min.) oe] JI Qp * Balanced Propagation Delays ------ tpLH & tpHL ENABLE P7(] Mo ENABLE T Wide Operating Voltage Range --- Vo-(opr)=2V~6V cnost 9 LOAD Pin and Function Compatible with 74LS160~163 (TOP VIEW) {EC LOGIC SYMBOL TC74HC160A TCT7T4HCIBIA TC74HC162A TC74HC163A Gael crs Craowt0 aplielscm Tos uy ere ous er 0 or 3 scteo}Sh canny ert a . xe Ltt canny ar] ie T+15) canny 7 i exe toy x : Conant Ct canse+ ex -besraes ae aie Hibs pHa, ca Bg. po, 4 7} ot ts Mo, D ptt, HC-320TCT4HC160AP/AF *TC74HC161AP/AF/AFN TC74HC162AP/AF TC74HC163AP/AF/AFN TRUTH TABLE TC74HC160A/161A TC74HC162A/163A OUTPUTS INPUTS INPUTS FUNCTION CLR} LO |ENP|ENT| CK ]GLR| LO [ENP/ ENT) CK | Q, | Gs | Qc | Op c{xixtix]xpeypxi> x, x|fpe;ueteqe RESET TO 0 H}Le|x}x ffHje {x }]x iflajsepitelo PRESET DATA H;}H/| xX; tf] oH] H; xX) ec jf NO CHANGE NO COUNT H} Hit: xi] ff Ht wil x jf NO CHANGE NO COUNT H}/H!H! HI] f{[HjH|H!|H|f | CountuP COUNT HH, xXx x iti x{ xi xl x oo NO CHANGE NO COUNT Note X : Don't care A, B, C, O : Logic Level of Data Inputs Carry CARRY= ENT: QyQp' Qe" Qo (TC74HC160A/162A) CARRY=ENT : Qa: Qg' Qc: Qo (TC74HCO161A/163A) TIMING CHART (TC74HC160A/162A: DECADE COUNTER) CLEAR L_] LOAD 1 LJ ' A LLL, tA KLE. DON'T CARE UNTIL LOAD GOES LOW VL, DATA INPUTS YA ULL Willia ULL |e ULa__ WLLL CLOCK TALI LLL ILL LIL INL SOL SY LSJ t t j t I 1 ENABLE P i - | { t t | | ! 4. ENABLE T 1 tf \ | 1 ' ' ao ZAA SLI LIE Ly t L % ZA2A ST | Tt OUTPUTS \ ZAA S| ! ! I 2 ZAA '| Fo |] I J | { ! 1 Il 1 ee ee ee ee | ' CARRY OUTPUT 7 3 5 ; 5 7 a in COUNT 4 INHIBIT ASYNC SYNC PRESET CLEAR CLEAR (160A) (162A) HC-321TC74HC1G0AP/AF TC74HC161AP/AF/AFN TC74HC162AP/AF *TC74HC163AP/AF/AFN TIMING CHART (TC74HC161A/163A: BINARY COUNTER) CLEAR 1 | LOAD ! L_J A ZL (AZ,__ DON'T CARE UNTIL LOAD GOES LOW Liss cara | 8 ULLAL LLL LL "2 CARRY OUTPUT 13 14 15 0 1 2 INPUTS ' Lia VTA CMLL LLL LLL LLL LLL Lb D ULL LLL LLL LLL LLL LLL LLL c ht Lp NABLE P I ! ! | ENABLE T 1! | \ { ee i | \ | a ZARB Tf 1_IAu a ZAA |} fo r OUTPUTS 1 a ZAA For LL % ZAA S| ! 3 ! 1 4 4 a COUNT e INHIBIT ASYNC SYNC PRESET CLEAR CLEAR (161A) (163A) HC-322TC74HC160AP/AF TC74HC161AP/AF/AFN TC74HC162AP/AF TC74HC163AP/AF/AFN SYSTEM DIAGRAM TC74HC160A/TC74HC162A n CLEAR ENT ENP LOAD 9 1 CARRY OUT Qs Qo 2 CLoOcK TC?74HC160A TC74HC162A *TRUTH TABLE OF INTERNAL F/F [0 Tek) R Qi a]olcKta 0 q | kixjtfeoiadxirjpey ele LiS;H! Li HLT EH LH HIS HH UAT Hil | X : Don't Care x '7L | HINO CHANGE?! L17L. HINO CHANGE HC-323TCT4HCIG0AP/AF *TC74HC161AP/AF/AFN TC74HC162AP/AF *TC74HC163AP/AF/AFN SYSTEM DIAGRAM TCIAHCIBIA/TC74HCIBIA == (Cw CLEAR Pb ENT d> 15 CARRY OUT 14 -> a, Qe oc t L i 1 J Pt t4oF gl 12 E CK Q Qc 2 cLock _po~<>_______ TCTGHCI61A, I Px KU rerans Lisa etn! Hj S| H pets XI L/H lino CHANGE! L L TL ~ TRUTH TABLE OF INTERNAL F/F D [ck at Q) Oo rp TC74HC163A CK RQ: 0 Aik } LH S| H Lik ' i i ie HH) |X: Don't Care Lb IINo chance HC-324ABSOLUTE MAXIMUM RATINGS TC74HC1G0AP/AF TC74HC161AP/AF/AFN TC74HC162AP/AF TC74HC163AP/AF/AFN PARAMETER SYMBOL VALUE UNIT Supply Voltage Range Voc -0.5~7 Vv *500mW in the range of Ta= , 0.5 ~ 40C~ 65C. From Ta=65C DC Input Voltage Vix 0-5 ~Vor 0.5 Vv to 85C a derating factor of DC Output Voltage Vout ~0.5 ~Voc+0.5 v -10mW/C shall be applied Input Diode Current lix +20 mA until 300mW. Output Diode Cdrrent lox +20 mA DC Output Current Io #25 mA DC V_-/Ground Current loc +50 mA Power Dissipation Py 500(DIP)*/180(MFP) mW Storage Temperature Tatg 65 ~150 Cc Lead Temperature 10sec TL 300 c RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL VALUE UNIT Supply Voltage Voc 2~6 Vv Input Voltage Vix 0~ Vo Vv Output Voltage Vout 0~ Ve Vv Operating Temperature Topr 40 ~ 85 c 0 ~ 1000(Voc=2.0V) Input Rise and Fall Time | tr, tr O~ 500(Voc=4.5V) ns O~ 4000 Vo-=6.0V) DC ELECTRICAL CHARACTERISTICS Ta=25C Ta=40 ~85C |, PARAMETER |SYMBOL TEST CONDITION Va | MIN] TYP. [MAX-| MIN. [MAX. UNIT _ 20/15 | - = Is | - High evel ce | CY a5 | 315| - - | sis] - |v P 6.0 | 4.2 = = 4,2 - ~ 2.0|.- To5s | - | 05 we Velage | Mi a5| ~ | - | vas] - | 135{ v P 6.0] ~ = 1.8 - 1.8 2.0) 1.9 2.0 - 1.9 - High-Level Vor Vix = Toy =" 204 A 5 5 4 ee _ * 4 _ Vv r . . . . Output Voltage VinorMi [gp =a mAT 4.5] 4.18] 4.31 | = 4.13]. fo =-5.2mA] 6.0 | 5.68 | 5,80 = 5. 63 = 2.0 ~ 0.0 0.1 - 0.1 Io = A - . . - . jeune | xy fyss, Pacmesieel = [eee] = feel, Output Voltage VnorVi. TQ =a mAT 45 | >] ~0.17) 0.26} - | 0.33 Iq. =5,2mA | 6.0 ~ 0. 18 0. 26 = 0. 33 Input Leakage Current [| Iyy Vix =Vec or GND 6.0 = ~ +0.1 = +1.0 uA Quiescent Supply Current Toc Vix =Voc or GND 6.0 = 4.0 - 40. 0 HC-325TC74HC1G0AP/AF TC74HC161AP/AF/AFN TC74HC162AP/AF :TC74HC163AP/AF/AFN TIMING REQUIREMENTS(Input t-=t=6ns) PARAMETER __ |SYMBOL| TEST CONDITION ve re UNIT Minimum Pulse Width | twan | pig. | is - Q (CLOCK) twa.) , 6.0 _ 13 16 . . 2.0 - 79 95 Minimum Pulse Width : _ (Lean) | Nw | Pe so; - | ag i Minimum Set-up Time t Fig. 2.3 e - 0 i. (LOAD, ENP, ENT) $ B.S. 50 - low 1 , . 2.0 - | 75 95 Minimum Set-up Time te Fig. 2 45 _ ! 15 19 ns (A, B,C, D) 6.0 - | oB 16 = T = Minimum Set-up Time 2.0 - yl 95 (CLEAR) ** ts | Fig.5 i: 5 | I ie 0 | 1 2.0 - ' 0 0 Minimum Hold Time th Fig. 2,3,5 4.5 - 0 0 6.0 - 0 0 Minimum Removal Time . 2.0 7 50 65 6.0 - 9 \ 2.0 ~ 1 6 5 Clock Frequency f 4.5 ~ 31 25 MHz 6.0 ~ | 36 29 AC ELECTRICAL CHARACTERISTICS(C,_=15pF, Vec=5V,.Ta=25) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. |UNIT Output Transition Time mul Fig. | - 4 8 Propagation Delay Time | tyc4; ; _ (CLOCK -Q) ta Fig. } 13 21 Propagation Delay Time t (CLOCK-CARRY) a Fig. | - 16 26 (Count Mode) pHI. Propagation Delay Time | ; - 18 30 (CLOCK-CARRY) mu | Fig. 2 ns (Preset Mode] ton ~ 20 39 Propagation Delay Time | t,.); . - (ENT-CARRY) tow | Pe: 8 0 | M Propagation Delay Time. : _ - | (CLEAR-Q)* to | Fig. 4 yw Propagation Delay Time . . \ (CLEAR-CARRY)* | ou | Fig-4 0 ; 3% Maximum Clock Frequency | fx 36 63 | = MHz * : for TC74HC1G60A/161A only * > for TC74HC162A/163A only HC-326TC74HC1G0AP/AF *TC74HC161AP/AF/AFN TC74HC162AP/AF TC74HC163AP/AF/AFN AC ELECTRICAL CHARACTERISTICS(C, =50pF , Input t-=t;=6ns) , Ta=25C Ta=40 ~85C PARAMETER SYMBOL} TEST CONDITION Voc | MIN 7 TYP. [MAX] MIN. [MAX UNIT t 2.0 - 25 75 - 95 Output Transition Time ta 4.5 - 7 15 - 19 THL 6.0 = 6 13 = 16 Propagation Delay Time | tpi; Fi 2.0 - 48 25 - 155 CLOCK -@) io ig. | 45] - 16 2 | - 31 PHL 6.0 = 14 2k - 26 Propagation Delay Time t 2.0 - 57 150 ~ 190 (CLOCK-CARRY) eu Fig. | 4.5 - 19 30 - 38 {Count Made} PHL 6.0 - 16 26 = 33 - : 2.0 - 66 175 - 220 Propagation Delay Time tou Fig. 2 45 _ 99 95 _ 44 _ | 6.0 = 19 30 = a7 (CLOCK-CARRY) 20 72 500 ~ 25H ns t 4.5 - 1 24 40 - 50 PHI. : (Preset Mode) 6.0 . _| 90 34 _ 43 Propagation Delay Time | toy Fig. 6 - | 8 O 7 1% | (ENT-CARRY) | ton 60, - | tl i7 | - 21 | Propagation Delay Time t Fig. 4 j . - " 7 " ~ PHL . . (CLEAR-Q) * 6.0 | - 17 26 - 33 | Propagation Delay Time t Fig. 4 : 7 x AP : : ol _ PHL : . (CLEAR-CARRY)* 6.0 - | 20 34 _ 43 2.0 6 18 - 5 - Maximum Clock Frequency | fyyax 4.5 31 53 - 25 - |MHz | 6.0 36 62 = 29 = Input Capacitance Cr - 5 10 - 10 F Power Dissipation Capacitance | Cpp(1) GE 1) - 34 = = = P Note(1) Cpp is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: leceps =C pp * Vacs in too When the outputs drive a capacitive load, total current consumption is the sum of Cj), and Alq which is obtained from the following formula: In case of TC74HCI60A/162A: . Con , Cop , Coe , Cp | Coo Ale: =fex+ Ver { a * 5 +0 * 0 * 10 ) In case of TC74HC161A/163A: Co: Cc Ce: Cc Cc Algc =fox* Vec (=92 + So, Soe + Sp , So ) Caa~Cap and Cco are the capacitances at QA~QD and CARRY OUT, respectively. fox is the input frequency of the CLOCK. {2) * for TCT4HCIGOA/I61A only HC-327TC74HCIG0AP/AF *TC74HC161AP/AF/AFN TC74HC162AP/AF TC74HC163AP/AF/AFN SWITCHING CHARACTERISTICS TEST WAVEFORM COUNT MODE (Fig. 1) CLEAR MODE (TC74HC160A/161A) (Fig. 4 tem bt 9. 4) Vec Vec J CLEAR / CLOCK 50% fom \ K som GNO GNO fren tyne ew | Fe i {ox Vou Vee 50% 50% 50% CARRY 10% 10% Vow CLOCK GNno bem foun fone. Von a. 50% CARRY fone Var PRESET MODE en v LOAD ce 50% GND CLEAR MODE (TC74HC162A/163A) 4 (Fig. 5) /. Vee A~D CLEAR 50% GNO Vee Vee CLOCK GNO GND tore boi Vv Vo Q o a. " CARRY 50% CARRY tf Vou Vou CASCADE MODE (Fig. 6) COUNT ENABLE MODE (Fig. 3) (Fix Maximum Count) Vee . Vee ENP f 50% 50% ENT } K ENT GND GNO CLOCK Veco Vou 50% 50% CARRY Vv GNO oo Oo ton Tore Vou Vou HC-328TC74HC160AP/AF -TC74HC161AP/AF/AFN TC74HC162AP/AF TC74HC163AP/AF/AFN TYPICAL APPLICATION PARALLEL CARRY N-BIT COUNTER H : COUNT . UL: DISABLE INPUTS INPUTS INPUTS nS 7 oF Litt Jit | bit tf ib aA BOD in A BOO ta A BOO Lene ENP L_enp H= COUNT ____ egy CARRY ENT CARRY ENT CARRY| ~~ > NEXT STAGE L | DISABLE racK { CK r cK CLR Qn Qa Qc Qn CLR OQ, Oe Qc Ao CLR Qs On Qc Qn T] 7 | rt Ty 4 Trt oo. Ho _ OUTPUTS OUTPUTS OUTPUTS CREAR _ cLocK _- HC-329