1. Product profile
1.1 General description
800 mA NPN low VCEsat Breakthrough In Small Signal (BISS) Resistor-Equipped
Transistors (RET) family in small plastic packages.
[1] Also available in SOT54A and SOT54 variant packages (see Section 2).
1.2 Features
1.3 Applications
1.4 Quick reference data
PBRN113E series
NPN 800 mA, 40 V BISS RETs; R1 = 1 kΩ, R2 = 1 kΩ
Rev. 01 — 1 March 2007 Product data sheet
Table 1. Product overview
Type number Package
NXP JEITA JEDEC
PBRN113EK SOT346 SC-59A TO-236
PBRN113ES[1] SOT54 SC-43A TO-92
PBRN113ET SOT23 - TO-236AB
n800 mA output current capability nLow collector-emitter saturation voltage
VCEsat
nHigh current gain hFE nReduces component count
nBuilt-in bias resistors nReduces pick and place costs
nSimplifies circuit design n±10 % resistor ratio tolerance
nDigital application in automotive and
industrial segments
nSwitching loads
nMedium current peripheral driver
Table 2. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VCEO collector-emitter voltage open base - - 40 V
IOoutput current [1]
PBRN113EK, PBRN113ET - - 600 mA
PBRN113ES - - 800 mA
PBRN113E_SER_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 1 March 2007 2 of 17
NXP Semiconductors PBRN113E series
NPN 800 mA, 40 V BISS RETs; R1 = 1 kΩ, R2 = 1 kΩ
[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
2. Pinning information
IORM repetitive peak output current
PBRN113EK, PBRN113ET tp≤1 ms; δ≤0.33 - - 800 mA
R1 bias resistor 1 (input) 0.7 1 1.3 kΩ
R2/R1 bias resistor ratio 0.9 1 1.1
Table 2. Quick reference data
…continued
Symbol Parameter Conditions Min Typ Max Unit
Table 3. Pinning
Pin Description Simplified outline Symbol
SOT54
1 input (base)
2 output (collector)
3 GND (emitter)
SOT54A
1 input (base)
2 output (collector)
3 GND (emitter)
SOT54 variant
1 input (base)
2 output (collector)
3 GND (emitter)
SOT23; SOT346
1 input (base)
2 GND (emitter)
3 output (collector)
001aab347
1
2
3
006aaa145
2
3
1R1
R2
001aab348
1
2
3
006aaa145
2
3
1R1
R2
001aab447
1
2
3
006aaa145
2
3
1R1
R2
006aaa144
12
3
sym007
3
2
1R1
R2
PBRN113E_SER_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 1 March 2007 3 of 17
NXP Semiconductors PBRN113E series
NPN 800 mA, 40 V BISS RETs; R1 = 1 kΩ, R2 = 1 kΩ
3. Ordering information
[1] Also available in SOT54A and SOT54 variant packages (see Section 2 and Section 9).
4. Marking
[1] * = -: made in Hong Kong
* = p: made in Hong Kong
* = t: made in Malaysia
* = W: made in China
5. Limiting values
Table 4. Ordering information
Type number Package
Name Description Version
PBRN113EK SC-59A plastic surface-mounted package; 3 leads SOT346
PBRN113ES[1] SC-43A plastic single-ended leaded (through hole) package;
3 leads SOT54
PBRN113ET - plastic surface-mounted package; 3 leads SOT23
Table 5. Marking codes
Type number Marking code[1]
PBRN113EK G1
PBRN113ES N113ES
PBRN113ET *7G
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCBO collector-base voltage open emitter - 40 V
VCEO collector-emitter voltage open base - 40 V
VEBO emitter-base voltage open collector - 10 V
VIinput voltage
positive - +10 V
negative - −10 V
IOoutput current
PBRN113EK, PBRN113ET [1] - 600 mA
[2][3] - 700 mA
PBRN113ES [1] - 800 mA
IORM repetitive peak output current
PBRN113EK, PBRN113ET tp≤1 ms; δ≤0.33 - 800 mA
PBRN113E_SER_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 1 March 2007 4 of 17
NXP Semiconductors PBRN113E series
NPN 800 mA, 40 V BISS RETs; R1 = 1 kΩ, R2 = 1 kΩ
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm2.
[3] Device mounted on a ceramic PCB, Al2O3, standard footprint.
Ptot total power dissipation Tamb ≤25 °C
PBRN113EK, PBRN113ET [1] - 250 mW
[2] - 370 mW
[3] - 570 mW
PBRN113ES [1] - 700 mW
Tjjunction temperature - 150 °C
Tamb ambient temperature −65 +150 °C
Tstg storage temperature −65 +150 °C
(1) Ceramic PCB, Al2O3, standard footprint
(2) FR4 PCB, mounting pad for collector 1 cm2
(3) FR4 PCB, standard footprint
Fig 1. Power derating curves for SOT23 (TO-236AB) and SOT346 (SC-59A/TO-236)
Table 6. Limiting values
…continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Tamb (°C)
−75 17512525 75−25
006aaa998
200
400
600
Ptot
(mW)
0
(1)
(2)
(3)
PBRN113E_SER_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 1 March 2007 5 of 17
NXP Semiconductors PBRN113E series
NPN 800 mA, 40 V BISS RETs; R1 = 1 kΩ, R2 = 1 kΩ
6. Thermal characteristics
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm2.
[3] Device mounted on a ceramic PCB, Al2O3, standard footprint.
FR4 PCB, standard footprint
Fig 2. Power derating curve for SOT54 (SC-43A/TO-92)
Tamb (°C)
−75 17512525 75−25
006aaa999
200
600
400
800
Ptot
(mW)
0
Table 7. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-a) thermal resistance from junction
to ambient in free air
PBRN113EK, PBRN113ET [1] - - 500 K/W
[2] - - 338 K/W
[3] - - 219 K/W
PBRN113ES [1] - - 179 K/W
Rth(j-sp) thermal resistance from junction
to solder point
PBRN113EK, PBRN113ET - - 105 K/W
PBRN113E_SER_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 1 March 2007 6 of 17
NXP Semiconductors PBRN113E series
NPN 800 mA, 40 V BISS RETs; R1 = 1 kΩ, R2 = 1 kΩ
FR4 PCB, standard footprint
Fig 3. Transient thermal impedance from junction to ambient as a function of pulse duration for
SOT23 (TO-236AB) and SOT346 (SC-59A/TO-236); typical values
FR4 PCB, mounting pad for collector 1 cm2
Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration for
SOT23 (TO-236AB) and SOT346 (SC-59A/TO-236); typical values
006aab000
10
1
102
103
Zth(j-a)
(K/W)
10−1
10−51010−2
10−4102
10−1tp (s)
10−3103
1
0.75
0.50 0.33
0.20
0.01
0.10
0.05
0.02
0
δ = 1
006aab001
10
1
102
103
Zth(j-a)
(K/W)
10−1
10−51010−2
10−4102
10−1tp (s)
10−3103
1
0.75
0.50 0.33
0.20
0.01
0.10
0.05
0.02
0
δ = 1
PBRN113E_SER_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 1 March 2007 7 of 17
NXP Semiconductors PBRN113E series
NPN 800 mA, 40 V BISS RETs; R1 = 1 kΩ, R2 = 1 kΩ
Ceramic PCB, Al2O3, standard footprint
Fig 5. Transient thermal impedance from junction to ambient as a function of pulse duration for
SOT23 (TO-236AB) and SOT346 (SC-59A/TO-236); typical values
FR4 PCB, standard footprint
Fig 6. Transient thermal impedance from junction to ambient as a function of pulse duration for
SOT54 (SC-43A/TO-92); typical values
006aab002
10
1
102
103
Zth(j-a)
(K/W)
10−1
10−51010−2
10−4102
10−1tp (s)
10−3103
1
0.75
0.50 0.33
0.20
0.01
0.10
0.05
0.02
0
δ = 1
006aab003
10−51010−2
10−4102
10−1tp (s)
10−3103
1
102
10
103
Zth(j-a)
(K/W)
1
0.75
0.50 0.33
0.20
0.01
0.10
0.05
0.02
0
δ = 1
PBRN113E_SER_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 1 March 2007 8 of 17
NXP Semiconductors PBRN113E series
NPN 800 mA, 40 V BISS RETs; R1 = 1 kΩ, R2 = 1 kΩ
7. Characteristics
[1] Pulse test: tp≤300 µs; δ≤0.02.
Table 8. Characteristics
T
amb
=25
°
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
ICBO collector-base cut-off
current VCB =30V;
IE=0A - - 100 nA
ICEO collector-emitter cut-off
current VCE =30V;
IB=0A - - 0.5 µA
IEBO emitter-base cut-off
current VEB =5V;
IC=0A --4mA
hFE DC current gain VCE =5V;
IC=50mA 40 75 -
VCE =5V;
IC= 300 mA [1] 180 300 -
VCE =5V;
IC= 600 mA [1] 250 400 -
VCE =5V;
IC= 800 mA [1] 270 420 -
VCEsat collector-emitter
saturation voltage IC= 50 mA;
IB= 2.5 mA - 2535mV
IC= 200 mA;
IB=10mA - 6085mV
IC= 500 mA;
IB=10mA [1] - 160 220 mV
IC= 600 mA;
IB=6mA [1] - 320 550 mV
IC= 800 mA;
IB=8mA [1] - 0.68 1.15 V
VI(off) off-state input voltage VCE =5V;
IC= 100 µA0.6 1 1.5 V
VI(on) on-state input voltage VCE = 0.3 V;
IC=20mA 1 1.3 1.8 V
R1 bias resistor 1 (input) 0.7 1 1.3 kΩ
R2/R1 bias resistor ratio 0.9 1 1.1
Cccollector capacitance VCB =10V;
IE=i
e=0A;
f=1MHz
-7-pF
PBRN113E_SER_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 1 March 2007 9 of 17
NXP Semiconductors PBRN113E series
NPN 800 mA, 40 V BISS RETs; R1 = 1 kΩ, R2 = 1 kΩ
VCE =5V
(1) Tamb = 100 °C
(2) Tamb =25°C
(3) Tamb =−40 °C
IC/IB=20
(1) Tamb = 100 °C
(2) Tamb =25°C
(3) Tamb =−40 °C
Fig 7. DC current gain as a function of collector
current; typical values Fig 8. Collector-emitter saturation voltage as a
function of collector current; typical values
IC/IB=50
(1) Tamb = 100 °C
(2) Tamb =25°C
(3) Tamb =−40 °C
IC/IB= 100
(1) Tamb = 100 °C
(2) Tamb =25°C
(3) Tamb =−40 °C
Fig 9. Collector-emitter saturation voltage as a
function of collector current; typical values Fig 10. Collector-emitter saturation voltage as a
function of collector current; typical values
006aab004
IC (mA)
10−1103
102
110
1
10
102
103
hFE
10−1
(1)
(2)
(3)
006aab005
IC (mA)
10 103
102
10−1
VCEsat
(V)
10−2
(1)
(2)
(3)
IC (mA)
10 103
102
006aab006
10−1
1
VCEsat
(V)
10−2
(1)
(2)
(3)
IC (mA)
10 103
102
006aab007
10−1
1
VCEsat
(V)
10−2
(1)
(2)
(3)
PBRN113E_SER_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 1 March 2007 10 of 17
NXP Semiconductors PBRN113E series
NPN 800 mA, 40 V BISS RETs; R1 = 1 kΩ, R2 = 1 kΩ
VCE = 0.3 V
(1) Tamb =−40 °C
(2) Tamb =25°C
(3) Tamb = 100 °C
VCE =5V
(1) Tamb =−40 °C
(2) Tamb =25°C
(3) Tamb = 100 °C
Fig 11. On-state input voltage as a function of collector
current; typical values Fig 12. Off-state input voltage as a function of collector
current; typical values
006aab008
IC (mA)
10−1103
102
110
1
10
VI(on)
(V)
10−1
(1)
(3)
(2)
006aab009
IC (mA)
10−1102
101
1
10
VI(off)
(V)
10−1
(1)
(3)
(2)
PBRN113E_SER_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 1 March 2007 11 of 17
NXP Semiconductors PBRN113E series
NPN 800 mA, 40 V BISS RETs; R1 = 1 kΩ, R2 = 1 kΩ
8. Package outline
Fig 13. Package outline SOT346 (SC-59A/TO-236) Fig 14. Package outline SOT54 (SC-43A/TO-92)
Fig 15. Package outline SOT54A Fig 16. Package outline SOT54 variant
Fig 17. Package outline SOT23 (TO-236AB)
04-11-11Dimensions in mm
3.0
2.5 1.7
1.3
0.26
0.10
12
3
1.9
0.50
0.35
1.3
1.0
3.1
2.7
0.6
0.2
04-11-16Dimensions in mm
5.2
5.0 14.5
12.7
4.8
4.4
4.2
3.6 0.45
0.38
0.48
0.40
1.27 2.54
3
2
1
04-06-28Dimensions in mm
5.2
5.0 14.5
12.7
4.8
4.4
4.2
3.6 0.45
0.38
0.48
0.40
2.54
5.08
3 max
3
2
1
05-01-10Dimensions in mm
5.2
5.0 14.5
12.7
4.8
4.4
4.2
3.6
0.45
0.38
0.48
0.40
1.27
1.27
2.54
2.5
max
3
2
1
04-11-04Dimensions in mm
0.45
0.15
1.9
1.1
0.9
3.0
2.8
2.5
2.1 1.4
1.2
0.48
0.38 0.15
0.09
12
3
PBRN113E_SER_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 1 March 2007 12 of 17
NXP Semiconductors PBRN113E series
NPN 800 mA, 40 V BISS RETs; R1 = 1 kΩ, R2 = 1 kΩ
9. Packing information
[1] For further information and the availability of packing methods, see Section 13.
10. Soldering
Table 9. Packing methods
The indicated -xxx are the last three digits of the 12NC ordering code.
[1]
Type number Package Description Packing quantity
3000 5000 10000
PBRN113EK SOT346 4 mm pitch, 8 mm tape and reel -115 - -135
PBRN113ES SOT54 bulk, straight leads - -412 -
SOT54A tape and reel, wide pitch - - -116
tape ammopack, wide pitch - - -126
SOT54 variant bulk, delta pinning - -112 -
PBRN113ET SOT23 4 mm pitch, 8 mm tape and reel -215 - -235
Fig 18. Reflow soldering footprint SOT346 (SC-59A/TO-236)
solder lands
solder paste
solder resist
occupied area Dimensions in mm
sot346
1.00
0.70
(3x)
1.55
2.60
3.40
0.95
3.15
3
12
1.20
0.60 (3x)
0.70 (3x)
3.30
0.95
2.90
PBRN113E_SER_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 1 March 2007 13 of 17
NXP Semiconductors PBRN113E series
NPN 800 mA, 40 V BISS RETs; R1 = 1 kΩ, R2 = 1 kΩ
Fig 19. Wave soldering footprint SOT346 (SC-59A/TO-236)
Fig 20. Reflow soldering footprint SOT23 (TO-236AB)
sot346
4.605.20
2.80
4.70
12
3
1.20
3.40
1.20 (2x)
preferred transport direction during soldering
solder lands
solder resist
occupied area
Dimensions in mm
solder resist
occupied area
solder lands
solder paste
Dimensions in mm
sot023
1.00
0.60
(3x)
1.30
12
3
2.50
3.00
0.85
2.70
2.90
0.50 (3x)
0.60 (3x)
3.30
0.85
PBRN113E_SER_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 1 March 2007 14 of 17
NXP Semiconductors PBRN113E series
NPN 800 mA, 40 V BISS RETs; R1 = 1 kΩ, R2 = 1 kΩ
Fig 21. Wave soldering footprint SOT23 (TO-236AB)
sot023
4.004.60
2.80
4.50
1.20
3.40
3
21
1.20 (2x)
preferred transport direction during soldering
Dimensions in mm
solder resist
occupied area
solder lands
PBRN113E_SER_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 1 March 2007 15 of 17
NXP Semiconductors PBRN113E series
NPN 800 mA, 40 V BISS RETs; R1 = 1 kΩ, R2 = 1 kΩ
11. Revision history
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PBRN113E_SER_1 20070301 Product data sheet - -
PBRN113E_SER_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 1 March 2007 16 of 17
NXP Semiconductors PBRN113E series
NPN 800 mA, 40 V BISS RETs; R1 = 1 kΩ, R2 = 1 kΩ
12. Legal information
12.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
12.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
12.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
12.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
13. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors PBRN113E series
NPN 800 mA, 40 V BISS RETs; R1 = 1 kΩ, R2 = 1 kΩ
© NXP B.V. 2007. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 1 March 2007
Document identifier: PBRN113E_SER_1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
14. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 3
4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 5
7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 8
8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
9 Packing information. . . . . . . . . . . . . . . . . . . . . 12
10 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
12.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
12.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
12.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
13 Contact information. . . . . . . . . . . . . . . . . . . . . 16
14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
