Sample & Buy Product Folder Support & Community Tools & Software Technical Documents Reference Design LM25101 SNVS859C - JULY 2012 - REVISED SEPTEMBER 2016 LM25101 3-A, 2-A, and 1-A 80-V Half-Bridge Gate Drivers 1 Features 3 Description * * * The LM25101 high-voltage gate driver is designed to drive both the high-side and the low-side N-Channel MOSFETs in a synchronous buck or a half-bridge configuration. The A version provides a full 3-A of gate drive while the B and C versions provide 2-A and 1-A, respectively. The outputs are independently controlled with TTL input thresholds. An integrated high voltage diode is provided to charge the high-side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from the control logic to the high-side gate driver. Undervoltage lockout is provided on both the low-side and the highside power rails. 1 * * * * * * Independent High and Low Driver Logic Inputs Bootstrap Supply Voltage up to 100-V DC Drives Both a High-Side and Low-Side N-Channel MOSFETs Fast Propagation Times (25 ns Typical) Drives 1000-pF Load With 8-ns Rise and Fall Times Excellent Propagation Delay Matching (3 ns Typical) Supply Rail Undervoltage Lockout Low Power Consumption Pin Compatible With HIP2100 and HIP2101 These devices are available in the standard 8-pin SOIC, 8-pin SO-PowerPAD, 8-pin WSON, 10-pin WSON, and 8-pin MSOP PowerPAD packages. 2 Applications * * * * * * * Motor-Controlled Drivers Half and Full Bridge Power Converters Synchronous Buck Converters Two Switch Forward Power Converters Forward With Active Clamp Converters 48-V Server Power Solar DC-DC and DC-AC Converters Device Information(1) PART NUMBER LM25101 PACKAGE BODY SIZE (NOM) MSOP PowerPAD (8) 3 mm x 3 mm WSON (8) 4 mm x 4 mm WSON (10) 4 mm x 4 mm SO PowerPAD (8) 3.9 mm x 4.89 mm SOIC (8) 3.91 mm x 4.9 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Application Diagram Optional external fast recovery diode VIN Anti-Parallel Diode (Optional) VCC RBOOT DBOOT HB RGATE HO VDD VDD CBOOT 0.1F PWM Controller HI OUT1 HS T1 LM25101 RGATE LI OUT2 LO 1.0F VSS Copyright (c) 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM25101 SNVS859C - JULY 2012 - REVISED SEPTEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Options....................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 4 5 5 5 6 7 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Detailed Description ............................................ 12 8.1 Overview ................................................................. 12 8.2 Functional Block Diagram ....................................... 12 8.3 Feature Description................................................. 12 8.4 Device Functional Modes........................................ 13 9 Application and Implementation ........................ 14 9.1 Application Information............................................ 14 9.2 Typical Application .................................................. 14 10 Power Supply Recommendations ..................... 16 11 Layout................................................................... 17 11.1 Layout Guidelines ................................................. 17 11.2 Layout Example .................................................... 18 12 Device and Documentation Support ................. 19 12.1 12.2 12.3 12.4 12.5 Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 19 19 19 19 19 13 Mechanical, Packaging, and Orderable Information ........................................................... 19 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (March 2013) to Revision C Page * Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1 * Added Thermal Information table ........................................................................................................................................... 5 Changes from Original (March 2013) to Revision A * 2 Page Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1 Submit Documentation Feedback Copyright (c) 2012-2016, Texas Instruments Incorporated Product Folder Links: LM25101 LM25101 www.ti.com SNVS859C - JULY 2012 - REVISED SEPTEMBER 2016 5 Device Options Table 1. Input/Output Options Part Number Input Thresholds Peak Output Current LM25101A TTL 3A LM25101B TTL 2A LM25101C TTL 1A 6 Pin Configuration and Functions DGN and DDA Packages 8-Pin MSOP and SO PowerPAD Top View VDD 1 HB 2 D Package 8-Pin SOIC Top View 8 LO 7 VDD 1 8 LO VSS HB 2 7 VSS PowerPAD HO 3 6 LI HO 3 6 LI HS 4 5 HI HS 4 5 HI Not to scale Not to scale NGT Package 8-Pin WSON Top View VDD 1 HB 2 DPR Package 10-Pin WSON Top View 8 LO 7 VDD 1 10 LO VSS HB 2 9 VSS 8 LI Thermal Pad Thermal Pad HO 3 6 LI HO 3 HS 4 5 HI HS 4 7 HI NC 5 6 NC Not to scale Not to scale Submit Documentation Feedback Copyright (c) 2012-2016, Texas Instruments Incorporated Product Folder Links: LM25101 3 LM25101 SNVS859C - JULY 2012 - REVISED SEPTEMBER 2016 www.ti.com Pin Functions PIN MSOP PowerPAD NAME WSON (8) WSON (10) SO PowerPAD SOIC TYPE DESCRIPTION HB 2 2 2 2 2 PWR High-side gate driver bootstrap rail. Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal to HS. The bootstrap capacitor should be placed as close to the IC as possible. HI 5 5 7 5 5 I High-side driver control input. The LM25101 inputs have TTL type thresholds. Unused inputs should be tied to ground and not left open. HO 3 3 3 3 3 O High-side gate driver output. Connect to the gate of high-side MOSFET with a short, low inductance path. HS 4 4 4 4 4 GND High-side MOSFET source connection. Connect to the bootstrap capacitor negative terminal and the source of the high-side MOSFET. LI 6 6 8 6 6 I Low-side driver control input. The LM25101 inputs have TTL type thresholds. Unused inputs should be tied to ground and not left open. LO 8 8 10 8 8 O Low-side gate driver output. Connect to the gate of the low-side MOSFET with a short, low inductance path. NC -- -- 5, 6 -- -- -- No connection VDD 1 1 1 1 1 PWR Positive gate drive supply. Locally decouple to VSS using a low ESR and ESL capacitor located as close to the IC as possible. VSS 7 7 9 7 7 GND Ground return. All signals are referenced to this ground. PowerPAD Thermal Pad Thermal Pad PowerPAD -- -- Thermal Pad (1) Solder to the ground plane under the IC to aid in heat dissipation. (1) TI recommends that the exposed thermal pad on the bottom of the applicable packages is soldered to ground plane of the PCB, and the ground plane should extend out from beneath the IC to help dissipate heat. 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VDD to VSS -0.3 18 V HB to HS -0.3 18 V LI or HI Input -0.3 VDD + 0.3 V LO Output -0.3 VDD + 0.3 V HO Output VHS - 0.3 VHB + 0.3 V -5 100 V HS to VSS (2) HB to VSS 100 V Junction temperature, TJ 150 C 150 C Storage temperature, Tstg (1) (2) 4 -55 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. For performance limits and associated test conditions, see the Electrical Characteristics tables. In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally not exceed -1 V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur, the HS voltage must never be more negative than VDD - 15 V. For example, if VDD = 10 V, the negative transients at HS must not exceed -5 V. Submit Documentation Feedback Copyright (c) 2012-2016, Texas Instruments Incorporated Product Folder Links: LM25101 LM25101 www.ti.com SNVS859C - JULY 2012 - REVISED SEPTEMBER 2016 7.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) V(ESD) (1) (2) Electrostatic discharge All pins except 2, 3, and 4 2000 Pins 2, 3, and 4 1000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 250 Machine model (MM) 100 UNIT V The Human Body Model (HBM) is a 100-pF capacitor discharged through a 1.5-k resistor into each pin. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX 9 14 V HS -1 100 - VDD V HB VHS + 8 VHS + 14 VDD Supply voltage VDD VHS Voltage VHB Voltage HS slew rate TJ Junction temperature -40 UNIT V 50 V/ns 125 C 7.4 Thermal Information LM25101A, LM25101B THERMAL METRIC (1) LM25101C D (SOIC) DDA (SO PowerPAD) NGT (WSON) DPR (WSON) D (SOIC) DPR (WSON) DGN (MSOP PowerPAD) UNIT 8 PINS 8 PINS 8 PINS 10 PINS 8 PINS 10 PINS 8 PINS RJA Junction-to-ambient thermal resistance 108.2 46.1 38.2 37.8 111.5 39.8 54.1 C/W RJC(top) Junction-to-case (top) thermal resistance 50.6 53.5 36.3 35.8 54.2 39.1 55.9 C/W RJB Junction-to-board thermal resistance 49.1 13.8 15.2 15.0 52.3 17.1 15.1 C/W JT Junction-to-top characterization parameter 7.6 4.2 0.3 0.3 9.0 0.4 2.4 C/W JB Junction-to-board characterization parameter 48.5 13.9 15.4 15.3 51.7 17.3 15.1 C/W RJC(bot) Junction-to-case (bottom) thermal resistance -- 3.9 4.5 4.4 -- 6.1 4.6 C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright (c) 2012-2016, Texas Instruments Incorporated Product Folder Links: LM25101 5 LM25101 SNVS859C - JULY 2012 - REVISED SEPTEMBER 2016 www.ti.com 7.5 Electrical Characteristics Typical values apply for TJ = 25C only. Minimum and maximum limits apply for TJ= -40C to 125C. (1) Unless otherwise specified, VDD = VHB = 12 V, VSS = VHS = 0 V, No Load on LO or HO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.25 0.4 mA 2.0 3 mA 0.06 0.2 mA mA SUPPLY CURRENTS IDD VDD quiescent current VLI = VHI = 0 V IDDO VDD operating current f = 500 kHz IHB Total HB quiescent current VLI = VHI = 0 V IHBO Total HB operating current f = 500 kHz 1.6 3 IHBS HB to VSS current (quiescent) VHS = VHB = 100 V 0.1 10 IHBSO HB to VSS current (operating) f = 500 kHz 0.4 A mA INPUT PINS VIL Input voltage threshold VIHYS Input voltage hysteresis RI Input pulldown resistance Rising Edge 1.3 1.8 2.3 50 V mV 100 200 400 k 6.0 6.9 7.4 V UNDER VOLTAGE PROTECTION VDDR VDD rising threshold VDDH VDD threshold hysteresis VHBR HB rising threshold VHBH HB threshold hysteresis 0.5 5.7 6.6 V 7.1 0.4 V V BOOT STRAP DIODE VDL Low-current forward voltage IVDD-HB = 100 A 0.52 0.85 V VDH High-current forward voltage IVDD-HB = 100 mA 0.8 1 V RD Dynamic resistance IVDD-HB = 100 mA 1.0 1.65 A version 0.12 0.25 B version 0.16 0.4 C version 0.28 0.65 A version 0.24 0.45 B version 0.28 0.60 C version 0.60 1.10 A version 3 B version 2 C version 1 A version 3 B version 2 C version 1 LO AND HO GATE DRIVER VOL VOH IOHL IOLL (1) 6 Low-level output voltage High-level output voltage Peak pullup current Peak pulldown current IHO = ILO = 100 mA IHO = ILO = 100 mA VOH = VDD - VLO or VOH = VHB - VHO HO, VLO = 0 V HO, VLO = 12 V V V A A Minimum and maximum limits are 100% production tested at 25C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). Submit Documentation Feedback Copyright (c) 2012-2016, Texas Instruments Incorporated Product Folder Links: LM25101 LM25101 www.ti.com SNVS859C - JULY 2012 - REVISED SEPTEMBER 2016 7.6 Switching Characteristics Typical values apply for TJ = 25C only. Minimum and maximum limits apply for TJ= -40C to 125C. (1) Unless otherwise specified, VDD = VHB = 12 V, VSS = VHS = 0 V, No Load on LO or HO. TYP MAX tLPHL LO turnoff propagation delay PARAMETER LI falling to LO falling 22 56 ns tLPLH LO turnon propagation delay LI rising to LO rising 26 56 ns tHPHL HO turnoff propagation delay HI falling to HO falling 22 56 ns tHPLH LO turnon propagation delay HI rising to HO rising 26 56 ns tMON Delay matching LO ON and HO OFF 4 10 ns tMOFF Delay matching LO OFF and HO ON 4 10 ns tRC, tFC Either output rise and fall time CL = 1000 pF 8 tR tF TEST CONDITIONS Output rise time (3 V to 9 V) CL = 0.1 F Output fall time (3 V to 9 V) CL = 0.1 F tPW Minimum input pulse duration that changes the output tBS Bootstrap diode reverse recovery time (1) MIN A version 430 B version 570 C version 990 A version 260 B version 430 C version 715 IF = 100 mA, IR = 100 mA UNIT ns ns ns 50 ns 37 ns Minimum and maximum limits are 100% production tested at 25C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). LI LI HI tHPLH tLPLH HI tHPHL tLPHL LO LO HO HO tMON tMOFF Figure 1. Timing Diagram Submit Documentation Feedback Copyright (c) 2012-2016, Texas Instruments Incorporated Product Folder Links: LM25101 7 LM25101 SNVS859C - JULY 2012 - REVISED SEPTEMBER 2016 www.ti.com 7.7 Typical Characteristics 5.0 5.0 4.5 4.5 4.0 4.0 3.5 LM25101A 3.0 CURRENT (A) CURRENT (A) 3.5 2.5 LM25101B 2.0 LM25101A 3.0 2.5 LM25101B 2.0 1.5 1.5 1.0 1.0 LM25101C 0.5 LM25101C 0.5 0.0 0.0 7 8 9 10 11 12 13 14 7 15 8 9 10 11 12 VDD = 12V VDD = 12V 3.0 3.0 2.5 2.5 LM25101A CURRENT (A) CURRENT (A) 15 3.5 3.5 2.0 LM25101B 1.5 1.0 LM25101A 2.0 LM25101B 1.5 1.0 LM25101C 0.5 LM25101C 0.5 0 2 4 6 8 10 0.0 12 2 0 OUTPUT VOLTAGE (V) 4 8 6 10 12 OUTPUT VOLTAGE (V) Figure 5. Source Current vs Output Voltage Figure 4. Sink Current vs Output Voltage 2.3 100000 2.1 VDD = 12V CL = 4400 pF IDDO 1.9 CURRENT (mA) CURRENT (PA) 14 VDD (V) Figure 3. Peak Sinking Current vs Supply Voltage VDD (V) Figure 2. Peak Sourcing Current vs Supply Voltage 0.0 13 10000 CL = 1000 pF 1000 1.7 IHBO 1.5 1.3 1.1 CL = 0 pF 100 0.1 1 10 100 FREQUENCY (kHz) Figure 6. IDD vs Frequency 8 1000 0.9 0.7 -50 -25 0 25 50 75 100 125 150 o TEMPERATURE ( C) Figure 7. Operating Current vs Temperature Submit Documentation Feedback Copyright (c) 2012-2016, Texas Instruments Incorporated Product Folder Links: LM25101 LM25101 www.ti.com SNVS859C - JULY 2012 - REVISED SEPTEMBER 2016 Typical Characteristics (continued) 400 100000 HB = 12V, HS = 0V 350 CL = 4400 pF IDD 300 CURRENT (PA) CURRENT (PA) 10000 CL = 1000 pF 1000 CL = 0 pF 100 250 200 150 100 IHB 50 10 0 0.1 1 10 100 1000 8 9 10 11 12 13 14 15 16 VDD, VHB (V) FREQUENCY (kHz) Figure 9. Quiescent Current vs Supply Voltage Figure 8. IHB vs Frequency 350 7.30 7.20 300 7.10 IDD THRESHOLD (V) CURRENT (PA) 250 200 150 100 7.00 VDDR 6.90 6.80 6.70 6.60 VHBR 6.50 50 0 -50 6.40 IHB -25 0 25 50 75 6.30 -50 100 125 150 0 25 50 75 100 125 150 TEMPERATURE (C) TEMPERATURE (C) Figure 10. Quiescent Current vs Temperature Figure 11. Undervoltage Rising Thresholds vs Temperature 1.00E-01 0.60 T = 150C 0.55 1.00E-02 VDDH 0.50 1.00E-03 ID (A) HYSTERESIS (V) -25 0.45 T = 25C 1.00E-04 VHBH 0.40 0.30 -50 T = -40C 1.00E-05 0.35 -25 0 25 50 75 100 125 150 TEMPERATURE (oC) Figure 12. Undervoltage Threshold Hysteresis vs Temperature 1.00E-06 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VD (V) Figure 13. Bootstrap Diode Forward Voltage Submit Documentation Feedback Copyright (c) 2012-2016, Texas Instruments Incorporated Product Folder Links: LM25101 9 LM25101 SNVS859C - JULY 2012 - REVISED SEPTEMBER 2016 www.ti.com 1.92 1.92 1.91 1.91 1.90 THRESHOLD VOLTAGE (V) THRESHOLD VOLTAGE (V) Typical Characteristics (continued) Rising 1.89 1.88 1.87 1.86 Falling 1.85 1.84 1.83 1.82 1.90 1.88 1.87 1.86 1.85 1.83 1.82 1.81 1.80 -50 -25 1.80 25 50 75 Falling 1.84 1.81 0 Rising 1.89 8 100 125 150 9 10 11 12 13 14 15 16 VDD (V) TEMPERATURE (C) Figure 15. Input Threshold vs Supply Voltage Figure 14. Input Threshold vs Temperature 1.0 40 VDD = 12V 0.9 35 0.8 30 T_PLH VOH (V) DELAY (ns) 0.7 25 T_PHL LM25101C 0.6 0.5 0.4 LM25101B 0.3 LM25101A 0.2 20 0.1 15 -50 -25 0 25 50 75 0.0 -50 -25 100 125 150 25 50 75 100 125 150 TEMPERATURE (C) Figure 17. LO and HO Gate Drive: High Level Output Voltage vs Temperature TEMPERATURE (C) Figure 16. Propagation Delay vs Temperature 0.50 0 0.8 VDD = 12V IOUT = -100 mA 0.45 0.7 0.40 0.6 0.30 LM25101C LM25101C VOH (V) VOL (V) 0.35 0.25 LM25101B 0.20 0.15 LM25101A 0.10 0.4 0.3 0 25 50 75 100 125 150 LM25101A 0.1 TEMPERATURE (C) Figure 18. LO and HO Gate Drive: Low Level Output Voltage vs Temperature 10 LM25101B 0.2 0.05 0.00 -50 -25 0.5 Submit Documentation Feedback 7 8 9 10 11 12 13 14 15 VDD (V) Figure 19. LO and HO Gate Drive: Output High Voltage vs Supply Voltage Copyright (c) 2012-2016, Texas Instruments Incorporated Product Folder Links: LM25101 LM25101 www.ti.com SNVS859C - JULY 2012 - REVISED SEPTEMBER 2016 Typical Characteristics (continued) 0.35 IOUT = 100 mA VOL (V) 0.30 LM25101C 0.25 0.20 LM25101B 0.15 LM25101A 0.10 7 8 9 10 11 12 13 14 15 VDD (V) Figure 20. LO and HO Gate Drive: Output Low Voltage vs Supply Voltage Submit Documentation Feedback Copyright (c) 2012-2016, Texas Instruments Incorporated Product Folder Links: LM25101 11 LM25101 SNVS859C - JULY 2012 - REVISED SEPTEMBER 2016 www.ti.com 8 Detailed Description 8.1 Overview To operate fast switching of power MOSFETs at high switching frequencies and to reduce associated switching losses, a powerful gate driver is employed between the PWM output of controller and the gates of the power semiconductor devices. Also, gate drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching devices. With the advent of digital power, this situation is often encountered because the PWM signal from the digital controller is often a 3.3 V logic signal which cannot effectively turn on a power switch. Level shift circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN or PNP bipolar transistors in totem-pole arrangement prove inadequate with digital power because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise (by placing the high-current driver IC physically close to the power switch), driving gate-drive transformers and controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving gate charge power losses from the controller into the driver. 8.2 Functional Block Diagram HB HO UVLO DRIVER LEVEL SHIFT HS HI VDD UVLO LO LI DRIVER VSS Copyright (c) 2016, Texas Instruments Incorporated 8.3 Feature Description 8.3.1 Start-Up and UVLO Both top and bottom drivers include UVLO protection circuitry which monitors the supply voltage (VDD) and bootstrap capacitor voltage (VHB-HS) independently. The UVLO circuit inhibits each output until sufficient supply voltage is available to turn on the external MOSFETs, and the built-in UVLO hysteresis prevents chattering during supply voltage variations. When the supply voltage is applied to the VDD pin of the LM25101, the top and bottom gates are held low until VDD exceeds the UVLO threshold, typically about 6.9 V. Any UVLO condition on the bootstrap capacitor (VHB-HS) will only disable the high-side output (HO). 12 Submit Documentation Feedback Copyright (c) 2012-2016, Texas Instruments Incorporated Product Folder Links: LM25101 LM25101 www.ti.com SNVS859C - JULY 2012 - REVISED SEPTEMBER 2016 Table 2. VDD UVLO Feature Logic Operation (1) CONDITION (1) HI LI HO LO VDD - VSS < VDDR during device start-up H L L L VDD - VSS < VDDR during device start-up L H L L VDD - VSS < VDDR during device start-up H H L L VDD - VSS < VDDR during device start-up L L L L VDD - VSS < VDDR - VDDH after device start-up H L L L VDD - VSS < VDDR - VDDH after device start-up L H L L VDD - VSS < VDDR - VDDH after device start-up H H L L VDD - VSS < VDDR - VDDH after device start-up L L L L LO VHB-HS > VHBR Table 3. VHB-HS UVLO Feature Logic Operation (1) CONDITION (1) HI LI HO VHBHS < VHBR during device start-up H L L L VHB-HS < VHBR during device start-up L H L H VHB-HS < VHBR during device start-up H H L H VHB-HS < VHBR during device start-up L L L L VHB-HS < VHBR - VHBH after device start-up H L L L VHB-HS < VHBR - VHBH after device start-up L H L H VHB-HS < VHBR - VHBH after device start-up H H L H VHB-HS < VHBR - VHBH after device start-up L L L L VDD>VDDR 8.3.2 Level Shift The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to the switch node (HS). The level shift allows control of the HO output which is referenced to the HS pin and provides excellent delay matching with the low-side driver. 8.3.3 Output Stages The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance, and high peak current capability of both outputs allow for efficient switching of the power MOSFETs. The lowside output stage is referenced to VSS and the high-side is referenced to HS. 8.4 Device Functional Modes The device operates in normal mode and UVLO mode. See Start-Up and UVLO for more information on UVLO operation mode. In normal mode when the VDD and VHB-HS are above UVLO threshold, the output stage is dependent on the states of the HI and LI pins. Unused inputs should be tied to ground and not left open. Table 4. INPUT and OUTPUT Logic Table (1) (2) HI LI HO (1) LO (2) L L L L H L H L H L H L H H H H HO is measured with respect to the HS pin. LO is measured with respect to the VSS pin. Submit Documentation Feedback Copyright (c) 2012-2016, Texas Instruments Incorporated Product Folder Links: LM25101 13 LM25101 SNVS859C - JULY 2012 - REVISED SEPTEMBER 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The LM25101 is a high voltage gate driver designed to drive both the high-side and low-side N-Channel MOSFETs in a half or full bridge configuration or in a synchronous buck circuit. The floating high side driver is capable of operating with supply voltages up to 100 V. This allows for N-Channel MOSFETs control in halfbridge, full-bridge, push-pull, two switch forward, and active clamp topologies. The outputs are independently controlled. Each channel is controlled by its respective input pins (HI and LI), allowing full and independent flexibility to control the state (ON and OFF) of the output. 9.2 Typical Application Optional external fast recovery diode VIN Anti-Parallel Diode (Optional) VCC RBOOT DBOOT HB RGATE HO VDD VDD CBOOT 0.1F PWM Controller HI OUT1 HS T1 LM25101 RGATE LI OUT2 LO 1.0F VSS Copyright (c) 2016, Texas Instruments Incorporated Figure 21. Application Diagram 9.2.1 Design Requirements For this design example, use the parameters listed in Table 5 as the input parameters. Table 5. Design Parameters PARAMETER 14 EXAMPLE VALUE Gate driver LM25101 (C version) MOSFET CSD19534KCS VDD 10 V QG 17 nC fSW 500 kHz Submit Documentation Feedback Copyright (c) 2012-2016, Texas Instruments Incorporated Product Folder Links: LM25101 LM25101 www.ti.com SNVS859C - JULY 2012 - REVISED SEPTEMBER 2016 9.2.2 Detailed Design Procedure 9.2.2.1 Selecting External Gate Driver Resistor External gate driver resistor (RGATE) is sized to reduce ringing caused by parasitic inductances and capacitances and also to limit the current coming out of the gate driver. Peak HO pullup current is calculated using Equation 1. IOHH RHOH VDD VDH RGate RGFET _ Int 10V 1.0V | 0.5A 1.1V / 100mA 4.7: 2.2: where * * * * * IOHHis the peak pullup current VDHis the bootstrap diode forward voltage drop RHOHis the gate driver internal HO pullup resistance (1) RGateis the external gate drive resistance R(GFET_Int) is the MOSFET internal gate resistance, provided by the transistor data sheet (1) Similarly, Peak HO pulldown current is calculated using Equation 2. VDD VDH IOLH RHOL RGate RGFET_Int where * RHOL is the HO pulldown resistance (2) Peak LO pullup current is calculated using Equation 3. VDD IOHL RLOH RGate RGFET_Int where * RLOH is the LO pullup resistance (3) Peak LO pulldown current is calculated using Equation 4. VDD IOLL RLOL RGate RFET_Int where * RLOL is the LO pulldown resistance (4) If the application requires fast turnoff, an anti-paralleled diode on RGate may be used to bypass the external gate drive resistor and speed up the turnoff transition. (1) This value is either provided directly by the data sheet or is estimated from the testing conditions using RHOH = VOHH / IHO. Submit Documentation Feedback Copyright (c) 2012-2016, Texas Instruments Incorporated Product Folder Links: LM25101 15 LM25101 SNVS859C - JULY 2012 - REVISED SEPTEMBER 2016 www.ti.com 9.2.3 Application Curves Figure 22 and Figure 23 show the rising and falling time and turnon and turnoff propagation delay testing waveform at room temperature. Each channel (HI, LI, HO, LO) is labeled and displayed on the left hand of the waveform. The HI and LI pins are shorted together for these test waveforms. Therefore, the propagation delay matching between the channels can be measured and inspected. CL = 1 nF VDD = 12 V fSW = 500 kHz Figure 22. Rising Time and Turnon Propagation Delay CL = 1 nF VDD = 12 V fSW = 500 kHz Figure 23. Falling Time and Turnoff Propagation Delay 10 Power Supply Recommendations The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply voltage (VDD), which can be roughly calculated using Equation 5. PDGATES = 2 x f x CL x VDD2 (5) There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and HO outputs. Figure 24 shows the measured gate driver power dissipation versus frequency and load capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the power losses driving the output loads and agrees well with Equation 5. Figure 24 can be used to approximate the power losses due to the gate drivers. The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads require more energy to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to the half bridge result in higher reverse recovery losses. Figure 25 was generated based on calculations and lab measurements of the diode recovery time and current under several operating conditions and can be used to approximate the diode power dissipation. The total IC power dissipation can be estimated from these plots by summing the gate drive losses with the bootstrap diode losses for the intended application. 16 Submit Documentation Feedback Copyright (c) 2012-2016, Texas Instruments Incorporated Product Folder Links: LM25101 LM25101 www.ti.com SNVS859C - JULY 2012 - REVISED SEPTEMBER 2016 1.000 0.100 CL = 4400 pF CL = 4400 pF POWER (W) POWER (W) 0.100 CL = 1000 pF 0.010 CL = 0 pF 0.010 CL = 0 pF 0.001 0.1 1.0 10.0 100.0 1000.0 0.001 SWITCHING FREQUENCY (kHz) VDD = 12 V Neglecting Diode Losses Figure 24. Gate Driver Power Dissipation (LO + HO) 1 10 100 1000 SWITCHING FREQUENCY (kHz) VIN = 50 V Figure 25. Diode Power Dissipation 11 Layout 11.1 Layout Guidelines The optimum performance of high and low-side gate drivers cannot be achieved without following certain guidelines during circuit-board layout. * Low ESR and ESL capacitors must be connected close to the IC, between the VDD and VSS pins and between the HB and HS pins to support the high peak currents being drawn from VDD during start-up of the external MOSFET. * To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be connected between the MOSFET drain and ground (VSS). * To avoid large negative transients on the switch node (HS pin), the parasitic inductances must be minimized in the source of the top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier). * Grounding Considerations: - The first priority in designing grounding connections is to confine to a minimal physical area the high peak currents that charge and discharge the MOSFET gate. This decreases the loop inductance and minimizes noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as possible to the gate driver. - The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground referenced bypass capacitor, and low-side MOSFET body diode. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation. Figure 26 shows a recommended layout pattern for the driver. If possible a single layer placement is preferred. Submit Documentation Feedback Copyright (c) 2012-2016, Texas Instruments Incorporated Product Folder Links: LM25101 17 LM25101 SNVS859C - JULY 2012 - REVISED SEPTEMBER 2016 www.ti.com 11.2 Layout Example Recommended Layout for Driver IC and Passives VDD LO VSS HB SO PowerPAD LI HS HI LO D N To Hi-Side FET Multi Layer Option G HO HS HO Single Layer Option HO To Low-Side FET Figure 26. Recommended Layout Pattern 18 Submit Documentation Feedback Copyright (c) 2012-2016, Texas Instruments Incorporated Product Folder Links: LM25101 LM25101 www.ti.com SNVS859C - JULY 2012 - REVISED SEPTEMBER 2016 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2012-2016, Texas Instruments Incorporated Product Folder Links: LM25101 19 PACKAGE OPTION ADDENDUM www.ti.com 15-Jul-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LM25101AM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L25101 AM LM25101AMR/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS & no Sb/Br) SN Level-3-260C-168 HR -40 to 125 L25101 AMR LM25101AMRX/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS & no Sb/Br) SN Level-3-260C-168 HR -40 to 125 L25101 AMR LM25101AMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L25101 AM LM25101ASD-1/NOPB ACTIVE WSON NGT 8 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 25101A1 LM25101ASD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 25101A LM25101ASDX-1/NOPB ACTIVE WSON NGT 8 4500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 25101A1 LM25101ASDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 25101A LM25101BMA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L25101 BMA LM25101BMAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L25101 BMA LM25101BSD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 25101B LM25101BSDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 25101B LM25101CMA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L25101 CMA LM25101CMAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L25101 CMA LM25101CMY/NOPB ACTIVE HVSSOP DGN 8 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 CMYN LM25101CMYE/NOPB ACTIVE HVSSOP DGN 8 250 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 CMYN Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 15-Jul-2020 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LM25101CMYX/NOPB ACTIVE HVSSOP DGN 8 3500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 CMYN LM25101CSD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 25101C LM25101CSDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 25101C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 15-Jul-2020 Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM25101AMRX/NOPB Package Package Pins Type Drawing SO Power PAD SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM25101AMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM25101ASD-1/NOPB WSON NGT 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM25101ASD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM25101ASDX-1/NOPB WSON NGT 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM25101ASDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM25101BMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM25101BSD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM25101BSDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM25101CMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM25101CMY/NOPB HVSSOP DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM25101CMYE/NOPB HVSSOP DGN 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM25101CMYX/NOPB HVSSOP DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM25101CSD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM25101CSDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2019 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM25101AMRX/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0 LM25101AMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM25101ASD-1/NOPB WSON NGT 8 1000 210.0 185.0 35.0 LM25101ASD/NOPB WSON DPR 10 1000 210.0 185.0 35.0 LM25101ASDX-1/NOPB WSON NGT 8 4500 367.0 367.0 35.0 LM25101ASDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0 LM25101BMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM25101BSD/NOPB WSON DPR 10 1000 210.0 185.0 35.0 LM25101BSDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0 LM25101CMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM25101CMY/NOPB HVSSOP DGN 8 1000 210.0 185.0 35.0 LM25101CMYE/NOPB HVSSOP DGN 8 250 210.0 185.0 35.0 LM25101CMYX/NOPB HVSSOP DGN 8 3500 367.0 367.0 35.0 LM25101CSD/NOPB WSON DPR 10 1000 210.0 185.0 35.0 LM25101CSDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE TM DGN0008A PowerPAD VSSOP - 1.1 mm max height SCALE 4.000 SMALL OUTLINE PACKAGE C 5.05 TYP 4.75 A 0.1 C SEATING PLANE PIN 1 INDEX AREA 6X 0.65 8 1 2X 3.1 2.9 NOTE 3 1.95 4 5 8X B 3.1 2.9 NOTE 4 0.38 0.25 0.13 C A B 0.23 0.13 SEE DETAIL A EXPOSED THERMAL PAD 4 5 0.25 GAGE PLANE 2.0 1.7 9 1.1 MAX 8 1 0 -8 0.15 0.05 0.7 0.4 DETAIL A A 20 1.88 1.58 TYPICAL 4218836/A 11/2019 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. www.ti.com EXAMPLE BOARD LAYOUT TM DGN0008A PowerPAD VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (2) NOTE 9 METAL COVERED BY SOLDER MASK (1.88) SOLDER MASK DEFINED PAD SYMM 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (3) NOTE 9 SYMM 9 (2) (1.22) 6X (0.65) 5 4 ( 0.2) TYP VIA (0.55) SEE DETAILS (4.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK OPENING METAL UNDER SOLDER MASK METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX ALL AROUND NON-SOLDER MASK DEFINED (PREFERRED) 0.05 MIN ALL AROUND SOLDER MASK DEFINED SOLDER MASK DETAILS 15.000 4218836/A 11/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. www.ti.com EXAMPLE STENCIL DESIGN TM DGN0008A PowerPAD VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (1.88) BASED ON 0.125 THICK STENCIL SYMM (R0.05) TYP 8X (1.4) 8X (0.45) 8 1 SYMM (2) BASED ON 0.125 THICK STENCIL 6X (0.65) 5 4 METAL COVERED BY SOLDER MASK (4.4) SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 9: 100% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X STENCIL THICKNESS SOLDER STENCIL OPENING 0.1 0.125 0.15 0.175 2.10 X 2.24 1.88 X 2.00 (SHOWN) 1.72 X 1.83 1.59 X 1.69 4218836/A 11/2019 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE DDA0008B PowerPAD TM SOIC - 1.7 mm max height SCALE 2.400 PLASTIC SMALL OUTLINE C 6.2 TYP 5.8 A SEATING PLANE PIN 1 ID AREA 0.1 C 6X 1.27 8 1 2X 3.81 5.0 4.8 NOTE 3 4 5 8X B 4.0 3.8 NOTE 4 0.51 0.31 0.25 1.7 MAX C A B 0.25 TYP 0.10 SEE DETAIL A 5 4 EXPOSED THERMAL PAD 3.4 2.8 0.25 GAGE PLANE 9 8 1 0 -8 0.15 0.00 1.27 0.40 DETAIL A 2.71 2.11 TYPICAL 4214849/A 08/2016 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MS-012. www.ti.com EXAMPLE BOARD LAYOUT DDA0008B PowerPAD TM SOIC - 1.7 mm max height PLASTIC SMALL OUTLINE (2.95) NOTE 9 SOLDER MASK DEFINED PAD (2.71) SOLDER MASK OPENING SEE DETAILS 8X (1.55) 1 8 8X (0.6) 9 SYMM (1.3) TYP (3.4) SOLDER MASK OPENING (4.9) NOTE 9 6X (1.27) 5 4 (R0.05) TYP METAL COVERED BY SOLDER MASK SYMM ( 0.2) TYP VIA (1.3) TYP (5.4) LAND PATTERN EXAMPLE SCALE:10X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS PADS 1-8 4214849/A 08/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). 9. Size of metal pad may vary due to creepage requirement. 10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN DDA0008B PowerPAD TM SOIC - 1.7 mm max height PLASTIC SMALL OUTLINE (2.71) BASED ON 0.125 THICK STENCIL 8X (1.55) (R0.05) TYP 1 8 8X (0.6) (3.4) BASED ON 0.125 THICK STENCIL 9 SYMM 6X (1.27) 5 4 METAL COVERED BY SOLDER MASK SYMM (5.4) SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 100% PRINTED SOLDER COVERAGE BY AREA SCALE:10X STENCIL THICKNESS SOLDER STENCIL OPENING 0.1 0.125 0.150 0.175 3.03 X 3.80 2.71 X 3.40 (SHOWN) 2.47 X 3.10 2.29 X 2.87 4214849/A 08/2016 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE NGT0008A WSON - 0.8 mm max height SCALE 3.000 PLASTIC SMALL OUTLINE - NO LEAD 4.1 3.9 A B PIN 1 INDEX AREA 4.1 3.9 C 0.8 MAX SEATING PLANE 0.05 0.00 0.08 C EXPOSED THERMAL PAD 2.6 0.05 (0.2) TYP 4 2X 2.4 5 SYMM 9 3 0.05 8 1 6X 0.8 PIN 1 ID 8X SYMM 8X 0.5 0.3 0.35 0.25 0.1 0.05 C A B C 4214935/A 08/2020 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT NGT0008A WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD (2.6) 8X (0.6) SYMM 1 8 8X (0.3) SYMM 9 (3) (1.25) 6X (0.8) 4 (R0.05) TYP 5 ( 0.2) VIA TYP (1.05) (3.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND EXPOSED METAL SOLDER MASK OPENING METAL EXPOSED METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED SOLDER MASK DETAILS 4214935/A 08/2020 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN NGT0008A WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD (0.675) SYMM 8X (0.6) METAL TYP 1 8 8X (0.3) (0.755) 9 SYMM (1.31) 6X (0.8) 5 4 (R0.05) TYP (1.15) (3.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 9: 77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4214935/A 08/2020 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com MECHANICAL DATA DPR0010A SDC10A (Rev A) www.ti.com PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. 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