SICOFI®2-µC
Two Channel Codec
Filter with PCM and
Microcontroller Interface
PEB 2266 Version 2.2
PEF 2266 Version 2.2
Hardware Reference Manual, DS 1, Feb. 2001
Wired
Communications
Never stop thinking.
Edition 2001-02-20
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2001.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
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question please contact your nearest Infineon Technologies Office.
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and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Wired
Communications
SICOFI®2-µC
Two Channel Codec
Filter with PCM and
Microcontroller Interface
PEB 2266 Version 2.2
PEF 2266 Version 2.2
Hardware Reference Manual, DS 1, Feb. 2001
Never stop thinking.
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
ABM®, AOP®, ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S,
ELIC®, FALC®54, FALC®56, FALC®-E1, FALC®-LH, IDEC®, IOM®, IOM®-1, IOM®-2,
IPAT®-2, ISAC®-P, ISAC®-S, ISAC®-S TE, ISAC®-P TE, ITAC®, IWE®, MUSAC®-A,
OCTAT®-P, QUAT®-S, SICAT®, SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4µC,
SLICOFI® are registered trademarks of Infineon Technologies AG.
ACE™, ASM™, ASP™, POTSWIRE™, QuadFALC™, SCOUT™ are trademarks of
Infineon Technologies AG.
PEB 2266
PEF 2266
Revision History: Current Version 2001-02-20 DS 1
Previous Version: Data Sheet 07.97 DS1 (V 1.1)
Delta Sheet 11.98 DS2 (V 1.4)
Errata Sheet 05.98 DS1 (V 1.4)
Page Subjects (major changes since last revision)
PEB 2266
PEF 2266
Table of Contents Page
Hardware Reference Manual 2001-02-20
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.3 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.1 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.1 DSP-based Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.2 Programming and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.1 Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.1.1 Power On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.1.2 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.2 Transmission Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.2.1 Overload Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.2.2 0 dBm0-Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.2.3 Compressor Gain Relative to Coding Law . . . . . . . . . . . . . . . . . . . . . . . .15
4.2.4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.2.5 Gain Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.2.6 Gain Tracking (Receive and Transmit) . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.2.7 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.2.8 Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.2.8.1 Group Delay, Absolute Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.2.8.2 Group Delay Distortion with Frequency . . . . . . . . . . . . . . . . . . . . . . . .19
4.2.9 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.2.10 Harmonic and Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . . .20
4.2.11 Total Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.2.12 Single Frequency Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.2.13 Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.2.14 Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.2.15 Out-of-Band Discrimination in Transmit Direction . . . . . . . . . . . . . . . . . .23
4.2.16 Out-of-Band Discrimination in Receive Direction . . . . . . . . . . . . . . . . . . .24
4.2.17 Out-of-Band Idle Channel Noise at Analog Output . . . . . . . . . . . . . . . . .25
4.2.18 Transhybrid Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.1 Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.1.1 Coupling Capacitors at the Analog Interface . . . . . . . . . . . . . . . . . . . . . .27
PEB 2266
PEF 2266
Table of Contents Page
Hardware Reference Manual 2001-02-20
5.1.2 Analog Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.2 PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.2.1 PCM Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.2.2 PCM Receive and Transmit Example . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.3 Signaling Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
5.3.1 Signaling Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
5.3.2 Debouncing Functions and Interrupt Generation . . . . . . . . . . . . . . . . . . .33
5.3.3 Clock Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5.4 Serial Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5.4.1 Serial Microcontroller Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5.4.2 Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.4.3 Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.4.4 Three-Wire Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
6 Programming Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
6.1 Programming Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
6.1.1 Register Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
6.1.2 Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
6.1.3 CRAM Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
6.2 Types of Commands and Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
7 Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
7.1 Support Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
7.1.1 Development Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
7.2 Guidelines for Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
7.2.1 Filter Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
7.3 Proposal for SICOFI®2-µC Board Design . . . . . . . . . . . . . . . . . . . . . . . . . .43
8 Electrical Characteristics and Timing Diagrams . . . . . . . . . . . . . . . . . .44
8.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
8.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
8.3 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
8.4.1 Coupling Capacitors at the Analog Interface . . . . . . . . . . . . . . . . . . . . . .46
8.5 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
8.4 Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
8.6 PCM-Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
8.6.1 Single Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
8.6.2 Double Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
8.7 Microcontroller Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
8.8 Signaling Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
8.8.1 Timing from the µC Interface to the SO/SB-pins . . . . . . . . . . . . . . . . . . .50
8.8.2 Timing from the SI/SB-pins to the µC Interface . . . . . . . . . . . . . . . . . . . .50
PEB 2266
PEF 2266
Table of Contents Page
Hardware Reference Manual 2001-02-20
9 Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
9.1 Analog Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
9.2 Digital Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
9.3 Cut-Off’s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
10 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
11 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
PEB 2266
PEF 2266
List of Figures Page
Hardware Reference Manual 2001-02-20
Figure 1 SICOFI®2-µC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Figure 2 SICOFI®2-µC Logic Symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3 Pin Configuration of SICOFI®2-µC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4 SICOFI®2-µC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 5 SICOFI®2-µC State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 6 Analog and PCM Signal Levels in A-Law Mode . . . . . . . . . . . . . . . . . .15
Figure 7 Analog and PCM Signal Levels in µ-Law Mode. . . . . . . . . . . . . . . . . . .15
Figure 8 Simplified Signal Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 9 Total Distortion Measured with Sine-Wave, Receive and Transmit. . . .20
Figure 10 Total Distortion Receive (Noise) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 11 Total Distortion Transmit (Noise) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 12 Overload Compression (µ-Law Coding, Transmit Direction) . . . . . . . . .22
Figure 13 Out-of-Band Discrimination in Transmit Direction . . . . . . . . . . . . . . . . .23
Figure 14 Analog Output: Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 15 Analog Output: Out-of-Band Idle Channel Noise . . . . . . . . . . . . . . . . . .25
Figure 16 Analog Interface to Two Subscriber Line Interface Circuits (SLICs) . . .28
Figure 17 PCM Interface Example: Location of Time Slots . . . . . . . . . . . . . . . . . .31
Figure 18 PCM Interface Example: Detail A . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 19 Signaling Example: Two Subscriber Lines. . . . . . . . . . . . . . . . . . . . . . .32
Figure 20 Serial Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 21 Example for a Two-Byte Write Access. . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 22 Example for a One-Byte Read Access . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 23 Example for a Read Access with Byte-by-Byte Transfer . . . . . . . . . . . .36
Figure 24 Bi-Directional Data Signal: DIN and DOUT Strapped Together. . . . . . .36
Figure 25 Channel-Specific and Common Coefficients . . . . . . . . . . . . . . . . . . . . .39
Figure 26 Development System with STUT 2466 Evaluation Board . . . . . . . . . . .41
Figure 27 SICOFI®2-µC Test Circuit Configuration . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 28 Proposal for a Ground Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 29 PCM Interface Timing in Single Clocking Mode. . . . . . . . . . . . . . . . . . .47
Figure 30 PCM Interface Timing in Double Clocking Mode . . . . . . . . . . . . . . . . . .48
Figure 31 Timing of the Microcontroller Interface. . . . . . . . . . . . . . . . . . . . . . . . . .49
Figure 32 Signaling Output Timing (data downstream) . . . . . . . . . . . . . . . . . . . . .50
Figure 33 Analog Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Figure 34 Digital Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Figure 35 Cut-Off’s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
PEB 2266
PEF 2266
List of Tables Page
Hardware Reference Manual 2001-02-20
Table 1 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2 Register Values and Accessibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3 Input and Output Pin Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5 Maximum Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6 Analog Voltage Levels Corresponding to 0 dBm0-Level . . . . . . . . . . . 14
Table 7 Gain Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8 Gain Deviations with Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9 Attenuation with Frequency in Transmit and Receive Direction. . . . . . 18
Table 10 Group Delay, Absolute Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11 Group Delay Distortion with Frequency . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 12 Idle Channel Noise in Transmit Direction. . . . . . . . . . . . . . . . . . . . . . . 19
Table 13 Idle Channel Noise in Receive Direction . . . . . . . . . . . . . . . . . . . . . . . 19
Table 14 Harmonic and Intermodulation Distortion. . . . . . . . . . . . . . . . . . . . . . . 20
Table 15 Signal-to-Total Distortion Ratio Measured with Sine Wave . . . . . . . . . 20
Table 16 Signal-to-Total Distortion Ratio Measured with Noise . . . . . . . . . . . . . 21
Table 17 Crosstalk Between Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 18 Out-of-Band Signals Applied to the Analog Inputs (VINx) . . . . . . . . . . 23
Table 19 Out-of-Band Signals at the Analog Outputs (VOUTx) . . . . . . . . . . . . . 24
Table 20 Transhybrid Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 21 Analog Interface Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 22 PCM Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 23 PCM Register Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 24 Signaling Interface: Pins and Functions for SLIC Interfaces . . . . . . . . 33
Table 25 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 26 Serial Microcontroller Interface: Pins and Functions . . . . . . . . . . . . . . 34
Table 27 Register Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 28 Read Access to Common Configuration Register (XR) Map . . . . . . . . 38
Table 29 Write Access to Common Configuration Register (XR) Map . . . . . . . . 38
Table 30 Channel-Specific Configuration Register (CR) Map (Read & Write) . . 38
Table 31 Coefficient RAM (CRAM) Structure per Channel. . . . . . . . . . . . . . . . . 39
Table 32 Coefficient RAM (CRAM) Structure per Set. . . . . . . . . . . . . . . . . . . . . 40
Table 33 Types of Commands and Data Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 34 Analog Loop Programming in Register CR3, Bits 7 to 4 . . . . . . . . . . . 51
Table 35 Digital Loop Programming in Register CR3, Bits 7 to 4 . . . . . . . . . . . . 52
Table 36 Cut-Off Programming in Register CR2, Bits 7 to 5. . . . . . . . . . . . . . . . 53
PEB 2266
PEF 2266
Hardware Reference Manual 1 2001-02-20
Preface
This document provides detailed technical information about the SICOFI®2-µC. It is
intended for anyone considering or using the device for system design or board layout
for a broad range of analog telephony applications. All content applies to both the
standard PEB 2266 and the extended temperature version, PEF 2266, unless specified.
Organization of this Document
This Hardware Reference Manual is organized as follows:
•Chapter 1, Overview
Includes a general description of the architecture, feature list, and logic symbol.
•Chapter 2, Pin Descriptions
Illustrates the Pin Configuration and provides detailed functional descriptions.
•Chapter 3, Functional Description
Provides a block diagram and summarizes the major functional blocks.
•Chapter 4, Operational Description
Begins with a state diagram and description of the operating states of all two channels
and concludes with detailed transmission characteristics.
•Chapter 5, Interface Descriptions
Describes the Analog, PCM, Signaling, and Serial Microcontroller interfaces.
•Chapter 6, Programming Overview
Illustrates the register model and coefficient RAM structure, provides a register map
and summary, and identifies the programming command sequences.
•Chapter 7, Application Hints
Describes the development system available for the PEB 2266, and provides
guidelines and schematics for board layout.
•Chapter 8, Electrical Characteristics and Timing Diagrams
Provides detailed tables for the electrical characteristics and includes timing diagrams
for the Analog, PCM, Serial Microcontroller, and Signaling interfaces.
•Chapter 9, Test Configuration
Describes the test loops and cut-offs available for functional tests and diagnostics.
•Chapter 10, Package Outlines
Illustrates the P-MQFP-64 package in which the PEB 2266 is manufactured.
•The Appendix
Includes a glossary and an index.
Related Documentation
Other documentation for the PEB 2266 includes a Product Brief, a Product Overview, a
Programmer’s Reference Manual, and assorted Application Notes. Similar
documentation is also available for the other members of the SICOFI Codec family
including the PSB 2132, PSB 2134, and PEB 2466. Documentation is available by
accessing our website: http://www.infineon.com/sicofi
PEB 2266
PEF 2266
Overview
Hardware Reference Manual 2 2001-02-20
1 Overview
The two-channel codec filter PEB 2266 SICOFI®2-µC is built around a central DSP-core
which provides independent filter structures for all channels. Its analog I/O pins are used
to connect to external subscriber line interface circuits (SLICs). Their signals are
internally routed to the analog-to-digital and digital-to-analog converters (ADC, DAC).
The signaling pins carry line status and control information to and from the SLICs. Two
programmable clock outputs are available. The SICOFI®2-µC connects to the digital
switching and transmission system through two PCM Highways. The digitized voice
band signals are available as A-Law or µ-Law codes within selectable 8-bit time slots.
The SICOFI®2-µC modes, features, and filter characteristics are programmed through a
serial interface to a microcontroller. The access mechanism is very simple, and can be
implemented with as few as three I/O ports. The PEB 2266 is available for standard
temperature range applications (0 °C to +70 °C); the PEF 2266 is available for extended
temperature range applications (-40 °C to +85 °C).
Figure 1 SICOFI®2-µC Architecture
SLIC 1 ADC - DAC
Signaling
SLIC 2 ADC - DAC
Signaling
Highway A
Highway B
Status and Control
Registers CRAM
PLL,
Clocking
Serial Microcontroller Interface
t/r
t/r
PEB 2266
SICOFI2-µC
Digital Filters
Channel 1
Digital Filters
Channel 2
DSP Core
PCM Interface
2266_201
P-MQFP-64
Hardware Reference Manual 3 2001-02-20
Two Channel Codec Filter with PCM and
Microcontroller Interface
SICOFI®2-µC
PEB 2266
PEF 2266
Version 2.2 CMOS
Type Package
PEB 2266 Version 2.2 P-MQFP-64
PEF 2266 Version 2.2 P-MQFP-64
1.1 Features
•Two-channel single chip codec with digital filters
•High analog driving capability (300 Ω, 50 pF) for
direct driving of transformers
•Digital Signal Processing (DSP) technique
•Programmable digital filters to adapt transmission
behavior, especially for:
–AC impedance matching
–Transhybrid balancing
–Frequency response
–Signal levels
–A/µ-Law compression and expansion
•Fulfills international (e.g. ITU-T Q.552, G.712) and country-specific requirements
•High performance ADC and DAC for excellent linearity and dynamic gain
•Programmable Analog Interface to electronic SLICs or transformer solutions
•Seven SLIC-signaling I/O pins per channel with programmable debouncing
•Two PCM Highways accessible by on-chip PCM Interface with Programmable time
slot assignment and variable data rates from 128 kbit/s to 8 Mbit/s
•Easy to use 4-pin Serial Microcontroller Interface (SPI compatible) for read/write
access
•Single supply voltage (5 V)
•Advanced low-power mixed-signal CMOS technology
•Two programmable tone generators (DTMF possible)
•Level metering function for system tests and for analog input signal testing
•Advanced on-chip functions for device and system diagnostics and manufacturing test
–Five digital loops
–Four analog loops
•Support tools include:
–Hardware development board — STUT 2466
–QSICOS Coefficient Calculation and Register Configuration Software
•Standard P-MQFP-64 package
PEB 2266
PEF 2266
Overview
Hardware Reference Manual 4 2001-02-20
1.2 Logic Symbol
Figure 2 SICOFI®2-µC Logic Symbol
1.3 Typical Applications
Many applications will benefit from the versatility of the SICOFI®2-µC codec and filter.
The inherent flexibility enables several products to be developed around one basic
architecture, thus affording potentially significant savings in time to market, inventory
costs, and support administration.
The following list represents some of the typical applications for which the SICOFI®2-µC
codec was designed: Analog linecards for Central Offices and PBXs, Small PBX or
Key Systems, Digital Loop Carrier (DLC) Systems, Digital Added Main Lines (DAML)
Systems, Pair-Gain Systems, Fiber-to-the-Curb (FTTC) Systems,
Radio-in-the-Loop (RITL) Systems, and
any Multi-channel, digital voice processing, storage, or communication applications.
Refer to the Product Overview, Chapter 5 Application Hints for more information.
Analog
Interface
INT12
RESET#
V
OUT2
Channel
2
Channel
1
V
IN2
V
OUT1
V
IN1
SICOFI
®
2-µC
PEB 2266
CHCLK2
CHCLK1
Microcontroller Interface
DOUT DIN DCLK CS#
SI1_0
SI1_1
SO1_0
SO1_1
SB1_0
SB1_1
SB1_2
SI2_0
SI2_1
SO2_0
SO2_1
SB2_0
SB2_1
SB2_2
Signaling
Interface
Ch. 1&2
Channel
2
Channel
1
PCLK
DRB
DXB
TCB#
DXA
TCA#
MCLK
DRA
FSC
PCM
Clocks
Master Clock
Highway
A
Highway
B
PCM
Interface
2266_203
PEB 2266
PEF 2266
Pin Descriptions
Hardware Reference Manual 5 2001-02-20
2 Pin Descriptions
2.1 Pin Diagram
(top view)
Figure 3 Pin Configuration of SICOFI®2-µC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
12345678910 11 12 13 14 15 16
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SICOFI
®
2-µC
PEB 2266-H
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
CHCLK1
INT12
SI1_1
SI1_0
SB1_2
SB1_1
SB1_0
SO1_1
SO1_0
SO2_0
SO2_1
SB2_0
SB2_1
SB2_2
SI2_0
SI2_1
PCLK
FSC
DRB
DXB
TCB#
DRA
DXA
TCA#
V
DDD
RESET#
MCLK
GNDD
DOUT
DIN
DCLK
CS#
CHCLK2
NC
NUI
NUI
NUIO
NUIO
NUIO
NC
NC
NC
NC
NUIO
NUIO
NUIO
NUI
NUI
NC
NC
V
IN2
V
IN1
GNDA
NC
V
DDA
NC
GNDA
V
DDREF
V
REF
GNDA2
V
OUT2
V
DDA12
V
OUT1
GNDA1
2266_204
P-MQFP-64
PEB 2266
PEF 2266
Pin Descriptions
Hardware Reference Manual 6 2001-02-20
2.2 Pin Definitions and Functions
Table 1 Pin Definitions and Functions
Pin Symbol Type Function Ch.
1, 2 NUI I Non Usable Input
Pins tie directly to digital ground (Pin 21)
3, 4,
5
NUIO I/O Non Usable Input/Output
Pins tie via a pull-down-resistor to digital ground (Pin 21)
6, 7,
8, 9
NC Not Connected
Pins not connected in this device.
10,
11,
12
NUIO I/O Non Usable Input/Output
Pins tie via a pull-down-resistor to digital ground (Pin 21)
13,
14
NUI I Non Usable Input
Pins tie directly to digital ground (Pin 21)
15 NC Not Connected
Pins not connected in this device.
16 CHCLK2 O Chopper Clock Output 2
Provides 256, 512, or 16,384 kHz signal; sync. to MCLK.
both
17 CS# I Chip Select
Microcontroller Interface chip select, enable to read or
write; active low.
both
18 DCLK I Data Clock
Microcontroller Interface data clock, shifts data from or to
device; maximum clock rate 8192 kHz.
both
19 DIN I Data Input
Microcontroller Interface control data input pin; DCLK
determines data rate.
both
20 DOUT O Data Output
Microcontroller Interface control data output pin; DCLK
determines data rate: DOUT is high impedance "Z" if no
data is transmitted from the SICOFI®2-µC.
both
21 GNDD I Digital Ground
Ground reference for all digital signals. Internally isolated
from GNDA1 (Pin 50), GNDA2 (Pin 54), and GNDA (Pins
59 and 63).
both
PEB 2266
PEF 2266
Pin Descriptions
Hardware Reference Manual 7 2001-02-20
22 MCLK I Master Clock Input
1536, 2048, 4096 or 8192 kHz must be applied for any
operation (selected in Register XR5). MCLK, PCLK, FSC
must be synchronous.
both
23 RESET# I Reset Input
Forces the device to default setting mode; active low.
both
24 VDDD IDigital Supply Voltage
+5 V supply for digital circuits (use 100 nF blocking cap.).
both
25 TCA# O Transmit Control Output A
PCM Interface: active if data is transmitted via DXA;
active low, open drain.
both
26 DXA O Data Transmit to PCM-Highway A
PCM Interface: PCM data for each channel is transmitted
in 8-bit bursts every 125 µs.
both
27 DRA I Data Receive from PCM-Highway A
PCM Interface: PCM data for each channel is received in
8-bit bursts every 125 µs.
both
28 TCB# O Transmit Control Output B
PCM Interface: active if data is transmitted via DXB;
active low, open drain.
both
29 DXB O Data Transmit to PCM-Highway B
PCM Interface: data for each channel is transmitted in
8-bit bursts every 125 µs.
both
30 DRB I Data Receive from PCM-highway B
PCM Interface: data for each channel is received in 8-bit
bursts every 125 µs.
both
31 FSC I Frame Synchronization Clock
8 kHz; reference for individual time slots, indicates start
of PCM frame; MCLK, PCLK, FSC must be synchronous.
both
32 PCLK I PCM Data Clock
128 to 8192 kHz; determines the rate at which PCM data
is shifted into or out of the PCM-ports. MCLK, PCLK,
FSC must be synchronous.
both
33 CHCLK1 O Chopper Clock Output 1
Provides programmable (2 …28 ms) output signal
(synchronous to MCLK).
both
Pin Symbol Type Function Ch.
PEB 2266
PEF 2266
Pin Descriptions
Hardware Reference Manual 8 2001-02-20
34 INT12 O Interrupt Output, Channels 1 and 2
Active high.
both
35 SI1_1 I Signaling Input Channel 1, Pin 1 1
36 SI1_0 I Signaling Input Channel 1, Pin 0 1
37 SB1_2 I/O Bi-directional Signaling, Channel 1 Pin 2 1
38 SB1_1 I/O Bi-directional Signaling, Channel 1 Pin 1 1
39 SB1_0 I/O Bi-directional Signaling, Channel 1 Pin 0 1
40 SO1_1 O Signaling Output, Channel 1, Pin 1 1
41 SO1_0 O Signaling Output, Channel 1, Pin 0 1
42 SO2_0 O Signaling Output, Channel 2, Pin 0 2
43 SO2_1 O Signaling Output, Channel 2, Pin 1 2
44 SB2_0 I/O Bi-directional Signaling, Channel 2 Pin 0 2
45 SB2_1 I/O Bi-directional Signaling, Channel 2 Pin 1 2
46 SB2_2 I/O Bi-directional Signaling, Channel 2 Pin 2 2
47 SI2_0 I Signaling Input, Channel 2, Pin 0 2
48 SI2_1 I Signaling Input, Channel 2, Pin 1 2
49 VIN1 IAnalog Voice (Voltage) Input, Channel 1
Requires a coupling capacitor >39 nF to the SLIC.
1
50 GNDA1 I Analog Ground, Channel 1
Not internally connected to GNDD or GNDA2 or GNDA.
1
51 VOUT1 OAnalog Voice (Voltage) Output, Channel 1
Requires a coupling capacitor to the SLIC. The capacitor
value depends on the SLIC’s input impedance. (See
Chapter 5.1, "Analog Interface" on page 27).
1
52 VDDA12 IAnalog Supply Voltage, Channels 1 and 2
+5 V (100 nF blocking capacitor required).
both
53 VOUT2 OAnalog Voice (Voltage) Output, Channel 2
Requires a coupling capacitor to the SLIC. The capacitor
value depends on the SLIC’s input impedance. (See
Chapter 5.1, "Analog Interface" on page 27).
2
54 GNDA2 I Analog Ground, Channel 2
Not internally connected to GNDD or GNDA1 or GNDA.
2
55 VIN2 IAnalog Voice (Voltage) Input, Channel 2
Requires a coupling capacitor >39 nF to the SLIC.
2
Pin Symbol Type Function Ch.
PEB 2266
PEF 2266
Pin Descriptions
Hardware Reference Manual 9 2001-02-20
56 VREF I/O Reference Voltage
Must connect to a 220 nF cap. to ground.
both
57 VDDREF IAnalog Supply Reference Voltage
+5 V (100 nF blocking capacitor required).
both
58 NC Not Connected
Pin not connected in this device.
59 GNDA I Analog Ground
Internally isolated from GNDD (Pin 21), GNDA1(Pin 50),
and GNDA2 (Pin 54).
60 NC Not Connected
Pin not connected in this device.
61 VDDA IAnalog Supply Voltage
+5 V (100 nF blocking capacitor required).
62 NC Not Connected
Pin not connected in this device.
63 GNDA I Analog Ground
Internally isolated from GNDD (Pin 21), GNDA1(Pin 50),
and GNDA2 (Pin 54).
64 NC Not Connected
Pin not connected in this device.
Pin Symbol Type Function Ch.
PEB 2266
PEF 2266
Functional Description
Hardware Reference Manual 10 2001-02-20
3 Functional Description
The telephone subscriber loop is a bi-directional two-wire line. The Subscriber Line
Interface Circuit (SLIC) on the network side converts the two-wire interface to a four-wire
interface which communicates with the SICOFI®2-µC via separate receive and transmit
signals, VIN and VOUT. The SLIC can be either a transformer or an electronic circuit with
operational amplifiers. It must have a defined input impedance towards the subscriber
line for maximum signal power transfer and return loss. The requirements for the input
impedance vary from country to country and demand impedance matching to the
different environments. Country-specific adaptations are also required for the
transhybrid loss, which is a loss between the transmit and the receive ports of the two-
wire to four-wire hybrid.
3.1 DSP-based Architecture
The impedance matching and transhybrid balancing functions are performed by loop
filters between the transmit path (analog to PCM) and the receive path (PCM to analog).
The filter characteristics must be adjusted according to the local requirements of each
market. In the analog domain, filters must be optimized in hardware; this is generally
both tedious and time-consuming. This is not the case with the DSP-based SICOFI®2-
µC two-channel codec. Its integrated signal processor implements the impedance
matching and transhybrid balancing functions as digital, programmable filters. It also
performs frequency response corrections and level adjustments to enable the design of
a truly universal and internationally applicable telephone linecard. Transmission
characteristics and frequency behavior are enhanced by the accuracy of the digital
filters, which do not fluctuate over temperature or with age.
As an additional benefit of its DSP-based architecture, the PEB 2266 also provides two
tone generators per channel. An on-chip level-metering unit allows line-characterization
without extra hardware; it can also be used to detect specific tones, e.g., modem tones.
3.2 Programming and Control
A very simple Microcontroller Interface is used to program the SICOFI®2-µC functions.
The same port provides access to 14 general purpose I/O pins of the Signaling Interface.
This allows efficient and convenient monitoring and control of other linecard functions,
such as on-/off-hook detection, ground-key detection, switching of ring signals and test
relays. The Serial Microcontroller Interface provides a programming and control
interface and is generic and non-proprietary for use with any microcontroller. It can be
implemented with as few as three signal lines, since the data receive and data transmit
pins may be strapped together.
PEB 2266
PEF 2266
Functional Description
Hardware Reference Manual 11 2001-02-20
Figure 4 SICOFI®2-µC Block Diagram
Figure 4 shows the functional blocks and the interface pins of the SICOFI®2-µC:
•Two independent bi-directional voice channels;
•Oversampling sigma-delta A/D and D/A converters with excellent resolution, dynamic
range, linearity, accuracy and signal-to-noise performance;
•Hardware filters for decimation and interpolation of the ADC and DAC bit stream, and
pre-processing of the voice data to reduce the load of the DSP;
•DSP core with programmable, channel-independent filter structures for impedance
matching, transhybrid balancing, frequency correction and level adjustments;
•Configurable A-Law or µ-Law compressor and expander units;
•Two PCM port with data rates from 128 kbps to 8 Mbps per highway;
•Programmable time slot assignment for each channel;
•Fourteen signaling input and output pins, accessible through registers;
•On-chip PLL for an internal 16,384 kHz clock;
•Two programmable versatile clock outputs;
•Eight common configuration registers (XR-Registers) affecting all two channels;
•Two sets of six channel-specific registers (CR-Registers); and
•Coefficient RAM (CRAM) for filter coefficients storage for each channel.
PEB 2266, SICOFI2-µC
PCM-
Interface
with
Time Slot
Assignment
ADC
DAC
Programmable
Filters and Gain
Hardware
Filters
Digital Signal Processing
ADC
DAC
Programmable
Filters and Gain
Hardware
Filters
A-Law
or
µ-Law
Signaling Interface
Serial Microcontroller Interface
Compander
A-Law
or
µ-Law
V
IN1
V
OUT1
V
IN2
V
OUT2
FSC
PCLK
DXA
DRA
TCA#
Highway A
DXB
DRB
TCB#
Highway B
DOUTDINCS#DCLKINT12
Registers and CRAM
SIx_y
SOx_y
SBx_y
PLL,
Clocking
MCLK
CHCLK2
CHCLK1
2266_205
PEB 2266
PEF 2266
Operational Description
Hardware Reference Manual 12 2001-02-20
4 Operational Description
Each channel of the SICOFI®2-µC can be in one of two stable states: “Standby” and
“Operating”. These states can be switched by programming Bit 0 (PU) in the
channel-specific configuration register CR1. “Standby” is a power-saving state. Keeping
any unused channels in this state reduces the overall system power dissipation. The
third state, “Reset”, is transient and is reached after applying power to the device (Power
On), after asserting a logic low signal to the RESET#-pin (HW-Reset), or after issuing an
XOP command with Bit 7 (RST) set to "1" (SW-Reset). Both channels would be affected
in any case.
4.1 Operating States
Figure 5 SICOFI®2-µC State Diagram
4.1.1 Power On
All input pins must be at GND level before applying VDD to the SICOFI®2-µC. Otherwise,
the device may not enter the Reset State. In this case, the SICOFI®2-µC can be reset by
HW- or SW-Reset, or can be initialized by setting all registers to zero.
4.1.2 Hardware Reset
Voltage levels lower than 1.2 V applied to Pin 23 (RESET#) for more than 3 µs will reset
the SICOFI®2-µC. Spikes that are shorter than 1 µs will be ignored. When RESET# is
released the SICOFI®2-µC will enter Standby State.
2266_206
Reset
(both channels)
Power-On
HW-Reset
SW-Reset
Power Up Ch.2
Power Down Ch.2
Power Up Ch.1
Power Down Ch.1
Operating
Ch.1
Standby
Ch.1
Operating
Ch.2
Standby
Ch.2
PEB 2266
PEF 2266
Operational Description
Hardware Reference Manual 13 2001-02-20
Table 2 Register Values and Accessibility
Table 3 Input and Output Pin Behavior
Table 4 Power Dissipation
Register SICOFI®2-µC State
Reset Standby Operating
CR0 ... CR4 00Huser configurable user configurable
XR0 ... XR7 00Huser configurable user configurable
CRAM unchanged user configurable user configurable
Pin SICOFI®2-µC State
Reset Standby Operating
DIN ignored serial input serial input
DOUT high impedance serial output serial output
DRA, DRB ignored ignored active receive time slot
DXA, DXB high impedance high impedance active transmit time slot
TCA#, TCB# high high low during active
transmit time slot
VOUT1 , VOUT2 high impedance high impedance analog output
VIN1 , VIN2 ignored ignored analog input
SBx_y configured as input programmable as
input or output
programmable as input
or output
SOx_y GNDD digital output digital output
SIx_y ignored digital input digital input
CHCLK1 high programmable
frequency
programmable
frequency
CHCLK2 high programmable freq.
(not 16,384 kHz)
programmable
frequency
No. of Channels Operating Typical Power Dissipation
None 2.5 mW
1 70 mW
2 90 mW
PEB 2266
PEF 2266
Operational Description
Hardware Reference Manual 14 2001-02-20
4.2 Transmission Characteristics
4.2.1 Overload Point
The overload point of the SICOFI®2-µC A/D converters is at 2.223 V. This is the peak
amplitude of a sine wave level of 1.572 Vrms. Higher input signal levels will be distorted.
Theoretical load capacities for A-Law and µ-Law encoded signals are defined in ITU-T
Recommendation G.711. These values correspond to the SICOFI®2-µC overload point:
Table 5 Maximum Signal Levels
4.2.2 0 dBm0-Levels
The analog voltage levels corresponding to a 0 dBm0 sine wave signal can be calculated
from the maximum signal levels shown in Table 5. The results are shown in Table 6.
Table 6 Analog Voltage Levels Corresponding to 0 dBm0-Level
Note: Periodic PCM codes for a 1 kHz sine wave signal with 0 dBm0 level can be found
in ITU-T G.711.
Encoding Law
PCM Interface Analog Interface
Theoretical Load Capacity
(according to ITU-T G.711)
Max. Sine Wave Level
(SICOFI®2-µC Overload Point)
A-Law 3.14 dBm0 1.572 Vrms
µ-Law 3.17 dBm0
Encoding Law Analog Sine Wave Level
corresponding to 0 dBm0 PCM Level
A-Law 1.572 Vrms*10^(-3.14/20) = 1.095 V rms
µ-Law 1.572 Vrms*10^(-3.17/20) = 1.091 V rms
PEB 2266
PEF 2266
Operational Description
Hardware Reference Manual 15 2001-02-20
4.2.3 Compressor Gain Relative to Coding Law
The µ-Law compressor unit of the SICOFI®2-µC automatically adds 1.94 dB gain, which
has to be considered for the total gain calculation. The accumulated gain of all
programmable transmit filters (AX1+AX2+FRX) must not exceed 7 dB if the device is set
to µ-Law operation. If the device is set to A-Law operation, then the accumulated gain
must not exceed 9 dB.
Figure 6 Analog and PCM Signal Levels in A-Law Mode
Figure 7 Analog and PCM Signal Levels in µ-Law Mode
A-Law
Compressor
Transmit
A-Law
Expander
Receive
0dBm0
1014 Hz
0dBm0
DXA/B
DXA/B
A/D 0dB
Gain
D/A 0dB
Gain
V
OUT
V
IN
1014 Hz
1.095 V
rms
1.095 V
rms
2266_207
A/D
µ
-Law
Compressor
[+1.94 dB]
Transmit
D/A
µ
-Law
Expander
Receive
V
OUT
V
IN
1014 Hz
1.091 V
rms
1.091 V
rms
1.94 dBm0
1014 Hz
0dBm0
DXA/B
DXA/B
0dB
Gain
0dB
Gain
2266_208
PEB 2266
PEF 2266
Operational Description
Hardware Reference Manual 16 2001-02-20
4.2.4 Operating Conditions
The specifications to which the SICOFI®2-µC are tested are tighter than the ITU-T Q.552
Specification to guardband various SLIC implementations. The guaranteed transmission
characteristics of the SICOFI®2-µC under test conditions ensure that the final linecard
design will meet the ITU-T specification.
The figures in this document are based on the subscriber-line board requirements.
Proper adjustment of the programmable filters (transhybrid balancing, impedance
matching, frequency-response correction) requires a complete knowledge of the analog
environment in which the SICOFI®2-µC is to be used. Unless otherwise stated, the
transmission characteristics are guaranteed within the following operating conditions:
•TA = 0 °C to 70 °C (PEB 2266), TA = -40 °C to 85 °C (PEF 2266);
•VDD = 5 V ± 5%;
•GNDA1,2,3,4 = GNDD = 0 V;
•Load on VOUT: RL > 300 Ω; CL < 50 pF;
•H(IM) = H(TH) = 0;
•H(R1) = H(FRX) = H(FRR) = 1;
•HPR and HPX enabled;
•AR = 0 to –9 dB (AR = AR1 + AR2 + FRR + R1);
•AX = 0 to +9 dB for A-Law,
AX = 0 to +7 dB for µ-Law (AX = AX1 + AX2 + FRX);
•f = 1014 Hz; 0 dBm0; A-Law or µ-Law;
•AGX = 0 dB, +6.02 dB; and
•AGR = 0 dB, –6.02 dB.
Figure 8 Simplified Signal Flow Diagram
2266_209
ADC
DAC
Receive Path
Transmit Path
Analog
Output
Analog
Input
PCM
Input
PCM
Output
IM
AGR R1 AR2 FRR AR1 EXP
CMPAX1FRXAX2AGX
TH
HPX
HPR
PEB 2266
PEF 2266
Operational Description
Hardware Reference Manual 17 2001-02-20
4.2.5 Gain Accuracy
Table 7 Gain Accuracy
4.2.6 Gain Tracking (Receive and Transmit)
The gain deviation for a 1014 Hz sine-wave input signal will stay within limits shown in
Table 8. All values are relative to the gain of a 0 dBm0 input signal.
Table 8 Gain Deviations with Input Level
Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Absolute Gain G–0.20 ±0.10 +0.20 dB TA=25°C,VDD =5V,
AGX = AGR = 0 dB
Variation with
Temperature ±0.05 dB TA = –40 °C to 85 °C
Variation with
Supply Voltage ±0.05 dB VDD = 5 V ± 5%
Variation with
Analog Gain ±0.05 dB AGX= +6.02 dB,
AGR= –6.02 dB
Input Level Symbol Gain Deviation Unit Test Conditions
min. typ. max.
-55 to -50 dBm0 ∆G ±1.4 dB 1014 Hz sine-wave
test signal. Reference
level is at 0 dBm0.
-50 to -37 dBm0 ∆G±0.5dB
-37 to 3 dBm0 ∆G ±0.25 dB
PEB 2266
PEF 2266
Operational Description
Hardware Reference Manual 18 2001-02-20
4.2.7 Frequency Response
Table 9 Attenuation with Frequency in Transmit and Receive Direction
4.2.8 Group Delay
4.2.8.1 Group Delay, Absolute Values
Table 10 shows the limit values for the Absolute Group Delay. The maximum delays are
valid when the SICOFI®2-µC is operating with H(TH) = H(IM) = 0, and H(FRR) = H(FRX)
= 1, and include the delay through the A/D and D/A converters. The typical delays are
the average of all different time slot delays during one PCM frame.
Table 10 Group Delay, Absolute Values
Input Frequency Receive Loss Transmit Loss Unit Test Conditions
min. max. min. max.
0 Hz to 100 Hz 0 > 2 dB 0 dBm0 input signal
level. 1014 Hz
reference frequency
100 Hz to 200 Hz 0 0 dB
200 Hz to 300 Hz -0.125 -0.125 1 dB
300 Hz to 3.0 kHz -0.125 0.125 -0.125 0.125 dB
3.0 kHz to 3.2 kHz -0.125 0.3 -0.125 0.3 dB
3.2 kHz to 3.4 kHz -0.125 0.65 -0.125 0.65 dB
> 3.4 kHz 0 0 dB
Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Transmit Delay DXA 300 375 450 µs 0 dBm0 input signal
level, fTest at TGmin.
Receive Delay DRA 300 375 450 µs
PEB 2266
PEF 2266
Operational Description
Hardware Reference Manual 19 2001-02-20
4.2.8.2 Group Delay Distortion with Frequency
The Group Delay Distortion in transmit and receive direction will stay within the limits
shown in Table 11. Group Delay Distortion values are referenced to the minimum value
of Group Delay (TGmin).
Table 11 Group Delay Distortion with Frequency
4.2.9 Noise
Table 12 Idle Channel Noise in Transmit Direction
Table 13 Idle Channel Noise in Receive Direction
Frequency Symbol Limit Values Unit Test Conditions
min. typ. max.
500 Hz to 600 Hz ∆tG300 µs 0 dBm0 input signal level,
reference point is at TGmin.
600 Hz to 1.0 kHz ∆tG150 µs
1.0 kHz to 2.6 kHz ∆tG100 µs
2.6 kHz to 3.0 kHz ∆tG300 µs
Parameter Symbol Limit Values Unit
min. typ. max.
A-Law, psophometric (VIN =0V) NTP –67.4 dBm0p
µ-Law, C-message (VIN =0V) NTC 17.5 dBmc
µ-Law, C-message (VIN =0V) NTC 17.5 dBrnC0
Parameter Symbol Limit Values Unit
min. typ. max.
A-Law, psophometric (idle code + 0) NRP –85 –78.0 dBm0p
µ-Law, C-message (idle code + 0) NRC 5 12.0 dBmc
µ-Law, C-message (idle code + 0) NRC 5 12.0 dBrnC0
PEB 2266
PEF 2266
Operational Description
Hardware Reference Manual 20 2001-02-20
4.2.10 Harmonic and Intermodulation Distortion
Table 14 Harmonic and Intermodulation Distortion
4.2.11 Total Distortion
Table 15 Signal-to-Total Distortion Ratio Measured with Sine Wave
Figure 9 Total Distortion Measured with Sine-Wave, Receive and Transmit
Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Harmonic Distortion
2nd, 3rd order HD –50 –44 dB 0 dBm0; f = 1014 Hz
Intermodulation
R2
R3
IMD
IMD
–46
–56
dB
dB
Equal-level, 4-tone method
(EIA-464) at composite
level of -13 dBm0;
f= 300 Hz to 3400 Hz
Input Level Symbol Min. Values Unit Test Conditions
A-Law µ-Law
-45 dB S/D 24.5 27 dB sine wave f=1014 Hz, receive and
transmit,
µ-Law: C-message weighted,
A-Law: psophometrically weighted.
-40 dB S/D 29.5 31 dB
-30 dB S/D 35.5 35.5 dB
> -28 dB S/D 36.4 36.4 dB
2266_210
-60
0
Input Level
10
20
30
40
-50 -40 -30 -20 -10 0dBm0
dB
27
24.5
-45
-28
35.5
29.5
31
A-Law
-Law
µ
36.4
S/D
PEB 2266
PEF 2266
Operational Description
Hardware Reference Manual 21 2001-02-20
Table 16 Signal-to-Total Distortion Ratio Measured with Noise
Figure 10 Total Distortion Receive (Noise)
Figure 11 Total Distortion Transmit (Noise)
Input Level Symbol Min. Value, PEB 2266 Min. Value, PEF 2266 Unit
Receive Transmit Receive Transmit
-55 dB S/D 14.7 13.7 14.7 12 dB
-40 dB S/D 29.7 28.7 29.7 27 dB
-34 dB S/D 34.3 33.3 34.3 33.3 dB
-27 dB S/D 36 35.4 36 35.4 dB
-24 to -6 dB S/D 36.7 36.3 36.7 36.3 dB
-3 dB S/D 28.4 27.4 28.4 27.4 dB
2266_211
-60
0
Input Level
10
20
30
40
-50-40-30-20-10
0
dBm0
dB
-55 -34 -24
-27 -3-6
14.7
28.4
29.7
36.7
34.3 36
S/D
2266_212
-30
20
13.7
-60
0
12
10
-55
-50 -40
-34
35.4
28.7
27.0
33.3
30
dB
40
-10-20
Input Level
-24-27
dBm0
-6 -3
0
27.4
36.3
S/D
PEB 2266
PEF 2266
PEB 2266
PEF 2266
Operational Description
Hardware Reference Manual 22 2001-02-20
4.2.12 Single Frequency Distortion
Any resulting signal with a frequency different from the test input signal will stay at least
28 dB below the input signal level.
4.2.13 Overload Compression
This is measured with a 1014 Hz sine-wave signal. The overload point in µ-Law Mode is
at 3.17 dBm0.
Figure 12 Overload Compression (µ-Law Coding, Transmit Direction)
4.2.14 Crosstalk
Table 17 Crosstalk Between Channels
Test Input Signal Frequency Range max. Input Level
Receive Direction 300 Hz to 3.4kHz 0 dBm0
Transmit Direction 0 Hz to 12 kHz 0 dBm0
Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Crosstalk, 0dBm0 CT – 85 – 80 dB f=200 Hz to 3400 Hz,
any combination of
directions and channels
2266_213
0
Fundamental Input Power
-1
Fundamental
0
1
2
3
4
5
6
7
8
dBm0
10
0.25
-0.25
1234567dBm09
Output Power
PEB 2266
PEF 2266
Operational Description
Hardware Reference Manual 23 2001-02-20
4.2.15 Out-of-Band Discrimination in Transmit Direction
With any 0 dBm0 sine-wave signal below 100 Hz and in the range from 3.4 kHz to 100
kHz (out-of-band signal) applied to an analog input (VINx), the level of any resulting
frequency component at the digital output will stay at least X dB (see Table 18) below
the output level of a 0 dBm0 1kHz sine-wave reference signal at the analog input.
Table 18 Out-of-Band Signals Applied to the Analog Inputs (VINx)
The Hardware Filters behind the A/D Converters reject teletax pulses with their poles at
12 kHz ±150 Hz and 16 kHz ±150 Hz.
Figure 13 Out-of-Band Discrimination in Transmit Direction
Input Frequency Min. Output Signal Rejection
XUnit Test Conditions
0 Hz to 60 Hz 25 dB 0 dBm0 sine-wave input
signal on VIN
60 Hz to 100 Hz 10 dB
3.4 kHz to 4 kHz dB
4 kHz 15 dB
4 kHz to 4.6 kHz
dB
4.6 kHz to 100 kHz 40 dB
14–π4000 f–
1200
---------------------
sin 1–
18–π4000 f–
1200
---------------------
sin 7
9
---–
0
0kHz
f
10
0
0.06 0.1 3.4 4 4.6 6 10 18
10
20
30
40
dB
Transmit Out-of-Band
Discrimination X
25
32
15
2266_214
PEB 2266
PEF 2266
Operational Description
Hardware Reference Manual 24 2001-02-20
4.2.16 Out-of-Band Discrimination in Receive Direction
With any 0 dBm0 sine-wave frequency in the range from 300 Hz to 3.99 kHz applied to
the digital input (PCM time slot), the level of any resulting out-of-band signal at the
analog output will stay at least X dB (see Table 19) below the output level of a 0 dBm0
1kHz sine-wave reference signal at the digital input.
Table 19 Out-of-Band Signals at the Analog Outputs (VOUTx)
Figure 14 Analog Output: Out-of-Band Signals
Output Frequency Min. Output Signal Rejection
X
Unit Test Conditions
3.4 kHz to 4.6 kHz dB 0 dBm0 sine-wave
input signal on digital
input (PCM time slot)
4.6 kHz to 10.55 kHz
dB
4 kHz 15 dB
4.6 kHz 28 dB
>10.55 kHz 57 dB
14
–
π4000 f–
1200
---------------------
sin 1–
35 22f 4600–
5950
---------------------+
0
0kHz
f
10
0
0.06 0.1 3.4 4 4.6 6 10 18
dB
Receive Out-of-Band
Discrimination X
10
20
30
40
50
60
15
35
10.55
816
28
57
2266_215
PEB 2266
PEF 2266
Operational Description
Hardware Reference Manual 25 2001-02-20
4.2.17 Out-of-Band Idle Channel Noise at Analog Output
With an idle code (any sequence of constant PCM octets) applied to the digital input, the
level of any resulting out-of-band power spectral density at the analog output, measured
with 3 kHz bandwidth, will be not greater than the limit curve shown in Figure 15.
Figure 15 Analog Output: Out-of-Band Idle Channel Noise
-100
f
10
12
10
3
10
4
10kHz
-90
-80
-70
-60
-50
-40
dBm0
-55
-78
Out of Band Noise
2266_216
PEB 2266
PEF 2266
Operational Description
Hardware Reference Manual 26 2001-02-20
4.2.18 Transhybrid Loss
The quality of Transhybrid-Balancing is very sensitive to deviations in gain, group delay,
and deviations inherent to the A/D- and D/A-converters, as well as to all external
components used on a linecard (SLIC, OP’s etc.).
Transhybrid loss test setup:
The SICOFI®2-µC test loop “DLB-ANA” is selected (see Figure 34), which connects the
analog output with the analog input. The programmable filters FRR, AR, FRX, AX are
by-passed. The IM-filter is disabled, (H(IM)=0). The balancing filter TH is enabled with
optimized coefficients for this configuration (VOUT = VIN).
A 0 dBm0 sine wave signal with a frequency in the range of 300 Hz to 3400 Hz is applied
to the digital input. The signal levels of the resulting echo at the digital output will stay
below the values shown in Table 20.
Table 20 Transhybrid Loss
Input Frequency Symbol Transhybrid Loss Unit Test Condition
min. typ.
300 Hz THL300 27 40 dB TA = 25 °C; VDD = 5 V
AGX = AGR = 0 dB;
typical variation of
amplitude: ± 0.15 dB
delay: ± 0.5 µs.
500 Hz THL500 30 45 dB
2500 Hz THL2500 29 40 dB
3000 Hz THL3000 27 35 dB
3400 Hz THL3400 27 35 dB
PEB 2266
PEF 2266
Interface Description
Hardware Reference Manual 27 2001-02-20
5 Interface Description
The SICOFI®2-µC provides four interfaces:
•Analog Interface,
•PCM Interface,
•Signaling Interface, and
•Serial Microcontroller Interface.
A general description of these interface is given in the Product Overview, Chapter 4.
Refer to the Programmers Reference Manual for information on the configuration and
operation of the four interfaces.
The subsequent chapters in this manual explain how to connect the SICOFI®2-µC to
subscriber line interface circuits (SLICs), microcontrollers, and PCM highways.
5.1 Analog Interface
The Analog Interface in combination with a Subscriber Line Interface Circuit (SLIC)
forms a configurable tip & ring (t/r) telephone line. The AC transmission characteristic of
the SICOFI®2-µC—SLIC combination can be controlled by programming the digital filter
structures inside the SICOFI®2-µC. The correct filter coefficients are determined by the
targeted AC transmission behavior (e.g. Telco specification) and by the transfer
functions of the SLIC.
The SICOFI®2-µC can be interfaced directly to electronic SLICs or transformer solutions.
The high driving capability of up to 300 Ohms eliminates the need for an external
amplifier that is normally used with transformer SLICs.
The peak amplitude of the analog inputs and outputs is at 2.223 V (overload point).
Out-of-band signals applied to the analog inputs are suppressed by the on-chip digital
hardware filters. The poles of these filters are fixed at 12 kHz and 16 kHz which
suppresses the echo signal from teletax pulses very efficiently: As long as the amplitude
of the teletax echo stays below the overload threshold of 2.223 Vp (1.57 Vrms), the voice
signal in the transmit path will not be disturbed. Thus, the on-chip hardware filters can
eliminate the need for external teletax filters.
5.1.1 Coupling Capacitors at the Analog Interface
A coupling capacitor >39 nF must be used on the VIN-pins in the transmit direction. The
required value for the coupling capacitor on the VOUT-pins depends on the input
resistance of the SLIC-circuitry (RLoad). It has to be chosen to fulfil the frequency
response requirement in the receive direction. Figure 16 can be used to determine an
appropriate value for the coupling capacitor (CExt1).
PEB 2266
PEF 2266
Interface Description
Hardware Reference Manual 28 2001-02-20
Figure 16 Analog Interface to Two Subscriber Line Interface Circuits (SLICs)
R
Load
Ext1
C
10
-3
10
23
10
4
10
-2
10
-1
10
1
10
2
10
0
10
F
Ω
µ
5
10
6
10
C
Ext1
=f
min
·R
Load
1
f
min
= 250 Hz
5756
51
49
50 54
53
55
V
DDA12
V
REF
V
DDREF
52
SICOFI2-µC
100nF220nF
Channel 1
V
IN1
V
OUT1
GNDA1
Channel 2
V
IN2
V
OUT2
GNDA2
C
Ext1
C
Ext1
> 39nF > 39nF
100nF 100nF
SLIC 1
t/r
R
Load
SLIC 2
t/r
R
Load
2266_217
PEB 2266
PEF 2266
Interface Description
Hardware Reference Manual 29 2001-02-20
5.1.2 Analog Interface Pins
Table 21 Analog Interface Pins
Channel Symbol Pin Function
VIN1 49
Analog Input.
Requires a coupling capacitor >39 nF to the SLIC
(see Figure 16).
VOUT1 51
Analog Output.
Requires a coupling capacitor to the SLIC. The
capacitor’s value depends on the input impedance of the
SLIC, (see Figure 16).
GNDA1 50 Analog Ground.
Internally isolated from GNDD, GNDA, or GNDA2.
VIN2 55
Analog Input.
Requires a coupling capacitor >39 nF to the SLIC
(see Figure 16).
VOUT2 53
Analog Output.
Requires a coupling capacitor to the SLIC. The
capacitor’s value depends on the input impedance of the
SLIC, (see Figure 16).
GNDA2 54 Analog Ground.
Internally isolated from GNDD, GNDA, or GNDA2.
VDDA12 52 Analog Supply Voltage.
+5 V (100 nF blocking capacitor required, see Figure 16).
VDDREF 57 Analog Supply Reference Voltage.
+5 V (100 nF blocking capacitor required, see Figure 16).
VREF 56 Reference Voltage
Must connect to a 220 nF cap. to ground, see Figure 16.
PEB 2266
PEF 2266
Interface Description
Hardware Reference Manual 30 2001-02-20
5.2 PCM Interface
The SICOFI®2-µC provides an industry–standard PCM Interface with access to one
PCM highways. The PCM Interface has the following features:
•Data rate from 128 kbit/s to 8 Mbit/s per highway,
•2 to 128 time slots per frame per highway,
•PCM data format serialized 8 bits with MSB first,
•Configurable A-Law or µ-Law coding,
•Independently configurable time slot and highway for each channel and direction,
•PCM clock speed of once or twice the bit rates,
•Programmable sampling slopes, and
•Programmable frame delay.
5.2.1 PCM Interface Pins
Table 22 PCM Interface Pins
5.2.2 PCM Receive and Transmit Example
Figure 17 and Figure 19 illustrate the time slot and bit positions resulting from the
programming example below:
Table 23 PCM Register Configuration Example
Symbol Pin Function
PCLK 32 PCM-Clock, 128 kHz to 8192 kHz; shared for both highways.
FSC 31 Frame Synchronization Clock, 8 kHz; shared for both highways.
DRA 27 Receive Data input for PCM-highway A.
DRB 30 Receive Data input for PCM-highway B.
DXA 26 Transmit Data output for PCM-highway A, open drain.
DXB 29 Transmit Data output for PCM-highway B, open drain.
TCA# 25 Transmit Control output for highway A, low when DXA is active.
TCB# 28 Transmit Control output for highway B, low when DXB is active.
Channel CR4 Receive Setting CR5 Transmit Setting
1 0000 0000 DRA, time slot 0 0000 0000 DXA, time slot 0
2 0000 1111 DRA, time slot 15 0001 0010 DXA, time slot 18
all XR6=0000 0000; single clock mode, no PCM offset; PCLK=2048 kHz.
PEB 2266
PEF 2266
Interface Description
Hardware Reference Manual 31 2001-02-20
Figure 17 PCM Interface Example: Location of Time Slots
Figure 18 PCM Interface Example: Detail A
The pins DRA/B and DXA/B may be strapped together to form a multiplexed
bi-directional PCM port.
2266_218
TCA#
Detail A
FSC
DXA
DRA
PCLK
23
High 'Z' High 'Z'
Time Slot
01
125 µs
31
15
180
DRA
PCLK
FSC
DXA
TCA#
High 'Z' High 'Z'
Voice Data
Voice Data
Clock01234567
01234567Bit
2266_219
PEB 2266
PEF 2266
Interface Description
Hardware Reference Manual 32 2001-02-20
5.3 Signaling Interface
The SICOFI®2-µC Signaling Interface is used to monitor and control supervision and
signaling functions on up to four subscriber lines. The device generates interrupt signals
to indicate signaling status changes on any of the input pins.
The Signaling Interface consists of the following I/O pins and functions:
•14 signaling pins (2 input pins, 2 output pins, and 3 user-configurable bi-directional
pins per channel),
•Debouncing functions,
•1 interrupts (one for each channel-pair), and
•2 clock output signals (user configurable).
5.3.1 Signaling Interface Pins
Figure 19 Signaling Example: Two Subscriber Lines
Subscriber Lines
SI1_0
SI1_1
SB1_2
SO1_1
SB1_1
Channel 1
SO1_0
SB1_0
Channel 2
SI2_0
SI2_1
SB2_2
SO2_1
SB2_1
SO2_0
SB2_0
SICOFI2-µC
INT 12
t/r t/r
Operating
Mode
Off-Hook Det.
Ring Relay
Status LED
Ring Relay
Status LED
Ground Key Det.
SLIC 2SLIC 1
Operating
Mode
Off-Hook Det.
Ground Key Det.
CHCLK1 CHCLK2
39
38
37
36
35
41
40 43
42
48
47
46
45
44
33 16
34
Microcontroller
2266_220
PEB 2266
PEF 2266
Interface Description
Hardware Reference Manual 33 2001-02-20
Table 24 Signaling Interface: Pins and Functions for SLIC Interfaces
5.3.2 Debouncing Functions and Interrupt Generation
All signaling inputs are sampled at programmable intervals (Field N in register XR4). If
all the inputs assigned to one channel-pair (1&2) have been stable for two subsequent
samples their values are stored in the signaling registers and the associated interrupt
output (INT12) is set high. Refer to the Programmer’s Reference Manual for further
details on this function.
5.3.3 Clock Output Signals
Two programmable Chopper Clock Output signals are provided by the PEB 2266:
•CHCLK1 (Pin 33) is configured in register XR4.Field T (bits XR4.3 to XR4.0)
•CHCLK2 (Pin 16) is configured in register XR5.CHCLK2 (bits XR5.3 and XR5.2)
•Both Chopper Clock Output signals are only available if a valid Master Clock signal is
applied to pin MCLK.
•CHCLK2 = 16,384 kHz: Requires at least one channel in POWER-UP state.
Table 25 Clock Programming
Channel 1 Channel 2
Pin Symbol Function Pin Symbol Function
36 SI1_0 Signaling Input 0 47 SI2_0 Signaling Input 0
35 SI1_1 Signaling Input 1 48 SI2_1 Signaling Input 1
41 SO1_0 Signaling Output 0 42 SO2_0 Signaling Output 0
40 SO1_1 Signaling Output 1 43 SO2_1 Signaling Output 1
39 SB1_0 Bi-directional Signaling 0 44 SB2_0 Bi-directional Signaling 0
38 SB1_1 Bi-directional Signaling 1 45 SB2_1 Bi-directional Signaling 1
37 SB1_2 Bi-directional Signaling 2 46 SB2_2 Bi-directional Signaling 2
34 INT12 Interrupt Output, Channels 1+2, active high
CHCLK1 CHCLK2
XR4.Field T Output (Pin 33) XR5.CHCLK2 Output (Pin 16)
0000 High level (+5V) 00 High level (+5V)
0001 to 1110 Clock period = T *2ms
(min. 2 ms, max. 28 ms)
01 512 kHz signal
10 256 kHz signal
1111 Low level (0V) 11 16,384 kHz signal
PEB 2266
PEF 2266
Interface Description
Hardware Reference Manual 34 2001-02-20
5.4 Serial Microcontroller Interface
The Serial Microcontroller Interface is used to access the SICOFI®2-µC’s internal
registers and the Coefficient RAM (CRAM). The Serial Microcontroller Interface consists
of four pins: two data pins (DIN, DOUT), one clock pin (DCLK) and one pin for chip select
(CS#). If DIN and DOUT are strapped together, only three microcontroller I/O pins are
required to build this interface.
Figure 20 Serial Microcontroller Interface
5.4.1 Serial Microcontroller Interface Pins
Table 26 Serial Microcontroller Interface: Pins and Functions
Symbol Pin Function
CS# 17 Chip Select, enable to read or write data, active low.
DCLK 18 Data Clock, shifts data from or to device; max. clock rate is 8192 kHz.
DIN 19 Control Data Input; sampled with rising edge of DCLK.
DOUT 20 Control Data Output; bits are shifted with the falling edge of DCLK;
DOUT is in high impedance state when no data is transmitted from
the SICOFI®2-µC.
SICOFI2-µC
Microcontroller
Out InOut Out
CS# DOUTDCLK DIN
SICOFI2-µC
Microcontroller
Out Out I/O
CS# DOUTDCLK DIN
Configuration A:
Separate DIN, DOUT
Configuration B:
Bi-Directional Data
2266_221
PEB 2266
PEF 2266
Interface Description
Hardware Reference Manual 35 2001-02-20
5.4.2 Write Access
Following a falling edge of CS#, the first eight bits received on DIN specify the type of
command. The data bytes following a write command are stored in the selected
configuration registers or the selected part of the Coefficient RAM. The number of data
bytes depends on the type of command. After every command CS# must be set to ’1’.
.
Figure 21 Example for a Two-Byte Write Access
5.4.3 Read Access
If the first eight bits received via DIN represent a read command, the SICOFI®2-µC will
initiate its response via DOUT. An identification byte (81H) is followed by the requested
number of data bytes (contents of configuration registers or contents of the CRAM).
During execution of a read command, the device will ignore data on DIN. After every
command CS# must be set to ’1’.
.
Figure 22 Example for a One-Byte Read Access
2266_222
76543210 0123456701234567DIN
DOUT
DCLK
CS#
Write Command Data Byte 1 Data Byte 2
High 'Z'
2266_223
76543210DIN
DOUT
DCLK
CS#
Read Command
Data Byte 1
High 'Z' 7654321076543210 High 'Z'
Identification 81
H
PEB 2266
PEF 2266
Interface Description
Hardware Reference Manual 36 2001-02-20
For byte-by-byte transfer, the high time of DCLK can be prolonged, resulting in a
user-defined ‘waiting time’ between bytes. This mechanism can be used for writing to
and reading from the device.
Figure 23 Example for a Read Access with Byte-by-Byte Transfer
Read and write commands can be chained by leaving CS# low after the completion of
each command sequence.
For read or write access to individual registers, the command sequence may be
terminated by rising CS# after the transmission of any number of bytes.
5.4.4 Three-Wire Access
DIN and DOUT may be strapped together and connected to a single I/O pin of the
microcontroller. The interface remains fully functional with only three wire connections.
After every command CS# must be set to ’1’.
Figure 24 Bi-Directional Data Signal: DIN and DOUT Strapped Together
76543210DIN
DOUT
DCLK
CS#
Read Command
Data Byte 1
High 'Z' High 'Z'
7654321 076543210
Identification 81
H
2266_224
DATA
DCLK
CS#
Read Command Identification 81
H
High 'Z'
Data Byte 1
765432107654321076543210
2266_225
PEB 2266
PEF 2266
Programming Overview
Hardware Reference Manual 37 2001-02-20
6 Programming Overview
The transmission characteristics and interfaces of the PEB 2266 can be adapted to
various environments. Configuring the functional blocks and programming the digital
filter behavior is accomplished by loading values to the Configuration Registers and the
Coefficient RAM (CRAM). Software utilities are available to determine the appropriate
register and CRAM values (see Programmer’s Reference Manual).
6.1 Programming Overview
The SICOFI®2-µC has eight Common Configuration Registers (XR0 to XR7). Settings in
these registers affect all two channels.
Each of the two channels has six Channel-Specific Configuration Registers (CR0 to
CR5). Settings in these registers affect only the designated channel.
The filters of each channel are individually programmable through channel-specific
coefficients in CRAM. There are two global sets of TH Filter coefficients that can be
assigned to any channel.
6.1.1 Register Model
Channel-specific and Common Configuration Registers and coefficients are shown in
Table 27.
Table 27 Register Model
Configuration Registers and CRAM Channel Usage
XR0 to XR7 (8 bytes) common
CR0 to CR5 (6 bytes)
channel-specific
IM/R1 Coefficients (16 bytes)
FRR, FRX Coefficients (16 bytes)
AR1, AR2, AX1, and AX2 Coefficients (8 bytes)
TG1 and TG2 Coefficients (8 bytes)
TH Coefficient Set 1 (24 bytes) one coefficient set per
channel
TH Coefficient Set 2 (24 bytes)
PEB 2266
PEF 2266
Programming Overview
Hardware Reference Manual 38 2001-02-20
6.1.2 Register Maps
Table 28 Read Access to Common Configuration Register (XR) Map
Table 29 Write Access to Common Configuration Register (XR) Map
Table 30 Channel-Specific Configuration Register (CR) Map (Read & Write)
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
XR0 0 0 0 0 SI2_1 SI2_0 SI1_1 SI1_0
XR1 0 0 0 0 SB2_1 SB2_0 SB1_1 SB1_0
XR2 0 0 0 0 PSB2_1 PSB2_0 PSB1_1 PSB1_0
XR3 0 0 SB2_2 SB1_2 0 0 PSB2_2 PSB1_2
XR4 Signal Debounce CHCLK1
XR5 MCLK-SEL CRSH-A CRSH-B CHCLK2 Version
XR6 C-Mode X-S R-S DRV_0 Shift PCM-OFFSET
XR7 OF7OF6OF5OF4OF3OF2OF1OF0
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
XR0 0 0 0 0 SO2_1 SO2_0 SO1_1 SO1_0
XR1 0 0 0 0 SB2_1 SB2_0 SB1_1 SB1_0
XR2 0 0 0 0 PSB2_1 PSB2_0 PSB1_1 PSB1_0
XR3 0 0 SB2_2 SB1_2 0 0 PSB2_2 PSB1_2
XR4 Signal Debounce CHCLK1
XR5 MCLK-SEL CRSH-A CRSH-B CHCLK2 Version
XR6 C-Mode X-S R-S DRV_0 Shift PCM-OFFSET
XR7 OF7OF6OF5OF4OF3OF2OF1OF0
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
CR0 TH IM/R1 FRX FRR AX AR TH-SEL
CR1 ETG2 ETG1 PTG2 PTG1 LAW 0 0 PU
CR2 COT/R 0 IDR LM LMR V+T
CR3 TEST-Loops AGX AGR D-HPX D-HPR
CR4 R-way RS6 RS5 RS4 RS3 RS2 RS1 RS0
CR5 X-way XS6 XS5 XS4 XS3 XS2 XS1 XS0
PEB 2266
PEF 2266
Programming Overview
Hardware Reference Manual 39 2001-02-20
6.1.3 CRAM Structure
Coefficient RAM (CRAM) is used to store the individual coefficients calculated for each
channel. The coefficients can be written and read through the Microcontroller Interface.
The IM, FRX, FRR, AX, AR, TG1, TG2, and TH coefficients are accessed through the
Coefficient Operation (COP) Command Sequences which include the channel address
(see Programmer’s Reference Manual Chapter 6.5).
Channel-specific coefficients always belong to their designated channel. Common
coefficients (TH) can be assigned to any of the two channels through field TH-SEL in
CR0 (see Figure 25).
Figure 25 Channel-Specific and Common Coefficients
Table 31 Coefficient RAM (CRAM) Structure per Channel
IM Part 1 8 Coefficient Bytes
IM Part 2 8 Coefficient Bytes
FRX 8 Coefficient Bytes
FRR 8 Coefficient Bytes
AX 4 Coefficient Bytes
AR 4 Coefficient Bytes
TG1 4 Coefficient Bytes
TG2 4 Coefficient Bytes
2266_226
Common Coefficients
Channel Specific
Coefficients
Set 1
TH Part
1, 2, 3
Set 2
TH Part
1, 2, 3
Channel 2
IM Part 1 & 2,
FRX, FRR,
AX, AR,
TG1, TG2
Channel 1
IM Part 1 & 2,
FRX, FRR,
AX, AR,
TG1, TG2
Channel Specific
Coefficients
PEB 2266
PEF 2266
Programming Overview
Hardware Reference Manual 40 2001-02-20
Table 32 Coefficient RAM (CRAM) Structure per Set
6.2 Types of Commands and Data Bytes
Coefficients and register contents are programmed and accessed through command
sequences via the Microcontroller Interface. There are three types of command
sequences:
•Extended Operation (XOP) for access to the Common Configuration Registers (XR0
to XR7) including the Control Registers for the signaling interface.
•Status Operation (SOP) for access to the Channel-Specific Registers (CR0 to CR5),
e.g. enabling and disabling of filters, time slot assignment, and test loops.
•Coefficient Operation (COP) for access to the CRAM structures. Coefficients can be
written to the SICOFI®2-µC, and also read back.
Table 33 Types of Commands and Data Bytes.
With the first byte received via DIN, a command type is selected through bits 3 and 4. A
two-bit address field (AD) in the COP and SOP commands allows access to the
channel-specific structures (CRAM and CR registers). Since the XR Registers are
common for all channels, no address field is required within the XOP command byte.
All three commands allow read and write access, which is indicated by bit 5 (RW). The
bit fields LSEL and CODE specify the type and the length of data that follows the
command.
TH Part 1 8 Coefficient Bytes
TH Part 2 8 Coefficient Bytes
TH Part 3 8 Coefficient Bytes
76543210
XOP RST 0 RW 11 LSEL
SOP AD RW 10 LSEL
COP AD RW 0CODE
PEB 2266
PEF 2266
Application Hints
Hardware Reference Manual 41 2001-02-20
7 Application Hints
7.1 Support Tools
7.1.1 Development Board
The Evaluation Package EASY 2466 includes the following hardware:
•One SICOFI®2-µC Evaluation Board STUT 2466 with connectors for four optional
SLIC daughter cards and BNC connectors to a PCM backplane.
•One microcontroller board EVC50x with RS-232 interface that translates data from a
PC to SICOFI®2-µC format.
•Two SLIC Babyboards STUT 5502 with HARRIS SLIC HC 5502 mounted.
The QSICOS software enables the calculation of the coefficients and the download of
the setup file to the evaluation board.
This setup allows measurements and optimization of the actual behavior of a complete
transmission system. The EASY 2466 evaluation system connects directly to
industry-standard test equipment.
Figure 26 Development System with STUT 2466 Evaluation Board
PCM in PCM out Clock out 4 wire in 2 wire 4 wire out
SLC2
SLC1
SLC4
SLC3
S1
out in in/
out
in/
out
ST2
ST1
SICOFI2/4
-µC/-TE
PCM PCLK FSC
Evaluation Board EVC50x
sw1
P4
Power Supply
reset EVC
SLIC (STUT5502)
ST3
COM 1
DC Loop-Holding
circuit
FSC in
tip ring
PC
SICOFIx -µC/-TE
Eval. Board V1.4
STUT 2466
PCM-4
PEB 2266
PEF 2266
Application Hints
Hardware Reference Manual 42 2001-02-20
7.2 Guidelines for Board Design
7.2.1 Filter Capacitors
•For high frequency noise rejection, use 100 nF SMD ceramic capacitors on pins
VDDA12, VDDA and VDDREF and connect to GNDA. Additional 2.2 µF tantalum capacitors
are recommended.
•Use one 100 nF SMD ceramic capacitor on pin VDDD and connect to GNDD.
•Use a 1 µF – 10 µF tantalum capacitor from +5 V supply to GND (central blocking).
Note: All blocking capacitors MUST be placed as close as possible to the
SICOFI®2-µC pins.
.
Figure 27 SICOFI®2-µC Test Circuit Configuration
SICOFI2-µC
PEB 2266-H
PCLK
FSC
DRB
DXB
TCB#
DRA
DXA
TCA#
V
DDD
RESET#
MCLK
GNDD
DOUT
DIN
DCLK
CS#
NC
NC
V
IN2
GNDA
NC
V
DDA
NC
GNDA
V
DDREF
V
REF
GNDA2
V
OUT2
V
DDA12
V
OUT1
GNDA1
V
IN1
CHCLK1
INT12
SI1_1
SI1_0
SB1_2
SB1_1
SB1_0
SO1_1
SO1_0
SO2_0
SO2_1
SB2_0
SB2_1
SB2_2
SI2_0
SI2_1
CHCLK2
NC
NUI
NUI
NUIO
NUIO
NUIO
NC
NC
NC
NC
NUIO
NUIO
NUIO
NUI
NUI
1-10µF100nF
10K
PCM Interface
Micro-
controller
Interface
Signaling Interface, Channels 1&2
Analog Interface
2.2µF 100nF
116
17
32
3348
49
64
5V
5 x 680K
5 x 680K
10µF
1µF
2.2µF 100nF
1µF
220nF
2.2µF 100nF
100nF
100nF
5V
5V
5V
10µF
6 x 680K
5V
4.7K
5V
4.7K
2266_228
PEB 2266
PEF 2266
Application Hints
Hardware Reference Manual 43 2001-02-20
7.3 Proposal for SICOFI®2-µC Board Design
For a new layout design it is recommended to use a separate ground-layer which gives
the possibilty to connect all ground-pins of the SICOFI®2-µC (GNDA and GNDD) low-
ohmic together.
Furthermore, an optimum board layout should follow these recommendations
• Separate all digital supply lines from analog supply lines as far as possible
• Applying the standard practice regarding blocking capacitors is recommended
• Place all SLIC circuits as close as possible to the Vinx/Voutx pins of the SICOFI
• Separate all analog circuitry (especially SLIC and Vinx/Voutx) as far as possible from
any digital signal source (esp. clock signals)
Figure 28 Proposal for a Ground Concept
VDD is the grey colored layer and the Ground-plane is the black colored layer. The
Ground-plane should be on both sides of the board on the top and on the ground layer.
49 51 5352 55 56 5857 60 6261 64
100 nF
GND
1-10 F
Tantal
V
DD
µ
PEB 2266 H
Ground-
plane
DDD
GNDD
V
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1718192024 22232526272829303132
GNDA2
GNDA
GNDA
VDDA12
GNDA1
VDDREF
VREF
Connector
Connector
next to the
connector pins
21
50
DDA
V
Ceramic nF
Ceramic
nF100
nF100
nF220
63
59
54
Ceramic
100
Ceramic
The ground-plane should
be used for shielding
SICOFI2-µC V2.2
PEB 2266
PEF 2266
Electrical Characteristics and Timing Diagrams
Hardware Reference Manual 44 2001-02-20
8 Electrical Characteristics and Timing Diagrams
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
8.1 Absolute Maximum Ratings
Parameter Symbol Limit Values Unit Test
Condition
min. max.
VDD referred to GNDD –0.3 7.0 V
GNDA to GNDD –0.6 0.6 V
Analog input and output voltage
Referred to VDD = 5 V;
Referred to GNDA = 0 V
–5.3
–0.3
0.3
5.3
V
V
All digital input voltages
Referred to GNDD = 0 V; (VDD =5V)
Referred to VDD = 5 V; (GNDD = 0 V)
–0.3
–5.3
5.3
0.3
V
V
DC input and output current at any input
or output pin (free from latch-up) 10 mA
Storage temperature TSTG –60 125 °C
Ambient temperature under bias TA–10 80 °C
Power dissipation (package) PD1W
PEB 2266
PEF 2266
Electrical Characteristics and Timing Diagrams
Hardware Reference Manual 45 2001-02-20
8.2 Operating Range
VDD = 5 V ±5%; GNDD = 0 V; GNDA = 0 V;
TA = 0 °C to +70 °C (PEF 2266: -40 °C to +85 °C)
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
VDD supply current: IDD FSC = 8 kHz,
Standby (PEB 2266) 0.5 1.0 mA PCLK = MCLK =
Standby (PEF 2266) 0.5 1.5 mA 2.048 MHz,
1 channel operating 14 25 mA no loads,
2 channels operating 18 30 mA PCM idle codes,
Power supply rejection
ratio (either direction) PSRR 30 dB
Ripple: sine wave
1014 Hz, 70 mVrms,
on every supply pin,
AGX=AGR=AX=AR=0dB
(see Chapter 4.2.4)
8.3 Digital Interface
VDD = 5 V ± 5%; GNDD = 0 V; GNDA = 0 V
TA = 0 °C to +70 °C (PEF 2266: -40 °C to +85 °C);
Parameter Symbol Limit Values Unit Test Condition
min. max.
Input voltages:
Low level VIL –0.3 0.8 V
High level VIH 2.0 V
Output voltages:
Low level VOL 0.45 V IOL = – 2mA
Low level VOL 0.8 V IOL = – 5mA
High level VOH 4.4 V IOH = 0.4 mA
High level VOH 4.0 V IOH = 2 mA
High level VOH 2.4 V IOH = 5 mA
Input leakage current VIL ±1µA–0.3 ≤ VIN ≤ VDD
PEB 2266
PEF 2266
Electrical Characteristics and Timing Diagrams
Hardware Reference Manual 46 2001-02-20
8.4.1 Coupling Capacitors at the Analog Interface
Coupling capacitors are required on pins VIN and VOUT.
The recommended value for VIN is >39 nF. The required value for the VOUT capacitor
depends on the input impedance of the SLIC (see Figure 16 in Chapter 5.1).
8.5 Reset Timing
To reset the SICOFI®2-µC to Reset State, logic low pulses applied to pin RESET# must
be below 1.2 V (TTL-Schmitt-Trigger Input) and must persist longer than 3 µs.
Note: Spikes shorter than 1 µs will be ignored.
8.4 Analog Interface
VDD = 5 V ±5%; GNDD = 0 V; GNDA = 0 V;
TA = 0 °C to +70 °C (PEF 2266: -40 °C to +85 °C)
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Input resistance
PEF 2266
PEB 2266
Ri160
160
270
270
500
380
kΩ
kΩ0 ≤ VIN ≤ VDD
Output resistance RO0.25 Ω
Output load RL
CL
300
50 Ω
pF
Input leakage current IIL ±0.1 ±1.0 µA 0 ≤ VIN ≤ VDD
Input offset voltage VIO ±50 mV
Output offset voltage VOO ±50 mV
Input voltage range (AC) VIN ±2.223 V
PEB 2266
PEF 2266
Electrical Characteristics and Timing Diagrams
Hardware Reference Manual 47 2001-02-20
8.6 PCM-Interface Timing
8.6.1 Single Clocking Mode
Figure 29 PCM Interface Timing in Single Clocking Mode
Parameter Symbol Limit Values Unit
min. typ. max.
Period of PCLK tPCLK 1/8192 1/128 ms
PCLK high time tPCLKh 0.4*tPCLK tPCLK/2 0.6*tPCLK µs
Period FSC tFSC 125 µs
FSC setup time tFSC_s 10 50 ns
FSC hold time tFSC_h 40 50 ns
DRA/B setup time tDR_s 10 50 ns
DRA/B hold time tDR_h 10 50 ns
DXA/B delay time 1)
1) Min. delay times: intrinsic time, caused by internal processing. Max. delay times: min. time + delay caused by
external components CLoad and RPullup.: tC_Load = 0.4ns*CLoad/pF,
tC*R = RPullup*CLoad; RPullup>1.5kΩ
tdDX 25 tdDX_min + tC_Load ns
DXA/B delay time to high Z tdDXhz 25 50 ns
TCA#/TCB# delay time on tdTCon 25 tdTCon_min + tC_Load ns
TCA#/TCB# delay time off tdTCoff 25 tdTCoff_min + tC*R ns
2266_229
t
PCLK
PCLK
FSC
DRA/B
DXA/B
FSC_S
t
PCLKh
t
High Imp.
t
DR_S DR_H
t
t
dDX dDXhz
t
t
FSC_H
FSC
t
TCA#/TCB#
dTCon
tt
dTCoff
50%
PEB 2266
PEF 2266
Electrical Characteristics and Timing Diagrams
Hardware Reference Manual 48 2001-02-20
8.6.2 Double Clocking Mode
Figure 30 PCM Interface Timing in Double Clocking Mode
Parameter Symbol Limit Values Unit
min. typ. max.
Period of PCLK tPCLK 1/8192 1/256 ms
PCLK high time tPCLKh 0.4*tPCLK tPCLK/2 0.6*tPCLK µs
Period FSC tFSC 125 µs
FSC setup time tFSC_s 10 50 ns
FSC hold time tFSC_h 40 50 ns
DRA/B setup time tDR_s 10 50 ns
DRA/B hold time tDR_h 10 50 ns
DXA/B delay time 1)
1) Min. delay times: intrinsic time, caused by internal processing. Max. delay times: min. time + delay caused by
external components CLoad and RPullup.: tC_Load = 0.4ns*CLoad/pF,
tC*R = RPullup*CLoad; RPullup>1.5kΩ
tdDX 25 tdDX_min + tC_Load ns
DXA/B delay time to high Z tdDXhz 25 50 ns
TCA#/TCB# delay time on tdTCon 25 tdTCon_min + tC_Load ns
TCA#/TCB# delay time off tdTCoff 25 tdTCoff_min + tC*R ns
2266_230
t
PCLK
PCLK
FSC
DRA/B
DXA/B
FSC_S
t
PCLKh
t
High Imp.
t
DR_S DR_H
t
t
dDX dDXhz
t
t
FSC_H
FSC
t
TCA#/TCB#
dTCon
t t
dDTCoff
50%
PEB 2266
PEF 2266
Electrical Characteristics and Timing Diagrams
Hardware Reference Manual 49 2001-02-20
8.7 Microcontroller Interface Timing
Figure 31 Timing of the Microcontroller Interface
Parameter Symbol Limit Values Unit
min. typ. max.
Period of DCLK tDCLK 1/8192 ms
DCLK high time tDCLKh 0.4*tDCLK tDCLK/2 0.6*tDCLK µs
CS# setup time tCS_s 10 50 ns
CS# hold time tCS_h 30 50 ns
DIN setup time tDIN_s 10 50 ns
DIN hold time tDIN_h 10 50 ns
DOUT delay time 1)
1) All delay times are made up by two components: an intrinsic time (min-time), caused by internal processing,
and a second component tC_Load = 0.4ns*CLoad/pF, caused by external circuitry (C-load).
tdDOUT 30 tdDOUT_min + tC_Load ns
DOUT delay time to high Z tdDOUThz 30 50 ns
2266_231
DCLK
CS#
DIN
DOUT
CS_S
t
High Imp.
t
DIN_S DIN_H
t
t
dDOUT dDOUThz
t
t
DCLKh
DCLK
t
t
CS_h
50%
PEB 2266
PEF 2266
Electrical Characteristics and Timing Diagrams
Hardware Reference Manual 50 2001-02-20
8.8 Signaling Interface Timing
8.8.1 Timing from the µC Interface to the SO/SB-pins
Figure 32 Signaling Output Timing (data downstream)
8.8.2 Timing from the SI/SB-pins to the µC Interface
The register update and interrupt behavior resulting from signaling input changes (data
upstream – pins SI and SB, if programmed as signaling inputs) depend on internal
sampling clocks, counters and register settings. See Chapter 5.3.2 for a functional
description.
Parameter Symbol Limit Values Unit
min. typ. max.
SO/SB delay time 1)
1) All delay times are made up by two components: an intrinsic time (min-time), caused by internal processing,
and a second component tC_Load = 0.4ns*CLoad/pF, caused by external circuitry (C-load).
tdSout 30 tdSout_min+ tC_Load ns
SB to ‘Z’ - time tdSBZ 40 100 ns
SB to ‘drive’-time tdSBD 40 tdSBD_min+ tC_Load ns
DCLK
Bit 2DIN
SO/SB Output Old Value New Value
SB
(Output Input)
Output)
(Input
SB
dSBD
t
High Imp.
t
dSBZ
t
dSout
High Imp.
Bit 1 Bit 0
2266_232
PEB 2266
PEF 2266
Test Modes
Hardware Reference Manual 51 2001-02-20
9Test Modes
Each SICOFI®2-µC channel has four test loops that feed the analog input signal back to
the analog output (analog test loops), and five test loops that feed the PCM input signal
back to the PCM output.
Note: The signal path can also be cut off at two different points per receive and transmit
direction.
9.1 Analog Loops
The four analog loops feed signals from the transmit path back into the receive path.
Figure 33 shows the locations of the analog loops.
Figure 33 Analog Loops
Table 34 Analog Loop Programming in Register CR3, Bits 7 to 4
Test-Loops Analog Loops (CR3.7 = 0)
0000 All loops are disabled (normal operation).
0001 ALB-PFI Analog Loop Back via PREFI-POFI is selected.
0011 ALB-4M Analog Loop Back via 4 MHz is selected.
0100 ALB-PCM Analog Loop Back via 8 kHz (PCM) is selected and in all
channels active.
(required slope setting in XR6.6, XR6.5 = 00 or 11).
0101 ALB-8K Analog Loop Back via 8 kHz (linear) is selected.
2266_233
Receive Path
Transmit Path
Analog
Output
Analog
Input
PCM
Input
PCM
Output
IM1 TH
Digital Gain 2
Digital Gain 2
IM2
Frequency
Response
Digital Gain 1
Frequency
Response
Digital Gain 1
HPX
HPR
ADC
DAC
AGX
AGR
CMP
EXP
ALB-PFI
ALB-4M
ALB-8K
ALB-PCM
PEB 2266
PEF 2266
Test Modes
Hardware Reference Manual 52 2001-02-20
9.2 Digital Loops
The digital loops feed signals from the receive path back to the transmit path. There are
five digital loops, which are shown in Figure 34.
Figure 34 Digital Loops
Table 35 Digital Loop Programming in Register CR3, Bits 7 to 4
Test-Loops Digital Loops (CR3.7 = 1)
1000 DLB-ANA Digital Loop Back via analog port is selected.
1001 DLB-4M Digital Loop Back via 4 MHz is selected.
1100 DLB-128K Digital Loop Back via 128 kHz is selected.
1101 DLB-64K Digital Loop Back via 64 kHz is selected.
1111 DLB-PCM Digital Loop Back via PCM Registers is selected.
Receive Path
Transmit Path
Analog
Output
Analog
Input
PCM
Input
PCM
Output
IM1 TH
Digital Gain 2
Digital Gain 2
DLB-PCM
DLB-64K
DLB-ANA
DLB-4M
IM2
DLB-128K
Frequency
Response
Digital Gain 1
Frequency
Response
Digital Gain 1
HPX
HPR
ADC
DAC
AGX
AGR
CMP
EXP
2266_234
PEB 2266
PEF 2266
Test Modes
Hardware Reference Manual 53 2001-02-20
9.3 Cut-Off’s
The transmit path and the receive path can be cut off at two locations each. Figure 35
shows the locations in the signal paths.
Figure 35 Cut-Off’s
Table 36 Cut-Off Programming in Register CR2, Bits 7 to 5.
COT/R Cut-Off’s in the Transmit and the Receive Paths
000 All Cut-offs disabled (Normal Operation).
001 COT16 Cut Off Transmit path at 16 kHz (input of TH-Filter).
010 COT8 Cut Off Transmit path at 8 kHz (shortens the input of the
compressor unit to ground, resulting in PCM idle codes in the
transmit time slot).
101 COR4M Cut Off Receive path at 4 MHz (POFI-output).
110 COR64 Cut Off Receive path at 64 kHz (IM-filter input).
2266_235
Receive Path
Transmit Path
Analog
Output
Analog
Input
PCM
Input
PCM
Output
IM1 TH
Digital Gain 2
Digital Gain 2
IM2
Frequency
Response
Digital Gain 1
Frequency
Response
Digital Gain 1
HPX
HPR
ADC
DAC
AGX
AGR
CMP
EXP
COT8COT16
COR64
COR4M
PEB 2266
PEF 2266
Package Outlines
Hardware Reference Manual 54 2001-02-20
10 Package Outlines
P-MQFP-64
(Plastic Metric Quad Flat Package)
GPM05250
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.Dimensions in mm
SMD = Surface Mounted Device
PEB 2266
PEF 2266
Glossary
Hardware Reference Manual 55 2001-02-20
11 Glossary
AC Alternating Current
ADC Analog-to-Digital Converter
CMOS Complementary Metal Oxide Semiconductor
CRAM Coefficient RAM
DAC Digital-to-Analog Converter
DC Direct Current
DLC Digital Loop Carrier
DSP Digital Signal Processor
DTMF Dual Tone Multi Frequency
FIR Finite Impulse Response
FTTC Fiber-To-The-Curb
IIR Infinite Impulse Response
IOM-2 ISDN-Oriented Modular 2nd Generation
ITU International Telecommunication Union
ITU-T International Telecommunication Union-Telecommunication
Standardization Sector (formerly CCITT)
PBX Private Branch Exchange
PCM Pulse Code Modulation
PSTN Public Switched Telephone Network
PTT Post Telephone Telegraph
QSICOS Quad SICOFI Coefficient Software
RITL Radio-In-The-Loop
RT Remote Terminal
SICOFI Signal Processor Codec Filter
SLIC Subscriber Line Interface Circuit
t/r tip/ring
PEB 2266
PEF 2266
Hardware Reference Manual 56 2001-02-20
Index
Symbols
µ-Law . . . . . . . . . . . . . . . 2, 11, 14, 19, 30
µ-Law mode . . . . . . . . . . . . . . . . . . 15, 22
Numerics
0 dBm0-Levels . . . . . . . . . . . . . . . . . . . 14
2-wire to 4-wire conversion. . . . . . . . . . 10
8-bit time slots. . . . . . . . . . . . . . . . . . . . . 2
A
A/µ-Law. . . . . . . . . . . . . . . . . . . . . . . . . . 3
A/D and D/A converters . . . . . . 11, 18, 26
A/D converters . . . . . . . . . . . . . . . . 14, 23
Absolute gain . . . . . . . . . . . . . . . . . . . . 17
Absolute group delay . . . . . . . . . . . . . . 18
Absolute maximum ratings . . . . . . . . . . 44
AC transmission characteristics . . . . . . 27
Accuracy of digital filters. . . . . . . . . 10, 11
ADC . . . . . . . . . . . . . . . . . . . . . . . 2, 3, 11
A-Law . . . . . . . . . . . . . . . 2, 11, 14, 19, 30
A-Law mode . . . . . . . . . . . . . . . . . . . . . 15
Ambient temperature . . . . . . . . . . . . . . 44
Analog ground pins. . . . . . . . . . . . 8, 9, 29
Analog I/O. . . . . . . . . . . . . . . . . . . . . . . . 2
Analog input . . . . . . . . . . . . . . . . . . . . . 13
Analog input/output pins . . . . . . . . . . . . 29
Analog Interface . . . . . . . . . . . . . 3, 27, 28
Analog interface . . . . . . . . . . . . . . . 14, 46
Analog Interface pins . . . . . . . . . . . . . . 29
Analog loop programming. . . . . . . . . . . 51
Analog loops. . . . . . . . . . . . . . . . . . . 3, 51
Analog output . . . . . . . . . . . . . . . . . . . . 13
Analog supply reference voltage . . . . . . 9
Analog supply voltage. . . . . . . . . . . . . . . 8
Analog voice input/output . . . . . . . . . . . . 8
Analog voltage levels . . . . . . . . . . . . . . 14
Application hints . . . . . . . . . . . . . . . . . . 41
Application Notes . . . . . . . . . . . . . . . . . . 1
AR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Architecture . . . . . . . . . . . . . . . . . . . . . . 2
Attenuation . . . . . . . . . . . . . . . . . . . . . 18
AX . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
B
Balancing filter. . . . . . . . . . . . . . . . . . . 26
Bi-directional signaling pins. . . . . . . 8, 33
Blocking capacitors . . . . . . . . . . . . . . . 42
Board design . . . . . . . . . . . . . . . . . . . . 42
Board layout . . . . . . . . . . . . . . . . . . . . 43
Byte-by-byte transfer . . . . . . . . . . . . . . 36
C
Ceramic capacitors . . . . . . . . . . . . . . . 42
Channel operating ranges . . . . . . . . . . 45
Channel-pair . . . . . . . . . . . . . . . . . . . . 33
Channels . . . . . . . . . . . . . . . . . . 2, 22, 37
Channel-specific coefficients. . . . . . . . 39
Channel-specific registers. . . .11, 12, 37, 38
Chip Select . . . . . . . . . . . . . . . . . . . 6, 34
Clock . . . . . . . . . . . . . . . . . 11, 32, 33, 34
Clock output signals . . . . . . . . . . . . . . . 2
Clock programming . . . . . . . . . . . . . . . 33
C-message . . . . . . . . . . . . . . . . . . . . . 19
Codec filter . . . . . . . . . . . . . . . . . . . . . . 2
Coefficient calculation &
configuration software . . . . . . . . . . . . . . 3
Coefficient Operation (COP) command . .40
Coefficient operation commands. . . . . 39
Coefficient RAM. . . . . . 11, 34, 35, 37, 39
Command sequences . . . . . . . . . . 36, 40
Command type . . . . . . . . . . . . . . . . . . 40
Commands . . . . . . . . . . . . . . . . . . . . . 35
Common configuration registers . . . 11, 37, 38
Compression . . . . . . . . . . . . . . . . . . . . . 3
Compressor. . . . . . . . . . . . . . . . . . . . . 11
Configuration of interfaces. . . . . . . . . . 27
Configuration registers . . . . . . . . . 35, 37
Control Data input/output pins. . . . . . . 34
PEB 2266
PEF 2266
Hardware Reference Manual 57 2001-02-20
Control data input/output pins. . . . . . . . 34
Conversion utilities . . . . . . . . . . . . . . . . 41
COP . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
COP command sequences. . . . . . . . . . 39
Country-specific adaptations . . . . . . . . 10
Coupling capacitors . . . . . . . . . 27, 29, 46
CR0 to CR5 . . . . . . . . . . . . . . . . . . . . . 37
CR0 to CR7 . . . . . . . . . . . . . . . . . . . . . 38
CRAM . . . . . . . . . . . 11, 34, 35, 37, 39, 40
CRAM structure . . . . . . . . . . . . . . . . . . 39
Crosstalk. . . . . . . . . . . . . . . . . . . . . . . . 22
CR-Registers . . . . . . . . . . . . . . . . . . . . 11
CS#. . . . . . . . . . . . . . . . . . . . . . . . . 34, 49
Cut-Off programming . . . . . . . . . . . . . . 53
Cut-Off’s . . . . . . . . . . . . . . . . . . . . . . . . 53
D
DAC . . . . . . . . . . . . . . . . . . . . . . . 2, 3, 11
Data bytes. . . . . . . . . . . . . . . . . . . . . . . 35
Data Clock . . . . . . . . . . . . . . . . . . . . . . . 6
Data clock. . . . . . . . . . . . . . . . . . . . . . . 34
Data input pins . . . . . . . . . . . . . . . . . . . . 6
Data output pins . . . . . . . . . . . . . . . . . . . 6
Data pins. . . . . . . . . . . . . . . . . . . . . . . . 34
Data rates . . . . . . . . . . . . . . . . . . 3, 11, 30
Data receive pins . . . . . . . . . . . . . . . . . . 7
Data transmit pins. . . . . . . . . . . . . . . . . . 7
DCLK . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Debouncing functions . . . . . . . . . . . 32, 33
Decimation . . . . . . . . . . . . . . . . . . . . . . 11
Detect specific tones. . . . . . . . . . . . . . . 10
Development boards. . . . . . . . . . . . . 3, 41
Digital filters . . . . . . . . . . . . . . . . . . . . . . 3
Digital ground pins . . . . . . . . . . . . . . . . . 6
Digital input. . . . . . . . . . . . . . . . . . . . . . 13
Digital interface. . . . . . . . . . . . . . . . . . . 45
Digital loop programming . . . . . . . . . . . 52
Digital loops . . . . . . . . . . . . . . . . . . . 3, 52
Digital output. . . . . . . . . . . . . . . . . . . . . 13
Digital supply voltage . . . . . . . . . . . . . . . 7
Digital switching & transmission system . . . . 2
Digital, programmable filters . . . . . . . . 10
DIN . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
DLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Double clocking mode timing. . . . . . . . 48
DOUT . . . . . . . . . . . . . . . . . . . . . . . . . 49
Driving capability . . . . . . . . . . . . . . . 3, 27
DSP core . . . . . . . . . . . . . . . . 2, 3, 10, 11
DTMF. . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Dynamic gain. . . . . . . . . . . . . . . . . . . . . 3
Dynamic range . . . . . . . . . . . . . . . . . . 11
E
EASY 2466 . . . . . . . . . . . . . . . . . . . 3, 41
EASY 2466 evaluation system . . . . . . 41
Echo . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Electrical characteristics . . . . . . . . . . . 44
Evaluation boards . . . . . . . . . . . . . . . . 41
EVC50x . . . . . . . . . . . . . . . . . . . . . . . . 41
Expander . . . . . . . . . . . . . . . . . . . . . . . 11
Expansion . . . . . . . . . . . . . . . . . . . . . . . 3
Extended Operation (XOP) command . . .40
Extended temperature range. . . . . . . . . 2
External amplifier. . . . . . . . . . . . . . . . . 27
External components. . . . . . . . . . . . . . 26
F
Fiber-to-the-Curb Systems . . . . . . . . . . 4
Filter capacitors . . . . . . . . . . . . . . . . . . 42
Filter characteristics. . . . . . . . . . . . . . . 10
Filter coefficients . . . . . . . . . . . . . . . . . 27
Filter coefficients storage. . . . . . . . . . . 11
Filter structures . . . . . . . . . . . . . . . . . . 11
Flow diagram. . . . . . . . . . . . . . . . . . . . 16
Fluctuation. . . . . . . . . . . . . . . . . . . . . . 10
Four-wire interface. . . . . . . . . . . . . . . . 10
Frame . . . . . . . . . . . . . . . . . . . . . . . . . 30
Frame delay. . . . . . . . . . . . . . . . . . . . . 30
Frame synchronization clock. . . . . . 7, 30
Frequency correction. . . . . . . . . . . . . . 11
Frequency response . . . . . . . . . 3, 18, 27
PEB 2266
PEF 2266
Hardware Reference Manual 58 2001-02-20
Frequency response corrections . . 10, 16
FRR . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
FRX. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
FSC. . . . . . . . . . . . . . . . . . . . . . . . . 47, 48
Functional blocks . . . . . . . . . . . . . . . . . 37
G
Gain . . . . . . . . . . . . . . . . . . . . . . . . 15, 26
Gain accuracy. . . . . . . . . . . . . . . . . . . . 17
Gain deviations with input level . . . . . . 17
Gain tracking. . . . . . . . . . . . . . . . . . . . . 17
Ground layer. . . . . . . . . . . . . . . . . . . . . 43
Ground pins . . . . . . . . . . . . . . . . . . . . . 43
Ground plane . . . . . . . . . . . . . . . . . . . . 43
Ground-key detection . . . . . . . . . . . . . . 10
Group delay . . . . . . . . . . . . . . . . . . 18, 26
Group delay absolute values . . . . . . . . 18
Group delay distortion. . . . . . . . . . . . . . 19
H
Hardware filters. . . . . . . . . . . . . . . . 11, 23
Hardware reset . . . . . . . . . . . . . . . . . . . 12
Harmonic distortion. . . . . . . . . . . . . . . . 20
High impedance state. . . . . . . . . . . . . . 34
Highway . . . . . . . . . . . . . . . . . . . . . . . . 11
HW-Reset . . . . . . . . . . . . . . . . . . . . . . . 12
I
I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . 32
Identification byte . . . . . . . . . . . . . . . . . 35
Idle channel noise. . . . . . . . . . . . . . . . . 19
IM-filter . . . . . . . . . . . . . . . . . . . . . . 26, 39
Impedance matching . . . . . . 3, 10, 11, 16
Independent filter structures . . . . . . . . . . 2
Industry–standard PCM Interface. . . . . 30
Input impedance . . . . . . . . . . . . 10, 29, 46
Input leakage current . . . . . . . . . . . 45, 46
Input offset voltage . . . . . . . . . . . . . . . . 46
Input pins . . . . . . . . . . . . . . . . . . . . 12, 32
Input resistance . . . . . . . . . . . . . . . 27, 46
Input voltage range (AC) . . . . . . . . . . . 46
Input voltages . . . . . . . . . . . . . . . . . . . 45
INT12. . . . . . . . . . . . . . . . . . . . . . . . . . 33
Interface description . . . . . . . . . . . . . . 27
Interfaces. . . . . . . . . . . . . . . . . . . . . . . 37
Intermodulation . . . . . . . . . . . . . . . . . . 20
Intermodulation distortion . . . . . . . . . . 20
Internal registers . . . . . . . . . . . . . . . . . 34
Interpolation. . . . . . . . . . . . . . . . . . . . . 11
Interrupt generation . . . . . . . . . . . . . . . 33
Interrupt output pins. . . . . . . . . . . . . . . 33
Interrupt pins . . . . . . . . . . . . . . . . . . . . 32
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 8
Inventory costs . . . . . . . . . . . . . . . . . . . 4
ITU-T . . . . . . . . . . . . . . . . . . . . . 3, 14, 16
K
Key Systems . . . . . . . . . . . . . . . . . . . . . 4
L
Level adjustments . . . . . . . . . . . . . 10, 11
Level metering. . . . . . . . . . . . . . . . . 3, 10
Line characterization . . . . . . . . . . . . . . 10
Linearity. . . . . . . . . . . . . . . . . . . . . . 3, 11
Linecard functions . . . . . . . . . . . . . . . . 10
Load capacities . . . . . . . . . . . . . . . . . . 14
Local requirements . . . . . . . . . . . . . . . 10
Loop filters. . . . . . . . . . . . . . . . . . . . . . 10
M
Manufacturing test. . . . . . . . . . . . . . . . . 3
Master clock . . . . . . . . . . . . . . . . . . 7, 33
Maximum signal levels . . . . . . . . . . . . 14
Measurements. . . . . . . . . . . . . . . . . . . 41
Microcontroller. . . . . . . . . . . . . . . . . . . 10
Microcontroller Interface . . 10, 34, 39, 40
Microcontroller interface timing . . . . . . 49
Microcontrollers . . . . . . . . . . . . . . . . . . 27
PEB 2266
PEF 2266
Hardware Reference Manual 59 2001-02-20
N
Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Noise rejection . . . . . . . . . . . . . . . . . . . 42
Non usable input. . . . . . . . . . . . . . . . . . . 6
Non usable input/output . . . . . . . . . . . . . 6
Not connected pins. . . . . . . . . . . . . . . 6, 9
O
On-/off-hook detection . . . . . . . . . . . . . 10
Operating conditions. . . . . . . . . . . . . . . 16
Operating range . . . . . . . . . . . . . . . . . . 45
Operating state . . . . . . . . . . . . . . . . 12, 13
Operating states . . . . . . . . . . . . . . . . . . 12
Operation of interfaces . . . . . . . . . . . . . 27
Operational description. . . . . . . . . . . . . 12
Optimization . . . . . . . . . . . . . . . . . . . . . 41
Out-of-band discrimination . . . . . . . 23, 24
Out-of-band idle channel noise. . . . . . . 25
Out-of-band signals . . . . . . . . . 23, 24, 27
Output load . . . . . . . . . . . . . . . . . . . . . . 46
Output offset voltage. . . . . . . . . . . . . . . 46
Output resistance . . . . . . . . . . . . . . . . . 46
Output voltages. . . . . . . . . . . . . . . . . . . 45
Overload compression . . . . . . . . . . . . . 22
Overload point . . . . . . . . . . . . . 14, 22, 27
Oversampling . . . . . . . . . . . . . . . . . . . . 11
P
Package . . . . . . . . . . . . . . . . . . . . . . . . . 3
Package Outlines . . . . . . . . . . . . . . . . . 54
Pair-Gain Systems . . . . . . . . . . . . . . . . . 4
PCLK . . . . . . . . . . . . . . . . . . . . . . . 47, 48
PCM clock. . . . . . . . . . . . . . . . . . . . . . . 30
PCM data clock. . . . . . . . . . . . . . . . . . . . 7
PCM data format. . . . . . . . . . . . . . . . . . 30
PCM Highway A . . . . . . . . . . . . . . . . . . . 7
PCM Highway B . . . . . . . . . . . . . . . . . . . 7
PCM highways . . . . . . . . . . . . 2, 3, 27, 30
PCM interface. . . . . . . . . . . . . . . 3, 14, 27
PCM interface pins . . . . . . . . . . . . . . . . 30
PCM interface timing . . . . . . . . . . . 47, 48
PCM ports . . . . . . . . . . . . . . . . . . . . . . 11
Peak amplitude . . . . . . . . . . . . . . . 14, 27
PEB 2466 . . . . . . . . . . . . . . . . . . . . . . . 1
Pin configuration . . . . . . . . . . . . . . . . . . 5
Pin definitions and functions . . . . . . . . . 6
Pin descriptions . . . . . . . . . . . . . . . . . . . 5
Pin diagram . . . . . . . . . . . . . . . . . . . . . . 5
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power dissipation . . . . . . . . . . . . . 12, 13
Power dissipation (package) . . . . . . . . 44
Power On. . . . . . . . . . . . . . . . . . . . . . . 12
Power spectral density . . . . . . . . . . . . 25
Power supply rejection ratio . . . . . . . . 45
Power-saving state . . . . . . . . . . . . . . . 12
POWER-UP state . . . . . . . . . . . . . . . . 33
Product Brief . . . . . . . . . . . . . . . . . . . . . 1
Product Overview . . . . . . . . . . . . . . . . . 1
Programmable debouncing . . . . . . . . . . 3
Programmable digital filters. . . . . . . . . . 3
Programmable filters . . . . . . . . . . . . . . 26
Programmable frequency . . . . . . . . . . 13
Programmable tone generators. . . . . . . 3
Programmer’s Reference Manual . . . . . 1
Programming overview . . . . . . . . . . . . 37
PSB 2132 . . . . . . . . . . . . . . . . . . . . . . . 1
PSB 2134 . . . . . . . . . . . . . . . . . . . . . . . 1
Psophometric. . . . . . . . . . . . . . . . . . . . 19
Q
QSICOS. . . . . . . . . . . . . . . . . . . . . . 3, 41
R
Radio-in-the-Loop Systems. . . . . . . . . . 4
Read access . . . . . . . . . . . . . . . . . 35, 38
Read commands . . . . . . . . . . . . . . 35, 36
Receive data input pins . . . . . . . . . . . . 30
Receive delay . . . . . . . . . . . . . . . . . . . 18
Receive path . . . . . . . . . . . 10, 51, 52, 53
Reference voltage pin . . . . . . . . . . . 9, 29
PEB 2266
PEF 2266
Hardware Reference Manual 60 2001-02-20
Register maps. . . . . . . . . . . . . . . . . . . . 38
Register model . . . . . . . . . . . . . . . . . . . 37
Register values. . . . . . . . . . . . . . . . . . . 13
Registers. . . . . . . . . . . . . . . . . . . . . . . . 11
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Reset state . . . . . . . . . . . . . . . . 12, 13, 46
Reset timing . . . . . . . . . . . . . . . . . . . . . 46
RESET# . . . . . . . . . . . . . . . . . . . . . . . . 12
RESET# pin . . . . . . . . . . . . . . . . . . . . . 46
Resolution. . . . . . . . . . . . . . . . . . . . . . . 11
Return loss . . . . . . . . . . . . . . . . . . . . . . 10
Ring signals . . . . . . . . . . . . . . . . . . . . . 10
RITL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
RST. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
S
Sampling. . . . . . . . . . . . . . . . . . . . . . . . 34
Sampling intervals . . . . . . . . . . . . . . . . 33
Sampling slopes . . . . . . . . . . . . . . . . . . 30
Schmitt-Trigger input . . . . . . . . . . . . . . 46
Serial input . . . . . . . . . . . . . . . . . . . . . . 13
Serial Interface . . . . . . . . . . . . . . . . . . . . 2
Serial Microcontroller Interface . . 10, 27, 34
Serial output . . . . . . . . . . . . . . . . . . . . . 13
Sigma-delta. . . . . . . . . . . . . . . . . . . . . . 11
Signal levels . . . . . . . . . . . . . . . . . . . 3, 15
Signal paths . . . . . . . . . . . . . . . . . . . . . 53
Signal power transfer . . . . . . . . . . . . . . 10
Signal processor. . . . . . . . . . . . . . . . . . 10
Signal reflections . . . . . . . . . . . . . . . . . 10
Signal rejection . . . . . . . . . . . . . . . . . . . 23
Signaling example . . . . . . . . . . . . . . . . 32
Signaling input pins. . . . . . . . . . . . . . 8, 33
Signaling input/output pins . . . . . . . . . . 11
Signaling Interface . . . . . . . . . . 10, 27, 32
Signaling Interface pins . . . . . . . . . . . . 33
Signaling interface timing . . . . . . . . . . . 50
Signaling output pins . . . . . . . . . . . . 8, 33
Signaling output timing . . . . . . . . . . . . . 50
Signaling pins . . . . . . . . . . . . . . . . . . 2, 32
Signaling registers . . . . . . . . . . . . . . . . 33
Signaling status changes. . . . . . . . . . . 32
Signal-to-noise performance . . . . . . . . 11
Signal-to-total distortion ratio. . . . . 20, 21
Sine wave signal . . . . . . . . . . . . . . . . . 14
Single clocking mode timing . . . . . . . . 47
Single frequency distortion . . . . . . . . . 22
SLIC. . . . . . . . . . . . . . 2, 3, 10, 16, 26, 27
SLIC daughter cards . . . . . . . . . . . . . . 41
SLIC interfaces . . . . . . . . . . . . . . . . . . 33
SOP. . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Specifications . . . . . . . . . . . . . . . . . . . 16
Spikes . . . . . . . . . . . . . . . . . . . . . . . . . 46
Standard temperature range . . . . . . . . . 2
Standby operating range . . . . . . . . . . . 45
Standby state. . . . . . . . . . . . . . . . . 12, 13
State diagram . . . . . . . . . . . . . . . . . . . 12
States . . . . . . . . . . . . . . . . . . . . . . 12, 13
Status Operation (SOP) command . . . 40
Storage temperature . . . . . . . . . . . . . . 44
Subscriber line interface circuits . . . 2, 10, 27
Subscriber lines. . . . . . . . . . . . . . . . . . 32
Supervision and signaling functions . . 32
Supply current . . . . . . . . . . . . . . . . . . . 45
Supply voltage. . . . . . . . . . . . . . . . . . . . 3
Supply voltage pins . . . . . . . . . . . . . . . 29
Support tools . . . . . . . . . . . . . . . . . . 3, 41
SW-Reset . . . . . . . . . . . . . . . . . . . . . . 12
System diagnostics . . . . . . . . . . . . . . . . 3
System tests . . . . . . . . . . . . . . . . . . . . . 3
T
Tantalum capacitors . . . . . . . . . . . . . . 42
Telco specification. . . . . . . . . . . . . . . . 27
Telephone line. . . . . . . . . . . . . . . . . . . 27
Telephone linecard . . . . . . . . . . . . . . . 10
Telephone subscriber loop . . . . . . . . . 10
Teletax filters . . . . . . . . . . . . . . . . . . . . 27
Teletax pulses . . . . . . . . . . . . . . . . 23, 27
Test circuit . . . . . . . . . . . . . . . . . . . . . . 42
Test conditions . . . . . . . . . . . . . . . . . . 16
Test loops . . . . . . . . . . . . . . . . . . . 26, 51
PEB 2266
PEF 2266
Hardware Reference Manual 61 2001-02-20
Test modes. . . . . . . . . . . . . . . . . . . . . . 51
Test relays . . . . . . . . . . . . . . . . . . . . . . 10
TG1 and TG2 . . . . . . . . . . . . . . . . . . . . 39
TH-filter. . . . . . . . . . . . . . . . . . . . . . 37, 39
Three-Wire access . . . . . . . . . . . . . . . . 36
Time slot assignment . . . . . . . . . . . . 3, 11
Time slots . . . . . . . . . . . . . . . . . . . . . 2, 30
Time to market . . . . . . . . . . . . . . . . . . . . 4
Timing. . . . . . . . . . . . . . . . . . . . 47, 49, 50
Timing diagrams . . . . . . . . . . . . . . . . . . 44
Tip & ring . . . . . . . . . . . . . . . . . . . . . . . 27
Tone generators . . . . . . . . . . . . . . . . 3, 10
Tool package . . . . . . . . . . . . . . . . . . . . 41
Total distortion receive/transmit . . . 20, 21
Total gain calculation . . . . . . . . . . . . . . 15
Transfer functions. . . . . . . . . . . . . . . . . 27
Transformer . . . . . . . . . . . . . . . . 3, 10, 27
Transformer SLIC . . . . . . . . . . . . . . . . . 27
Transhybrid balancing . . 3, 10, 11, 16, 26
Transhybrid loss . . . . . . . . . . . . . . . 10, 26
Transmission characteristics. . . 10, 14, 16, 37
Transmission system . . . . . . . . . . . . . . 41
Transmit control output pins . . . . . . . . . 30
Transmit control pins . . . . . . . . . . . . . . . 7
Transmit data output pins . . . . . . . . . . . 30
Transmit delay . . . . . . . . . . . . . . . . . . . 18
Transmit path . . . . . . . . . . . 10, 51, 52, 53
Two-wire interface . . . . . . . . . . . . . . . . 10
Types of commands . . . . . . . . . . . . . . . 40
V
VIN-pins . . . . . . . . . . . . . . . . . . . . . . . . 27
Voice channels . . . . . . . . . . . . . . . . . . . 11
Voltage levels . . . . . . . . . . . . . . . . . . . . 12
VOUT-pins . . . . . . . . . . . . . . . . . . . . . . 27
W
Waiting time . . . . . . . . . . . . . . . . . . . . . 36
Website. . . . . . . . . . . . . . . . . . . . . . . . . . 1
Write access . . . . . . . . . . . . . . . . . . 35, 38
Write commands . . . . . . . . . . . . . . 35, 36
X
XOP. . . . . . . . . . . . . . . . . . . . . . . . . . . 40
XR0 to XR7 . . . . . . . . . . . . . . . . . . . . . 38
XR-Registers . . . . . . . . . . . . . . . . . . . . 11
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