MT8870D-1 - Zarlink Semiconductor, Inc.

4-11

MT8870D/MT8870D-1

Integrated DTMF Receiver

Features

• Complete DTMF Receiver

• Low power consumption

• Internal gain setting ampliﬁer

• Adjustable guard time

• Central ofﬁce quality

• Power-down mode

• Inhibit mode

• Backward compatible with

MT8870C/MT8870C-1

Applications

• Receiver system for British Telecom (BT) or

CEPT Spec (MT8870D-1)

• Paging systems

• Repeater systems/mobile radio

• Credit card systems

• Remote control

• Personal computers

• Telephone answering machine

Description

The MT8870D/MT8870D-1 is a complete DTMF

receiver integrating both the bandsplit ﬁlter and

digital decoder functions. The ﬁlter section uses

switched capacitor techniques for high and low

group ﬁlters; the decoder uses

digital counting

techniques to detect and decode all 16 DTMF tone-

pairs into a 4-bit code. External component count is

minimized by on chip provision of a differential input

ampliﬁer, clock oscillator and latched three-state bus

interface.

Ordering Information

MT8870DE/DE-1 18 Pin Plastic DIP

MT8870DS/DS-1 18 Pin SOIC

MT8870DN/DN-1 20 Pin SSOP

-40

C to +85

Figure 1 - Functional Block Diagram

PWDN

IN +

IN -

OSC1 OSC2 St/GT ESt STD TOE

VDD VSS VRef INH

Bias

Circuit

Dial

Tone

Filter

High Group

Filter

Low Group

Filter

Digital

Detection

Algorithm

Code

Converter

and Latch

Steering

Logic

Chip

Power

Chip

Bias

VRef

Buffer

Zero Crossing

Detectors

to all

Chip

Clocks

ISSUE 5 March 1997

ISO

-CMOS

MT8870D/MT8870D-1

ISO

-CMOS

4-12

Figure 2 - Pin Connections

Pin Description

Pin #

Name Description

18 20

1 1 IN+

Non-Inverting Op-Amp

(Input)

2 2 IN-

Inverting Op-Amp

(Input)

33 GS

Gain Select.

Gives access to output of front end differential ampliﬁer for connection of

feedback resistor.

44 V

Ref

Reference Voltage (Output).

Nominally V

/2 is used to bias inputs at mid-rail (see Fig. 6

and Fig. 10).

5 5 INH

Inhibit (Input).

Logic high inhibits the detection of tones representing characters A, B, C

and D. This pin input is internally pulled down.

6 6 PWDN

Power Down (Input).

Active high. Powers down the device and inhibits the oscillator. This

pin input is internally pulled down.

7 8 OSC1

Clock

(Input)

8 9 OSC2

Clock

(Output)

. A 3.579545 MHz crystal connected between pins OSC1 and OSC2

completes the internal oscillator circuit.

910 V

Ground

(Input)

. 0V typical.

10 11 TOE

Three State Output Enable (Input).

Logic high enables the outputs Q1-Q4. This pin is

pulled up internally.

11-

12-

Q1-Q4

Three State Data (Output).

When enabled by TOE, provide the code corresponding to the

last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high

impedance.

15 17 StD

Delayed Steering (Output).

Presents a logic high when a received tone-pair has been

registered and the output latch updated; returns to logic low when the voltage on St/GT falls

below V

TSt

16 18 ESt

Early Steering (Output).

Presents a logic high once the digital algorithm has detected a

valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to

return to a logic low.

17 19 St/GT

Steering Input/Guard time (Output) Bidirectional.

A voltage greater than V

TSt

detected at

St causes the device to register the detected tone pair and update the output latch. A

voltage less than V

TSt

frees the device to accept a new tone pair. The GT output acts to

reset the external steering time-constant; its state is a function of ESt and the voltage on St.

18 20 V

Positive power supply (Input)

. +5V typical.

NC No Connection.

910

IN+

IN-

VRef

INH

PWDN

OSC1

OSC2

VSS

VDD

St/GT

ESt

StD

TOE

18 PIN PLASTIC DIP/SOIC

10 11

IN+

IN-

VRef

INH

PWDN

OSC1

OSC2

VSS

20 PIN SSOP

VDD

St/GT

ESt

StD

TOE

ISO

-CMOS

MT8870D/MT8870D-1

4-13

Functional Description

The MT8870D/MT8870D-1 monolithic DTMF

receiver offers small size, low power consumption

and high performance. Its architecture consists of a

bandsplit ﬁlter section, which separates the high and

low group tones, followed by a digital counting

section which veriﬁes the frequency and duration of

the received tones before passing the corresponding

code to the output bus.

Filter Section

Separation of the low-group and high group tones is

achieved by applying the DTMF signal to the inputs

of two sixth-order switched capacitor bandpass

ﬁlters, the bandwidths of which correspond to the low

and high group frequencies. The ﬁlter section also

incorporates notches at 350 and 440 Hz for

exceptional dial tone rejection (see Figure 3). Each

ﬁlter output is followed by a single order switched

capacitor ﬁlter section which smooths the signals

prior to limiting. Limiting is performed by high-gain

comparators which are provided with hysteresis to

prevent detection of unwanted low-level signals. The

outputs of the comparators provide full rail logic

swings at the frequencies of the incoming DTMF

signals.

Decoder Section

Following the ﬁlter section is a decoder employing

digital counting techniques to determine the

frequencies of the incoming tones and to verify that

they correspond to standard DTMF frequencies. A

complex averaging algorithm protects against tone

simulation by extraneous signals such as voice while

Figure 4 - Basic Steering Circuit

providing tolerance to small frequency deviations

and variations. This averaging algorithm has been

developed to ensure an optimum combination of

immunity to talk-off and tolerance to the presence of

interfering frequencies (third tones) and noise. When

the detector recognizes the presence of two valid

tones (this is referred to as the “signal condition” in

some industry speciﬁcations) the “Early Steering”

(ESt) output will go to an active state. Any

subsequent loss of signal condition will cause ESt to

assume an inactive state (see “Steering Circuit”).

Steering Circuit

Before registration of a decoded tone pair, the

receiver checks for a valid signal duration (referred to

as character recognition condition). This check is

performed by an external RC time constant driven by

ESt. A logic high on ESt causes v

(see Figure 4) to

rise as the capacitor discharges. Provided signal

VDD

St/GT

ESt

StD

MT8870D/

MT8870D-1

tGTA=(RC)In(VDD/VTSt)

tGTP=(RC)In[VDD/(VDD-VTSt)]

Figure 3 - Filter Response

ATTENUATION

(dB)

XY ABCD

1kHz

EF G H

PRECISE

DIAL TONES

X=350 Hz

Y=440 Hz

DTMF TONES

A=697 Hz

B=770 Hz

C=852 Hz

D=941 Hz

E=1209 Hz

F=1336 Hz

G=1477 Hz

H=1633 Hz

FREQUENCY (Hz)

MT8870D/MT8870D-1

ISO

-CMOS

4-14

condition is maintained (ESt remains high) for the

validation period (t

GTP

), v

reaches the threshold

TSt

) of the

steering logic to register the tone pair,

latching its corresponding 4-bit code (see Table 1)

into the output latch. At this point the GT output is

activated and drives v

to V

. GT continues to drive

high as long as ESt remains high. Finally, after a

short delay to allow the output latch to settle, the

delayed steering output ﬂag (StD) goes high,

signalling that a received tone pair has been

registered. The contents of the output latch are made

available on the 4-bit output bus by raising the three

state control input (TOE) to a logic high. The

steering circuit works in reverse to validate the

interdigit pause between signals. Thus, as well as

rejecting signals too short to be considered valid, the

receiver will tolerate signal interruptions (dropout)

too short to be considered a valid pause. This facility,

together with the capability of selecting the steering

time constants externally, allows the designer to

tailor performance to meet a wide variety of system

requirements.

Guard Time Adjustment

In many situations not requiring selection of tone

duration and interdigital pause, the simple steering

circuit shown in Figure 4 is applicable. Component

values are chosen according to the formula:

REC

GTP

GTA

The value of t

is a device parameter (see Figure

11) and t

REC

is the minimum signal duration to be

recognized by the receiver. A value for C of 0.1

F is

Figure 5 - Guard Time Adjustment

Table 1. Functional Decode Table

L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE

X = DON‘T CARE

recommended for most applications, leaving R to be

selected by the designer.

Different steering arrangements may be used to

select independently the guard times for tone

present (t

GTP

) and tone absent (t

GTA

). This may be

necessary to meet system speciﬁcations which place

both accept and reject limits on both tone duration

and interdigital pause. Guard time adjustment also

allows the designer to tailor system parameters

such as talk off and noise immunity. Increasing t

REC

improves talk-off performance since it reduces the

probability that tones simulated by speech will

maintain signal condition long enough to be

registered. Alternatively, a relatively short t

REC

with

a long t

would be appropriate for extremely noisy

environments where fast acquisition time and

immunity to tone drop-outs are required. Design

information for guard time adjustment is shown in

Figure 5.

VDD

St/GT

ESt

R1R2

a) decreasing tGTP; (tGTP<tGTA)

tGTP=(RPC1)In[VDD/(VDD-VTSt)]

tGTA=(R1C1)In(VDD/VTSt)

RP=(R1R2)/(R1+R2)

VDD

St/GT

ESt

R1R2

tGTP=(R1C1)In[VDD/(VDD-VTSt)]

tGTA=(RPC1)In(VDD/VTSt)

RP=(R1R2)/(R1+R2)

b) decreasing tGTA; (tGTP>tGTA)

Digit TOE INH ESt Q4Q3Q2Q1

ANYLXHZZZZ

1HXH0001

2HXH0010

3HXH0011

4HXH0100

5HXH0101

6HXH0110

7HXH0111

8HXH1000

9HXH1001

0HXH1010

*HXH1011

#HXH1100

AHLH1101

BHLH1110

CHLH1111

DHLH0000

AHHL

undetected, the output code

will remain the same as the

previous detected code

BHHL

CHHL

DHHL

ISO2-CMOS MT8870D/MT8870D-1

4-15

Power-down and Inhibit Mode

A logic high applied to pin 6 (PWDN) will power down

the device to minimize the power consumption in a

standby mode. It stops the oscillator and the

functions of the ﬁlters.

Inhibit mode is enabled by a logic high input to the

pin 5 (INH). It inhibits the detection of tones

representing characters A, B, C, and D. The output

code will remain the same as the previous detected

code (see Table 1).

Differential Input Conﬁguration

The input arrangement of the MT8870D/MT8870D-1

provides a differential-input operational ampliﬁer as

well as a bias source (VRef) which is used to bias the

inputs at mid-rail. Provision is made for connection of

a feedback resistor to the op-amp output (GS) for

adjustment of gain. In a single-ended conﬁguration,

the input pins are connected as shown in Figure 10

with the op-amp connected for unity gain and VRef

biasing the input at 1/2VDD. Figure 6 shows the

differential conﬁguration, which permits the

adjustment of gain with the feedback resistor R5.

Crystal Oscillator

The internal clock circuit is completed with the

addition of an external 3.579545 MHz crystal and is

normally connected as shown in Figure 10 (Single-

Ended Input Conﬁguration). However, it is possible to

conﬁgure several MT8870D/MT8870D-1 devices

employing only a single oscillator crystal. The

oscillator output of the ﬁrst device in the chain is

coupled through a 30 pF capacitor to the oscillator

input (OSC1) of the next device. Subsequent devices

are connected in a similar fashion. Refer to Figure 7

for details. The problems associated with unbalanced

loading are not a concern with the arrangement

shown, i.e., precision balancing capacitors are not

required.

Figure 6 - Differential Input Conﬁguration

Figure 7 - Oscillator Connection

Table 2. Recommended Resonator Speciﬁcations

Note: Qm=quality factor of RLC model, i.e., 1/2ΠƒR1C1.

Parameter Unit Resonator

R1 Ohms 10.752

L1 mH .432

C1 pF 4.984

C0 pF 37.915

Qm - 896.37

∆f%±0.2%

C1R1

C2R4

IN+

IN-

R5GS

R2VRef

MT8870D/

MT8870D-1

Differential Input Amplifier

C1=C2=10 nF

R1=R4=R5=100 kΩ

R2=60kΩ, R3=37.5 kΩ

All resistors are ±1% tolerance.

All capacitors are ±5% tolerance.

R3=R2R5

R2+R5

VOLTAGE GAIN (Av diff)= R5

INPUT IMPEDANCE

(ZINDIFF) = 2 R12+1

ωc

OSC1

OSC2

OSC1

X-tal

To OSC1 of next

MT8870D/MT8870D-1

C=30 pF

X-tal=3.579545 MHz

MT8870D/MT8870D-1 ISO2-CMOS

4-16

Applications

RECEIVER SYSTEM FOR BRITISH TELECOM

SPEC POR 1151

The circuit shown in Fig. 9 illustrates the use of

MT8870D-1 device in a typical receiver system. BT

Spec deﬁnes the input signals less than -34 dBm as

the non-operate level. This condition can be attained

by choosing a suitable values of R1 and R2 to

provide 3 dB attenuation, such that -34 dBm input

signal will correspond to -37 dBm at the gain setting

pin GS of MT8870D-1. As shown in the diagram, the

component values of R3 and C2 are the guard time

requirements when the total component tolerance is

6%. For better performance, it is recommended to

use the non-symmetric guard time circuit in Fig. 8.

Figure 8 - Non-Symmetric Guard Time Circuit

tGTP=(RPC1)In[VDD/(VDD-VTSt)]

tGTA=(R1C1)In(VDD/VTSt)

RP=(R1R2)/(R1+R2)

VDD

St/GT

ESt

R1Notes:

R1=368K Ω ± 1%

R2=2.2M Ω ± 1%

C1=100nF ± 5%

Figure 9 - Single-Ended Input Conﬁguration for BT or CEPT Spec

IN+

IN-

VRef

INH

PWDN

OSC 1

OSC 2

VSS TOE

VDD

St/GT

ESt

StD

DTMF

Input

VDD

MT8870D-1

NOTES:

R1 = 102KΩ ± 1%

R2 = 71.5KΩ ± 1%

R3 = 390KΩ ±1 %

C1,C2 = 100 nF ± 5%

X1 = 3.579545 MHz ± 0.1%

VDD = 5.0V ± 5%

ISO2-CMOS MT8870D/MT8870D-1

4-17

† Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Derate above 75 °C at 16 mW / °C. All leads soldered to board.

‡ Typical ﬁgures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Absolute Maximum Ratings†

Parameter Symbol Min Max Units

1 DC Power Supply Voltage VDD 7V

2 Voltage on any pin VIVSS-0.3 VDD+0.3 V

3 Current at any pin (other than supply) II10 mA

4 Storage temperature TSTG -65 +150 °C

5 Package power dissipation PD500 mW

Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.

Parameter Sym Min Typ‡Max Units Test Conditions

1 DC Power Supply Voltage VDD 4.75 5.0 5.25 V

2 Operating Temperature TO-40 +85 °C

3 Crystal/Clock Frequency fc 3.579545 MHz

4 Crystal/Clock Freq.Tolerance ∆fc ±0.1 %

DC Electrical Characteristics - VDD=5.0V± 5%, VSS=0V, -40°C ≤ TO ≤ +85°C, unless otherwise stated.

Characteristics Sym Min Typ‡Max Units Test Conditions

Standby supply current IDDQ 10 25 µA PWDN=VDD

2 Operating supply current IDD 3.0 9.0 mA

3 Power consumption PO15 mW fc=3.579545 MHz

High level input VIH 3.5 V VDD=5.0V

5 Low level input voltage VIL 1.5 V VDD=5.0V

6 Input leakage current IIH/IIL 0.1 µAV

IN=VSS or VDD

7 Pull up (source) current ISO 7.5 20 µA TOE (pin 10)=0,

VDD=5.0V

8 Pull down (sink) current ISI 15 45 µA INH=5.0V, PWDN=5.0V,

VDD=5.0V

9 Input impedance (IN+, IN-) RIN 10 MΩ@ 1 kHz

10 Steering threshold voltage VTSt 2.2 2.4 2.5 V VDD = 5.0V

Low level output voltage VOL VSS+0.03 V No load

12 High level output voltage VOH VDD-0.03 V No load

13 Output low (sink) current IOL 1.0 2.5 mA VOUT=0.4 V

14 Output high (source) current IOH 0.4 0.8 mA VOUT=4.6 V

15 VRef output voltage VRef 2.3 2.5 2.7 V No load, VDD = 5.0V

16 VRef output resistance ROR 1kΩ

MT8870D/MT8870D-1 ISO2-CMOS

4-18

‡ Typical ﬁgures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.

*NOTES

1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load.

2. Digit sequence consists of all DTMF tones.

3. Tone duration= 40 ms, tone pause= 40 ms.

4. Signal condition consists of nominal DTMF frequencies.

5. Both tones in composite signal have an equal amplitude.

6. Tone pair is deviated by ±1.5 %± 2 Hz.

7. Bandwidth limited (3 kHz ) Gaussian noise.

8. The precise dial tone frequencies are (350 Hz and 440 Hz) ± 2 %.

9. For an error rate of better than 1 in 10,000.

10. Referenced to lowest level frequency component in DTMF signal.

11. Referenced to the minimum valid accept level.

12. Guaranteed by design and characterization.

Operating Characteristics - VDD=5.0V±5%, VSS=0V, -40°C ≤ TO ≤ +85°C ,unless otherwise stated.

Gain Setting Ampliﬁer

Characteristics Sym Min Typ‡Max Units Test Conditions

1 Input leakage current IIN 100 nA VSS ≤ VIN ≤ VDD

2 Input resistance RIN 10 MΩ

3 Input offset voltage VOS 25 mV

4 Power supply rejection PSRR 50 dB 1 kHz

5 Common mode rejection CMRR 40 dB 0.75 V ≤ VIN ≤ 4.25 V biased

at VRef =2.5 V

6 DC open loop voltage gain AVOL 32 dB

7 Unity gain bandwidth fC0.30 MHz

8 Output voltage swing VO4.0 Vpp Load ≥ 100 kΩ to VSS @ GS

9 Maximum capacitive load (GS) CL100 pF

10 Resistive load (GS) RL50 kΩ

11 Common mode range VCM 2.5 Vpp No Load

MT8870D AC Electrical Characteristics -V

DD=5.0V ±5%, VSS=0V, -40°C ≤ TO ≤ +85°C , using Test Circuit shown in

Figure 10.

Characteristics Sym Min Typ‡Max Units Notes*

1Valid input signal levels (each

tone of composite signal)

-29 +1 dBm 1,2,3,5,6,9

27.5 869 mVRMS 1,2,3,5,6,9

2 Negative twist accept 8 dB 2,3,6,9,12

3 Positive twist accept 8 dB 2,3,6,9,12

4 Frequency deviation accept ±1.5% ± 2 Hz 2,3,5,9

5 Frequency deviation reject ±3.5% 2,3,5,9

6 Third tone tolerance -16 dB 2,3,4,5,9,10

7 Noise tolerance -12 dB 2,3,4,5,7,9,10

8 Dial tone tolerance +22 dB 2,3,4,5,8,9,11

ISO2-CMOS MT8870D/MT8870D-1

4-19

‡ Typical ﬁgures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.

*NOTES

1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load.

2. Digit sequence consists of all DTMF tones.

3. Tone duration= 40 ms, tone pause= 40 ms.

4. Signal condition consists of nominal DTMF frequencies.

5. Both tones in composite signal have an equal amplitude.

6. Tone pair is deviated by ±1.5 %± 2 Hz.

7. Bandwidth limited (3 kHz ) Gaussian noise.

8. The precise dial tone frequencies are (350 Hz and 440 Hz) ± 2 %.

9. For an error rate of better than 1 in 10,000.

10. Referenced to lowest level frequency component in DTMF signal.

11. Referenced to the minimum valid accept level.

12. Referenced to Fig. 10 input DTMF tone level at -25dBm (-28dBm at GS Pin) interference frequency range between 480-3400Hz.

13. Guaranteed by design and characterization.

MT8870D-1 AC Electrical Characteristics -V

DD=5.0V±5%, VSS=0V, -40°C ≤ TO ≤ +85°C , using Test Circuit shown

in Figure 10.

Characteristics Sym Min Typ‡Max Units Notes*

1Valid input signal levels (each

tone of composite signal)

-31 +1 dBm Tested at VDD=5.0V

1,2,3,5,6,9

21.8 869 mVRMS

2 Input Signal Level Reject -37 dBm Tested at VDD=5.0V

1,2,3,5,6,9

10.9 mVRMS

3 Negative twist accept 8 dB 2,3,6,9,13

4 Positive twist accept 8 dB 2,3,6,9,13

5 Frequency deviation accept ±1.5%± 2 Hz 2,3,5,9

6 Frequency deviation reject ±3.5% 2,3,5,9

7 Third zone tolerance -18.5 dB 2,3,4,5,9,12

8 Noise tolerance -12 dB 2,3,4,5,7,9,10

9 Dial tone tolerance +22 dB 2,3,4,5,8,9,11

MT8870D/MT8870D-1 ISO2-CMOS

4-20

‡ Typical ﬁgures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

*NOTES:

1. Used for guard-time calculation purposes only.

2. These, user adjustable parameters, are not device speciﬁcations. The adjustable settings of these minimums and maximums

are recommendations based upon network requirements.

3. With valid tone present at input, tPU equals time from PDWN going low until ESt going high.

Figure 10 - Single-Ended Input Conﬁguration

AC Electrical Characteristics - VDD=5.0V±5%, VSS=0V, -40°C ≤ To ≤ +85°C , using Test Circuit shown in Figure 10.

Characteristics Sym Min Typ‡Max Units Conditions

Tone present detect time tDP 5 11 14 ms Note 1

2 Tone absent detect time tDA 0.5 4 8.5 ms Note 1

3 Tone duration accept tREC 40 ms Note 2

4 Tone duration reject tREC 20 ms Note 2

5 Interdigit pause accept tID 40 ms Note 2

6 Interdigit pause reject tDO 20 ms Note 2

Propagation delay (St to Q) tPQ 811µs TOE=VDD

8 Propagation delay (St to StD) tPStD 12 16 µs TOE=VDD

9 Output data set up (Q to StD) tQStD 3.4 µs TOE=VDD

10 Propagation delay (TOE to Q ENABLE) tPTE 50 ns load of 10 kΩ,

50 pF

11 Propagation delay (TOE to Q DISABLE) tPTD 300 ns load of 10 kΩ,

50 pF

12 P

Power-up time tPU 30 ms Note 3

13 Power-down time tPD 20 ms

Crystal/clock frequency fC3.5759 3.5795 3.5831 MHz

15 Clock input rise time tLHCL 110 ns Ext. clock

16 Clock input fall time tHLCL 110 ns Ext. clock

17 Clock input duty cycle DCCL 40 50 60 % Ext. clock

18 Capacitive load (OSC2) CLO 30 pF

IN+

IN-

VRef

INH

PDWN

OSC 1

OSC 2

VSS TOE

VDD

St/GT

ESt

StD

DTMF

Input

X-tal

VDD

NOTES:

R1,R2=100KΩ ± 1%

R3=300KΩ ± 1%

C1,C2=100 nF ± 5%

X-tal=3.579545 MHz ± 0.1%

MT8870D/MT8870D-1

ISO2-CMOS MT8870D/MT8870D-1

4-21

Figure 11 - Timing Diagram

EXPLANATION OF EVENTS

EXPLANATION OF SYMBOLS

A) TONE BURSTS DETECTED, TONE DURATION INVALID, OUTPUTS NOT UPDATED.

B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS

C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMIAN LATCHED UNTIL NEXT VALID

TONE.

D) OUTPUTS SWITCHED TO HIGH IMPEDANCE STATE.

E) TONE #n + 1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS (CURRENTLY HIGH

IMPEDANCE).

F) ACCEPTABLE DROPOUT OF TONE #n + 1, TONE ABSENT DURATION INVALID, OUTPUTS REMAIN LATCHED.

G) END OF TONE #n + 1 DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT VALID

TONE.

Vin DTMF COMPOSITE INPUT SIGNAL.

ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.

St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.

Q1-Q44-BIT DECODED TONE OUTPUT.

StD DELAYED STEERING OUTPUT. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE

REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL.

TOE TONE OUTPUT ENABLE (INPUT). A LOW LEVEL SHIFTS Q1-Q4 TO ITS HIGH IMPEDANCE STATE.

tREC MAXIMUM DTMF SIGNAL DURATION NOT DETECED AS VALID

tREC MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION

tID MAXIMUM TIME BETWEEN VALID DTMF SIGNALS.

tDO MAXIMUM ALLOWABLE DROP OUT DURING VALID DTMF SIGNAL.

tDP TIME TO DETECT THE PRESENCE OF VALID DTMF SIGNALS.

tDA TIME TO DETECT THE ABSENCE OF VALID DTMF SIGNALS.

tGTP GUARD TIME, TONE PRESENT.

tGTA GUARD TIME, TONE ABSENT.

Vin

ESt

St/GT

Q1-Q4

StD

TOE

EVENTS ABC

EFG

tREC tREC tID tDO

TONE #n TONE

#n + 1 TONE

#n + 1

tDP tDA

tGTP tGTA

tPQ tQStD

tPSrD

tPTD

tPTE

# n # (n + 1)

HIGH IMPEDANCE

DECODED TONE # (n-1)

VTSt

MT8870D/MT8870D-1 ISO2-CMOS

4-22

Notes:

Package Outlines

Plastic Dual-In-Line Packages (PDIP) - E Sufﬁx

NOTE: Controlling dimensions in parenthesis ( ) are in millimeters.

DIM

8-Pin 16-Pin 18-Pin 20-Pin

Plastic Plastic Plastic Plastic

Min Max Min Max Min Max Min Max

A0.210 (5.33) 0.210 (5.33) 0.210 (5.33) 0.210 (5.33)

A20.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95)

b0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558)

b20.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77)

C0.008

(0.203) 0.014 (0.356) 0.008 (0.203) 0.014(0.356) 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014 (0.356)

D0.355 (9.02) 0.400 (10.16) 0.780 (19.81) 0.800 (20.32) 0.880 (22.35) 0.920 (23.37) 0.980 (24.89) 1.060 (26.9)

D10.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13)

E0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26)

E10.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11)

e0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54)

eA0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62)

L0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81)

eB0.430 (10.92) 0.430 (10.92) 0.430 (10.92) 0.430 (10.92)

eC0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52)

321

n-2 n-1 n

Notes:

1) Not to scale

2) Dimensions in inches

3) (Dimensions in millimeters)

General-8

Package Outlines

Plastic Dual-In-Line Packages (PDIP) - E Sufﬁx

DIM

22-Pin 24-Pin 28-Pin 40-Pin

Plastic Plastic Plastic Plastic

Min Max Min Max Min Max Min Max

A0.210 (5.33) 0.250 (6.35) 0.250 (6.35) 0.250 (6.35)

A20.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95)

b0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558)

b20.045 (1.15) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77)

C0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381)

D1.050 (26.67) 1.120 (28.44) 1.150 (29.3) 1.290 (32.7) 1.380 (35.1) 1.565 (39.7) 1.980 (50.3) 2.095 (53.2)

D10.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13)

E0.390 (9.91) 0.430 (10.92) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02)

E0.290 (7.37) .330 (8.38)

E10.330 (8.39) 0.380 (9.65) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73)

E10.246 (6.25) 0.254 (6.45)

e0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54)

eA0.400 BSC (10.16) 0.600 BSC (15.24) 0.600 BSC (15.24) 0.600 BSC (15.24)

eA0.300 BSC (7.62)

eB0.430 (10.92)

L0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08)

α15°15°15°15°

321

n-2 n-1 n

Notes:

1) Not to scale

2) Dimensions in inches

3) (Dimensions in millimeters)

Shaded areas for 300 Mil Body Width 24 PDIP only

Package Outlines

Lead SOIC Package - S Sufﬁx

NOTES: 1. Controlling dimensions in parenthesis ( ) are in millimeters.

2. Conver ted inch dimensions are not necessarily exact.

DIM 16-Pin 18-Pin 20-Pin 24-Pin 28-Pin

Min Max Min Max Min Max Min Max Min Max

A0.093

(2.35) 0.104

(2.65) 0.093

(2.35) 0.104

(2.65) 0.093

(2.35) 0.104

(2.65) 0.093

(2.35) 0.104

(2.65) 0.093

(2.35) 0.104

(2.65)

A10.004

(0.10) 0.012

(0.30) 0.004

(0.10) 0.012

(0.30) 0.004

(0.10) 0.012

(0.30) 0.004

(0.10) 0.012

(0.30) 0.004

(0.10) 0.012

(0.30)

B0.013

(0.33) 0.020

(0.51) 0.013

(0.33) 0.030

(0.51) 0.013

(0.33) 0.020

(0.51) 0.013

(0.33) 0.020

(0.51) 0.013

(0.33) 0.020

(0.51)

C0.009

(0.231) 0.013

(0.318) 0.009

(0.231) 0.013

(0.318) 0.009

(0.231) 0.013

(0.318) 0.009

(0.231) 0.013

(0.318) 0.009

(0.231) 0.013

(0.318)

D0.398

(10.1) 0.413

(10.5) 0.447

(11.35) 0.4625

(11.75) 0.496

(12.60) 0.512

(13.00) 0.5985

(15.2) 0.614

(15.6) 0.697

(17.7) 0.7125

(18.1)

E0.291

(7.40) 0.299

(7.40) 0.291

(7.40) 0.299

(7.40) 0.291

(7.40) 0.299

(7.40) 0.291

(7.40) 0.299

(7.40) 0.291

(7.40) 0.299

(7.40)

e0.050 BSC

(1.27 BSC) 0.050 BSC

(1.27 BSC)

H0.394

(10.00) 0.419

(10.65) 0.394

(10.00) 0.419

(10.65) 0.394

(10.00) 0.419

(10.65) 0.394

(10.00) 0.419

(10.65) 0.394

(10.00) 0.419

(10.65)

L0.016

(0.40) 0.050

(1.27) 0.016

(0.40) 0.050

(1.27) 0.016

(0.40) 0.050

(1.27) 0.016

(0.40) 0.050

(1.27) 0.016

(0.40) 0.050

(1.27)

Pin 1

Notes:

1) Not to scale

2) Dimensions in inches

3) (Dimensions in millimeters)

4) A & B Maximum dimensions include allowable mold flash

4 mils (lead coplanarity)

General-7

Package Outlines

Small Shrink Outline Package (SSOP) - N Sufﬁx

Pin 1

Dim 20-Pin 24-Pin 28-Pin 48-Pin

Min Max Min Max Min Max Min Max

A0.079

(2) - 0.079

(2) 0.079

(2) 0.095

(2.41) 0.110

(2.79)

A10.002

(0.05) 0.002

(0.05) 0.008

(0.2) 0.016

(0.406)

B0.0087

(0.22) 0.013

(0.33) 0.0087

(0.22) 0.013

(0.33) 0.0087

(0.22) 0.013

(0.33) 0.008

(0.2) 0.0135

(0.342)

C0.008

(0.21) 0.008

(0.21) 0.010

(0.25)

D0.27

(6.9) 0.295

(7.5) 0.31

(7.9) 0.33

(8.5) 0.39

(9.9) 0.42

(10.5) 0.62

(15.75) 0.63

(16.00)

E0.2

(5.0) 0.22

(5.6) 0.2

(5.0) 0.22

(5.6) 0.2

(5.0) 0.22

(5.6) 0.291

(7.39) 0.299

(7.59)

e0.025 BSC

(0.635 BSC) 0.025 BSC

(0.635 BSC)

A20.065

(1.65) 0.073

(1.85) 0.065

(1.65) 0.073

(1.85) 0.065

(1.65) 0.073

(1.85) 0.089

(2.26) 0.099

(2.52)

H0.29

(7.4) 0.32

(8.2) 0.29

(7.4) 0.32

(8.2) 0.29

(7.4) 0.32

(8.2) 0.395

(10.03) 0.42

(10.67)

L0.022

(0.55) 0.037

(0.95) 0.022

(0.55) 0.037

(0.95) 0.022

(0.55) 0.037

(0.95) 0.02

(0.51) 0.04

(1.02)

Notes:

1) Not to scale

2) Dimensions in inches

3) (Dimensions in millimeters)

4) Ref. JEDEC Standard M0-150/M0118 for 48 Pin

5) A & B Maximum dimensions include allowable mold flash

General-11

Purchase of Zarlink’s I

C components conveys a licence under the Philips I

C Patent rights to use these components in an I

C System, provided that the system conforms

to the I

C Standard Speciﬁcation as deﬁned by Philips

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