XTR108
SBOS187C – OCTOBER 2001 – REVISED JULY 2005
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2001-2005, Texas Instruments Incorporated
SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners.
4-20mA, TWO-WIRE TRANSMITTER
“Smart” Programmable with Signal Conditioning
FEATURES
COMPLETE TRANSMITTER + RTD
LINEARIZATION
TWO-WIRE, 4-20mA OUTPUT
VOLTAGE OUTPUT (0.5V to 4.5V)
ELIMINATES POTENTIOMETERS AND
TRIMMING
DIGITALLY CALIBRATED
5V SUB-REGULATOR OUTPUT
SERIAL SPI BUS INTERFACE
SSOP-24 PACKAGE
APPLICATIONS
REMOTE RTD TRANSMITTERS
PRESSURE BRIDGE TRANSMITTERS
STRAIN GAGE TRANSMITTERS
SCADA REMOTE DATA ACQUISITION
WEIGHING SYSTEMS
INDUSTRIAL PROCESS CONTROL
DESCRIPTION
The XTR108 is a “smart,” programmable, 4-20mA, two-wire
transmitter designed for temperature and bridge sensors.
Zero, span, and linearization errors in the analog signal
path can be calibrated via a standard digital serial interface,
eliminating manual trimming. Non-volatile external EEPROM
stores calibration settings.
The all-analog signal path contains an input multiplexer,
autozeroed programmable-gain instrumentation amplifier, dual
programmable current sources, linearization circuit, voltage
reference, sub-regulator, internal oscillator, control logic, and
an output current amplifier. Programmable level shifting
compensates for sensor DC offsets. Selectable
up- and down-scale output indicates out-of-range and burn-
out per NAMUR NE43. Automatic reset is initiated when
supply is lost.
Current sources, steered through the multiplexer, can be
used to directly excite RTD temperature sensors, pressure
bridges, or other transducers. An uncommitted op amp can
be used to convert current into a voltage. The XTR108 is
specified for –40°C to +85°C.
XTR108
SPI and
Control Circuits
4-20mA
EEPROM
Linearization
Excitation
I
O
I
Ret
Multiplexer
Gain and Offset SDIO
SCLK
CS2
CS1
V/I-0
V/I-1
V/I-2
V/I-3
V/I-4
V/I-5
RTD
R
1
R
2
R
3
R
4
R
5
PGA V/I
V
PS
R
LOAD
XTR108
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
XTR108
2SBOS187C
www.ti.com
Loop Supply Voltage, VPS ............................ Dependent on External FET
XTR Supply Voltage, External VS (Referenced to IRET Pin) ............ +5.5V
Input Voltage to Multiplexer (Referenced to IRET Pin) ................ 0V to VS
Output Current Limit ................................................................ Continuous
Storage Temperature Range .........................................55°C to +125°C
Junction Temperature.................................................................... +165°C
Lead Temperature (soldering, 10s)............................................... +300°C
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
SPECIFIED
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
XTR108EA SSOP-24 DBQ 40°C to +85°C XTR108EA XTR108EA Rails
" """"XTR108EA/2K5 Tape and Reel, 2500
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at
www.ti.com.
PACKAGE/ORDERING INFORMATION(1)
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA = 40°C to +85°C.
At TA = +25°C, VPS = 24V, and Supertex DN2540 external depletion-mode FET transistor, unless otherwise noted, all voltages measured with respect to IRET pin.
XTR108EA
PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN TO IOUT TRANSFER FUNCTION IO = VIN (Span) + 4mA
Output
Specified Range 420mA
Over-Scale Limit Resolution Digital Select: 21-28.5mA 0.5 mA
Fault Over-Scale Level(1) Above Over-Scale Selected +1.0 mA
Under-Scale Limit Resolution Digital Select: 2.2-3.6mA 0.2 mA
Fault Under-Scale Level(1) Below Under-Scale Selected 0.4 mA
Output for Zero Input
Zero Error, Unadjusted VIN = 0V ±50 µA
vs Temperature ±0.2 ±1.5 µA/°C
vs Loop-Supply Voltage, VLOOP VLOOP = 7.5V to 24V 0.02 µA/V
vs Common-Mode Voltage VCM = 0.2V to 3.5V ±1µA/V
Adjustment Resolution, Zero Input 1.8 µA/Step
Adjustment Range, Zero Input ±4mA
Span(2) Span = IO/VIN
Initial, Unadjusted ±1%
Drift (vs Temperature) 40 ppm/°C
Span Adjustment Resolution 0.05 %
Span Adjustment Range
PGA + Output Amplifier(3) RVI = 6.34k49.3 3150 mA/V
Nonlinearity, Ideal Input Full-Scale VIN = 50mV 0.01 %
PGA
Autozeroing Internal Frequency 6.5 kHz
PGA Offset Voltage (RTI)(4) VCM = 1V ±10 ±50 µV
vs Temperature ±0.02 µV/°C
vs Supply Voltage, VSVS = 4.5V to 5.5V ±0.5 µV/V
vs Common-Mode Voltage VCM = 0.2V to 3.5V 105 dB
Common-Mode Input Range 0.2 VS 1.5 V
Input Bias Current 50 pA
vs Temperature
Doubles/10°C
pA
Input Offset Current 10 pA
vs Temperature
Doubles/10°C
pA
XTR108 3
SBOS187C www.ti.com
ELECTRICAL CHARACTERISTICS (Cont.)
Boldface limits apply over the specified temperature range, TA = 40°C to +85°C.
At TA = +25°C, VPS = 24V, and Supertex DN2540 external depletion-mode FET transistor, unless otherwise noted, all voltages measured with respect to IRET pin.
XTR108EA
PARAMETER CONDITIONS MIN TYP MAX UNITS
PGA (Cont.)
Input Impedance: Differential 30 || 6 G || pF
Input Impedance: Common-Mode 50 || 20 G || pF
Voltage Noise, 0.1Hz to 10Hz 6µVp-p
PGA Gain
Gain Range Steps 6.25, 12.5, 25, 50, 100, 200, 400 6.25 400 V/V
Initial Error Gain = 6.25, 12.5, 25, 50 ±0.5 ±2.5 %
G = 100, 200 ±0.5 ±3%
G = 400 ±0.8 ±3.5 %
vs Temperature ±30 ppm/°C
Output Voltage Range(5) RLOAD = 6.34k to IRET 0.2 4.5 V
Typical Operating Range for 4-20mA XTR Output 0.5 to 2.5 V
Capacitive Drive 200 pF
Short-Circuit Current +6/9mA
ZERO OFFSET DACS
Zero-Code Output Level VCM = 1V, VIN = 0V
RTO(6) of Current Amplifier RV/I = 6.34k4.116 mA
RTO(6) of PGA 522 mV
Coarse DAC, 256 Steps 7 Bits + Sign
Adjustment Range Relative to Zero-Code Level
RTO(6) of Current Amplifier
3.77 to +3.77
mA
RTO(6) of PGA 470 to +470 mV
Step Size
RTO(6) of Current Amplifier 0.029 mA
RTO(6) of PGA 3.7 mV
Linearity ±0.5 LSB
Fine DAC, 256 Steps Relative to Zero-Code Level 7 Bits + Sign
Adjustment Range
RTO(6) of Current Amplifier 236 to +236 µA
RTO(6) of PGA
29.4 to +29.4
mV
Step Size
RTO(6) of Current Amplifier 0.0018 mA
RTO(6) of PGA 0.23 mV
Linearity ±1LSB
Noise, RTO(6) f = 0.1Hz to 10Hz 1.1 µAp-p
CURRENT AMPLIFIER
Current Gain 49 50 51 A/A
Current Gain Drift 10 ppm/°C
CURRENT SOURCES, IREF1 AND IREF2
Zero-Code Output Level, Each RSET = 12.1k480 493 510 µA
Coarse DAC, 256 Steps 7 Bits + Sign
Adjustment Range(7) 195 to +195 µA
Step Size 1.54 µA
Fine DAC, 256 Steps 7 Bits + Sign
Adjustment Range(7)
12.2 to +12.2
µA
Step Size 96 nA
Linearity
Coarse ±0.2 LSB
Fine ±0.5 LSB
vs Temperature ±35 ppm/°C
Matching ±0.2 %
vs Temperature ±10 ppm/°C
Compliance Voltage, Positive(5) VS 2V
S 1.5 V
Output Impedance 100 M
Current Noise f = 0.1Hz to 10Hz 0.015 µAp-p
LINEARIZATION DAC
Linearization Range, 256 Steps 8 Bits
Max Linearization Coefficient IREF/VIN, RLIN = 15.8k0.99 µA/mV
Step Size 3.9 nA/mV
SUB-REGULATOR, VSSupply Voltage for XTR
Voltage 4.8 5.1 5.4 V
vs Temperature ±50 ppm/°C
vs Loop-Supply Voltage VLOOP = 7.5V to 24V ±0.03 mV/V
XTR108
4SBOS187C
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XTR108EA
PARAMETER CONDITIONS MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS (Cont.)
Boldface limits apply over the specified temperature range, TA = 40°C to +85°C.
At TA = +25°C, VPS = 24V, and Supertex DN2540 external depletion-mode FET transistor, unless otherwise noted, all voltages measured with respect to IRET pin.
NOTES: (1) Over-scale and under-scale complies with NAMUR NE43 recommendation. (2) Span adjustment is determined by PGA gain and sensor
excitation. (3) Span can be digitally adjusted in three ways: PGA gain, current reference Coarse, and current reference Fine. (4) RTI = Referred to Input.
(5) Current source output voltage measured with respect to IRET. (6) RTO = Referred to Output. (7) Excitation DAC range sufficient to adjust span fully
between PGA gain steps. (8) Output current into external circuitry is limited by an external MOS power FET. (9) Measured with over- and under-scale limits
disabled.
OVER- AND UNDER-SCALE LIMITING
Over-Scale DAC: 16 Steps 4 Bits
Adjustment Range
RTO(6) of Current Amplifier RVI = 6.34k20.7 to 28.1 mA
RTO(6) of PGA
2.625 to 3.563
V
Step Size
RTO(6) of Current Amplifier 0.49 mA
RTO(6) of PGA 62.5 mV
Accuracy ±10 %
Under-Scale DAC: 8 Steps 3 Bits
Adjustment Range
RTO(6) of Current Amplifier RVI = 6.34k2.17 to 3.55 mA
RTO(6) of PGA 275 to 450 mV
Step Size
RTO(6) of Current Amplifier 0.195 mA
RTO(6) of PGA 25 mV
Accuracy ±5%
VOLTAGE REFERENCE, VREF
Internal Bandgap 1.193 V
vs Temperature ±5±50 ppm/°C
UNCOMMITTED OP AMP
Input
Offset Voltage VCM = 2V ±2mV
vs Temperature ±3µV/°C
vs Common-Mode Voltage 90 dB
Open-Loop Gain 110 dB
Common-Mode Input Range 0 to 3.5 V
Output Voltage Range RL = 10k to VS/2 0.2 VS 0.2 V
DIGITAL INPUT/OUTPUT
Logic Family CMOS
Logic Levels
VIL 0 0.8 V
VIH 3.5 VSV
VOL IOL = 300µA 0.4 V
VOH IOH = 300µAV
S 1V
Input Current
IIH (CS1) 3.5 < VIN < VS200 120 10 µA
IIL (CS1) 0 < VIN < 0.8 20 610 µA
IIH, IIL (SCLK, DIO) 0 < VIN < VS20 610 µA
INTERNAL OSCILLATOR
Frequency, fOSC 210 kHz
TEMPERATURE RANGE
Specification 40 +85 °C
Operating 55 +125 °C
θ
JA, Junction to Ambient 100 °C/W
LOOP SUPPLY
Voltage Range with Supertex DN2540 7.5 V
Quiescent Current RSET Open, LINReg = 0, No Sensor Current(8)(9) 0.5 mA
XTR108 5
SBOS187C www.ti.com
Top View SSOP
PIN CONFIGURATION
V/I-0
V/I-1
V/I-2
V/I-3
V/I-4
V/I-5
CFILTER
RLIN
VO
IIN
IO
IRET
XTR108
OPA +IN
OPA IN
OPA OUT
REFOUT
REFIN
RSET
CS1
SCLK
SDIO
CS2
VGATE
VS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PIN ASSIGNMENTS
PIN NAME FUNCTION
V/I-0 MUX Input Channel 0 and/or IREF Out MUX Input to PGA and/or IREF to Sensor
V/I-1 MUX Input Channel 1 and/or IREF Out MUX Input to PGA and/or IREF to Sensor
V/I-2 MUX Input Channel 2 and/or IREF Out MUX Input to PGA and/or IREF to Sensor
V/I-3 MUX Input Channel 3 and/or IREF Out MUX Input to PGA and/or IREF to Sensor
V/I-4 MUX Input Channel 4 and/or IREF Out MUX Input to PGA and/or IREF to Sensor
V/I-5 MUX Input Channel 5 and/or IREF Out MUX Input to PGA and/or IREF to Sensor
CFILTER Filter Capacitor Filter to Reduce Chopper Noise in Autozeroing PGA
RLIN Linearization Linearization Range Adjustment Resistor
VOPGA Output PGA Amplified Output of Differential Sensor Input
IIN Current Input Input to Output Current Amplifier
IOOutput Current 4-20mA Current for Output Loop
IRET Return Current Return for All External Circuitry Current
VSVoltage Regulator Supply Voltage for XTR and External Circuitry, If Used
VGATE Gate Voltage Gate Voltage for External MOSFET Transistor
CS2 Chip Select 2 Select for XTR Serial Port to External EEPROM (Output from XTR Only)
SDIO Serial Data Input/Output Serial Data Input or Output
SCLK Serial Clock Serial Clock
CS1 Chip Select 1 Select for External µC Serial Port (Input to XTR Only)
RSET Resistor for Reference Sets Current Reference
REFIN Voltage Reference Input Voltage Reference Input to XTR
REFOUT Voltage Reference Output Voltage Reference Output from Internal Bandgap
OPA OUT Uncommitted Op Amp Output Uncommitted Op Amp Output
OPA IN Uncommitted Op Amp Negative Input Uncommitted Op Amp Negative Input
OPA +IN Uncommitted Op Amp Positive Input Uncommitted Op Amp Positive Input
XTR108
6SBOS187C
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TYPICAL CHARACTERISTICS
At TA = +25°C, V+ = 24V, unless otherwise noted. RVI = 6.34k.
TRANSCONDUCTANCE vs FREQUENCY
1k 10k 100k 200k100
Frequency (Hz)
70
60
50
40
30
20
10
0
10
20
30
Transconductance (20log )
mA
V
G = 400
G = 200
G = 6.25
G = 50
COMMON-MODE REJECTION vs FREQUENCY
100 1k 10k 100k10
Frequency (Hz)
90
80
70
60
50
40
30
20
10
Rejection (20log )
mA
V
G = 6.25
G = 100
G = 400
I
ZERO
V
LOOP
REJECTION RATIO vs FREQUENCY
100 10k10 1k
Frequency (Hz)
Transconductance
(20 log(mA/V))
100
90
80
70
60
50
40
30
20
I
REF
V
LOOP
REJECTION RATIO vs FREQUENCY
100 10k10 1k
Frequency (Hz)
Transconductance
(20 log(mA/V))
120
110
100
90
80
70
60
I
REF
vs TEMPERATURE
50 25 0 12575 50 75 10025
Temperature (°C)
I
REF
(µA)
492
490
488
486
IOUT DRIFT AVERAGE
0.90
0.70
0.50
0.30
0.10
0.10
0.30
0.50
0.70
0.90
1.00
IOUT Drift (µA/°C)
Percent of Units
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
XTR108 7
SBOS187C www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, V+ = 24V, unless otherwise noted. RVI = 6.34k.
LARGE INPUT STEP RESPONSE
250µs/div
PGA Gain = 6.25 C
FILT
= 0
V
IN
I
OUT
20mA
4mA
LARGE INPUT STEP RESPONSE
500µs/div
PGA Gain = 6.25 CFILT = 0.01µF
VIN
IOUT
20mA
4mA
SMALL INPUT STEP RESPONSE
250µs/div
VIN
IOUT
20mA
4mA PGA Gain = 200 CFILT = 0
SMALL INPUT STEP RESPONSE
VIN
IOUT
20mA
4mA
500µs/div
PGA Gain = 200 CFILT = 0.01µF
IREF NOISE POWER
Frequency (Hz)
10 100 1k 10k1
Noise Density (nA/Hz)
10
1.0
0.1
IZERO CURRENT NOISE POWER
Frequency (Hz)
10 100 1k 10k1
Noise Density (nA/Hz)
100
10
1
XTR108
8SBOS187C
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OVERVIEW
The XTR108 is a 4-20mA current-loop transmitter that
allows the user to digitally adjust the gain, offset, and
linearity correction of the analog output to calibrate the
sensor. The digital data for adjustment are stored in an
external EEPROM device.
The analog signal path is composed of a compound multi-
plexer (MUX), programmable gain instrumentation amplifier
(PGA), and an output current amplifier. Analog support func-
tions include digitally controlled current sources for sensor
excitation, PGA offset control, linearization, voltage refer-
ence, and voltage regulator.
The digital interface communicates with external devices for
calibration and to store the resultant data in an SPI compat-
ible EEPROM. A complete system is shown in Figure 1. The
XTR108 serial interface is SPI compatible and only requires
four connections to the calibration controller: a serial clock
(SCLK), a serial data line (SDIO), a chip select line (CS1),
and a ground sense line. All logic signals to the XTR108
must be referenced to the potential of the ground sense line
(IRET pin on the XTR108).
Within this entire system there may exist three different
“GND” voltage levels. In addition, the voltage difference
between the IRET and IO potential will depend on the output
current level. It is not certain that the “GND” potential of the
calibration system will be at the same potential of either the
IRET or IO potential, and therefore the isolation couplers are
shown in Figure 1. All voltages specified for the XTR108
are with reference to the IRET pin.
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, V+ = 24V, unless otherwise noted. RVI = 6.34k.
INPUT NOISE POWER DENSITY
10 100 1k 10k1
Frequency (Hz)
Noise Density (nVHz)
1000
100
10 C
FILT
= 0.01
PGA PEAK-TO-PEAK NOISE (RTI)
5s/div
1.25µV/div
BW: 0.1Hz to 10Hz
The XTR108 also needs to communicate with the external
EEPROM device independently from the calibration control-
ler to retrieve the calibration constants during normal opera-
tion. The XTR108 provides a second chip select function
(CS2) for the EEPROM device to facilitate this communica-
tion.
EE PROM
SDIO
CS2
SCLK
CS1 Isolation
Couplers
I
O
I
RET
XTR108
R
V
R
X
GND
PS
Calibration
System
Calib
GND
T
X
GND
FIGURE 1. Complete System Level Configuration with
Three Unique Ground Voltage Levels.
XTR108 9
SBOS187C www.ti.com
THEORY OF OPERATION
REFERENCE
The XTR108 has an on-board precision bandgap voltage
reference with output at pin 21 (REFOUT). The value of the
reference is factory-trimmed to 1.193V, with a typical tem-
perature drift of 5ppm/°C. Pins 21 (REFOUT) and 20 (REFIN)
must be connected together to use the internal reference.
External circuitry, such as a voltage excited sensor or an
Analog-to-Digital Converter (ADC), can be connected to the
REFOUT pin. The unbuffered REFOUT is capable of sourcing
current but not sinking.
If the application necessitates, an external reference can be
connected to the XTR108 REFIN pin, as long as the reference
does not exceed 1.4V. The REFIN pin has a high input
impedance with the input current not exceeding a few
nanoamps.
INPUT MULTIPLEXER
The XTR108 input multiplexer is a full 6 by (2+2) cross-
point switch. The current references and PGA inputs can be
independently connected to any of the six external pins,
including simultaneous connections to the same pin. This
allows a great flexibility in the sensor excitation and input
configuration. The input pins must not be driven below the
IRET potential or above VS.
See Figure 2 for an RTD sensor connected to pin VIN0 with
both IREF supplied and PGA VIN+ sensed at that pin. The
other five input pins are used for a bank of RZ resistors that
can be selected during the calibration process for a particular
measurement range.
PROGRAMMABLE GAIN
INSTRUMENTATION AMPLIFIER
The programmable gain instrumentation amplifier has seven
voltage-gain settings in binary steps from 6.25V/V to 400V/V.
The input common-mode range of the PGA is 0.2V to 3.5V
above the IRET potential.
Normally, in the application for 4-20mA transmitters, the
PGA output voltage range should be set to VZERO = 0.5V and
VFS = 2.5V. Connecting a resistor (RVI = 6.34k) between
pin 9 (VO) and pin 10 (IIN) converts this voltage to the signal
for the output amplifier that produces a 4-20mA scale
current output. In this mode, the PGA voltage gain converts
to an overall transconductance in the range of 50mA/V to
3200mA/V (approximately). Table I shows the gain to
transconductance relationship.
If over-scale and under-scale limiting is disabled, the PGA
can be used with rail-to-rail voltage output, for example, in
applications that require a 0.5V to 4.5V voltage scale.
The PGA uses advanced auto-zero circuit techniques to achieve
high DC precision, and reduce mismatches and errors within
the chip such as input offset, offset temperature drift, and low-
frequency noise (see the input noise typical characteristic).
The basic clock frequency of the auto-zero loop is about
6.5kHz. Due to the switching nature of the auto-zero circuit,
the output of the PGA can have a noticeable clock feed-
through ripple in higher gains. This noise can be reduced by
the addition of a 0.01µF capacitor between pin 7 (CFILTER)
and the local ground, pin 12 (IRET). This creates a one-pole
low-pass filter with –3dB frequency at about 1.5kHz. If
wider bandwidth or faster settling time is needed, the CFILTER
can be reduced or eliminated at the expense of higher glitch
amplitude at the output. Please refer to the typical step
response traces for settling time comparisons.
ZERO DACS
Two output-referred, 8-bit Digital-to-Analog Converters
(DACs) (coarse and fine with a pedestal) set the zero level of
the PGA output. They allow setting a desired zero-scale
output level and compensate the initial offset at the PGA input
due to the sensor and resistor mismatches, sensor non-ideali-
ties, etc. Both coarse and fine DACs are bidirectional and
allow the output level to be set above or below a preset
pedestal.
Output signals of the DACs, IZ COARSE and IZ FINE, are
summed with the pedestal, IZ PROGRAM. Each of the DACs
has 8-bit resolution (256 steps) with 4-bit overlap between
the coarse and fine DACs. This means that one LSB of the
coarse DAC is equal to 16 fine LSBs, and the full-scale
range of the fine DAC is equal to 16 coarse LSBs. This
effectively produces 12-bit adjustment resolution.
This overlap allows the user to set pre-calculated values
before the calibration, using the coarse DAC only and adjust
the zero output level with the fine DAC during the calibra-
tion process see Table II for the equations for calculating the
value of the output when zero differential voltage is applied
at the PGA input. For the adjustment range, LSB sizes, and
linearity values of the Zero DACs, please refer to the
electrical characteristics table.
Note that a DAC can be set to a value that produces an
output below the under-scale level. In this case, the under-
scale limit will prevent the output from getting to the desired
value. The value of the minimum scale should not be set so
low that the PGA voltage output, VO, goes below its speci-
fied range of 0.2V from IRET.
ADJUSTABLE OVER-SCALE AND
UNDER-SCALE LIMITING CIRCUIT
The XTR108 incorporates circuitry to set adjustable limits at
the output in cases when the sensor signal goes above or
below its range. There are 16 levels for over-scale limit
adjustment (4-bit DAC) and 8 levels for the under-scale (3-bit
DAC).
VOLTAGE GAIN 6.25 12.5 25 50 100 200 400
V/V
OUTPUT TRANSCONDUCTANCE 49 99 197 394 789 1577 3155
mA/V
FULL-SCALE DIFFERENTIAL VIN 320 160 80 40 20 10 5
mV
TABLE I. PGA Gain, Corresponding Loop Transductance
and Input Full-Scale Differential Voltage.
XTR108
10 SBOS187C
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FIGURE 2. XTR108 Internal Block Diagram.
4-20mA
Voltage
Reference
Sub-Regulator
Driver
Linearization
Circuit
Multiplexer
SDIO SCLK
CS2
CS1
V/I-0
V/I-1
V/I-2
V/I-3
V/I-4
V/I-5
RTD
R
Z1
R
Z2
R
Z3
R
Z4
R
Z5
C
FILT
0.01µF
R
CM
15.8k12.1k
R
SET
R
LIN
R
VI
6.34k
V
OUT
I
IN
PGA
OPA +IN
OPA IN
OPA OUT REF
IN
REF
OUT
Σ
V
Gate
V
S
I
O
I
RET
I
REF
DAC
I
LIN
DAC
Zero
DAC
SPI and
Control Circuits
OSC
R
LOAD
+
Loop
Supply
XTR108
C
GATE
C
REG
C
LOOP
Output
Current
Amplifier
12
2.5k
51
XTR108 11
SBOS187C www.ti.com
The circuit is designed for compliance with NAMUR NE43
recommendation for sensor interfaces. The limit levels are
listed in Tables VII and VIII. Because of the large step sizes,
units that use this feature should be checked if the value is
critical. The under-scale limit circuit will override the Zero
DAC level if it is set lower and there is not enough sensor
offset at the PGA input.
It may be necessary to disable limiting if the XTR108 is used
in applications other than a 4-20mA transmitter, where the
PGA output is between 0.5V and 4.5V.
SENSOR FAULT DETECTION CIRCUIT
To detect sensor burnout and/or short, a set of four compara-
tors is connected to the inputs of the PGA. If any of the
inputs are taken outside of the PGA’s common-mode range,
the corresponding comparator sets a sensor fault flag that
causes the PGA output to go either to the upper or lower
error limit. The state of the fault condition can be read in the
digital form from register 3. The direction of the analog
output is set according to the “Alarm Configuration Regis-
ter” (see Table X). The level of the output is produced as
follows: if the over-scale/under-scale limiting is enabled, the
error levels are: over-scale limit +2LSBs of the over-scale
DAC, about 1mA referred to IOUT or 0.125V referred to VO,
of under-scale limit –2LSBs of the under-scale DAC, about
0.4mA referred to IOUT or 0.05V referred to VO. If the over-
scale/under-scale limiting is disabled, the PGA output volt-
age will go to within 150mV of either positive or negative
supply (VS or IRET), depending on the alarm configuration
bit corresponding to the error condition.
OUTPUT CURRENT AMPLIFIER + RVI RESISTOR
To produce the 4-20mA output, the XTR108 uses a current
amplifier with a fixed gain of 50A/A. The voltage from the
PGA is converted to current by the external resistor, RVI. Pin
IRET, the common potential of the circuit (substrate and local
ground), is connected to the output and inverting input of the
amplifier. This allows collecting all external and internal
supply currents, sensor return current, and leakage currents
from the different parts of the system and accounting for
them in the output current. The current from RVI flows into
the pin IIN that is connected to the noninverting input and
therefore, is at ground potential as well. The ratio of two
VOLTAGE REFERRED TO VO PIN
WITH RESPECT TO IRET CURRENT REFERRED TO IOUT PIN
OVERALL VZERO = VZ PROGRAM + VZ COARSE + VZ FINE IZERO = IZ PROGRAM + IZ COARSE + IZ FINE
PROGRAM VV
ZPROGRAM REF
=358
.
IV
R
ZPROGRAM REF
VI
=175
8
COARSE DAC VVN
Z COARSE REF
=•
80 4
13
IV
RN
Z COARSE REF
VI
=•
584
13
FINE DAC
VVN
ZFINE REF
=•
80 64
12
IV
RN
ZFINE REF
VI
=•
5864
12
NOTE: N13 and N12 are assigned decimal values of registers 13 and 12, respectively.
TABLE II. Equations for Calculating Zero Output.
matched internal resistors determines a current gain of this
block. Note that the IOUT pin is always biased below the
substrate potential.
EXCITATION CURRENT DACS AND R
SET
RESISTOR
Two matched adjustable reference current sources are avail-
able for sensor excitation. The defining equations are given
in Table III. Both current sources are controlled simulta-
neously by the coarse and fine DACs with a pedestal.
The external resistor RSET is used to convert the REF voltage
into the reference current for the sensor excitation DACs.
The total current output of the DACs is split, producing two
references: IREF1 and IREF2. Both of the current references
match very closely over the full adjustment range without
mismatched differential steps. Both current reference out-
puts must be within the compliance range, i.e.: one reference
cannot be floated since it will change the value of the other
current source.
The recommended value of RSET is 12.1k for use with
100 RTD sensors. This generates IREF1, 2 = 492µA currents
when both coarse and fine DACs are set to zero. The value
of the RSET resistor can be increased if lower reference
currents are required, i.e.: for 1000 RTD or a bridge
sensor.
Similar to the Zero DACs, the outputs of the fine and coarse
DAC are summed together with the pedestal IREF PROGRAM.
Each of the excitation DACs has 8-bit resolution (256 steps)
with 4-bit overlap between the coarse and the fine. This
REFERENCE CURRENT
OVERALL IREF1, 2 = IREF PROGRAM + IREF COARSE + IREF FINE
PROGRAM
IV
R
REFPROGRAM REF
SET
=5
COARSE DAC
IV
RN
REF COARSE REF
SET
=•
11
64
FINE DAC
IV
RN
REFFINE REF
SET
=•
10
1024
NOTE: N11 and N10 are the decimal values of registers 11 and 10,
respectively.
TABLE III. Equations for Calculating the Values of Each
Reference Current.
XTR108
12 SBOS187C
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means that one LSB of the coarse DAC is equal to 16 fine
LSBs, and the full-scale range of the fine DAC is equal to 16
coarse LSBs. This effectively produces 12-bit adjustment
resolution. This allows the user to set pre-calculated values
before the calibration, using the coarse DAC only and adjust
the reference current output level with the fine DAC during
the calibration process.
LINEARIZATION CIRCUIT AND RLIN RESISTOR
The XTR108 incorporates circuitry for correcting a second-
order sensor nonlinearity. A current proportional to the
voltage at the input of the PGA is added to the sensor
excitation. The RLIN resistor is used to convert this voltage
into current. By appropriately scaling this current using the
linearization DAC, parabolic sensor nonlinearity can be
improved by up to a 40:1 ratio, as shown in Figure 3. The
linearization coefficient (ratio of the reference current change
to the input voltage) is expressed in µA/mV as follows:
GI
VNR
LIN REF
IN LIN
=•
14
16
where N14 is the decimal value from register 14.
The recommended value of the resistor is 15.8k, for use
with 100 RTD sensors. This value produces a full-scale
linearization coefficient of about 1mA/V. Please see the
section below on using the XTR108 with an RTD tempera-
ture sensor. If the sensor excitation is scaled down by
increasing the value of RSET, the value of RLIN should be
scaled proportionally.
SUB-REGULATOR WITH EXTERNAL MOSFET
The XTR108 is manufactured using a low-voltage CMOS
process with maximum supply voltage limited to 5.5V. For
applications in a 4-20mA current loop, a special sub-regulator
circuit is incorporated in the device that requires an external
n-channel depletion-mode MOS transistor and three capaci-
tors, see Figure 2.
A number of third-party suppliers make n-channel deple-
tion-mode MOSFETs. A list of devices tested by Texas
Instruments, Inc. is shown in Table IV with the capacitor
values recommended for those devices.
The capacitors CLOOP (0.01µF), CREG (2.2µF), and CGATE
are required for the regulator loop stability and supply
bypass. They should be placed in close proximity to the
XTR108 on the PCB. An additional 1µF capacitor may be
used to bypass the supply of an EEPROM chip.
If a MOSFET other than those listed in Table IV is used, the
value of CGATE should be adjusted such that there is no
overshoot of VS during power-up and supply glitches. Any
VS overshoot above 7.5V may damage the XTR108 or
deteriorate its performance.
LOOP VOLTAGE
The XTR108 transmitter minimum loop voltage can some-
what be effected by the choice of the external MOSFET. The
devices are tested to 7.5V compliance with Supertex DN2540;
choosing other MOSFETs can change this value slightly.
The maximum loop voltage is limited by the power dissipa-
tion on the MOSFET as well as its breakdown voltage.
Possible ambient temperatures and the power dissipation
should be taken into account when selecting the MOSFET
package. The external MOSFET can dissipate a consider-
able amount of power when running at high loop supply. For
example, if VLOOP = 24V and IOUT = 20mA, the DC power
dissipated by the MOSFET is:
PMOSFET = IOUT (VLOOP – VS) = 380m
For a SOT-89 package soldered on an FR5 board, this will
cause a 30°C rise in the temperature. The power dissipation
gets significantly higher when the circuit is driven into an
over-scale condition. Therefore, special attention should be
paid to removing the heat from the MOSFET, especially
with small-footprint packages such as SOT-89 and TO-92.
Please follow manufacturer’s recommendations about the
package thermal characteristics and board mounting.
UNCOMMITTED OP AMP
For added flexibility in various applications, the XTR108
has an on-chip uncommitted operational amplifier. The op
amp has rail-to-rail output range. The input range extends to
IRET potential.
FIGURE 3. Pt100 Nonlinearity Correction Using the XTR108.
200°CProcess Temperature (°C) +850°C
5
4
3
2
1
0
1
Uncorrected
RTD Nonlinearity
Corrected
Nonlinearity
Nonlinearity (%)
MANUFACTURER MOSFET MODEL CGATE VALUE
Supertex DN2535, DN2540 220pF
DN3535, DN3525 1000pF
Siliconix ND2012, ND2020 220pF
Infineon BSP149 1000pF
TABLE IV. Recommended Gate Capacitor Values For Se-
lected MOSFETs.
XTR108 13
SBOS187C www.ti.com
The uncommitted amplifier can be used for a variety of
purposes, such as voltage sensor excitation, buffering the
REFOUT pin, four-wire RTD connection, or sensing the
bridge voltage for temperature compensation.
POWER-GOOD/POWER-ON RESET
In case of a supply brownout condition or short interruption,
the XTR108 power-good detection circuit will initiate a chip
reset that will cause all registers to be reset to 0’s and a cycle
of EEPROM read to begin. The circuit generates a reset if
VS droops below 1.5V and then recovers up to the normal
level.
USING THE XTR108 IN VOLTAGE OUTPUT MODE
The XTR108 can be used not only in 4-20mA current loops,
but also as a low-power, single-supply, "smart" sensor-
conditioning chip with voltage output. In this mode,
the IRET pin must be connected below ground
(–200mV < IRET < –25mV). This negative voltage is
required to overcome the input offset voltage of the output
current amplifier and prevent it from turning on and drawing
excessive current. An application circuit that generates this
negative voltage using the XTR108 clock output and a
simple charge pump is shown in the application section.
The sub-regulator with an external MOSFET may or may not
be used. If the circuit is powered externally, the supply
voltage must be in the range of 5V ±0.5V.
CONTROL REGISTERS
Table V shows the registers that control the analog functions
of the XTR108.
DESCRIPTION OF CONTROL REGISTERS
Address = 0: Control Register 1
If the RST bit is set to ‘1’ in a write operation, all the
registers in the XTR108 will be returned to their power-on
reset condition. The RST bit will always read as a ‘0’. CSE,
the checksum error bit, is read only and will be set to ‘1’ if
a checksum error has been detected. This bit is cleared by a
reset operation or by detection of a valid checksum. The
remaining bits are reserved and must be set to ‘0’.
Address = 3: Fault Status Register
This register is a read-only register. If the input voltage to
the PGA exceeds the linear range of operation, the XTR108
will indicate this error condition (typically caused by a
sensor fault) by setting the under-scale or over-scale error
level depending on the state of the Alarm Configuration
Register (Address = 7). Information on the nature of the fault
may be read in digital form from this register, as shown in
Table VI. The remaining bits will be set to ‘0’.
TABLE V. Analog Control Registers.
Instruction D7 D6 D5 D4 D3 D2 D1 D0
Read/Write R/W 0 0 0 A3 A2 A1 A0
EEPROM Mode 0 1 1 1 1111
D7 D6 D5 D4 D3 D2 D1 D0
0 RST CSE 0 0 0 0 0 0 Read/Write Control Register 1
100000000Reserved
200000000Reserved
30000F3F2F1F0Read Only Fault Status Register
40000000RBDRead/Write Control Register 2
5 FD US2 US1 US0 OS3 OS2 OS1 OS0 Read/Write Over/Under-Scale Register
600000G2G1G0Read/Write PGA Gain
7 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Read/Write Alarm Config. Register
8 0 VP2 VP1 VP0 0 VN2 VN1 VN0 Read/Write PGA Input Config. Register
9 0 IB2 IB1 IB0 0 IA2 IA1 IA0 Read/Write IREF Output Config. Register
10 FG7 FG6 FG5 FG4 FG3 FG2 FG1 FG0 Read/Write Fine IREF Adjust Register
11 CG7 CG6 CG5 CG4 CG3 CG2 CG1 CG0 Read/Write Coarse IREF Adjust Register
12 FZ7 FZ6 FZ5 FZ4 FZ3 FZ2 FZ1 FZ0 Read/Write Fine Zero Adjust Register
13 CZ7 CZ6 CZ5 CZ4 CZ3 CZ2 CZ1 CZ0 Read/Write Coarse Zero Adjust Register
14 L7 L6 L5 L4 L3 L2 L1 L0 Read/Write Linearization Adjust Register
15 S7 S6 S5 S4 S3 S2 S1 S0 Read/Write Checksum Register
Read/Write Operation
Data Bit
Assert CS2
Ignore Serial Data/A
BIT FAULT MODE
F0 Negative Input Exceeds Positive Limit.
F1 Negative Input Exceeds Negative Limit.
F2 Positive Input Exceeds Positive Limit.
F3 Positive Input Exceeds Negative Limit.
TABLE VI. Register 3, Fault Status Register.
XTR108
14 SBOS187C
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Address = 4: Control Register 2
If the RBD bit is set to ‘1’, the automatic read-back from the
EEPROM will be disabled after a valid checksum byte is
received in Register 15. This bit is read from the EEPROM
during a read-back by the XTR108 and allows the user to
program the XTR108 to read the EEPROM data once
(instead of continuously), and then disables the automatic
read-back function. The XTR108 will continuously read the
EEPROM if RBD is set to ‘0’. The remaining bits in this
register must be set to ‘0’.
Address = 5: Over- and Under-Scale Register
This register sets the magnitude of the over-scale current
limit and the magnitude of the under-scale current limit. The
threshold level, as shown in Table VII and VIII, is the
normal analog (no error condition) output limit. If an input
voltage to the PGA exceeds the linear operation range, the
output will be programmed to either the over-scale error
level or the under-scale error level. The over-scale error
level is 10mA greater than the over-scale threshold level.
The under-scale error level is 0.4mA less than the under-
scale threshold level. The FD bit will disable the over-scale
and under-scale limiting function as well as the PGA fault
indication error levels.
Address = 6: PGA Gain Register
This register sets the gain of the programmable-gain ampli-
fier. The unused bits must always be set to ‘0’. The gain step
to register content is given in Table IX.
Address = 7: Alarm Configuration Register
This register configures whether the XTR108 will go over-
scale or under-scale for various detected fault conditions at
the input of the PGA. Table X defines each of the bits.
If a bit corresponding to the particular error is set to ‘1’, the
output will go over-scale when it occurs and if a bit corre-
sponding to the particular error is set to ‘0’, the output will
go under-scale.
Address = 8: PGA Input Configuration Register
This register connects the inputs of the PGA to the various
multiplexed input pins. Tables XI and XII show the relation-
ship between register, contents, and PGA inputs.
IO OVER-SCALE
VO OVER-SCALE THRESHOLD
OS3 OS2 OS1 OS0 THRESHOLD RVI = 6.34k
0 0 0 0 2.625V 20.7mA
0 0 0 1 2.6875V 21.2mA
0 0 1 0 2.75V 21.7mA
0 0 1 1 2.8125V 22.2mA
0 1 0 0 2.875V 22.7mA
0 1 0 1 2.9375V 23.2mA
0 1 1 0 3.0V 23.7mA
0 1 1 1 3.0625V 24.2mA
1 0 0 0 3.125V 24.6mA
1 0 0 1 3.1875V 25.1mA
1 0 1 0 3.25V 25.6mA
1 0 1 1 3.3125V 26.1mA
1 1 0 0 3.375V 26.6mA
1 1 0 1 3.4375V 27.1mA
1 1 1 0 3.5V 27.6mA
1 1 1 1 3.5625V 28.1mA
TABLE VII. Register 5, Over-Scale Threshold.
IO UNDER-SCALE
VO UNDER-SCALE THRESHOLD
US2 US1 US0 THRESHOLD RVI = 6.34k
0 0 0 450mV 3.55mA
0 0 1 425mV 3.35mA
0 1 0 400mV 3.15mA
0 1 1 375mV 2.96mA
1 0 0 350mV 2.76mA
1 0 1 325mV 2.56mA
1 1 0 300mV 2.37mA
1 1 1 275mV 2.17mA
TABLE VIII. Register 5, Under-Scale Threshold.
SIGNAL PATH
PGA TRANSCONDUCTANCE
G2 G1 G0 VOLTAGE GAIN RVI = 6.34k
0 0 0 6.25V/V 49mA/V
0 0 1 12.5V/V 99mA/V
0 1 0 25V/V 197mA/V
0 1 1 50V/V 394mA/V
1 0 0 100V/V 789mA/V
1 0 1 200V/V 1577mA/V
1 1 0 400V/V 3155mA/V
1 1 1 Reserved
TABLE IX. Register 6, PGA Gains.
BITACACACACACACAC AC
#7654321 0
VINN hllhnnl h
VINP lhlhlhnn
NOTES: h = input exceeds positive common-mode range, l = input exceeds
negative common-mode range, and n = input pin is within the CM range.
TABLE X. Register 7, Alarm Configuration Register.
VP2 VP1 VP0 PGA POSITIVE INPUT
0 0 0 PGA VIN+ Connected to V/I-0
0 0 1 PGA VIN+ Connected to V/I-1
0 1 0 PGA VIN+ Connected to V/I-2
0 1 1 PGA VIN+ Connected to V/I-3
1 0 0 PGA VIN+ Connected to V/I-4
1 0 1 PGA VIN+ Connected to V/I-5
1 1 0 Reserved
1 1 1 Reserved
TABLE XI. Register 8, PGA Positive Input Selection.
VN2 VN1 VN0 PGA NEGATIVE INPUT
0 0 0 PGA VIN Connected to V/ I-0
0 0 1 PGA VIN Connected to V/I-1
0 1 0 PGA VIN Connected to V/ I-2
0 1 1 PGA VIN Connected to V/ I-3
1 0 0 PGA VIN Connected to V/ I-4
1 0 1 PGA VIN Connected to V/ I-5
1 1 0 Reserved
1 1 1 Reserved
TABLE XII. Register 8, PGA Negative Input Selection.
XTR108 15
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Address = 9: IREF Output Configuration Register
This register connects the reference currents to the various
multiplexed input pins. IREF connection codes are given in
Table XIII.
Address = 10: Fine IREF Adjust Register
This register sets the code to the 8-bit Fine DAC that adjusts
the magnitude of both reference currents. The DAC output
value has a bipolar range (for each reference current) and
can be calculated using the equations in Table III.
Address = 11: Coarse IREF Adjust Register
This register sets the code to the 8-bit coarse DAC that adjusts
the magnitude of both reference currents. The nominal value
for the reference current (both Coarse and Fine adjust set to ‘0’)
is I
PROGRAM
• 5. See Table III for formulas.
Address = 12: Fine Zero-Adjust Register
This register sets the code to the 8-bit Fine DAC that adjusts
the magnitude of the zero output currents. Equations are
given in Table II. Negative numbers are in Binary Two’s
Complement.
Address = 13: Coarse Zero-Adjust Register
This register sets the code to the 8-bit Coarse DAC that
adjusts the magnitude of zero-output current. See Table II
for equations. Negative numbers are given in Binary Two’s
Complement.
Address = 14: Linearization Adjust Register
This register sets the code to the 8-bit DAC that adjusts the
magnitude of the linearization feedback current. Value is
unipolar to 255.
Address = 15: Checksum Register
This register contains the checksum byte that is used to
validate the data read from the EEPROM. If a write occurs
to this register, and the checksum is invalid, an error condi-
tion will set (CSE = ‘1’). If the checksum is valid, the error
condition will be cleared (CSE = ‘0’).
If a checksum error is detected, the XTR108 will program
itself to the lowest under-scale error level.
SERIAL INTERFACE
PROTOCOL
The XTR108 has an SPI-compatible serial interface. The
data is transmitted MSB first in 8-bit bytes. The first byte is
an instruction byte in which the first bit is a read/write flag
(‘0’ = write, ‘1’ = read), the lowest four bits are the register
address and the remaining three bits are set to zero. The
second, and all successive bytes, are data. During a write
operation, the successive data bytes are written to successive
registers within the XTR108. The address is automatically
incremented at the completion of each byte. The SDIO line
is always an input during a write operation. During a read
operation, the SDIO line becomes an output during the
second and successive bytes. As in the case of a write
operation, the address is automatically incremented at the
completion of each byte. Each communication transaction is
terminated when CS1 is de-asserted. The CS2 line remains
de-asserted during read and write operations.
The calibration controller also needs to be able to read from
and write to the external EEPROM device. This is accom-
plished by sending a special instruction code (0x7F) to the
XTR108. At the completion of this instruction byte, the
XTR108 will assert the CS2 line to select the EEPROM
device and ignore all data on the SDIO line until CS1 is de-
asserted and reasserted. The CS2 line will also be de-
asserted when CS1 is de-asserted. This allows the calibra-
tion controller to communicate with the EEPROM device
directly. The calibration controller then has control over the
timing required to write data to the EEPROM device.
In normal operation, the XTR108 reads data from the EEPROM
device to retrieve calibration coefficients. This is accom-
plished by the read-back controller on the XTR108. The read-
back controller is clocked by an on-chip oscillator and pro-
vides stimulus to the EEPROM device over the SCLK, SDIO,
and CS2 lines to perform the read operation, while simulta-
neously providing stimulus to the serial interface controller in
the XTR108. The read-back controller defaults to being active
when the XTR108 is powered on and will be continuously
active unless disabled. (It will start a new read operation as
soon as the previous operation is completed, see Figure 4.) A
control bit (RBD) is provided to allow the XTR108 to read the
EEPROM once and then stop.
The read-back controller will abort a read-back operation
when the CS1 line is asserted. The calibration controller
must wait at least 40µs after setting the CS1 line LOW
before the first rising edge of SCLK occurs.
For an external controller to write directly to the XTR108
(sensor calibration operation) or load data into the EEPROM,
it is necessary to interrupt the default read-back mode. For
both of these modes, the SCLK direction must be reversed.
See Figure 5 for the timing of this operation. First, the SCLK
line must be pulled LOW for at least 20ns (t10). Then CS1
is set LOW. The XTR108 will set DIO to a tri-state within
20ns (t13) and CS2 HIGH within 50ns (t12). After a delay of
at least 40µs (t11), the external system will start communica-
tion with a rising edge on SCLK.
IA2 IA1 IA0 IREF CONNECTION
000 I
REF1 Connected to V/I-0
001 I
REF1 Connected to V/I-1
010 I
REF1 Connected to V/I-2
011 I
REF1 Connected to V/ I-3
100 I
REF1 Connected to V/ I-4
101 I
REF1 Connected to V/I-5
1 1 0 Reserved
1 1 1 Reserved
IB2 IB1 IB0 IREF CONNECTION
000 I
REF2 Connected to V/I-0
001 I
REF2 Connected to V/I-1
010 I
REF2 Connected to V/ I-2
011 I
REF2 Connected to V/I-3
100 I
REF2 Connected to V/I-4
101 I
REF2 Connected to V/ I-5
1 1 0 Reserved
1 1 1 Reserved
TABLE XIII. Register 9, IREF Output Configuration.
XTR108
16 SBOS187C
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As long as CS1 is held LOW, the external system can write to
the EEPROM. See Figure 7 for this timing. Releasing CS1
will allow the XTR108 to resume in the read-back mode.
For interactive calibration operations, the first command to
the XTR108 should set bit 0, Register 4 (RBD). This will
disable the read-back mode. It will be possible to write to the
various registers and cycle CS1. If RBD is not set, then as
soon as CS1 is released, the XTR108 will read the EEPROM
contents which will overwrite the data just loaded. Figure 6
shows read and write timing.
To be compatible with SPI EEPROM devices, the XTR108
latches input data on the rising edge of SCLK. Output data
transitions on the falling edge of SCLK. All serial interface
transactions must be framed by CS1. CS1 must be asserted
to start an operation, and it must be de-asserted to terminate
an operation.
FIGURE 5. Interrupting an XTR108 EEPROM Readback Cycle. (See Table XIV for timing key.)
FIGURE 4. Timing Diagram for the XTR108 Continuous Readback Cycle. (See Table XIV for timing key.)
Instruction/Address to EEPROM Data from EEPROM
CS2
SCLK
t
8
t
8
t
9
DIO 0000001100000100
Hi-Z
t10
CS2
SCLK
t11
t13
t12
DIO
CS1
XTR108 17
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FIGURE 6. Timing Diagram for Writing to and Reading From the XTR108 with EEPROM Readback Disabled. (See Table
XIV for timing key.)
CS1
SCLK
t1
t2t2
t3t4t6
t5
t7
DIO
FIGURE 7. Writing to and Reading From the EEPROM Device From External Controller. (See Table XIV for timing key.)
Instruction to XTR108 Data to/from EEPROM
CS2
SCLK
t
14
DIO 01111111
CS1
SPEC DESCRIPTION MIN TYP MAX UNITS
t1CS1 LOW to SCLK Rising Setup Time 2.0 ns
t2SCLK Pulse Width HIGH and LOW 100 ns
t3DIO to SCLK Rising Setup Time 20 ns
t4DIO to SCLK Rising Hold Time 20 ns
t5CS1 to Last SCLK Rising Hold Time 20 ns
t6SCLK Falling to DIO Driven Valid by XTR108 0 50 ns
t7CS1 to DIO Tri-State 0 20 ns
t8SCLK Pulse Width During EEPROM Readback 5 us
t9CS2 HIGH Between Successive EEPROM Readbacks 10 us
t10 SCLK Driven LOW Before CS1 LOW When Interrupting XTR108 Readback from EEPROM 20 ns
t11 CS1 LOW to SCLK Rising Setup Time When Interrupting XTR108 EEPROM Readback 40 us
t12 CS1 Falling to CS2 HIGH 0 50 ns
t13 CS1 Falling to DIO Tri-State 0 20 ns
t14 CS1 Rising to CS2 HIGH 0 20 ns
XTR108 EEPROM Update Rate in Continuous Readback Mode 0.9 kHz
TABLE XIV. Timing Diagram Key.
XTR108
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EEPROM DATA STORAGE
The XTR108 automatically reads data from an SPI-compat-
ible EEPROM device. The models 25C040 from MicroChip
and the AT25010 from Atmel have been tested and are
known to work. Equivalent devices with an SPI interface can
be expected to work. The XTR108 will read data from
addresses 4 through 15 of the EEPROM. The address in the
EEPROM is the same as the address for the corresponding
data in the XTR108. The XTR108 will not write data to the
EEPROM. The external calibration controller is responsible
for writing data to the EEPROM.
CHECKSUM FUNCTION
To validate the data from the EEPROM device, the XTR108
calculates a checksum on the incoming serial-data stream
during each write operation. The value written to the EEPROM
that will be transferred to register 15 during an EEPROM read
operation must be such that the sum of the data in registers 4
through 15 totals 0xFF (255). The sum is calculated by
performing an add/accumulate function on all of the data
bytes of a read operation. An end-around carry is used during
the add/accumulate operation. If a carry-out was generated in
the previous add operation, it is used as a carry-in for the next
add operation for the checksum operation. The following code
shows how the value of register 15 could be calculated:
Sum = 0
FOR Index = 4 TO 14
Sum = Sum + Data [Index]
IF Sum > 255 THEN
Sum = Sum – 255
NEXT Index
Data [15] = 255 – Sum
For a test or calibration operation, it may be necessary to
write to a few select registers. This may be accomplished
without writing to register 15. To accomplish this, write to
the necessary registers and release CS1. There is no need to
update register 15.
If the command is to disable the automatic read-back func-
tion by setting the RDB bit in register 4, it is necessary to
rewrite the entire register set data with a correct checksum
value in register 15. The automatic read-back mode will be
disabled upon successful checksum operation.
The checksum error flag is also cleared when the XTR108
is reset (i.e.: at power ON). Write operations that do not
write to the checksum register will have no effect on the
checksum error flag. By locating the checksum register after
the last configuration register and including the checksum
register in the EEPROM read operation, the data is validated
by the checksum function.
EEPROM DATA SECURITY
Since the data in the EEPROM directly affects the analog
output of the XTR108, the data in the EEPROM needs to be
secure from accidental write operations. SPI EEPROM de-
vices have a write-protect function on one of the pins. An
additional connection to the calibration controller would be
required if the write-protect pin is used to prevent accidental
write operations. SPI EEPROM devices require a special
write enable instruction to be executed to write data to the
EEPROM. It is unlikely that this would accidentally be
written to the EEPROM device and then be followed by a
valid write operation. Further security can be obtained by
using an SPI EEPROM device that has internal write-protect
control bits. These bits are nonvolatile and must be cleared
before write operations are allowed.
SURGE PROTECTION
Remote connections to current transmitters can sometimes
be subjected to voltage surges. It is prudent to limit the
maximum surge voltage applied to the XTR108 with various
zener diodes and surge-clamping diodes specially designed
for this purpose. Since the maximum voltage on the XTR108
loop is limited by the external MOSFET breakdown voltage,
usually more than 200V, the requirement to the clamping
devices are not very strict. For example, a 50V protection
diode will assure proper transmitter operation at normal loop
voltages without significant leakage yet provide an appro-
priate level of protection against voltage surges. In case of
prolonged (seconds and longer) overvoltage, lower voltage
clamps may be used to limit the power dissipation on the
transmitter.
Most surge-protection zener diodes have a diode character-
istic in the forward direction that will conduct excessive
current, possibly damaging receiving-side circuitry if the
loop connections are reversed. If a surge protection diode is
used, a series diode or diode bridge should be used for
protection against reversed connections.
REVERSE-VOLTAGE PROTECTION
The XTR108’s low compliance rating (7.5V) permits the
use of various voltage protection methods without compro-
mising operating range. Figure 8 shows a diode bridge
circuit which allows normal operation even when the volt-
age connection lines are reversed. The bridge causes a two
diode drop (approximately 1.4V) loss in loop supply volt-
age. This results in a compliance voltage of approximately
9V—satisfactory for most applications. If 1.4V drop in loop
supply is too much, a diode can be inserted in series with the
loop supply voltage and the V+ pin. This protects against
reverse output connection lines with only a 0.7V loss in loop
supply voltage.
RADIO FREQUENCY INTERFERENCE
The long wire lengths of current loops invite radio frequency
interference. RF energy can be rectified by the sensitive
input circuitry of the XTR108 causing errors. This generally
appears as an unstable output current that varies with the
position of loop supply or input wiring.
If the RTD sensor is remotely located, the interference may
enter at the input terminals. For integrated transmitter as-
semblies with short connection to the sensor, the interfer-
ence more likely comes from the current loop connections.
Bypass capacitors on the input reduce or eliminate this input
interference. Connect these bypass capacitors to the IRET
terminal, see Figure 9. Although the DC voltage at the IRET
terminal is not equal to 0V (at the loop supply, VPS) this
circuit point can be considered the transmitter’s “ground.”
The 0.01µF capacitor connected between VLOOP and IO may
help minimize output interference.
XTR108 19
SBOS187C www.ti.com
FIGURE 8. Reverse Voltage and Over-Voltage Protection.
XTR108
11
V+
IO
VPS
10
0.01µF
RL
D1(1)
14
13
NOTE: (1) Zener Diode 36V: 1N4753A or General
Semiconductor TransorbTM 1N6286A. Use lower
voltage zener diodes with loop power supply
voltages less than 30V for increased protection.
See Over-Voltage Surge Protection.
Maximum VPS must be
less than minimum
voltage rating of zener
diode.
The diode bridge causes
a 1.4V loss in loop supply
voltage.
1N4148
Diodes
12
IRET
RTD APPLICATION
The values to be entered into the DAC control registers are
given by the formulas in Table XV.
1) For a chosen temperature range, using an industry-stan-
dard polynomial set as shown in Table XVI, calculate
RTD values at min, max, and the middle temperatures:
RR andR
MIN MAX MID
,,
()
2) Calculate a relative nonlinearity BV using the RTD val-
ues from above:
BRRR
RR
VMID MAX MIN
MAX MIN
=
+
2
3) Pick an external zero resistor, RZ closest to RMIN. Select-
ing RZ greater than RMIN will cause a voltage offset that
must be corrected by the PGA zero adjustment.
4) Calculate the linearization coefficient::
GB
BR BR BR
LIN V
V MAX V MIN V Z
=+
()()
2
05 05 2.–.
If the value of GLIN is larger than GLIN MAX = (16/
RLIN) the external resistor RLIN has to be changed. If
GLIN is significantly smaller (> 10 times) than GLIN
MAX, the RLIN value should be increased to minimize
the DAC quantization errors. For 100 RTD sensors
the required linearization coefficients are in the range
from 0.3 to 0.6 mA/V (1/k) for all measurement
ranges. Therefore an external RLIN value of 15.8k is
good setting the full-scale GLIN MAX ~ = 1mA/V. For
1k RTD’s the RLIN should be increased proportion-
ally.
5) Choose the output zero and full-scale level values, for
instance: IOUTMIN = 4mA, IOUTMAX = 20mA.
EXCITATION CURRENT IREF
Coarse DAC code
N round IR
V
REF SET
REF
11
64 320=
Fine DAC Code
N round IR
VN
REF SET
REF
10 11
1024 5120 16=−−
ZERO OUTPUT IZERO
Coarse DAC Code
N round IR
V
ZERO VI
REF
13
325140=
Fine DAC Code
N round IR
VN
ZERO VI
REF
12 13
512
52240 16=−−
LINEARIZATION COEFFICIENT GLIN
Lin DAC Code
N round G R
LIN LIN14 16=•
()
TABLE XV. Equations for DAC Code Calculation.
TABLE XVI. Standard RTD Descriptive Equations.
This procedure allows calculation of the parameters needed
to calculate the DAC codes for an RTD sensors application.
S dardRTD Polynomials
R R At B C t C t for C t C
R R At B for C t C
Ae
Be
Ce
R base RTD value at C or k
tO
tO
O
tan :
...
=+++°
()
[]
−°<<°
=++
[]
°<< °
=−
=−
=−
−°
()
1 1 100 200 0
1 1 0 850
3 9083 3
5 775 7
4 183 12 0 100 1
23
2
ΩΩ
XTR108
20 SBOS187C
www.ti.com
6) Choose PGA gain from the available list and calculate
the initial excitation current using:
III GRRR
ARR
REF OUT OUT LIN MAX Z VI
PGA MAX MIN
MAX MIN
12
1
50
,
––
=
()
()
()
••
()
Important: the PGA gain value should be chosen such
that the IREF value is within ±35% of 5VREF/RSET to
allow room for calibration adjustments without having
to go to another span step.
7) The required DAC zero offset current value can be
calculated by:
II AI R R
R
ZERO OUT PGA REF MIN Z
VI
MIN
=
()
50
Example:
Measurement Range: TMIN = –20°C, TMAX = 50°C; 100
RTD.
1) RMIN = 92.16, RMAX = 119.40, RMID = 105.85;
2) Sensor relative nonlinearity: BV = 0.0026;
3) Choosing RZ = 90.9 (closest to RMIN 2% value);
4) Linearization coefficient: GLIN = 0.3804mA/V;
5) 4-20mA output span;
6) PGA voltage gain APGA = 200, sensor excitation current
IREF1,2 = 368.39mA;
7) Zero offset DAC: IZERO = 3.268mA
CALIBRATION PROCEDURE FOR RTD SENSORS
Step 1 Initial parameters calculation.
Using the procedure above, compute IREF, APGA, IZERO,
and GLIN based on TMIN, TMAX, and nominal values of
RZ, RSET, and RVI. Use the equation in Table XV to
calculate the DAC register values.
Configure the input MUX, write PGA gain, reference,
and offset DAC registers of the XTR108 with calcu-
lated settings. Note: write GLIN = 0 (no linearization) to
XTR108 at this step;
Step 2 Measurement.
Set RTD resistor value (or oven temperature) to mini-
mum scale, measure output signal IMEAS1;
Set RTD resistor value (or oven temperature) to maxi-
mum scale, measure output signal IMEAS2;
Step 3.
Calculate corrections using the following equations:
IIIR
AR R
RR IIR
AI
GB
BR BR BR
REF MEAS MEAS VI
PGA MAX MIN
ZMIN
ZERO MEAS VI
PGA REFA
LINA V
V MAX V MIN V ZA
A
A
=
()
()
=+
()
=+
()()
21
1
50
50
2
05 05 2
.–.
III GRRR
ARR
III II
AdjustedI fineDAC Code N N round IR
V
II I AI
REFBOUTMAX OUTMIN LIN A MAX ZAVI
PGA MAX MIN
REF REF REFAREF REFB
REF AREF SET
REF
ZERO OUTMIN ZERO PGA REF
=
(
)
(
)
(
)
••
(
)
=
(
)
+
(
)
=+
=
––
––
:
––
_
1
50
1024
50
10 10
BB MIN ZA
VI
ZERO AZERO VI
REF
RR
R
AdjustedI fine DAC Code N N round IR
V
:
(
)
=+
12 12 5125
This takes into account resistor value deviations, all
offsets and gain errors of the coarse DACs and PGA. If
the adjusted abs(N12A) > 128 or abs(N10A) > 128, adjust
the coarse DAC first, then recalculate the fine DAC
value;
Update all the DAC register value, including lineariza-
tion DAC.
Step 4 (optional).
Measure output signal IMEAS3 with maximum RTD value
still connected to the input from step 2;
Step 5 (optional).
Compute GLIN correction and update LinDAC register;
Step 6 (optional).
Make verification measurements at min- and max-input
signal; If linearity check is needed: make a measurement at
mid-scale; write EEPROM data.
Step 7.
Set the desired over-scale, under-scale signal limits and
sensor burnout indication configuration. Verify and adjust
the over-scale and under-scale levels by applying the posi-
tive and negative overdriving differential signals to the PGA
inputs.
XTR108 21
SBOS187C www.ti.com
SAMPLE ERROR ANALYSIS
Table XVII shows a detailed computation of the error
accumulation. The sample error budget is based on a typical
RTD circuit (Pt100, 200°C measurement span). Note that
these calculations are based on typical characteristics where
no maximum or minimum characteristic is available. The
assumption is made that all errors are positive and additive.
As the various error sources are independent, a closer
approximation to nominal performance might be to accumu-
late the errors with a root-sum-square calculation.
CALIBRATED ERROR
ERROR SOURCE ERROR EQUATION SAMPLE ERROR CALCULATION (ppm of Full Scale)
INPUT
Input Offset Voltage Note (1) 0
vs Common Mode CMRR CM/(VIN MAX) 1065µV/V 0.1V/0.04V 10612.5
Input Bias Current Note (1) 0
Input Offset Current Note (1) 0
Total Input Error: 12.5
EXCITATION
Current Reference Accuracy Note (1) 0
vs Common Mode CM/ROUT RRTD MIN/(VIN MAX) 1060.1V/100M 100/40mV 2.5
Current Reference Matching Note (1)
DAC Resolution and Linearity 1LSBFINE RRTD MIN/(VIN MAX ) 10696nA 100/40mV 106240
Total Excitation Error: 242.5
GAIN
Span Note (1) 0
Nonlinearity Nonlinearity (%)/100% 1060.01%/100% 106100
Total Gain Error: 100
OUTPUT
Zero Output Note (1) 0
vs Supply (IZERO vs V+) V+/16mA 106Note (2) 6
DAC Resolution and Linearity 2LSBFINE/16mA 1062 1.8µA/16mA 106225
Total Output Error: 231
DRIFT (TA = 20°C)
Input Offset Voltage Drift TA/(VIN MAX) 1060.02µV/°C 20°C/40mV 106 10
Current Reference Accuracy Drift TA35ppm 20°C 700
Current Reference Matching Drift TA IREF RRTD MIN/(VIN MAX) 15ppm 20°C 518.9µA 100/40mV 390
Span Drift TA30ppm 20°C 600
Zero Output Drift TANote (1) 250
Total Drift Error: 1950
NOISE (0.1Hz to 10Hz, Typ)
Input Offset Voltage VN/(VIN MAX) 1066µV/40mV 106150
Current Reference IREF Noise RRTD MIN/(VIN MAX) 1060.015µA 100/40mV 10637.5
Zero Output IZERO Noise/16mA 1061.1µA/16mA 10668.5
Total Noise Error: 256
TOTAL ERROR: 2792 (1997)(3)
0.28% (0.20%)(3)
SAMPLE ERROR CALCULATION
RTD value at 4mA Output (RRTD MIN) 100: RTD Measurement Range 200°C; Ambient Temperature Range (TA) 20°C; Supply Voltage Change (V+) 5V; Common-
Mode Voltage Change (CM) 0.1V.
Chosen XTR108 parameters: PGIA gain = 50; I
REF
= 518.9µA; Full-scale V
IN
= 40mW. Register 06 = 0
H
03; Register 11 = 0
H
11; Register 13 = 0
H
FC; Register 14 = 0
H
70.
NOTES: (1) Does not contribute to the output error due to calibration. (2) All errors are referred to input unless otherwise stated. (3) Calculated as root-
sumsquare.
TABLE XVII. Sample Error Budget Calculation.
XTR108
22 SBOS187C
www.ti.com
APPLICATIONS
RTD CONNECTION METHODS
Two-Wire Connection
The simplest circuit that can be used to connect an RTD to
the XTR108 is the two-wire connection shown in Figure 9.
If the RTD is separated from the XTR108 by any distance
the resistance of the lead wires can cause significant error in
the reading. This wire resistance is noted as RLINE1 and
RLINE2. If the RF filter is not required, then the PGA inputs
could be taken from the same pins as are used for the current
sources.
Three-Wire Connection
It is possible to minimize the errors caused by the lead-wire
resistance by connecting the RTD, see Figure 10. Operating
under the assumption that the wire connecting pin 1 to the
XTR108 is the same length as the wire at pin 2, and with the
current through the RTD identical to the current through RZ
any error voltage caused by the lead-wire is the same on both
sides. This appears as a common-mode voltage and is
subtracted by the PGA.
The circuit in Figure 10 also shows a scheme where one
board can be optimized for a wide range of temperatures.
Consider a range of applications where there are up to five
different minimum temperatures. Select RZ1 through RZ5 to
be optimum for each of the minimum temperatures. The
configuration codes in the EEPROM can be set to select that
resistor for that unique situation.
Four-Wire Connection
For those applications where the resistance of the lead-wires
is not equal, it may be an advantage to add a precision op
amp to a four-wire connection, see Figure 11. The voltage
offset and drift are error terms that degrade the operation of
the system. This circuit does not suf fer any loss of accuracy
for the resistance of the RTD lead-wires.
BRIDGE SENSOR CONNECTIONS
Fixed Voltage Excitation
There exists a class of sensors that are best supplied with a
voltage source excitation such as the bridge sensor shown in
Figure 12. The excitation voltage here is given by:
VV R
R
EX REF
=+
1
1
2
Uni-Directional Linearity Control
The circuit in Figure 13 shows a bridge sensor with an
excitation voltage that is adjusted to linearize the response
using the same algorithm as the RTD linearization.
VIR
EX REF I
=•2
FIGURE 9. Two-Wire RTD Connection with RF Filter at Input Terminals.
Multiplexer
0.01µF0.01µF
1k
1k
RLINE2
RLINE1
RZ
1
2
RTD
RCM IRET
0.01µF
XTR108 23
SBOS187C www.ti.com
FIGURE 10. Three-Wire RTD Connection with Multiple Minimum Temperature Capabilities.
FIGURE 11. Four-Wire RTD Connection.
Multiplexer
R
LINE3
R
LINE2
R
LINE1
21
3
RTD
R
21
R
22
R
23
R
24
R
25
R
CM
I
RET
0.01µF
Equal line resistances here create a
small common-mode voltage which is
rejected by the XTR108.
Resistance in this line causes a small
common-mode voltage which is rejected
by the XTR108.
Multiplexer
4
3
2
1
RTD
RCM
0.01µF
OPA277
IRET
VS
RLINE1
RZ
RLINE2
RLINE3
RLINE4
XTR108
24 SBOS187C
www.ti.com
FIGURE 12. Voltage Excited Bridge with Excitation Derived from VREF.
FIGURE 13. Voltage Excited Bridge with Uni-Directional Linearity by Control.
Multiplexer
IRET
VREF
R2
R1
Multiplexer
I
RET
V
REF
R
1
XTR108 25
SBOS187C www.ti.com
VOLTAGE OUTPUT MODE USING SIMPLE
CURRENT PUMP
In order for the voltage output mode of the XTR108 to
operate properly, a negative voltage needs to be applied to
the IRET pin (–200mV < IRET < –25mV). For systems without
a negative supply a charge pump is an easy way to generate
this voltage. Figure 14 shows a simple and inexpensive way
to build this charge pump using two resistors, two capaci-
tors, and two diodes (in an SOT package). The charge pump
uses the clock signal from the XTR108 SCLK pin to operate;
consequently, the XTR108 must be in continuous EEPROM
read mode (register 4, bit 0). Figure 15 shows the typical
output of this circuit (–50mV dc).
Voltage
Reference
Linearization
Circuit
Multiplexer
SDIO SCLK
CS2
CS1
V/I-0
V/I-1
V/I-2
V/I-3
V/I-4
V/I-5
RTD
RZ1 RZ2 RZ3 RZ4 RZ5
CFILT
0.01µF
RCM
15.8k12.1k
RSET
RLIN VOUT IIN
PGA
OPA +INOPA IN
OPA OUT
REFIN
REFOUT
ΣIREF
DAC
ILIN
DAC
Zero
DAC
SPI and
Control Circuits
OSC
XTR108
12 Sub-Regulator
Driver
VOUT
VOUT = 50mV
VGate
+5V
VS
IO
IQ1 = 0mA
Q1
0mV
+0V
IRET
Output
Current
Amplifier
2.5k
51
330pF
1nF
30k
36.5k
BAV99
DSUB
200mV < VOA+ < 25mV
FIGURE 14. Voltage Output Mode Using Simple Current Pump.
FIGURE 15. Output Waveform of Simple Current Pump.
5.0V XTR108
SCLK
Charge
Pump
Output
50mV
XTR108
26 SBOS187C
www.ti.com
COMMUNICATIONS WITH THE XTR108 USING A
MICROCONTROLLER
When communicating with the XTR108, special care must
be taken to avoid getting a false clock. When CS1 is driven
low, the false clock is generated because the microcontroller
clock pin is in high-impedance state, which forces the clock
pin to a logic high. Immediately after CS1 is driven low, the
microcontroller drives the clock pin low. This sequence
creates a glitch that the XTR interprets as a clock; see Figure
16. This condition can be avoided by driving the SCLK pin
low just prior to applying CS1 low; see Figure 17. A series
resistance should be placed between the microcontroller and
the XTR108 because driving SCLK low before CS1 can
create a bus contention; see Figure 18.
SCLK
SCLK is in High Z mode
(Pulled high by the pull-up
in the XTR108)
SCLK will be high immediately
after CS1 is driven low. This is
seen by the XTR108 as an
false clock.
CS1
FIGURE 16. False Clock.
SCLK
SCLK is in High Z mode
(Pulled high by the pull-up
in the XTR108)
SCLK is driven low by the
microcontroller just before
CS1 is driven low.
CS1
FIGURE 17. Proper Method to Drive the XTR108 to Avoid
False Clock.
FIGURE 18. Resistor Protects XTR108 and Microcontroller
During Bus Contention.
1k
SCLK
Memory
Microcontroller
DIOCS
SCLK
CS1
DIO
SCLK
DIO
XTR108
CS2
V
CC
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
XTR108EA ACTIVE SSOP DBQ 24 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
XTR108EA/2K5 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
XTR108EA/2K5G4 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
XTR108EAG4 ACTIVE SSOP DBQ 24 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
XTR108EA/2K5 SSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
XTR108EA/2K5 SSOP DBQ 24 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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