INFINEON Technologies 1 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
256 MBit Synchronous DRAM
The HYB39S256400/800/160CT(L) are four bank Synchronous DRAM’s organized as 4 banks x
16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices
achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to a system clock. The chip is
fabricated with INFINEON’s advanced 0.17 µm 256MBit DRAM process technology.
The dev ice is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible
depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a
single 3.3V +/- 0.3V power supply and are available in TSOPII packages.
•High Performance:
•Fully Synchronous to Positive Clock Edge
•0 to 70 °C operating temperature
•Four Banks controlled by BA0 & BA1
•Programmable CA S Latency: 2 & 3
•Programmable Wrap Sequence: Sequential
or Interleave
•Programmable Burst Length:
1, 2, 4, 8
•Full page burst length (optional) for
sequential wrap around
-7.5 -8 -8A Units
fCK 133 125 125 MHz
tCK3 7.5 8 8 ns
tAC3 5.4 6 6 ns
tCK2 10 10 12 ns
tAC2 6 6 6 ns
•Multiple Burst Read with Single Write
Operation
•Automatic and Controlled Precharge
Command
•Data Mask for Read / Write control (x4, x8)
•Data Mask for byte control (x16)
•Auto Refresh (CBR) and Self Refresh
•Power Down and Clock Suspend Mode
•8192 refresh cycles / 64 ms (7,8 µs)
•Random Column Address every CLK
( 1-N Rule)
•Single 3.3V +/- 0.3V Power Supply
•LVTTL Interface versions
•Plastic P a ckages:
P-TSOPII-54 400mil width (x4, x8, x16)
•-7.5 parts for PC133 3-3-3 operation
-8 parts for PC100 2-2-2 operation
-8A parts for PC100 3-2-2 operation
INFINEON Technologies 2 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Ordering Information
Pin Description and Pinouts:
Type Speed Grade Package Description
HYB 39S256400CT-7.5 PC133-333-520 P-TSOP-54-2 (400mil) 133MHz 4B x 16M x 4 SDRAM
HYB 39S256400CT-8 PC100-222-620 P-TSOP-54-2 (400mil) 125MHz 4B x 16M x 4 SDRAM
HYB 39S256400CT-8A PC100-322-620 P-TSOP-54-2 (400mil) 125MHz 4B x 16M x 4 SDRAM
HYB 39S256800CT-7.5 PC133-333-520 P-TSOP-54-2 (400mil) 133MHz 4B x 8M x 8 SDRAM
HYB 39S256800CT-8 PC100-222-620 P-TSOP-54-2 (400mil) 125MHz 4B x 8M x 8 SDRAM
HYB 39S256800CT-8A PC100-322-620 P-TSOP-54-2 (400mil) 125MHz 4B x 8M x 8 SDRAM
HYB 39S256160CT-7.5 PC133-333-520 P-TSOP-54-2 (400mil) 133MHz 4B x 4M x 16 SDRAM
HYB 39S256160CT-8 PC100-222-620 P-TSOP-54-2 (400mil) 125MHz 4B x 4M x 16 SDRAM
HYB 39S256160CT-8A PC100-322-620 P-TSOP-54-2 (400mil) 125MHz 4B x 4M x 16 SDRAM
HYB39S256xx0CTL PC100-xxx-620 P-TSOP-54-2 (400mil) Low Power Versions (on request)
CLK Clock Input DQ Data Input /Output
CKE Clo ck Enable DQM, LDQM, UDQM Data Mask
CS Chip Select Vdd Powe r (+ 3 .3 V )
RAS Row Addr ess Strobe Vss Ground
CAS Column Address Strobe Vddq Powe r fo r DQ’s (+ 3.3V)
WE Write Enable Vssq Ground for DQ’s
A0-A12 Ad dress Inputs NC not connected
BA0, BA1 Bank Select
INFINEON Technologies 3 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Pinout for x4, x8 & x16 organised 256M-DRAMs
SPP04126
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VDD
DQ0
A10/AP
A0
A1
A2
A3
VDD
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
CAS
WE
RAS
CS
BA0
BA1 BA1
BA0
CS
RAS
WE
CAS
N.C.
VDD
N.C.
VSSQ
DQ3
N.C.
VDDQ
DQ2
N.C.
VSSQ
DQ1
N.C.
VDDQ
VDD
A3
A2
A1
A0
A10/AP
DQ0
VDD VDD
BA1
BA0
CS
RAS
WE
CAS
N.C.
VDD
N.C.
VSSQ
DQ1
N.C.
VDDQ
N.C.
N.C.
VSSQ
DQ0
N.C.
VDDQ
VDD
A3
A2
A1
A0
A10/AP
N.C. VSS
N.C.
A8
A7
A6
A5
A4
VSS
VSSQ
N.C.
DQ3
VDDQ
N.C.
N.C.
VSSQ
N.C.
DQ2
VDDQ
N.C.
VSS
N.C.
CLK
DQM
CKE
A12
A11
A9 A9
A11
A12
CKE
DQM
CLK
N.C.
VSS
N.C.
VDDQ
DQ4
N.C.
VSSQ
DQ5
N.C.
VDDQ
DQ6
N.C.
VSSQ
VSS
A4
A5
A6
A7
A8
DQ7
VSS VSS
A9
A11
A12
CKE
UDQM
CLK
N.C.
VSS
DQ8
VDDQ
DQ9
DQ10
VSSQ
DQ11
DQ12
VDDQ
DQ13
DQ14
VSSQ
VSS
A4
A5
A6
A7
A8
DQ15
TSOPII-54 (400 mil x 875 mil, 0.8 mm pitch)
64 M x 4
32 M x 8
16 M x 16
INFINEON Technologies 4 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Block Diagram for 64M x 4 SDRAM ( 13 / 11 / 2 addressing)
Memory
Array
Bank 1
8196
x 2048
x 4 Bit
Memory
Array
Bank 2
8196
x 2048
x 4 Bit
Memory
Array
Bank 3
8196
x 2048
x 4 Bit
Column Address
Counter
Row
Decoder
Memory
Array
Bank 0
8196
x 2048
x 4 Bit
Column Decoder
Sense amplifier & I(O) Bus
Row
Decoder
Sense amplifier & I(O) Bus
Row
Decoder Row
Decoder
Column Decoder
Sense amplifier & I(O) Bus
Row Address
Buffer
Column Address
Buffer Refresh Counter
Sense amplifier & I(O) Bus
A0 - A12,
BA0, BA1
A0 - A9, A11, AP,
BA0, BA1
Column
Addresses Row
Addresses
Input Buffer Output Buffer
DQ0 - DQ3
Control Logic &
Timing Generator
CLK
CKE
CS
RAS
CAS
WE
DQM
Column Decoder
Column Decoder
INFINEON Technologies 5 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Block Diagram for 32M x 8 SDRAM ( 13 / 10 / 2 addressing)
Memory
Array
Bank 1
8192
x 1024
x 8 Bit
Memory
Array
Bank 2
8192
x 1024
x 8 Bit
Memory
Array
Bank 3
8192
x 1024
x 8 Bit
Column Address
Counter
Row
Decoder
Memory
Array
Bank 0
8192
x 1024
x 8 Bit
Column Decoder
Sense amplifier & I(O) Bus
Row
Decoder
Sense amplifier & I(O) Bus
Row
Decoder Row
Decoder
Column Decoder
Sense amplifier & I(O) Bus
Row Address
Buffer
Column Address
Buffer Refresh Counter
Sense amplifier & I(O) Bus
A0 - A12,
BA0, BA1
A0 - A9, AP,
BA0, BA1
Column
Addresses Row
Addresses
Input Buffer Output Buffer
DQ0 - DQ7
Control Logic &
Timing Generator
CLK
CKE
CS
RAS
CAS
WE
DQM
Column Decoder
Column Decoder
INFINEON Technologies 6 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Block Diagram for 16M x16 SDRAM ( 13 / 9 / 2 addressing)
Memory
Array
Bank 1
8192 x 512
x 16 Bit
Memory
Array
Bank 2
8192 x 512
x 16 Bit
Memory
Array
Bank 3
8192 x 512
x 16 Bit
Column Address
Counter
Row
Decoder
Memory
Array
Bank 0
8192 x 512
x 16 Bit
Column Decoder
Sense amplifier & I(O) Bus
Row
Decoder
Sense amplifier & I(O) Bus
Row
Decoder Row
Decoder
Column Decoder
Sense amplifier & I(O) Bus
Row Address
Buffer
Column Address
Buffer Refresh Counter
Sense amplifier & I(O) Bus
A0 - A12,
BA0, BA1
A0 - A8, AP,
BA0, BA1
Column
Addresses Row
Addresses
Input Buffer Output Buffer
DQ0 - DQ15
Control Logic &
Timing Generator
CLK
CKE
CS
RAS
CAS
WE
DQMU
DQML
Column Decoder
Column Decoder
INFINEON Technologies 7 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Signal Pin Description
Pin Type Signal Polarity Function
CLK Input Pulse Positive
Edge The system clock input. All of the SDRAM inputs are
sampled on the rising edge of the clock.
CKE Input Level Active
High Activates the CLK signal when high and deactivates the
CLK signal when low, thereby initiates either the Power
Down mode, Suspend mode, or the S elf Refresh mode.
CS Input Pulse Active
Low CS enables the command decoder when low and disables
the command decoder when high. When the command
decoder is disabled, new commands are ignored but
previous operations continue.
RAS
CAS
WE
Input Pulse Active
Low When sampled at the positive rising edge of the clock,
CAS, RAS, and WE define the command to be executed by
the SDRAM.
A0 - A 12 Input Level –During a Bank Activate command cycle, A0-A12 define the
row address (RA0-RA12) when sampled at the risin g clock
edge.
During a Read or Write command cycle, A0-An define the
column address (CA 0 -CAn) when sampled at the rising
clock edge.CAn depends from the SDRAM organization:
64M x4 SDRAM CAn = CA9, CA11 (Page Length = 2048 bits)
32M x8 SDRAM CAn = CA9 (Page Length = 1024 bits)
16M x16 SDRA M CAn = CA8 (Page Length = 512 bits)
In addition to the column address, A10(= AP) is used to
invoke autoprecharge operation at the end of the burst read
or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 (= AP) is used in
conjunction with BA0 and BA1 to c ontrol which bank(s) to
precharge. If A10 is high, all four banks will be precharged
regardless of the state of BA0 and BA1. If A10 is low, then
BA0 and BA1 are used to define which bank to precharge.
BA0, BA1 Input Level –Bank Select Inputs. Bank address inputs selects which of
the four banks a command applies to.
DQx Input
Output Level –Data Input/Output pins operate in the same manner as on
conventional DRAMs.
INFINEON Technologies 8 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
DQM
LDQM
UDQM
Input Pulse Active
High The Data Input/Output mask places the DQ buffers in a
high impedance state when sampled high. In Read mode,
DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQM
has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the
write operation if DQM is high.
One DQM input it present in x4 and x8 SDRAMs, L DQM
and UDQM controls the lower and upper bytes in x16
SDRAMs.
VDD
VSS
Supply –– Power and ground for the input buffers and the core logic.
VDDQ
VSSQ
Supply –– Isolated power supply and ground for the output buffers to
provide improved noise immunity.
Pin Type Signal Polarity Function
INFINEON Technologies 9 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.
Notes
1. V = Valid, x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock
before the commands are provided.
3. This is the state of the banks designated by BA0, BA1 signals.
4. Power Down Mode can’t be entered in a burst cycle. When this command assert in the burst
mode cycle device is clock suspend mode.
Operation Device
State CKE
n-1 CKE
nDQM BA0
BA1 AP=
A10 Addr
.CS RAS CAS WE
Bank Active Idle3 HXXVVVLLHH
Bank Precharge Any H X X V L X L L H L
Precharge All Any H X X X H X L L H L
Write Active3HXXVLVLHLL
Write with Autoprecharge Act ive3HXXVHVLHLL
Read Active3HXXVLVLHLH
Read with Autoprecharge Acti ve3HXXVHVLHLH
Mode Register Set Idle H X X V V V LLLL
No Operation Any H X X X X X L H H H
Burst Stop Active H X X X X X L H H L
Device Deselect Any H X X X X X H X X X
Auto Refresh Idle H H X X X X L L L H
Self Refresh Entry Idle H L X X X X L L L H
Self Refresh Exit Idle
(Self
Refr.) LHXXXXHXXX
LHHX
Clock Suspend Entry Active H L X X XXXXXX
Power Down Entry
(Precharge or active
standby)
Idle
Active4HLXXXXHXXX
LHHX
Clock Suspend Exit Active L H X X XXXXXX
Power Down Exit Any
(Power
Down) LHXXXXHXXX
LHHL
Data Write/Output EnableActive HXLXXXXXXX
Data Write/Output DisableActive HXHXXXXXXX
INFINEON Techn o logies 10 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
*) optional feature on this device
A11 A3A4 A2 A1 A0
A10 A9 A8 A7 A6 A5 Address Bus (Ax)
BT Burst LengthCAS Latency Mode Register (Mx)
CAS Latency
M6 M5 M4 Latency
000Reserved
001Reserved
010 2
011 3
100
Reserved
101
110
111
B urs t Len gth
M2 M1 M0 Length
Sequential Interleave
000 1 1
001 2 2
010 4 4
011 8 8
100
Reserved Reserved
101
110
1 1 1 Full page *)
Burst Type
M3 Type
0 Sequential
1 Interleave
Operation Mode
M9 Mode
0 burst read / burst write
1 burst read / single write
Operation Mode
BA0
BA1 A12
INFINEON Techn o logies 11 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Power On and Initializat ion
The default power on state of the mode register is supplier specific and may be undefined.
The following power on and initialization sequence guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and
initialized in a predefined manner.During power on, all VDD and VDDQ pins must be built up
simultaneously to the specified voltage when the input signals are held in the “NOP” state. The
power on vol tage must not exc eed VDD+ 0.3V on any of the i nput pins or VDD supp lies. The CLK
signal must be started at the same time. After power on, an initial pause of 200 µs is required
followed by a precharge of all banks using the precharge command. To prevent data contention on
the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial
pause period. Once all banks have been precharged, the Mode Register Set Command must be
issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also
required.These may be done before or after programming the Mode Register. Failure to follow these
steps may lead to unpredictable start-up modes.
Programming the Mode Register
The Mode register designates the operation mode at the read or write cycle. This register is
divided into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit
to program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency
Field to set the access time at clock cycle and a Operation mode field to differentiate between
normal operation (Burst read and burst Write) and a special Burst Read and Single Write mode. The
mode set operation must be done before any activate command after the initial power up. Any
content of the mode register can be altered by re-executing the mode set command. All banks must
be in precharged state and CKE must be high at least one clock before the mode set operation. After
the mode register i s s et, a Standby or NOP c ommand is required. Low signals of RAS, CAS , and
WE at the positive edge of the clock activate the mode set operation. Address input data at this
timing defines parameters to be set as shown in the previous table.
Read and Write Operatio n
When RAS i s low and both CAS and WE are hi gh at the pos itive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the wordline are set. A CAS cycle i s triggered by setting RAS high and CAS
low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either
a read (WE = H) or a wr ite ( WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read
or write operations are allowed at up to a 133 MHz data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page, where full
page is an optional feature on thi s devic e. Column addresses are s egmented by the bur st length
and serial data accesses are done within this boundary. The fi rst column address to be accessed is
supplied at the CAS timing and the subsequent addresses are generated automatically by the
programmed burst length and its sequence. For example, in a burst length of 8 with interleave
sequence, if the first address is ‘2’, then the re st of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using sequential burst type and page length is a function
of the I/O organisation and column addressing. Full page burst operation do nor self terminate once
the burst leng th has b een r eached. In other words , unlike burst length of 2, 4 or 8, full pa ge bur st
INFINEON Techn o logies 12 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
continues until it is terminated using other commands. Full page operation is an optional feature on
this device, which is built in by design, but not tested on every component.
Similar to the page mode of conventional DRAM’s, burst read or writ e accesses on any column
address are possible once the RAS cycle l atches the sense a mplifiers. T he ma ximum tRAS or the
refresh interval time limits the number of random column accesses. A new burst access can be
done even before the previous burst ends. The interrupt operation at every clock cycle is supported.
When the previous burst is interrupted, the remaining addresses are overridden by the new address
with the full burst length. An interrupt which accompanies an operation change from a read to a write
is possi ble by exploiting DQM to avoid bus contention.
When two or more banks are activated sequentially, interleaved bank read or write operations
are possible. With the programmed burst length, alternate access and precharge operations on two
or more banks can reali ze fast serial data ac cess modes among many different pages. Once two or
more banks are activated, column to column interleave operation can be performed between
different pages.
Burst Length and Sequence:
Re fresh Mode
SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the
CAS -before-R AS refr esh of conv entional DRA Ms. Al l banks must be precharg ed before appl ying
any refresh mode. An on-chip address counter increments the word and the bank addresses and no
bank information is required for both refresh modes.
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE
are held high at a clock timing. The mode restores word line after the refresh and no external
precharge command is necessary. A minimum tRC time is required between two automatic
Burst
Length Starting Address
(A2 A1 A0) Sequential Burst Addressing
(decim al) Interleave Burst Addressing
(decim al)
2 xx0
xx1 0, 1
1, 0 0, 1
1, 0
4x00
x01
x10
x11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
8 000
001
010
011
100
101
110
111
0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0
2 3 4 5 6 7 0 1
3 4 5 6 7 0 1 2
4 5 6 7 0 1 2 3
5 6 7 0 1 2 3 4
6 7 0 1 2 3 4 5
7 0 1 2 3 4 5 6
0 1 2 3 4 5 6 7
1 0 3 2 5 4 7 6
2 3 0 1 6 7 4 5
3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3
5 4 7 6 1 0 3 2
6 7 4 5 2 3 0 1
7 6 5 4 3 2 1 0
F u ll P a g e
(optional) nnn Cn, Cn+1, Cn+2 not supported
INFINEON Techn o logies 13 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
refreshes in a burst refresh mode. The same rule applies to any access command after the
automatic refresh operation.
The chip has an on-chip timer and the Self Refresh mode is available. The mode restores the
word lines after RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control
signals including the clock are disabled. Returning CKE to high enables the clock and initiates the
refresh exit operation. After the exit command, at least one tRC delay is required prior to any access
command.
DQM Function
DQM has two functions for data I/O read and write operations. During reads, when it turns to
„high“ at a clock timing, data outputs are disabled and become high impedance after two clock delay
(DQM Data Disable Latency tDQZ). It also prov ides a data mask function for wr ites. When DQM is
activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero
clocks).
Suspend Mode
Dur ing normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes
the internal clock and extends data read and write operations. One clock delay is required for mode
entry and exit (Clock Suspend Latenc y tCSL).
Power Down
In order to reduce standby power consu mption, a power dow n mode is available. All banks
must be precharged and the necessary Pr echarge delay (trp) must occur before the SDRAM can
enter the Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the
receiver circuits except CLK and CKE are gated off. The P ower Down mode do es not perform any
refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh
period (tref) of the device. Exit from this mode is performed by taking CKE „high“. One clock delay
is required for power down mode entry and and exit.
Auto Precharge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge
function is initiated. If CA10 is high when a Write Command is issued, the Write with Auto-
Precharge fu nction is initiated. The S DRAM automatically enters the precharge operation a time
delay equal to tWR (“write recovery time”) after the last data in.
Precharge Command
There is also a separate precharge command available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are
used to define banks as shown in the following list. The precharge command can be imposed one
clock before the last data out for CAS latency = 2 and two clocks before the last data out for CAS
latency = 3. Writes require a time delay twr (“write recovery time”) of 2 clocks minimum from the last
data out to apply the precharge command.
INFINEON Techn o logies 14 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Bank Selection by Address Bits
Burst Termination
Once a burst read or write operation has been initiated, there are several methods in which to
terminate the burst operation prematurely. These methods include using another Read or Write
Command to inte rrupt an e xisting burs t operation, us e a Precharg e Comm and to interrupt a bur st
cycle and c lose the ac tive bank, or using the Bur st St op Comman d to termina te the existing bur st
operation but leave the bank open for future Read or Write Commands to the same page of the
active bank. When interrupting a burst with another Read or Write Command care must be taken to
avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the
easiest method to use when terminating a burst operation before it has been completed. If a Burst
Stop command is issued during a burst write operation, then any residual data from the burst write
cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is
registered will be written to the memory.
A10 BA0 BA1
0 0 0 Bank 0
0 0 1 Bank 1
0 1 0 Bank 2
0 1 1 Bank 3
1xx all Banks
INFINEON Techn o logies 15 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Absol ute Maximum Ratings
Operating temperature range .........................................................................................0 to + 70 °C
Storage temperature range......................................................................................– 55 to + 150 °C
Input/output voltage............................................................................................ .– 0.3 to Vdd+0.3 V
Power supply voltage VDD / VDDQ ............................................................................– 0.3 to + 4.6 V
Power Dissipation............................................. ..........................................................................1 W
Da ta out current (short circuit)... .............................................................................................50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Recommended Operation and Characteristics:
TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V
Notes:
1. All voltages are referenced to VSS.
2. Vih may overshoot to Vdd + 2.0 V for pulse width of < 4ns wi th 3.3V. Vil may undershoot to
-2.0 V for pulse width < 4.0 ns with 3.3V. Pulse width m easured at 50% points with amplitude measured peak
to DC reference.
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter Symbol Limit Values Unit Notes
min. max.
Input high voltage VIH2.0 Vdd+0.3 V 1, 2
Input low voltage VIL– 0.3 0.8 V 1, 2
Output high voltage (IOUT = – 4.0 mA) VOH 2.4 –V3
Output low voltage (IOUT = 4.0 mA) VOL –0.4 V 3
Input leakage current, any input
(0 V < VIN < Vddq, all other inputs = 0 V) II(L) – 55µA
Output leakage current
(DQ is disabled, 0 V < VOUT < Vdd)IO(L) – 55µA
Parameter Symbol Values Unit
min. max.
Input capacitance (CLK) CI12.5 3.5 pF
Input capacitance
(A0-A12, BA0,BA1,RAS, CAS, W E , CS, CKE, DQM) CI22.5 3.8 pF
Input / Output capacitance (DQ) CIO4.0 6.0 pF
INFINEON Techn o logies 16 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Operating Currents (TA = 0 to 70oC, V dd = 3.3V ± 0.3V
(Recommended Ope rating Conditions unl ess otherwise noted)
Notes:
3. These parameters depend on the cycle rate. All values are measured at 133 MHz operation frequency for
-7.5 devices and at 100 M Hz for -8/-8A devices.
Input signals are changed once during tck.
4. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3
and BL=4 is assumed and the VDDQ current is excluded.
Parameter & Test Condition Symb. -7.5 -8/-8A Note
max. max.
OPERATING CURRENT
tck=tckmin,
All banks operated in random access,
all banks operated in ping-pong manner.
ICC1 230 170 mA
3, 4
PRECHARGE STANDBY CURRENT in
Power Dow n Mode
CS =VIH (min.), CKE<=Vil(max)
tck = m in. ICC2P 22mA3
PRECHARGE STANDBY CURRENT in
Non- Pow er Down Mode
CS = VI H (min . ) , C K E >= V ih(min )
tck = m in. ICC2N 40 30 mA 3
NO OPERAT ING CURR ENT
tck = min., CS = VIH(m in),
active state ( max. 4 banks)
CKE>=VIH(min.) ICC3N 50 45 mA 3
CKE<=VIL(max.) ICC3P 10 10 mA 3
BURST OPERATING CURRENT
tck = min.,
Read command cycling
ICC4 150 100 mA 3,4
AUTO REFRESH CURRENT
tck = min., trc=trcmin.,
Auto Refresh command cycling
ICC5 240 220 mA 3
SELF REFRESH CURR ENT
Self Refresh Mode, CKE=0.2V
tck=infinity
standard version ICC 6 33mA
L-version 1.7 1.7 mA
INFINEON Techn o logies 17 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
AC Characteristics 1)2)
TA = 0 to 70 °C; VSS = 0 V; Vdd = 3.3 V ± 0.3 V, tT = 1 ns
Parameter Symbol Limit Values Unit
-7.5
PC133-
333
-8
PC100-
222
-8A
PC100-
322
min. max. min. max. min. max.
Clock and Clock Enable
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2 tCK 7.5
10 8
10 –
–8
12 –
–ns
ns
Clock Frequency
CAS Latency = 3
CAS Latency = 2 tCK –
–133
100 –
–125
100 –
–125
83 MHz
MHz
Access Time from Clock
CAS Latency = 3
CAS Latency = 2 tAC –
–5.4
6–
–6
6–
–6
6ns
ns 2,
3,
7
Clock High Pulse Width tCH 2.5 –3–3–ns
Clock Low Pulse Width tCL 2.5 –3–3–ns
Transition time tT0.3 1.2 0.5 10 0.5 10 ns
Setup and Hold Times
Input Setup Time tIS 1.5 –2–2–ns 4
Input Hold Time tIH 0.8 –1–1–ns 4
CKE Setup Time tCKS 1.5 –2–2–ns 4
CKE Hold Time tCKH 0.8 –1–1–ns 4
Mode Register set to Active
delay tRSC 2–2–2–CLK
Power Down Mode Entry Time tSB 07.50808ns
Common Parameters
Ro w to Column Delay Time tRCD 20 –20 –20 ns 5
Row Precharge Time tRP 20 –20 –20 ns 5
Row Active Time tRAS 45 100k 48 100k 48 100k ns 5
Row Cycle Time tRC 67 –70 –70 –ns 5
INFINEON Techn o logies 18 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Activate(a) to Activate(b)
Command period tRRD 15 –16 –16 ns 5
CAS(a) to CAS(b) Command
period tCCD 1–1–1–CLK
Refresh Cycle
Refres h Period (8192 cycles) tREF –64 –64 –64 ms
Self Refresh Exit Time tSREX 1–11CLK
6
Re ad Cycle
Da ta Out Hold Time tOH 3–3–3–ns 2,
7
Data Out to Low Impedance Time tLZ 0–0–0–ns
Data Out to High Impedance Time tHZ 373838ns
DQM Data Out Disable Latenc y tDQZ –2–2–2CLK
Write Cycle
Data Input to Precharge
(write recovery) tWR 2–2–2–CLK 8
DQM Write Mask Latency tDQW 0–0–0–CLK
Parameter Symbol Limit Values Unit
-7.5
PC133-
333
-8
PC100-
222
-8A
PC100-
322
min. max. min. max. min. max.
INFINEON Techn o logies 19 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Notes for AC Parameters:
1. For proper power -up see the operation section of this data sheet.
2. AC t iming tests have Vil = 0.4 V and Vih = 2.4 V wi th the timing referenced to the 1.4 V crossover p oint. The
transition t ime is meas ured between Vih and Vil. All AC measurements assume tT=1ns with the AC output l oad
circuit shown in fig.1.Specified tac and toh parameters are measured wi th a 50 pF onl y, without any resistive
termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V.
3. If clock rising time is longer t han 1 ns, a time (tT/2 - 0. 5) ns has to be added to this parameter.
4. If tT is longer than 1 ns, a time (tT -1) ns has to be added to t his parameter.
5. These par ameter account for the numbe r of clock cycle and depend on the operating frequency of the clock,
as follows:
the number of clock cycle = specif ied value of timing period (counted in fr actions as a whole num ber)
6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit
command is registered.
7. Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF l oad,
Data out hold time toh is 1.8 ns for PC133 components with no t ermination and 0 pF load.
8. The write recovery time twr = 2 CLK cycles is a digital interlock on this device. Special devices with twr = 1 CLK
for operations at less or equal 83 MHz will be available.
fig.1
50 pF
I/O
Measurement conditions for
tac and toh
SPT03404
CLOCK 2.4 V
0.4 V
INPUT
HOLD
t
SETUP
t
t
T
OUTPUT 1.4 V
t
LZ
AC
t t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
INFINEON Techn o logies 20 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Package Outlines
GPX09039
22.22±0.131)
127
54 28
0.35+0.1
-0.05
0.1
1
0.1
10.16±0.13
±0.211.76
±0.10.5
Does not include plastic or metal protrusion of 0.15 max per side
1)
54x
±0.05
±0.05
0.15
-0.03
+0.06
15˚±5˚
15˚±5˚
6 max
2.5 max
2)
3)
Does not include plastic protrusion of 0.25 max per side
2)
Does not include dambar protrusion of 0.13 max per side
3)
Index Marking
0.8
20.8
26x 0.8 =0.2 M54x
Plastic Pac kage P-TSOPII-54
(400 mil, 0.8 mm lead pitch)
Thin Small Outl ine Package, SMD
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEO N T echnologi es 21
T iming Diagrams
1. Bank Activate Command Cycle
2. Burs t Read Operation
3. Read Interrupted by a Read
4. Read to Write Int erval
4.1 Read to Write Int erval
4.2 Minimum Read to Write Interv al
4.3 Non-Minim um Read to Wri te Interval
5. Burst Write Operation
6. Write and Read Interrupt
6.1 W ri te Interrupted by a Wr ite
6.2 W ri te Interrupted by Read
7. Burs t Wri te & Read with Auto-Precharge
7.1 Burst Write with Auto-Precharge
7.2 Burst Read with Auto-Precharge
8. AC- Paramete rs
8.1 AC Paramet ers for a Write Timing
8.2 AC Parameters for a Read Timing
9. Mode Register Set
10. Power on Sequence and Auto Refresh (CBR)
11. Cl ock Suspension (using CKE)
11. 1 Clo ck Suspension During Bur st Read CAS Latency = 2
11. 2 Clo ck Suspension During Bur st Read CAS Latency = 3
11. 3 Clo ck Suspension During Bur st Wri te CAS Latency = 2
11. 4 Clo ck Suspension During Bur st Wri te CAS Latency = 3
12. Power Down Mode and Clock Suspend
13. Sel f Refresh ( Entr y and Exit )
14. Aut o Refresh ( CBR )
15. Random Column Read ( Page withi n same Bank)
15.1 CAS Lat ency = 2
15.2 CAS Lat ency = 3
16. Random Column Write ( Page wi thi n same Bank)
16.1 CAS Lat ency = 2
16.2 CAS Lat ency = 3
17. Random Row Read ( Interl eaving Bank s) wi th Precharge
17.1 CAS Lat ency = 2
17.2 CAS Lat ency = 3
18. Random Row Write ( Inte rl eaving Banks) with Precharge
18.1 CAS Lat ency = 2
18.2 CAS Lat ency = 3
19. Precharge Terminat ion of a Burst
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEON Technologies 22
1. Bank Activate Command Cycle
2. Burst Read Operation
RC
"H" or "L"
t
T0
(CAS latency = 3)
Bank B
Row Addr.
Activate
Bank B
Address
Command
CLK
T
NOPNOP
RCD
t
T1
Col. Addr.
Bank B
with Auto
Precharge
Write B
T
SPT03784
Bank B
Row Addr.
Activate
Bank B
Row Addr.
Bank A
Activate
Bank A
T
NOP
RRD
t
TT
SPT03712
CLK
Read A NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
Command NOP NOP NOP NOP NOP NOP NOP
DOUT A3
CK2
latency = 2
t, DQ’s DOUT A1DOUT A0 DOUT A2
DOUT A2
CK3
latency = 3
t, DQ’s DOUT A0 DOUT A1 DOUT A3
(Burst Length = 4, CAS latency = 2, 3)
CAS
CAS
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEO N T echnologi es 23
3. Read Interrupted by a Read
4. Read to Write Interval
4.1 Read to Write Interval
SPT03713
CLK
Read A
T0 T1 T2 T3 T4 T5 T6 T7 T8
Command
DOUT A0 DOUT B0 DOUT B1 DOUT B2
NOP NOP NOP NOP NOP NOP NOP
latency = 2
, DQ’s
CK2
t
CK3
latency = 3
t, DQ’s
(Burst Length = 4, CAS latency = 2, 3)
CAS
CAS
Read B
DOUT B3
DOUT B1DOUT A0 DOUT B0 DOUT B3DOUT B2
Commands = 4 + 1 = 5 cycles
Minimum delay between the Read and Write
DOUT A0
DQ’s
(Burst Length = 4, CAS latency = 3)
DQMx
Command
CLK
NOP Read A
T0 T1
NOP NOP
T2 T3
the Write Command
Must be Hi-Z before
DIN B0 DIN B1
SPT03787
DIN B2
DQW
NOP
DQZ
t
NOP
t
T4 T5
Write B NOP
T6 T7
NOP
T8
"H" or "L"
Write latency of DQMx
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEON Technologies 24
4 2. Minimum Read to Write Interval
4. 3. Non-Minimum Read to Write Interval
the Write Command
Must be Hi-Z before
Activate
CAS
CK2
latency = 2
t, DQ’s
(Burst Length = 4, CAS latency = 2)
CLK
DQM
Command NOP
T0 T1
Bank A
NOP
DQZ
t
T2 T3
DIN A0 DIN A1 DIN A2
SPT03939
DIN A3
1 Clk Interval
Read A Write A
T4 T5
NOP NOP
T6 T7
NOP
T8
"H" or "L"
t
DQW
NOP
CAS
latency = 3
CK3
CAS
CK2
latency = 2
t
t
, DQ’s
, DQ’s DOUT A0
(Burst Length = 4, CAS latency = 2, 3)
CLK
DQM
Command NOP Read A
T0 T1
NOP NOP
T2 T3
the Write Command
Must be Hi-Z before
DOUT A0
DOUT A1
DIN B0
DIN B0
DIN B1
DIN B1
SPT03940
DIN B2
DIN B2
Read A
DQZ
t
NOP
T4 T5
Write B NOP
T6 T7
NOP
T8
"H" or "L"
tDQW
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEO N T echnologi es 25
5. Burst Write Operation
(
Extra data is ignored after
termination of a Burst.
DIN A3
T4
are registered on the same clock edge.
The first data element and the Write
NOP
(Burst Length = 4, CAS latency = 2, 3)
T0
Command
DQ’s
CLK
DIN A1
T2
NOP
DIN A0
Write A
T1
DIN A2
NOP
T3
SPT03790
T6
NOP NOP
T5
NOP NOP
T7
NOP
T8
don’t care
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEON Technologies 26
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by a Read
1 Clk Interval
SPT03791
CLK
T0 T1 T2 T3 T4 T5 T6 T7 T8
Command NOP NOP NOP NOP NOP NOP
DQ’s
(Burst Length = 4, CAS latency = 2, 3)
NOP Write A
DIN A0 DIN B0 DIN B1 DIN B2 DIN B3
Write B
1 Clk Interval
T5
NOP
DOUT B1
DOUT B0
Input data for the Write is ignored.
, DQ’s
latency = 3
CK3
CAS
t
don’t care
DIN A0
don’t care
(Burst Length = 4, CAS latency = 2, 3)
CLK
, DQ’s
Command
latency = 2
CK2
CAS
t
NOP
T0
DIN A0
Write A
don’t care
Read B
T1 T2
DOUT B0
NOP NOP
T4T3
SPT03719
appears on the outputs to avoid data contention.
DOUT B2
Input data must be removed from the DQ’s
at least one clock cycle before the Read data
DOUT B1 DOUT B3
NOP
DOUT B3
NOP
DOUT B2
T6 T7
NOP
T8
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEO N T echnologi es 27
7. Burst Write and Read with Auto Precharge
7.1 Burst Write with Auto-Precharge
7.2 Burst Read with Auto-Precharge
CLK
Active
NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
Command NOP NOP NOP NOP
DQ’s
Bank A
Begin Auto Precharge
Bank can be reactivated after trp
Wri te A
Auto Precharge
DIN A1DIN A0
DIN A1DIN A0
CAS Latency = 2:
DQ’s
CAS Latency = 3:
WR
t
WR
t
RP
t
RP
t
*
*
*
Active
NOPCommand NOP NOP NOP NOP NOP NOP
Bank A Write A
Auto Precharge
NOP
Activate
(Burst Length = 2, CAS latency = 2, 3 )
Activate
SPT03721_2
CLK
with AP
NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
Command
DO UT A0 DOUT A1 DOUT A2 DO UT A3
NOP NOP NOP NOP NOP NOP NOP
latency = 2
DQ’s
DOUT A 3
latency = 3
DOUT A1DOUT A0 DOUT A2
(Bu rst Length = 4, CA S latency = 2, 3)
CAS
CAS
Read A
Bank can be reactivated after trp
Begin Auto Precharge
DQ’s
RP
t
*
*
*
t
RP
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEON Technologies 28
8. AC Parameters
8.1 AC Parameters for a Write Timing
A uto Precharge
Bank B
Command
Writ e wi t h
Activate
Writ e wi t h
Activate
Bank A
Command
Auto Precharge
Bank A
Command Command
Bank B
Addr.
AP
DQM
DQ
BS
Hi-Z
RCD
t
Ax2Ax1Ax0 Ax3
RC
t
RAx
t
AS
t
AH
RBx
CAx
Command
SPT03910_2
Bx1Bx0
CBx
T8
Precharge
Begin Auto
Bank A
CLK
WE
CAS
RAS
CS
CKE
CK2
t
CS
t
CH
CKS
t
CH
t
t
CL
t
T3T0 T2T1 T4 T5 T7T6 T18
B urst Length = 4, CAS Latency = 2
T13T9 T10 T12T11 T14 T15 T17T16 T19 T20 T22T21
RBx
RAx
Activate Write
Command
Bank AB ank A
DS
t
t
DH
RAy
B ank B
Precharge
B egin Auto
RBy
ActivatePrecharge
Command
Bank A Bank A
Command Activate
Bank B
Command
t
WR
t
CKH
RAz
RAz RBy
RAy
RAy
Bx2 Bx3
t
WR RP
t
Ay2Ay1Ay0 Ay3
RP
t
RRD
t
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEO N T echnologi es 29
8.2 AC Parameters for a Read Timing
AC2
Hi-Z
DQ
Activate
Command
Bank A
Read
Bank A
Command
DQM
Addr.
AP
t
RCD
t
LZ
t
t
AS
RAx
RAx
t
AH
CAx
RRD
t
Command
Bank B
R ead with
Auto Precharge
Activate
Bank B
Command
Ax1
Ax0 Bx0
Activate
SPT03911_2
Command
Bank A
Bx1
t
AC2
OH
t
HZ
t
t
RAS
RC
t
RBx
RBx
RBx
HZ
t
RAy
RAy
T5
tt
BS
WE
CAS
RAS
t
CS
CKE
CKS
t
CH
t
t
CS
CH
CL
CK2
CLK
T0 T1 T2 T3 T4
Precharge
Bank B
Begin Auto
t
CKH
Burst Length = 2, CA S Latency = 2
T6 T7 T8 T10T9 T11 T13T12
RP
t
Precharge
Bank A
Command
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEON Technologies 30
9. Mode Register Set
Set Command
Mode Register
All Banks
Precharge
Command Any
Command
Address Key
T0 T1 T2 T8
RSC
t
T4
T3 T5 T6 T7 T11T9 T10 T12 T13
SPT03912_2
T19T16T15T14 T17 T18
CAS Latency = 2
T20 T21 T22
BS
Addr.
AP
CS
WE
CAS
RAS
CKE
CLK
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEO N T echnologi es 31
10. Power on Sequence and Auto Refresh (CBR)
Inputs must be
200stable for
µ
s
DQM
AP
DQ
Addr.
BS
RP
Command
All Banks
Precharge
Hi-Z
~
~
t
1st Auto Refresh
Command
~
~
~
~
~
~
~
~
~
~
~
~
~
~
SPT03913
Mode Register
Set Command
Address Key
8th Auto Refresh
Command
~
~
t
RC
~
~
~
~
~
~~
~
~
~~
~
~
~
Command
Any
Minimum of 8 Refresh Cycles are required
T8
WE
CAS
RAS
CS
CKE
CLK
required
~
~~
~
~
~
~
~
~
~
~
~
~
~
T3
is
~
~
~
~
LevelHigh
T0 T2T1 T5T4 T7T6 T18
2 Clock min.
~
~~
~
~
~
~
~
~
~
~
~~
~
T13
~
~
~
~
T10T9 T12T11 T14 T15 T17T16 T20T19 T22T21
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEON Technologies 32
11. Clock Suspen sion ( Using CKE)
11.1 Clock Suspension During Burst Re ad CAS Latency = 2
Command
Bank A
DQM
Addr.
DQ
AP
BS
Read
Command
Bank A
Activate
Hi-Z
Suspend
1 Cycle
Clock
Ax0
CSL
t
Ax1
CAxRAx
RAx
SPT03914
t
Suspend
3 Cycles
Suspend
2 Cycles
Clock
Ax2
CSL
t
Clock
Ax3
HZ
T7
WE
CAS
RAS
CS
CKE
CLK
CK2
t
T0 T1 T2 T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15
Burst Length = 4, CAS Latency = 2
T18T17 T19 T20 T21 T22
CSL
t
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEO N T echnologi es 33
11.2 Clock Suspension During Burst Read CAS La tency = 3
CSL
DQM
Addr.
DQ
AP
BS
Bank A
Activate
Command
Hi-Z
Command
Bank A
Read
Ax0
t
RAx
RAx
CAx
HZ
t
t
Suspend
1 Cycle
Clock Suspend
2 Cycles
Clock
CSL
Ax1 Ax2
Clock
Suspend
3 Cycles
t
CSL
Ax3
SPT03915
T7
WE
CAS
RAS
CS
CKE
CLK
CK3
t
T0 T1 T2 T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15
Burst Length = 4, CAS Latency = 3
T18T17 T19 T20 T21 T22
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEON Technologies 34
11.3 Clock Suspension During Burst Write CAS Latency = 2
Bank A
DQM
Addr.
DQ
AP
BS
DAx0
Command
Write
Activate
Command
Bank A
Hi-Z
Clock Clock
1 Cycle
Suspend Suspend
2 Cycles
DAx1
CAxRAx
RAx
DAx3
Clock
Suspend
3 Cycles
DAx2
SPT03916
T7
WE
CAS
RAS
CS
CKE
CLK
CK2
t
T0 T1 T2 T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15
Burst Length = 4, CAS Latency = 2
T18T17 T19 T20 T21 T22
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEO N T echnologi es 35
11.4 Clock Suspension During Burst Write CAS Latency = 3
Clock
Suspend
2 Cycles
Bank A
DQMx
Addr.
DQ
A8/AP
BA
Activate
Command
Bank A
Hi-Z
Clock
1 Cycle
Suspend
Command
Write
DAx0 DAx1
RAx
RAx
CAx
Clock
Suspend
3 Cycles
DAx2 DAx3
SPT03917
T7
WE
CAS
RAS
CS
CKE
CLK
CK3
t
T0 T1 T2 T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15
Burst Length = 4, CAS Latency = 3
T18T17 T19 T20 T21 T22
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEON Technologies 36
12. Power Down Mode and Clock Suspend
BS
Clock SuspendClock Suspend
Mode Entry Mode Exit
Addr.
DQM
DQ
AP
Standby
Active
Activate
Bank A
Command
Hi-Z
Read
Command
Bank A
RAx
RAx
CAx
Power Down Power Down
Mode ExitMode Entry
SPT03918
End
Clock Mask
Clock Mask
Start
Ax0 Ax1 Ax2
Precharge
Command
Bank A
Ax3
t
HZ
Precharge
Standby Any
Command
T7
CAS
WE
RAS
CS
CKE
CLK
CK2
t
T0 T1 T2
CKS
t
T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15
Burst Length = 4, CAS Latency = 2
CKS
t
T18
T17 T19 T20 T21 T22
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEO N T echnologi es 37
13 . Self Refresh (E ntry and Exit)
BS
t
S elf Refresh Exit
Comm and issued
Addr.
DQM
DQ
AP
Entry
Self Refresh
mus t be idle
A ll Banks
Hi-Z
SPT03919-2
Exit Com mand
Begin Self Refresh
SREX
t
RC
Self Refresh
Command
Exit
Any
T7
CS
CAS
WE
RAS
CKE
CLK
t
CKS
T0 T1 T2 T3 T4 T6T5 T16
CKS
t
T8 T9 T10 T11 T14T12 T13 T15 T18T17 T19 T20 T21 T22
*)
*)
minimum RAS cycle
time depends on CAS
Latency and trc
~
~
~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEON Technologies 38
14. Auto Refresh (CBR)
(Minimum Interval)
Addr.
DQM
DQ
AP
BS
Auto Refresh
Command
All Banks
Precharge
Command
Hi-Z
t
RP
t
RC
SPT03920_2
RC
t
RAx
RAx
CAx
T7
WE
CAS
RAS
CS
CKE
CLK
CK2
t
T0 T1 T2 T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15
Burst Length = 4, CAS Latency = 2
T18T17 T19 T20 T21 T22
Command
Auto Re fre sh CommandCommand
Bank A
Activate
Bank A
Read
Ax2Ax0 Ax1 Ax3
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEO N T echnologi es 39
15. Random Column Read (Page within same Bank )
15.1 CAS Latency = 2
Ay1
Addr.
BS
DQ
DQM
AP
Activate
Command
ZHi
Bank A
RAw
RAw
Command
Read
Command
Bank A
Read
Bank A
Aw0 Aw1
CAw CAx
Read
Bank A
Command
Aw3Aw2 Ax0 Ax1 Ay0
CAy
CS
WE
CAS
RAS
CKE
CLK
T0
CK2
t
T1 T2 T8T4T3 T5 T6 T7 T11T9 T10 T12 T13
Precharge
Command
Bank A
Ay2 Ay3
Activate
Command
Bank A
RAz
RAz
SPT03921
Read
Bank A
Command
CAz
Burst Length = 4, CAS Latency = 2
T19T16T15T14 T17 T18 T20 T21 T22
Az3Az0 Az1 Az2
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEON Technologies 40
15.2 CAS Latency = 3
Ay3
CAw
Addr.
BS
DQ
DQM
AP
ZHi
Bank A
Activate
Command Read
Command
Bank A
RAw
RAw
Bank A
Command
Aw1Aw0
Read
Bank A
Command
Aw2 Aw3
CAx
Read
Ax1Ax0 Ay0
Precharge
Command
Bank A
Ay1 Ay2
CAy
CS
WE
CAS
RAS
CKE
CLK
T0
CK3
t
T1 T2 T8T4T3 T5 T6 T7 T11T9 T10 T12 T13
Bank A
Read
Command
Activate
Command
Bank A
RAz
RAz
CAz
SPT03922
Burst Length = 4, CAS Latency = 3
T19T16T15T14 T17 T18 T20 T21 T22
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEO N T echnologi es 41
16. Random Column write (Page within same Bank)
16.1 CAS Latency = 2
DBy1
Addr.
BS
DQ
DQM
AP
Activate
Command
ZHi
Bank B
RBw
RBw
Command
Write
Command
Bank B
Write
Bank B
DBw0 DBw1
CBw CBx
Write
Bank B
Command
DBw3DBw2 DBx0 DBx1 DBy0
CBy
CS
WE
CAS
RAS
CKE
CLK
T0
CK2
t
T1 T2 T8T4T3 T5 T6 T7 T11T9 T10 T12 T13
Precharge
Command
Bank B
DBy2 DBy3
Activate
Command
Bank B
RBz
RBz
SPT03923_2
Read
Bank B
Command
CBz
Burst Length = 4, CAS Latency = 2
T19T16T15T14 T17 T18 T20 T21 T22
DBz1DBz0 DBz2 DBz3
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEON Technologies 42
16.2. CAS Latency = 3
Command
Write
Bank B
CBz
DBw0
Addr.
BS
DQ
DQM
AP
Bank B
Activate
Command
ZHi
RBz
RBz
Command
Bank B
DBw3DBw1 DBw2
Write
Bank B
Command
DBx0 DBx1
CBx
Write
DBy1DBy0 DBy2
Precharge
Command
Bank B
DBy3
CBy
CS
WE
CAS
RAS
CKE
CLK
T0
CK3
t
T1 T2 T8T4T3 T5 T6 T7 T11T9 T10 T12 T13
Command
Bank B
DBz0
Activate
Command
Bank B
Write
DBz1
RBz
RBz
CBz
SPT03924
Burst Length = 4, CAS Latency = 3
T19T16T15T14 T17 T18 T20 T21 T22
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEO N T echnologi es 43
17. Random Row Read (Interleaving Banks) with Precharge
17.1 CAS Latency = 2
Ax2
t
BS
Addr.
DQ
DQM
AP
Bank B
Activate
Command
Hi-Z
Command
Read
Bank B
RBx
RBx
RCD
t
CBx
Read
Activate
Bank A
Command
Command
Bank B
Command
Bx2Bx0
AC2
Bx1
Bank A
Activate
Bx3 Bx4
RAx
RAx
Command
Precharge
Bank B
Bx6Bx5 Bx7 Ax0 Ax1
CAx RBy
RBy
CS
WE
CAS
RAS
CKE
CLK
T0
High
t
CK2
T1 T2 T8T4T3 T5 T6 T7 T11T9 T10 T12 T13
SPT03925_2
Bank B
Command
Ax5Ax3 Ax4
Read
Ax6 Ax7
CBy
By1By0
Burst Length = 8, C AS Latency = 2
T19T16T15
T14 T17 T18 T20 T21 T22
RP
t
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEON Technologies 44
17.2 CAS Latency = 3
Activate
Command
Bank A
Addr.
DQM
DQ
AP
BS
Read
Bank B
Command
Command
Bank B
Activate
Hi-Z Bx1Bx0
CBxRBx
RCD
t
RBx
t
AC3
Activate
Command
Bank B
Bx6
Bank A
Command
Read
Bx4Bx3Bx2 Bx5
Bank B
Precharge
Command
Ax0Bx7 Ax2Ax1
RAx CAx
RAx
RP
t
RBy
RBy
Precharge
Bank A
Command
Ax7
Read
Bank B
Command
Ax5Ax4Ax3 Ax6
SPT03926
By0
CBy
T7
WE
CAS
RAS
CS
CKE
CLK
High
CK3
t
T0 T1 T2 T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15
Burst Length = 8, CAS Latency = 3
T18T17 T19 T20 T21 T22
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEO N T echnologi es 45
18. Random Row Write (Interleaving Banks) with Precharge
18.1 CAS Latency = 2
DBx4DAx1
BS
AP
Addr.
DQ
DQM
Activate
Command
Bank A
Hi-Z
Write
Command
Bank A
DAx0
RAx
RAx
RCD
t
CAx
CommandCommand
Bank B Bank A
Command
DAx4DAx2 DAx3
Bank B
Activate
DAx5 DAx6
RBx
RBx
Command
Precharge
Bank A
Write
DBx0DAx7 DBx1
Activate
DBx2 DBx3
CBx RAy
RAy
CLK
CKE
CS
RAS
CAS
WE
T0
High
CK2
t
T1 T2 T8T4T3 T5 T6 T7 T11T9 T10 T12 T13
Command
Bank A
SPT03927_2
Command
Precharge
Bank B
DBx7DBx5 DBx6
Write
DAy0 DAy1
CAy
WR
t
DAy4DAy3DAy2
T19
Burst Length = 8, CAS Latency = 2
T16T15T14 T17 T18 T20 T21 T22
WR
t
RP
t
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEON Technologies 46
18.2 CAS Latency = 3
DAx4
Addr.
DQM
DQ
AP
BS
Command
Bank A
Bank A
Activate
Command
Hi-Z
Write
DAx0 DAx1 DAx3DAx2
RAx
RCD
t
RAx
CAx
DBx4DBx0
Write
Command
Bank B
Bank B
Activate
Command
DAx6DAx5 DAx7
Precharge
Command
Bank A
DBx2DBx1 DBx3
CBxRBx
RBx
WR
t
RP
t
Command
Bank A
Activate
Command Bank A
Write
DBx5 DBx6 DAy0DBx7
Precharge
Bank B
Command
SPT03928
DAy1 DAy2 DAy3
WR
RAy
t
CAy
RAy
CAS
RAS
CKE
CLK
WE
CS
T2
High
CK3
t
T0 T1 T4T3 T5 T6 T15T7 T8 T9 T10 T11 T12 T13 T14
Burst Length = 8, CAS Latency = 3
T19T17T16 T18 T21T20 T22
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEO N T echnologi es 47
19. Precharge termination of a Burst
19.1 CAS Latency = 2
Command
Activate
Bank A
T14
BS
Write Data is masked.
of a Write Burst.
Precharge Termination
Addr.
DQ
DQM
AP
Command
Bank A
Activate
Hi Z
Bank A
Write
Command
DAx0 DAx1
RAx
RAx
CAx
Command
Bank A
Command
Precharge
Bank A
DAx3DAx2
Activate
RAy
RP
t
RAy
Ay0
Command
Bank A
Read
Bank A
Precharge
Command
Ay1 Ay2
CAy
RP
t
T3
CS
WE
CAS
RAS
CKE
CLK
T0
High
CK2
t
T1 T2 T4 T5 T7T6 T8 T10T9 T11 T13T12
Precharge Termination
of a Read Burst.
SPT03933
Bank A
Command
Precharge
Command
Bank A
Read
Az0 Az1
RAz CAz
RAz
Az2
RP
t
Burst Length = 8 or Full Page, CAS Latency = 2
T20
T17T15 T16 T18 T19 T21 T22
HYB39S256400/800/160CT(L)
256-MBit Synchronous DRAM
INFINEON Technologies 48
INFINEON Techn o logies 21 8.00
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Change List
23.8.99 First Rev.
6.10.99 Clock Suspend Mode not supported anymore (Dr.Savignac)
Changes on pages 1, 8 & 15
Waveforms: chapters 11 & 12 deleted and renumbered
3.12.99 some PC 133 parameters changed according to INTELs PC133 specificati on
27.1.2000 Some ICC currents changed after measurement of first lots
Datasheet changed from Target to Preliminary
11.4.2000 confusion note 4 on page 8, removed, burst stop is supported for BL =2,4 & 8
14.4.2000 Full page bur st is funct ional beginning with designstep DD3A.
Implemented into t he datasheet as optional (unt ested) feature
Mail from Ralf Schneider, April 12. 00
25.4.2000
Power Down Exit with one clock beginning with DD3D designst ep
Clock suspend mode functional with DD3D designstep
Clock sus pend mode is added in the datasheet and the waveform drawings again.
Tras interlock changed to 4 clocks
twr = 2 C lock on this design version
Note for availability of compo nents with twr = 1 clock interlock
28.6.2000
Preli minary datasheet changed to final
Change request from Mr . Lüken:
Text change on page 16 (for clarification)
page 17: “mode register set-up t ime” renamed to “Mode Register set to Active
delay”
Waveform Drawing changed from SPT03910 to SPT03910_2
Waveform Drawing changed from SPT03923 to SPT03923_2
Waveform Drawing changed from SPT03925 to SPT03925_2
Waveform Drawing changed from SPT03927 to SPT03927_2
20.7.2000
Last minute changes requested by Mr. Lüken
page 16: note 4 for ICC1
Waveform Drawing changed from SPT03911 to SPT03911_2
Waveform Drawing SPT03925_2 trp arrow corrected
8.8.2000 ICC 6 for Low Power Versions changed from 1.5 to 1.7 mA
(Discussion with Hahn and Lüken)
