MAX3208EAUB+ - Maxim Integrated

General Description

The MAX3205E/MAX3207E/MAX3208E low-capaci-

tance, ±15kV ESD-protection diode arrays with an inte-

grated transient voltage suppressor (TVS) clamp are

suitable for high-speed and general-signal ESD protec-

tion. Low input capacitance makes these devices ideal

for ESD protection of signals in HDTV, PC monitors

(DVI™, HDMI®), PC peripherals (FireWire®, USB 2.0),

server interconnect (PCI Express®, InfiniBand™),

datacom, and interchassis interconnect. Each channel

consists of a pair of diodes that steer ESD current puls-

es to VCC or GND.

The MAX3205E/MAX3207E/MAX3208E protect against

ESD pulses up to ±15kV Human Body Model, ±8kV

Contact Discharge, and ±15kV Air-Gap Discharge, as

specified in IEC 61000-4-2. An integrated TVS ensures

that the voltage rise seen on VCC during an ESD event

is clamped to a known voltage. These devices have a

2pF input capacitance per channel, and a channel-to-

channel capacitance variation of only 0.05pF, making

them ideal for use on high-speed, single-ended, or dif-

ferential signals.

The MAX3207E is a two-channel device suitable for

USB 1.1, USB 2.0 (480Mbps), and USB OTG applica-

tions. The MAX3208E is a four-channel device for

Ethernet and FireWire applications. The MAX3205E is a

six-channel device for cell phone connectors and

SVGA video connections.

The MAX3205E is available in 9-bump, tiny wafer-level

package (WLP) and 16-pin, 3mm x 3mm, thin QFN

packages. The MAX3207E is available in a small 6-pin

SOT23 package. The MAX3208E is available in 10-pin

µMAX®and 16-pin, 3mm x 3mm TQFN packages. All

devices are specified for the -40°C to +125°C automo-

tive operating temperature range.

Applications

DVI Input/Output Protection

Set-Top Boxes

PDAs/Cell Phones

Graphics Controller Cards

Displays/Projectors

High-Speed, Full-Speed and Low-Speed USB

Port Protection

FireWire IEEE 1394 Ports

Consumer Equipment

High-Speed Differential Signal Protection

Features

♦Low Input Capacitance of 2pF Typical

♦Low Channel-to-Channel Variation of 0.05pF

from I/O to I/O

♦High-Speed Differential or Single-Ended ESD

Protection

±15kV–Human Body Model

±8kV–IEC 61000-4-2, Contact Discharge

±15kV–IEC 61000-4-2, Air-Gap Discharge

♦Integrated Transient Voltage Suppressor (TVS)

♦Optimized Pinout for Minimized Stub Inductance

on Controlled-Impedance Differential-

Transmission Line Routing

♦-40°C to +125°C Automotive Operating

Temperature Range

♦WLP Packaging Available

MAX3205E/MAX3207E/MAX3208E

Dual, Quad, and Hex High-Speed

Differential ESD-Protection ICs

________________________________________________________________

Maxim Integrated Products

Ordering Information

19-3361; Rev 3; 7/10

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

FireWire is a registered trademark of Apple Inc.

PCI Express is a registered service mark of PCI-SIG Corporation.

DVI is a trademark of Digital Display Working Group.

HDMI is a registered trademark and registered service mark of

HDMI Licensing, LCC.

InfiniBand is a trademark and service mark of InfiniBand Trade

Association.

µMAX is a registered trademark of Maxim Integrated Products, Inc.

Typical Operating Circuit and Pin Configurations appear at

end of data sheet.

PART TEMP RANGE PIN-PACKAGE

MAX3205EAWL+T -40°C to +125°C 9 WLP

MAX3205EATE+ -40°C to +125°C 16 TQFN-EP*

MAX3207EAUT+T -40°C to +125°C 6 SOT23

MAX3208EAUB+ -40°C to +125°C 10 μMAX

MAX3208EATE+ -40°C to +125°C 16 TQFN-EP*

Selector Guide

PART ESD-PROTECTED

I/O PORTS TOP MARK

MAX3205EAWL+T 6 AIN

MAX3205EATE+ 6 ACO

MAX3207EAUT+T 2 ABVG

MAX3208EAUB+ 4 —

MAX3208EATE+ 4 ACN

Denotes a lead(Pb)-free/RoHS-compliant package.

T = Tape and reel.

EP = Exposed pad.

MAX3205E/MAX3207E/MAX3208E

Dual, Quad, and Hex High-Speed

Differential ESD-Protection ICs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VCC = +5V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA= +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

Note 1: Parameters are 100% production tested at +25°C. Limits over temperature are guaranteed by design only.

Note 2: Idealized clamp voltages. See the

Applications Information

section for more information.

Note 3: Guaranteed by design, not production tested.

VCC to GND...........................................................-0.3V to +6.0V

I/O_ to GND................................................-0.3V to (VCC + 0.3V)

Continuous Power Dissipation (TA= +70°C)

6-Pin SOT23 (derate 8.7mW/°C above +70°C)............696mW

9-Bump WLP (derate 14.1mW/°C above +70°C).............0mW

10-Pin µMAX (derate 5.6mW/°C above +70°C) ...........444mW

16-Pin TQFN (derate 20.8mW/°C above +70°C) .......1667mW

Operating Temperature Range .........................-40°C to +125°C

Storage Temperature Range .............................-65°C to +150°C

Junction Temperature .....................................................+150°C

Lead Temperature (excluding WLP; soldering, 10s) .......+300°C

Soldering Temperature (reflow) .......................................+260°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage VCC 0.9 5.5 V

Supply Current ICC 1 100 nA

Diode Forward Voltage VFIF = 10mA 0.65 0.95 V

Positive transients VCC + 25

TA = +25°C, ±15kV Human

Body Model, IF= 10A Negative transients -25

Positive transients VCC + 60

TA = +25°C, ±8kV Contact

Discharge (IEC 61000-4-2),

IF = 24A Negative transients -60

Positive transients VCC + 100

Channel Clamp Voltage

(Note 2) VC

TA = +25°C, ±15kV Air-Gap

Discharge (IEC 61000-4-2),

IF = 45A Negative transients -100

Channel Leakage Current -0.1 +0.1 μA

MAX3205EAWL+T

MAX3207EAUT+T 2.5 3

MAX3205EATE+

MAX3208EATE+ 2.7 3.2

Channel I/O Capacitance VCC = +3.3V, bias of VCC / 2

MAX3208EAUB+ 2.6 3.1

Channel I/O to I/O

Variation in Capacitance CIN V

CC = +3.3V, bias of VCC / 2, CI/O_ to GND ±0.05 pF

TRANSIENT SUPPRESSOR

VCC Capacitance to GND 10 pF

ESD Trigger Voltage dV/dt  1V/ns (Note 3) 9 V

MAX3205E/MAX3207E/MAX3208E

Dual, Quad, and Hex High-Speed

Differential ESD-Protection ICs

_______________________________________________________________________________________

CLAMP VOLTAGE

vs. DC CURRENT

MAX3205E toc01

DC CURRENT (mA)

CLAMP VOLTAGE (V)

13011090705030

0.5

0.7

0.9

1.1

1.3

1.5

0.3

10 150

I/O_ TO VCC

GND TO I/O_

LEAKAGE CURRENT

vs. TEMPERATURE

MAX3205E toc02

TEMPERATURE (°C)

LEAKAGE CURRENT (pA)

80400

100

1000

10,000

-40 120

INPUT CAPACITANCE

vs. INPUT VOLTAGE

MAX3205E toc03

INPUT VOLTAGE (V)

INPUT CAPACITANCE (pF)

4321

Typical Operating Characteristics

(VCC = +5V, TA = +25°C, unless otherwise noted.)

Pin Description

MAX3205E MAX3207E MAX3208E

TQFN-EP WLP SOT23 μMAX TQFN-EP

NAME FUNCTION

4, 5, 7,

12, 13, 15

A2, A3, B1,

B3, C1, C2 1, 4 1, 4, 6, 9 4, 7, 12, 15 I/O_ ESD-Protected Channel

1, 3, 6, 8,

9, 11, 14,

— 3, 6 2, 5, 7, 10

1, 3, 5, 6,

8, 9, 11,

13, 14, 16

N.C. No Connection. Not internally connected.

— B2 — — — N.C.

No Connection. The solder sphere is omitted from

this location (see the Package Information section).

2 A1 2 3 2 GND

Ground. Connect GND with a low-impedance

connection to the ground plane.

10 C3 5 8 10 VCC

Power-Supply Input. Bypass VCC to GND with a

0.1μF ceramic capacitor as close to the device as

possible.

— — — — — EP Exposed Pad (TQFN Only). Connect EP to GND.

MAX3205E/MAX3207E/MAX3208E

Detailed Description

The MAX3205E/MAX3207E/MAX3208E low-capacitance,

±15kV ESD-protection diode arrays with an integrated

transient voltage suppressor (TVS) clamp are suitable for

high-speed and general-signal ESD protection. Low

input capacitance makes these devices ideal for ESD

protection of signals in HDTV, PC monitors (DVI, HDMI),

PC peripherals (FireWire, USB 2.0), server interconnect

(PCI Express, InfiniBand), datacom, and interchassis

interconnect. Each channel consists of a pair of diodes

that steer ESD current pulses to VCC or GND. The

MAX3207E, MAX3208E, and MAX3205E are two, four,

and six channels (see the

Functional Diagram

The MAX3205E/MAX3207E/MAX3208E are designed to

work in conjunction with a device’s intrinsic ESD pro-

tection. The MAX3205E/MAX3207E/MAX3208E limit the

excursion of the ESD event to below ±25V peak voltage

when subjected to the Human Body Model waveform.

When subjected to the IEC 61000-4-2 waveform and

Contact Discharge, the peak voltage is limited to ±60V.

The peak voltage is limited to ±100V when subjected to

Air-Gap Discharge. The device protected by the

MAX3205E/MAX3207E/MAX3208E must be able to

withstand these peak voltages, plus any additional volt-

age generated by the parasitic of the board.

A TVS is integrated into the MAX3205E/MAX3207E/

MAX3208E to help clamp ESD to a known voltage. This

helps reduce the effects of parasitic inductance on the

VCC rail by clamping VCC to a known voltage during an

ESD event. For the lowest possible clamp voltage dur-

ing an ESD event, placing a 0.1µF capacitor as close to

VCC as possible is recommended.

Dual, Quad, and Hex High-Speed

Differential ESD-Protection ICs

4 _______________________________________________________________________________________

MAX3207E

VCC

GND

I/O1 I/O2

MAX3208E

VCC

GND

I/O1 I/O2 I/O3 I/O4

MAX3205E

VCC

GND

I/O1 I/O2 I/O5 I/O6

I/O3 I/O4

Functional Diagram

Applications Information

Design Considerations

Maximum protection against ESD damage results from

proper board layout (see the

Layout Recommendations

section). A good layout reduces the parasitic series

inductance on the ground line, supply line, and protect-

ed signal lines. The MAX3205E/MAX3207E/MAX3208E

ESD diodes clamp the voltage on the protected lines

during an ESD event and shunt the current to GND or

VCC. In an ideal circuit, the clamping voltage (VC) is

defined as the forward voltage drop (VF) of the protec-

tion diode, plus any supply voltage present on the cath-

ode.

For positive ESD pulses:

VC= VCC + VF

For negative ESD pulses:

VC=-V

The effect of the parasitic series inductance on the

lines must also be considered (Figure 1).

For positive ESD pulses:

For negative ESD pulses:

where IESD is the ESD current pulse.

During an ESD event, the current pulse rises from zero

to peak value in nanoseconds (Figure 2). For example,

in a 15kV IEC 61000 Air-Gap Discharge ESD event, the

pulse current rises to approximately 45A in 1ns (di/dt =

45 x 109). An inductance of only 10nH adds an addi-

tional 450V to the clamp voltage and represents

approximately 0.5in of board trace. Regardless of the

device’s specified diode clamp voltage, a poor layout

with parasitic inductance significantly increases the

effective clamp voltage at the protected signal line.

Minimize the effects of parasitic inductance by placing

the MAX3205E/MAX3207E/MAX3208E as close to the

connector (or ESD contact point) as possible.

A low-ESR 0.1µF capacitor is recommended between

VCC and GND in order to get the maximum ESD protec-

tion possible. This bypass capacitor absorbs the

charge transferred by a positive ESD event. Ideally, the

supply rail (VCC) would absorb the charge caused by a

positive ESD strike without changing its regulated

value. All power supplies have an effective output

impedance on their positive rails. If a power supply’s

effective output impedance is 1Ω, then by using V = I x

R, the clamping voltage of VCincreases by the equa-

tion VC= IESD x ROUT. A +8kV IEC 61000-4-2 ESD

event generates a current spike of 24A. The clamping

voltage increases by VC= 24A x 1Ω, or VC= 24V.

Again, a poor layout without proper bypassing increas-

es the clamping voltage. A ceramic chip capacitor

mounted as close as possible to the MAX3205E/

MAX3207E/MAX3208E VCC pin is the best choice for

this application. A bypass capacitor should also be

placed as close to the protected device as possible.

VV Lx

dt Lx

CFD ESD ESD

() ()

=− +

⎛

⎝

⎜⎞

⎠

⎟+⎛

⎝

⎜⎞

⎠

⎟

⎛

⎝

⎜⎞

⎠

⎟

()

213

VV V Lx

dt Lx

CCCFD ESD ESD

() ()

=+ +

⎛

⎝

⎜⎞

⎠

⎟+⎛

⎝

⎜⎞

⎠

⎟

()

112

MAX3205E/MAX3207E/MAX3208E

Dual, Quad, and Hex High-Speed

Differential ESD-Protection ICs

_______________________________________________________________________________________ 5

PROTECTED

LINE

GROUND RAIL

POSITIVE SUPPLY RAIL

I/O_

Figure 1. Parasitic Series Inductance

tR = 0.7ns to 1ns 30ns

60ns

100%

90%

10%

PEAK

Figure 2. IEC 61000-4-2 ESD Generator Current Waveform

MAX3205E/MAX3207E/MAX3208E

±15kV ESD Protection

ESD protection can be tested in various ways. The

MAX3205E/MAX3207E/MAX3208E are characterized

for protection to the following limits:

• ±15kV using the Human Body Model

• ±8kV using the Contact Discharge Method specified

in IEC 61000-4-2

• ±15kV using the IEC 61000-4-2 Air-Gap Discharge

Method

ESD Test Conditions

ESD performance depends on a number of conditions.

Contact Maxim for a reliability report that documents

test setup, methodology, and results.

Human Body Model

Figure 3 shows the Human Body Model, and Figure 4

shows the current waveform it generates when dis-

charged into a low impedance. This model consists of

a 100pF capacitor charged to the ESD voltage of inter-

est, which is then discharged into the device through a

1.5kΩresistor.

IEC 61000-4-2

The IEC 61000-4-2 standard covers ESD testing and

performance of finished equipment. The MAX3205E/

MAX3207E/MAX3208E help users design equipment

that meets Level 4 of IEC 61000-4-2. The main differ-

ence between tests done using the Human Body Model

and IEC 61000-4-2 is higher peak current in IEC 61000-

4-2. Because series resistance is lower in the IEC

61000-4-2 ESD test model (Figure 5), the ESD-

withstand voltage measured to this standard is general-

ly lower than that measured using the Human Body

Model. Figure 2 shows the current waveform for the

±8kV, IEC 61000-4-2 Level 4, ESD Contact Discharge

test. The Air-Gap Discharge test involves approaching

the device with a charged probe. The Contact

Discharge method connects the probe to the device

before the probe is energized.

Dual, Quad, and Hex High-Speed

Differential ESD-Protection ICs

6 _______________________________________________________________________________________

CHARGE-CURRENT-

LIMIT RESISTOR

DISCHARGE

RESISTANCE

STORAGE

CAPACITOR

100pF

1MΩ

1.5kΩ

HIGH-

VOLTAGE

SOURCE

DEVICE

UNDER

TEST

Figure 3. Human Body ESD Test Model

IP 100%

90%

36.8%

tRL TIME

tDL

CURRENT WAVEFORM

PEAK-TO-PEAK RINGING

(NOT DRAWN TO SCALE)

10%

AMPERES

Figure 4. Human Body Model Current Waveform

CHARGE-CURRENT-

LIMIT RESISTOR

DISCHARGE

RESISTANCE

STORAGE

CAPACITOR

150pF

50MΩ TO 100MΩRD

330Ω

HIGH-

VOLTAGE

SOURCE

DEVICE

UNDER

TEST

Figure 5. IEC 61000-4-2 ESD Test Model

Layout Recommendations

Proper circuit-board layout is critical to suppress ESD-

induced line transients (See Figure 6). The MAX3205E/

MAX3207E/MAX3208E clamp to 100V; however, with

improper layout, the voltage spike at the device can be

much higher. A lead inductance of 10nH with a 45A

current spike results in an additional 450V spike on the

protected line. It is essential that the layout of the PC

board follows these guidelines:

1) Minimize trace length between the connector or

input terminal, I/O_, and the protected signal line.

2) Use separate planes for power and ground to reduce

parasitic inductance and to reduce the impedance to

the power rails for shunted ESD current.

3) Ensure short low-inductance ESD transient return

paths to GND and VCC.

4) Minimize conductive power and ground loops.

5) Do not place critical signals near the edge of the PC

board.

6) Bypass VCC to GND with a low-ESR ceramic capaci-

tor as close to VCC as possible.

7) Bypass the supply of the protected device to GND

with a low-ESR ceramic capacitor as close to the

supply pin as possible.

WLP Applications Information

For the latest application details on WLP construction,

dimensions, tape carrier information, printed circuit

board techniques, bump-pad layout, and recommend-

ed reflow temperature profile, as well as the latest infor-

mation on reliability testing results, refer to Application

Note 1891:

Wafer-Level Packaging (WLP) and Its

Applications

Chip Information

PROCESS: BiCMOS

MAX3205E/MAX3207E/MAX3208E

Dual, Quad, and Hex High-Speed

Differential ESD-Protection ICs

_______________________________________________________________________________________ 7

VCC

PROTECTED LINE

NEGATIVE ESD-

CURRENT

PULSE

PATH TO

GROUND

PROTECTED

CIRCUIT

GND

I/O_ VC

Figure 6. Layout Considerations

MAX3205E

MAX3207E

MAX3208E

0.1μF

I/0_

I/0

I/0 LINE

VCC

PROTECTED

CIRCUIT

Typical Operating Circuit

MAX3205E/MAX3207E/MAX3208E

Dual, Quad, and Hex High-Speed

Differential ESD-Protection ICs

8 _______________________________________________________________________________________

TOP VIEW

16 15 14 13

N.C.

VCC

N.C.

I/O2

I/O4

N.C.

GND

N.C.

5678

N.C.

I/O3

N.C.

I/O1

N.C.

MAX3208E

TQFN

16 15 14 13

N.C.

VCC

N.C.

I/O3

I/O6

N.C.

GND

N.C.

5678

I/O5

N.C.

I/O4

N.C.

I/O1

N.C.

I/O2

MAX3205E

TQFN

GND

I/O2N.C.

1 6 N.C.

I/O1

MAX3207E

SOT23

N.C.

I/O4

VCC

N.C.I/O2

GND

N.C.

I/O1

MAX3208E

μMAX

I/O3N.C.

MAX3205E

WLP

(BUMPS ON BOTTOM)

A2 A3 I/O5

GND

I/O1

I/O2

I/O6

*EP

*CONNECT EP TO GND.

B1 B3 I/O4

C1 C2 C3 VCC

I/O3

Pin Configurations

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in

the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to

the package regardless of RoHS status.

PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

9 WLP W91B1+5 21-0067 —

16 TQFN-EP T1633+4 21-0136 90-0031

6 SOT23 U6+1 21-0058 90-0175

10 µMAX U10+2 21-0061 90-0330

MAX3205E/MAX3207E/MAX3208E

Dual, Quad, and Hex High-Speed

Differential ESD-Protection ICs

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________

Revision History

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

3 7/10

Changed the 9 UCSP package to a 9 WLP package in the Ordering Information table,

Absolute Maximum Ratings,Pin Description table, and the Pin Configurations;

changed leaded packages to lead-free packages in the Ordering Information table;

changed the MAX3205EAWL+T part number and its top mark in the Selector Guide;

deleted all information in the Chip Information section except “Process: BiCMOS”

1, 2, 3, 7, 8