A61L73081 Series
128K X 8 BIT HIGH SPEED CMOS SRAM
(April, 2001, Version 1.0) AMIC Technology, Inc.
Document Title
128K X 8 BIT HIGH SPEED CMOS SRAM
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue July 14, 2000 Preliminary
1.0 Change ICC1 from 120mA to 220mA April 26, 2001 Final
100mA to 210mA
Change ISB1 from 8mA to 12mA
Change ICDR from 1mA to 5mA
Final spec. release
A61L73081 Series
128K X 8 BIT HIGH SPEED CMOS SRAM
(April, 2001, Version 1.0) 1 AMIC Technology, Inc.
Features
n Center power pinout
n Supply voltage: 3.3V±10%
n Access times: 12/15 ns (max.)
n Current: Operating: -12: 220mA (max.)
-15: 210mA (max.)
Standby: TTL: 25mA (max.)
CMOS: 12mA (max.)
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL compatible
n Common I/O using three-state output
n Data retention voltage: 2V (min.)
n Available in 32-pin 300mil / 400mil SOJ packages
General Description
The A61L73081 is a high-speed 1,048,576-bit static
random access memory organized as 131,072 words by
8 bits and operates on a 3.3V power supply. It is built
using high performance CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Minimum standby power is drawn by this device when
chip enable is disable, independent of the other input
levels.
Data retention is guaranteed at a power supply voltage
as low as 2V.
Pin Configurations
n SOJ
A0
A2
A3
I/O0
I/O1
VCC
GND
I/O2
I/O3
A4
A5
A6
A8A7
A9
A10
A11
A12
I/O5
I/O6
I/O7
A14
A15
A16
GND
A61L73081S(SW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VCC
I/O4
OE
A1
CE
WE
A13
A61L73081 Series
(April, 2001, Version 1.0) 2 AMIC Technology, Inc.
Block Diagram
Pin Descriptions – SOJ
Pin No. Symbol Description
1-4, 13-21, 29-32 A0 - A16 Address Inputs
6-7, 10-11, 22-23, 26-27 I/O0 - I/O7 Data Inputs/Outputs
5 CE Chip Enable
28 OE Output Enable
12 WE Write Enable
8, 24 VCC Power Supply
9, 25 GND Ground
ADDRESS
DECODER
1,048,576-BIT
MEMORY ARRAY
I/O CONTROL
CONTROL
LOGIC
A16
A0
OE
WE
88
8
I/O0 - I/O7
CE
A61L73081 Series
(April, 2001, Version 1.0) 3 AMIC Technology, Inc.
Recommended DC Operating Conditions
(TA = 0°C to + 70°C)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 3.0 3.3 3.6 V
GND Ground 0 0 0 V
VIH Input High Voltage 2.2 - VCC + 0.5 V
VIL Input Low (1) Voltage -0.5 0 +0.8 V
CL Output Load - - 30 pF
Absolute Maximum Ratings*
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V
IN, IN/OUT Volt to GND . . . . . . . . . . -0.5V to VCC +0.5V
Operating Temperature, Topr . . . . . . . . . . . 0°C to +70°C
Storage Temperature, Tstg . . . . . . . . . . -55°C to +125°C
Temperature Under Bias, Tbias . . . . . . . . -10°C to +85°C
Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . . 0.7W
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute maximum
rating conditions for extended periods may affect device
reliability.
DC Electrical Characteristics (TA = 0°C to + 70°C, VCC = 3.3V ± 10%, GND = 0V)
Symbol Parameter A61L73081-12 A61L73081-15 Unit Conditions
Min. Max. Min. Max.
ILI Input Leakage - 2 - 2 µA VIN = GND to VCC
ILO Output Leakage - 2 - 2 µA CE = VIH, OE = VIH
VI/O = GND to VCC
ICC1 (2) Dynamic Operating
Current - 220 - 210 mA CE= VIL, II/O = 0 mA
Min. Cycle, Duty = 100%
ISB - 25 - 25 mA CE= VIH
ISB1
Standby Power
Supply Current
- 12
- 12
mA CE ≥ VCC - 0.2V,
VIN ≥ VCC -0.2V or VIN ≤ 0.2V
VOL Output Low Voltage - 0.4 - 0.4 V IOL = 8 mA
VOH Output High Voltage 2.4 - 2.4 - V IOH = -4 mA
Notes: 1. VIL = -3.0V for pulses less than 20 ns.
2. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns.
A61L73081 Series
(April, 2001, Version 1.0) 4 AMIC Technology, Inc.
Truth Table
Mode
CE
OE
WE
I/O Operation Supply Current
Standby H X X High Z ISB, ISB1
Output Disable L H H High Z ICC1
Read L L H DOUT ICC1
Write L X L DIN ICC1
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol Parameter Min. Max. Unit Conditions
CIN* Input Capacitance - 8 pF VIN = 0V
CI/O* Input/Output Capacitance - 8 pF VI/O = 0V
* These parameters are sampled and not 100% tested.
AC Characteristics (TA = 0°C to +70°C, VCC = 3.3V ± 10%)
Symbol Parameter A61L73081-12 A61L73081-15 Unit
Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 12 - 15 - ns
tAA Address Access Time - 12 - 15 ns
tACE Chip Enable Access Time - 12 - 15 ns
tOE Output Enable to Output Valid - 6 - 8 ns
tCLZ Chip Enable to Output in Low Z 3 - 3 - ns
tOLZ Output Enable to Output in Low Z 0 - 0 - ns
tCHZ Chip Disable Output in High Z 0 6 - 8 ns
tOHZ Output Disable to Output in High Z 0 6 0 8 ns
tOH Output Hold from Address Change 3 - 3 - ns
A61L73081 Series
(April, 2001, Version 1.0) 5 AMIC Technology, Inc.
AC Characteristics (continued)
Symbol
Parameter A61L73081-12 A61L73081-15 Unit
Min. Max. Min. Max.
Write Cycle
tWC Write Cycle Time 12 - 15 - ns
tCW Chip Enable to End of Write 10 - 12 - ns
tAS Address Setup Time of Write 0 - 0 - ns
tAW Address Valid to End of Write 10 - 12 - ns
tWP Write Pulse Width 10 - 12 - ns
tWR Write Recovery Time 0 - 0 - ns
tWHZ Write to Output in High Z 0 6 0 8 ns
tDW Data to Write Time Overlap 6 - 7 - ns
tDH Data Hold from Write Time 0 - 0 - ns
tOW Output Active from End of Write 3 - 3 - ns
Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not
referred to output voltage levels.
Timing Waveforms
Read Cycle 1(1)
tRC
Address
DOUT
tAA
tOE
tOLZ5
tACE
tCLZ5tCHZ5
tOH
OE
tOHZ5
CE
A61L73081 Series
(April, 2001, Version 1.0) 6 AMIC Technology, Inc.
Timing Waveforms (continued)
Read Cycle 2(1, 2, 4)
tRC
tOH
tAA
tOH
Address
DOUT
Read Cycle 3(1, 3, 4,)
tCLZ5
tACE
tCHZ5
DOUT
CE
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled, CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
A61L73081 Series
(April, 2001, Version 1.0) 7 AMIC Technology, Inc.
Timing Waveforms (continued)
Write Cycle 1(6)
(Write Enable Controlled)
tWC
Address
DIN
tOW7
tDH
tDW
tWHZ7
tWP2
tAS1
(4)
tCW5
tAW tWR3
DOUT
WE
CE
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
DIN
tDW
tWHZ
tAW tWR3
DOUT
tDH
(4)
tWP2
tCW5
tAS1
CE
WE
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE and a low WE .
3. tWR is measured from the earliest of CE or WE going high to the end of the Write cycle
4. If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs
remain in a high impedance state.
5. tCW is measured from the later of CE going low to the end of Write.
6. OE is continuously low. (OE = VIL)
7. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
A61L73081 Series
(April, 2001, Version 1.0) 8 AMIC Technology, Inc.
AC Test Conditions
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Time 3 ns
Input and Output Timing Reference Levels 1.5V
Output Load See Figures 1 and 2
* Including scope and jig.
3.3V
DATAOUT
5pF*
317
Ω
351
Ω
ZO=50
Ω
OUTPUT
RL=50
Ω
VT=1.5V
Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ,
tCHZ, tOHZ, tWHZ, and tOW
Data Retention Characteristics (TA = 0°C to 70°C)
Symbol Parameter Min. Max. Unit Conditions
VDR VCC for Data Retention 2 3.6 V CE ≥ VCC - 0.2V
ICCDR
Data Retention Current
-
5
mA
VCC = 2.0V
CE ≥ VCC - 0.2V
VIN ≥ VCC - 0.2V or
VIN ≤ 0.2V
tCDR Chip Disable to Data Retention
Time 0 - ns
See Retention Waveform
tR Operation Recovery Time TRC* - ms
tRC = Read Cycle Time
A61L73081 Series
(April, 2001, Version 1.0) 9 AMIC Technology, Inc.
Low VCC Data Retention Waveform
VCC
CE
tCDR
VIH
3.0V
tR
VIH
3.0V
DATA RETENTION MODE
VDR ³ > 2.0V
CE ³ > VDR - 0.2V
Ordering Information
Part No. Access Time (ns) Operating Current
Max. (mA) CMOS Standby
Max. (mA) Package
A61L73081S-12 32L 300mil SOJ
A61L73081SW-12 12 220 12 32L 400mil SOJ
A61L73081S-15 32L 300mil SOJ
A61L73081SW-15 15 210 12 32L 400mil SOJ
A61L73081 Series
(April, 2001, Version 1.0) 10 AMIC Technology, Inc.
Package Information
SOJ 32L(300mil) Outline Dimensions unit: inches/mm
Dimensions in inches Dimensions in mm
Symbol Min Nom Max Min Nom Max
A 0.128 0.132 0.140 3.25 3.35 3.56
A1 0.052 - - 2.08 - -
A2 0.095 0.100 0.105 2.41 2.54 2.67
b 0.016 0.018 0.020 0.41 0.46 0.51
b1 0.026 0.028 0.032 0.66 0.71 0.81
C 0.006 0.008 0.012 0.15 0.20 0.30
D 0.820 0.825 0.830 20.83 20.96 21.08
E 0.330 0.335 0.340 8.39 8.51 8.63
E1 0.295 0.300 0.305 7.49 7.62 7.75
E2 0.260 0.267 0.274 6.61 6.78 6.96
e - 0.050 - - 1.27 -
S - - 0.048 - - 1.22
y - - 0.004 - - 0.10
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension E1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
Package Information
1
A1
A2
A
eE2
C
16
1732
S
Seating Plane
D
y
b1
b
E1
D
Min
0.025"
0.004
E
yy
A61L73081 Series
(April, 2001, Version 1.0) 11 AMIC Technology, Inc.
SOJ 32L (400mil) Outline Dimensions unit: inches/mm
Dimensions in inches Dimensions in mm
Symbol Min Nom Max Min Nom Max
A 0.131 0.138 0.145 3.33 3.51 3.68
A1 0.082 - - 2.08 - -
A2 0.105 0.110 0.115 2.67 2.79 2.91
b 0.016 0.018 0.020 0.41 0.46 0.51
b1 0.026 0.028 0.032 0.66 0.71 0.81
C 0.006 0.008 0.011 0.15 0.20 0.28
D 0.820 0.825 0.830 20.83 20.96 21.08
E 0.435 0.440 0.445 11.05 11.18 11.31
E1 0.395 0.400 0.405 10.03 10.16 10.29
E2 0.360 0.370 0.380 9.15 9.40 9.65
e - 0.050 - - 1.27 -
S - - 0.045 - - 1.14
y - - 0.004 - - 0.10
θ -5° 2° 6° -5° 2° 6°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension E1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
1
A1
A2
A
eE2
C
16
1732
S
Seating Plane
D
y
b1
b
E1
D
Min
0.025"
0.004
E
yy θ
