HARRIS SEMICOND SECTOR Gi? HARRIS CMOS WHE D = 4u302271 oo37389 2 BMHAS T=4S-23-27 CD4026B, CD4033B Types eo. Noo Decade Counters/Dividers eo teas High-Voltage Types (20-Volt Rating) a | ie 5 With Decoded 7-Segment Display Outputs and: - inti le, g Display Enable ~ CD4026B acter cos Ripple Blanking CD4033B @ CD4026B and CD4033B each con- sist of a 5-stage Johnson decade counter and an output decoder which converts the Johnson code to a 7-seqment decoded out- put for driving one stage in a numerical display. These devices are particularly advantageous in display applications where low power dissipation and/or low package count are important. Inputs common to both types are CLOCK, RESET, & CLOCK INHI8IT; common outputs are CARRY OUT and the seven decoded outputs (a, b, c, d, e, f, g). Addi- tional inputs and outputs for the CD4026B include DISPLAY ENABLE input and DISPLAY ENABLE and UNGATED C- SEGMENT outputs. Signals pecutiar to the CD40338 are RIPPLE-BLANKING INPUT AND LAMP TEST INPUT and a RIPPLE- BLANKING OUTPUT. A high RESET signai clears the decade counter to its zero count. The counter is advanced one count at the positive clack signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock fine is inhibited when the CLOCK INHIBIT signal is high. The CLOCK INHI- BIT signal can be used as a negative-edge clock if the clack line is held high. Antilock gating is provided on the JOHNSON counter, thus assuring proper counting sequence. The CARRY-OUT (Co),4) signal completes one cycle every ten abc INPUT cycles and is used 9 clock the succeeding decade di- rectly in a multi-decade counting chain. The seven decoded outputs (a, b, c, d, e, f, g) illuminate the proper segments in a seven MAXIMUM RATINGS, Absolulte-Maximum Values: DC SUPPLY-VOLTAGE RANGE, (Vpp) Voitages raferanced to Vgg Terminal) INPUT VOLTAGE RANGE, ALL INPUTS. OC INPUT CURRENT, ANY ONE INPUT ............ POWER DISSIPATION PER PACKAGE (Pp): For Ta = -55C to #1009C 20... cece eee For Ta = +100C to +125C. eee eee DEVICE DISSIPATION PER OUTPUT TRANSISTOR FOR Ta = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)..........eseseeeceees 10OmW RIPPLE GLANKeIG OUT Features: Counter and 7-segment decoding in one package orseiar| @ Easily interfaced with 7-segment display types i" @ Fully static counter operation: DC te 6 MHz (typ.) at Vpp=10 V Ideal for low-power displays Display enable output (CD40268) Ripple blanking and tamp test (CD4033B) 100% tested for quiescent current at 20 V Standardized, symmetrical output characteristics . Ys$ azcs-asoraar D4026B FUNCTIONAL DIAGRAM @ 6-V, 10-V, and 15-V parametric ratings Schmitt-triggered clock inputs = Meets all requirements of JEDEC Tentative crock Standard No, 13B, Standard Specifications E for Description of B Series CMOS Devices 2 5 ji j clock Applications euock a = Decade counting 7-segment decimal 1s 8 display RESET | 3 B Frequency division 7-segment decimal . r displays Lau 4 Clocks, watches, timers TEST RY (e.g. +60, + 60, + 12 counter/display) - 3 : Counter/display driver for meter RIPPLE = RiPrLE applications in - Vss -- - 92CS-25076A) a _CD40338 : FUNCTIONAL DIAGRAM segment display device used for representing the decimal numbers 0 to 9. The 7-seqment outputs go high on selection in the CD40338; in the CD4026B these outputs go high only TERMINAL DIAGRAMS when the DISPLAY ENABLE IN is high. Top View CLOCK CLOCK INHIBIT: DISPLAY ENASLE IN. DISPLAY ENABLE OUT Yoo RESET c aun OvVaoe 3s CARRY OUT a t e q o ss d -0.5V to +20V 9205-24465R1 ~0.5V to Vp +0.5V cp4026B eae eee eee ree een eet n ee nnee tte reeenee 10mA Top View Pee a eee e eee ene e ence eee beeen nestaeees soomw crock CLOCK INHIBIT RIPPLE BLANKINGIN - Yoo RESET LAMP TEST - we DAH euns CARAY OUT 6 OPERATING~TEMPERATURE RANGE (Ta)........- t ~@ STORAGE TEMPERATURE RANGE stg) Vee 5 LEAD TEMPERATURE (DURING SOLDERING): At distance 1/16 + 1/32 inch (1.59 + 0.79mm) from case for 108 MAX ....... eee e eee nee e reas +265C 9208-24478A1 CbD40338 3-70 UNGATED C" SEGMENT OVTHARRIS SEMICOND SECTOR CD4026B, CD4033B Types RECOMMENDED OPERATING CONDITIONS Habit For t Y, / operating ditions should be sel: 1 so that operation is always within the following ranges: CHARACTERISTIC Vpp LIMITS UNITS . (v) MIN. MAX. Supply-Voltage Range {For Ta = Fuil Package Temperature Range) 3 18 Vv Clack Input Frequency, fei 5 - 2.5 10 - 5.5 MHz 15 = 8 Clock Pulse Width, twee 5 220 - 10 100 - 18 80 - Clock Rise and Fall Time, tou Yer 5 - 10 - Unlimited 1s = Clock Inhibit Set Up Time, tsy 5 200 - 10 50 - ns 15 30 - Reset Pulse Width, tw 5 200 - 10 100 - 15 50 - Reset Removal Time 5 30 ~ 10 18 - 15 10 - STATIC ELECTRICAL CHARACTERISTICS CONDITIONS LIMITS AT INDICATED TEMPERATURES (C) CHARACTER. UNITS ISTIC 325 Vo | Vin | Yoo {v) iv) | (v) | -55 | 40 +85 +125 | Min. Typ. | Max. Quiescent Device - 0,5 5 5 5 150 150 - 0.04 5 Current, - 0,10] 10 | 10 10 300 | 300 | - 0.04 | 10 IDO Max. _fors|is 1 2 | 3 [00 | 600} | o0s) 20] - [0,20] 20 | 100 [100 [3000 | 3000[ | 0.08 | 100 Output Low oa {05 | 5 | 064/061 | 042 | 0.36 [051 1 = (Sink) Current 05 [010] 10} 16 | 15 Ww 09 | 1.3 2.6 - 'OL Min. 15 [015] 15 {42 | 4 | 28 | 24)34 | 68 | - Output High 46 {05 | 5 | -0.64]-0.61|-0.42|-o.36/-o51] ~1 | mA (Source) 25 |o5/] 5 | -2 |-18 |-13 |-1.15|/-16}| -32) Current. 96 |010| 101-16]-15 |-1.1|-09 |-13) -26] JOH Min. 135 [015] 15 |-42] -4 |-28 |-24[-34 | -68 | Output Voltage: - 0,5 5 0.05 - 0 0.05 Loweteve. - [0.10] to 0.05 = 0 | 005 OL er ~ 0.15] 15 0.05 ~ o [oo| | Output Voltage - 05 5 4.95 4.95 5 - High-Level, |o10] 10 9.95 9.95 | 10 VOH Min. [015] 15 14.95 14.95] 15 | input Low 0.5, 4.5 - 5 15 - - 15 Voltage, 1.9 _ 10 3 _ _ 3 vi Max, Te aael 2 Tas 4 a aly Input High 05.45[ - | 5 3.5 36 [ Voltage, 19 - | 10 7 7 - = Vin Ming 15135] - | 15 11 mu f] [ ne current - for} ia | sor] sor] 41 | ar | - fe10-S) 400] pa 3-71 44E D MM 4302271 0037390 9 BBHAS T24S5Q3-27 cD4026B : When the DISPLAY ENABLE IN is low the seven decoded outputs are forced low re- gardiess of the state of the counter. Acti- vation of the display only when required results in significant power savings. This system also facilitates implementation of display-charagter multiplexing. The CARRY OUT and UNGATED c- SEGMENT" signals are not gated by the DISPLAY ENABLE and therefore are avail- able continuously. This feature is a re- quirement in implementation of certain di- vider functions such as divide-by-60 and divide-by-12, CD4033B The CD40338 has provisions for automatic blanking of the non-significant zeros in a multi-digit decimal number which results in an easily readable display consistent with normal writing practice. For example, the number 0050.0700 in an eight digit display would be displayed as 50.07, Zero suppres- sion on the integer side is obtained by con- necting the RBI terminal of the CD4033B associated with the most significant digit in the display to a low-level voltage and con- necting the RBO terminal of that stage to the RBI terminal of the CD40338 in the next-lower significant position in the dis- play. This procedure is continued for each succeeding CD4033B on the integer side of the display. On the fraction side of the display the RB! of the CD4033B associated with the least significant bit is connected to a low-level voltage and the RBO of that CD4033B is connected to the RBI terminal of the CD4033B in the next more-significant-bit position, Again, this procedure is continued for all CD4033Bs on the fraction side of the display. In a purely fractional number the zero immediately preceding the decimal point can be displayed by connecting the- RBI of that stage to ahigh level voltage (instead of to the RBO of the next more-significant-stage). For example: optional zero > 0.7346. Likewise, the zero in a number such as 763.0 can be displayed by connecting the RBI of the CD4033B associated with it to a high- level voltage. . Ripple blanking of non-significant zeros provides an appreciable savings in display power. : The CD4033B has a LAMP TEST input which, when connected to a high-level volt- age, overrides normal decoder operation and enables a check to be made on possible display malfunctions by putting the seven outputs in the high state. The CD40268- and CD40338-series types are supplied in 16-lead hermetic duat-in-line ceramic packages (D and F suffixes),.16- lead dual-in-line plastic packages (E suffix), and in chip form (H suffix). COMMERCIAL CMOS HIGH VOLTAGE iCsSECTOR HARRIS SEMICOND CD4026B, CD4033B Types I "esa * crockO | INHABIT 2 i> oisPLay ENABLE 16 YooO oxvo ALL INPUTS PROTECTED BY CMOS INFUT PROTECTION NETWORK " = SS Fig. 1 COD40268 togic diagram. ' *evock crock > cl (NHIQIT 2 WUE D MM 4302271 0037391 0 MMHAS UNGATED "C SEGMENT q OISPLAY ENABLE ouT tla kb wl d SEGMENT Je DESIGNATIONS Ste.-290r8 g a tla lo SEGMENT CESIGNATIONS | fe o 16 o00 "ALL INPUTS PROTECTED oo aY CMOS INPUT GRDOS PROTECTION NETWORK. "7 ss Fig. 2 CD4033B logie diagram. ORA'N-TO-SQURCE VOLTAGE (Vog) sacs-zenians Fig. 6 Typical a-channel output low (sink) current characteristics. s2cu- 22078 ORAIN-TO-SOURCE VOLTAGE (Vpg)V. Fig. 7 Minimum n-channel output low {sink) current characteristics. s2es-zeu9m P5-93-3 9 COUNT eL RESET ojije}s 4 efrlefejolsjels CLOCK INHIBIT OISPLAY. ERAGLE IR OISPLAY ENABLE OUT ~eaog 9 CARRY OUT UNGATEO "c* SEG. 92ts-mcezas Fig. 3 CD40268 timing diagram. C006 TULL LU, RESET cLoce AIT Sl Lane r vest Ral aL Cour RCLOCK S10) yp SI ep o CT FL rT rs Oo on oe 25456189018 456789 12 92CS-29084 oi Fig. 4 CO40338 timing diagram. ca stes-29077 Fig. 5 Detail of typical flip-flop stage for both types. ORAIN-TO-SOYRCE VOLTAGE Wosl= g2cs-f4as2cas Fig. 8 Typical p-channel output high (source) current characteristics, :-2 : : see pemee e e HARRIS SEMICOND SECTOR WUE D MM 4302271 0037392 2 MBHAS CD4026B, CD4033B Types T+ 48-23-29 DRAIN-TO-SOURCE VOLTAGE (Vp3) DYNAMIC ELECTRICAL CHARACTERISTICS at Ta= 25C, Input t,, t= 20 ns, Cy = 50 pF, A, = 200k2Q TEST 3 CONDITIONS LIMITS 5 CHARACTERISTIC Vpp UNITS 5 (V)_|Min.] Typ.| Max. CLOCKED OPERATION 3 Propagation Delay Time; tepLH, tpHL 5 | | 250 |500 = Carry-Out Line 10 | | 100 [200 z is | | 75 [180 - 9205 -249718g ; 51 | 350 |700 Fig. 9 Minimum p-channel output high (source) Decode Outlines 10 | | 125 {250 ns current characteristics. 15 | ~ {| 90 |180 Transition Time; tHE tTLH 5 | ~ | 100 |200 Carry-Out Line 10 | - 50 $100 15 | - | 251 50 Maximum Clock Input Frequency, fora 5 12.5 5 | 10 j55] 11] ~ | MHz 15 | 8{ 16 | 8 & Min. Clock Pulse Width, ty 5_| [110 |220 oy 1o_|- | 50 [100 =e 15 [ | 40 | 80 aS Clock and Clock Inhibit Rise or Fall Time; 5 LOAD CAPACITANCE (CLIpF _g2s-31705 = 5 tet 4eL 10 Unlimited ns Fig. 10 - Typical propagation delay time as a 8 = > function of load capacitance for - - 15 decoded outputs. Average Input Capacitance, Cin Any Input _ | 5 | 7 | pF RESET OPERATION Propagation Delay Time; |- |275 |550 To Carry-Out Line, tPLH 10 | |120 |240 15 | | 80 {160 To Decode Out Lines, tPHL- tPLH 5 | [300 {600 10 [ [125 1250 15 _ | | 90 |180 ns Min. Reset Pulse Width, tw 5 |- |100 120 10 = 50 [100 LOAD CAPALITANCE (1)~pF azes-31708 15 |~ | 25 | 50 Fig, 11 Typical propagation delay time asa Min. Reset Removal Time 5 }- 0 | 30 function af load capacitance for . carry-out outputs. 10 |- Oj 15 15 |~ 0 410 SENT TEMPERATURE (Tals 4 Measured with respect to carry-out lina. SUPPLY VOLTAGE {gpI 92CS-31703 Fig. 12 Typical maximum clock input-trequency as a function of supply voltage. 3-73HARRIS SEMICOND SECTOR 44HE D MM 4302271 0037393 4 MMHAS CD4026B, CD4033B Types T45-Q3-2 9 Yoo LOAD CAPACITANCE (C1: 50pF 1a pF (tue TEST PEFORMED WITH THE FOLLOWING SEQUENCE OF 1"s AND O"s AT EACH INPUT 7} S$) Sq Sz Sq Sg 2 roooo ; 3 loroo. 2 5 oo!1dot 6 oriett 3 7 4 a * DISCONNECT PIN 14 5 [ FOR cD40268 6 = = 925-31706 ? . ' 10 8 . . CLOCK INPUT-FREQUENCY tteg} MM 92s-31701 Fig. 15 Quiescent device current. Fig. 13 Typical power dissipation as a function of clock input frequency. 928-31702 y, 00 Fig. 14 Dynamic power dissipation test circuit 4 for CD40338. INPUTS OUTPUTS - - _ ora Yin cel : Noe La. INTERFACING THE CD4026B AND CD4033B WITH COMMERCIALLY AVAILABLE ve <| L Z th LIGHT EMITTING DIODE DISPLAYS + | ae = NOTE: 7 TEST ANY COMBINATION Yoo 8s OF INPUTS MONSANTO MAN 3 MONSANTO MAN I vTcasoa; = tMANT [? 92$-27441RE owPowen Vv? Caxog2 OF EOUIVALENT on EQuy. : Ad Fig. 16 input volta, id OR EQUIVALENT Yoo | \ % put voltage. i a Ty || enaozsar (t y, croce O-{6040338 | 7 1 \ a i= | ! i e . 2 It | 1 1 I woe Ot ceouburs E | ; | | | 1] i INPUTS L Yoo | + I : RESET - te i har | y j ei, \ Yoo NOTE: I \ 6 I ifs No-(Z)> MEASURE INPUTS > bys I ! a SEQUENTIALLY, vop235 + ic 1 } Voozsvimny Vss TO BOTH Vop AND Vgs- Te $ mAs SEGMERT l I Ig 20.4mA ~ 8 | CONNECT ALL UNUSED 100% OUTY CYCLE ! \ Tp2 12 majSeg. 100 OUTYCYGLED iL INPUTS To E\THER A Npogg-Ve (LEO) ! | fae (Minas s0 . } Von OF Vss- LED WHERE vp+ INPUT PULSE l Vee ISATI$0.5 Vss" Vp FORWARD DROP . BY Vo0-Ycetaan Vr ited? ACAOSS OIODE 92cs-31708 Trep 92cs-31709 ; 92c$-27402 WHERE Vp FORWARD DROP ACROSS DIODE Fig. 17 input current, 107 A an-96 {2.235 -2.438) Pill Naren hc Saha earn beiof 3 25a f : a : re 3B say ~*~ 19102 -0.254) | " sees-32207 104 -|12 (2.642 - 2 845) 92C$-31700R1 a Chip dimansions and pad layout for CD40268 Chip dimensions and pad layout for GD4033B. Oimensions in parentheses are sn millimeters and are derved from the basic :nch dimensions as in- Gicated Gad graduations are sn mils (1073 inch). 3-74 r 1 oe ete ee gee we ager cre ee eeHARRIS SEMICOND SECTOR 44HE D MM 4302271 0037394 & MBHAS CD4026B, CD4033B Types Tug 2329 INTERFACING THE CD4026B AND CD40338 WITH COMMERCIALLY AVAILABLE 7 * 7-SEGMENT DISPLAY DEVICES* Yr Yoo t | T WCANOEICEMT BadguTS RCA Numitron A200 Senes TUBE REQUIREMENTS COsoregy clock cocares c vyeamn Vy 13.5-5V A. 4 inHient | ook cou. by * 24 mA Segmere 7 secuents | > ASSUMED comene - TRANSISTOR RESET - vz CHARACTERISTICS @Vog # OV fmin} ~ Bac tmnt 2 25 Yoos i = %s5 Yegtunas 054 ty Fad fase Yop 8(any TSREVTOSY = tg tmd tous.) t+ Medlond @y os oveminy Wo S$ O8y Ups bat inn) . LOW-POWER INCANDESCENT READOUTS ASSURED PINLITES INC-Saries O and R Vn #6 Emin) TUBE REQUIREMENTS Vy() mASegment CHARACTERISTICS QVoe ' 0-00-15 15 8 wos 0-04-30 3 6 iy # Sea (aia) 0-06-30 3 8 Vest A-R-20 2 43 tg 2 0.25 A (ein) THEY TORS Y R-A4-30 4 43 {T $7.5 ah (ain) 920N~- 31707 * The interfacing buffers shown, while a necessity with the CD4026A and D4033A, are nat required when using the B devices; the "B" outputs (* 10 times the A outputs) can drive most display devices directly especially at voltages above 10 V. COMMERCIAL CMOS HIGH VOLTAGE ICs TNESS Vr2 US OC WATH Vou #8 VEDIUM BRIGHTNES oo Von I LOW AMB:ENT LIGHT BACKGROUND - OO WILL RES! THE POINT OF NO . NOTICEBLE GLOWS Vorr & 4.5 cos0z6e/ aay cua 0403368 tH BIT oOo TSEGMENTS cLock atser 13.5 y INHIBIT ? Locic SEGMENTS _L VORTAGE 1 . oN RESET| NEON READOUT {NIXIE TUBE4} ~ 1. Alco Electronics ~ MG19 4 ss 2. Burroughs 85971, 87971, 88971 nay TUBE REQUIREMENTS Vy(Vdel mA Segment = P dusy LOW VOLTAGE VACUUM FLUORESCENT ac on oc AleoMGI9.. 2... wo... O5 REAOOUTS Burroughs 85971. . . . W70...2. 3 . Burraughs@7971, 88971. 170... 6 1. Tung-Sol DIGIVAC S/G $ Tyne OT1704A o 973705 2. Nippon Electric (NEC): Type OG12E or LDS? TUBE REQUIREMENTS: 100 to 300 pA "seqract TRANSISTOR CHARACTERISTICS a1 tube voltages of 12 V to 25 V depending ca Leakage with transistor cutoff - 0.05 mA required brightness Filament requirement 45 ma VipRICER - >Vr at t.6 V, ac ar de. Age (min.) > 30 9268-31710 5 (Trademark) Wagner Electric Co. * (Trademark) Burroughs Camp. 92CS-31711 3-75