TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
FAMILY OF MICROPOWER RAIL-TO-RAIL INPUT AND OUTPUT
OPERATIONAL AMPLIFIERS
1
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FEATURES
D
BiMOS Rail-to-Rail Input/Output
D
Input Bias Current ...1 pA
D
High Wide Bandwidth ...160 kHz
D
High Slew Rate ...0.1 V/µs
D
Supply Current ...7 µA (per channel)
D
Input Noise Voltage ...90 nV/√Hz
D
Supply Voltage Range ...2.7 V to 16 V
D
Specified Temperature Range
– –40°C to 125°C...Industrial Grade
D
Ultra-Small Packaging
– 5 Pin SOT-23 (TLV2381)
APPLICATIONS
D
Portable Medical
D
Power Monitoring
D
Low Power Security Detection Systems
D
Smoke Detectors
DESCRIPTION
The TLV238x single supply operational amplifiers
provide rail-to-rail input and output capability. The
TLV238x takes the minimum operating supply voltage
down to 2.7 V over the extended industrial temperature
range, while adding the rail-to-rail output swing feature.
The TLV238x also provides 160-kHz bandwidth from
only 7 µA. The maximum recommended supply voltage
is 16 V, which allows the devices to be operated from
(±8 V supplies down to ±1.35 V) two rechargeable cells.
The combination of rail-to-rail inputs and outputs make
them good upgrades for the TLC27Lx family—offering
more bandwidth at a lower quiescent current. The offset
voltage is lower than the TLC27LxA variant.
To maintain cost effectiveness the TLV2381/2 are only
available in the extended industrial temperature range.
This means that one device can be used in a wide range
of applications that include PDAs as well as automotive
sensor interface.
All members are available in SOIC, with the singles in
the small SOT-23 package, duals in the MSOP.
SELECTION GUIDE
DEVICE VS
[V] IQ/ch
[µA] VICR
[V] VIO
[mV] IIB
[pA] GBW
[MHz] SLEW RATE
[V/µs] Vn, 1 kHz
[nV/√Hz]
TLV238x 2.7 to 16 10 –0.2 to VS + 0.2 4.5 60 0.16 0.06 100
TLV27Lx 2.7 to 16 11 –0.2 to VS – 1.2 5 60 0.16 0.06 100
TLC27Lx 4 to 16 17 –0.2 to VS – 1.5 10/5/2 60 0.085 0.03 68
OPAx349 1.8 to 5.5 2–0.2 to VS + 0.2 10 10 0.070 0.02 300
OPAx347 2.3 to 5.5 34 –0.2 to VS + 0.2 6 10 0.35 0.01 60
TLC225x 2.7 to 16 62.5 0 to VS – 1.5 1.5/0.85 60 0.200 0.02 19
NOTE: All dc specs are maximums while ac specs are typicals.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2001–2003 Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
2www.ti.com
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE PACKAGE
CODE SYMBOL SPECIFIED
TEMPERATURE
RANGE ORDER NUMBER TRANSPORT MEDIA
TLV2381ID
SOIC-8
D
2381I
–40 C to 125 C
TLV2381ID Tube
TLV2381ID
SOIC-8
D
2381I
–40 C to 125 C
TLV2381IDR Tape and Reel
TLV2381IDBV
SOT-23
DBV
VBKI
–40°C to 125°C
TLV2381IDBVR
Tape and Reel
TLV2381IDBV
SOT-23
DBV
VBKI
–40°C to 125°C
TLV2381IDBVT
Tape and Reel
TLV2382ID
SOIC-8
D
2382I
TLV2382ID Tube
TLV2382ID
SOIC-8
D
2382I
TLV2382IDR Tape and Reel
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VS16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI (see Notes 1 and 2) VS + 0.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID VS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, TJ150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: I suffix –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. Relative to GND pin.
2. Maximum is 16.5 V or VS+0.2 V whichever is the lesser value.
DISSIPATION RATING TABLE
PACKAGE θJC
(°C/W) θJA
(°C/W) TA ≤ 25°C
POWER RATING TA = 85°C
POWER RATING
D (8) 38.3 176 710 mW 370 mW
DBV (5) 55 324.1 385 mW 201 mW
DBV (6) 55 294.3 425 mW 221 mW
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
3
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recommended operating conditions
MIN MAX UNIT
Supply voltage, (VS)
Dual supply ±1.35 ±8
V
Supply voltage, (VS)
Single supply 2.7 16
V
Input common-mode voltage range –0.2 VS+0.2 V
Operating free air temperature, TAI-suffix –40 125 °C
electrical characteristics at recommended operating conditions, VS = 2.7 V, 5 V, and 15 V (unless
otherwise noted)
dc performance
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
VIO
Input offset voltage
VIC = VS/2, VO = VS/2
25°C 0.5 4.5
mV
VIO
Input offset voltage
V
IC
= V
S
/2, V
O
= V
S
/2
RL = 100 kΩ R
S = 50 Ω
Full range 6.5
mV
αVIO Offset voltage drift
RL = 100 kΩ R
S = 50 Ω
25°C 1.1 µV/°C
CMRR
Common-mode rejection ratio
VIC = 0 V to VS,
V = 2.7 V
25°C 54 69
dB
CMRR
Common-mode rejection ratio
VIC = 0 V to VS,
RS = 50 Ω
VS = 2.7 V
Full range 53
dB
CMRR
Common-mode rejection ratio
VIC = 0 V to VS–1.3 V,
VS = 2.7 V
25°C 71 86
dB
CMRR
Common-mode rejection ratio
VIC = 0 V to VS–1.3 V,
RS = 50 ΩFull range 70
CMRR
Common-mode rejection ratio
VIC = 0 V to VS,
V = 5 V
25°C 58 74
dB
CMRR
Common-mode rejection ratio
VIC = 0 V to VS,
RS = 50 Ω
VS = 5 V
Full range 57
dB
CMRR
Common-mode rejection ratio
VIC = 0 V to VS–1.3 V,
VS = 5 V
25°C 72 88
dB
VIC = 0 V to VS–1.3 V,
RS = 50 ΩFull range 70
VIC = 0 V to VS,
V = 15 V
25°C 65 80
dB
VIC = 0 V to VS,
RS = 50 Ω
VS = 15 V
Full range 64
dB
VIC = 0 V to VS–1.3 V,
VS = 15 V
25°C 72 90
dB
VIC = 0 V to VS–1.3 V,
RS = 50 ΩFull range 70
A
Large-signal differential voltage
V =V /2,
VS = 2.7 V
25°C 80 100
dB
A
Large-signal differential voltage
V =V /2,
VS = 2.7 V
Full range 77
dB
AVD
Large-signal differential voltage
VO(PP)=VS/2,
VS = 5 V
25°C 80 100
dB
AVD
Large-signal differential voltage
amplification
VO(PP)=VS/2,
RL = 100 kΩ
VS = 5 V
Full range 77
dB
VS = 15 V
25°C 77 83
VS = 15 V
Full range 74
†Full range is –40°C to 125°C.
input characteristics
PARAMETER TEST CONDITIONS TAMIN TYP MAX UNIT
I
Input offset current
V = V /2, V = V /2,
≤25°C 1 60
pA
IIO
Input offset current
V = V /2, V = V /2,
≤70°C 100
pA
IO
VIC = VS/2, VO = VS/2,
≤125°C 1000
I
Input bias current
VIC = VS/2, VO = VS/2,
RL = 100 kΩ ,R
S = 50 Ω≤25°C 1 60
pA
IIB
Input bias current
≤70°C 200
pA
IB
≤125°C 1000
ri(d) Differential input resistance 25°C 1000 GΩ
CIC Common-mode input capacitance f = 1 kHz 25°C 8 pF
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
4www.ti.com
electrical characteristics at recommended operating conditions, VS = 2.7 V, 5 V, and 15 V (unless
otherwise noted) (continued)
power supply
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
IDD
Supply current (per channel)
VO = VS/2
25°C 7 10
µA
IDD
Supply current (per channel)
VO = VS/2
Full range 15 µ
A
PSRR
Power supply rejection ratio (∆VS/∆VIO)
VS = 2.7 V to 16V,
No load,
25°C 74 82
dB
PSRR
Power supply rejection ratio (∆VS/∆VIO)
VS = 2.7 V to 16V,
VIC = VS/2 V
No load,
Full range 70
dB
†Full range is –40°C to 125°C for I suffix.
output characteristics
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
V
Output voltage swing from rail
V = V /2,
VS = 2.7 V
25°C 200 160
mV
V
Output voltage swing from rail
V = V /2,
VS = 2.7 V
Full range 220
mV
V
Output voltage swing from rail
VIC = VS/2,
VS = 5 V
25°C 120 85
mV
V
Output voltage swing from rail
VIC = VS/2,
IO = 100 µA
VS = 5 V
Full range 200
mV
VO
Output voltage swing from rail
VS = 15 V
25°C 120 50
VO
Output voltage swing from rail
VS = 15 V
Full range 150
V = V /2,
VS = 5 V
25°C 800 420
mV
VIC = VS/2,
VS = 5 V
Full range 900
mV
VIC = VS/2,
IO = 500 µA
VS = 15 V
25°C 400 200
mV
VS = 15 V
Full range 500
IOOutput current VO = 0.5 V from rail VS = 2.7 V 25°C 400 µA
†Full range is –40°C to 125°C for I suffix.
dynamic performance
PARAMETER TEST CONDITIONS TAMIN TYP MAX UNIT
GBP Gain bandwidth product RL = 100 kΩ , CL = 10 pF, f = 1 kHz 25°C 160 kHz
SR
Slew rate at unity gain
VO(pp) = 2 V, RL = 100 kΩ
25°C 0.06
V/ s
SR
Slew rate at unity gain
V
O(pp)
= 2 V, R
L
= 100 k
Ω,
CL = 10 pF
–40°C 0.05
V/
µ
s
CL = 10 pF
125°C 0.08
φMPhase margin
RL = 100 kΩ, CL = 50 pF
25°C 62 °
Gain margin
RL = 100 kΩ, CL = 50 pF
25°C 6.7 dB
ts
Settling time (0.1%)
V(STEP)pp = 1 V, AV = –1,
Rise
25
°
C
31
µs
ts
Settling time (0.1%)
V(STEP)pp = 1 V, AV = –1,
CL = 10 pF, RL = 100 kΩFall
25°C
61 µ
s
noise/distortion performance
PARAMETER TEST CONDITIONS TAMIN TYP MAX UNIT
VnEquivalent input noise voltage f = 1 kHz 25°C 90 nV/√Hz
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
5
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input of fset voltage vs Common-mode input voltage 1, 2, 3
IIB/IIO Input bias and offset current vs Free-air temperature 4
VOH High-level output voltage vs High-level output current 5, 7, 9
VOL Low-level output voltage vs Low-level output current 6, 8, 10
IQ
Quiescent current
vs Supply voltage 11
IQ
Quiescent current
vs Free-air temperature 12
Supply voltage and supply current ramp up 13
AVD Differential voltage gain and phase shift vs Frequency 14
GBP Gain-bandwidth product vs Free-air temperature 15
φmPhase margin vs Load capacitance 16
CMRR Common-mode rejection ratio vs Frequency 17
PSRR Power supply rejection ratio vs Frequency 18
Input referred noise voltage vs Frequency 19
SR Slew rate vs Free-air temperature 20
VO(PP) Peak-to-peak output voltage vs Frequency 21
Inverting small-signal response 22
Inverting large-signal response 23
Crosstalk vs Frequency 24
Figure 1
–2000
–1500
–1000
–500
0
500
1000
1500
2000
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
– Input Offset Voltage –
VIO Aµ
VIC – Common-Mode Input Voltage – V
VS = 2.7 V
TA = 25°C
Figure 2
–2000
–1500
–1000
–500
0
500
1000
1500
2000
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
VIC – Common-Mode Input Voltage – V
– Input Offset Voltage –
VIO Aµ
VS = 5 V
TA = 25°C
Figure 3
–2000
–1500
–1000
–500
0
500
1000
1500
2000
–0.2 7.5 15.
2
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
VIC – Common-Mode Input Voltage – V
– Input Offset Voltage –
VIO Aµ
VS = 15 V
TA = 25°C
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
6www.ti.com
TYPICAL CHARACTERISTICS
Figure 4
– Input Bias and Input
INPUT BIAS AND INPUT
OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
IIB IIO
TA – Free-Air Temperature – °C
100
90
80
70
60
50
40
30
20
10
025 45 65 85 105 125
VDD± = ±2.5 V
VIC = 0
VO = 0
RS = 50 Ω
IIB
and
Offset Currents – pA
IIO
Figure 5
0
2.5
5
7.5
10
12.5
15
20024681012141618 2224
–40°C
0°C
25°C
70°C
125°C
VS = 15 V
IOH – High-Level Output Current – mA
– High-Level Output Voltage – V
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VOH
Figure 6
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0246810121416182
0
–40°C
0°C
25°C
125°C
VS = 15 V
70°C
IOL – Low-Level Output Current – mA
– Low-Level Output Voltage – V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VOL
Figure 7
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
–40°C
0°C
25°C
70°C
125°C
VS = 5 V
IOH – High-Level Output Current – mA
– High-Level Output Voltage – V
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VOH
Figure 8
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
–40°C
0°C
25°C
125°C
VS = 5 V
70°C
IOL – Low-Level Output Current – mA
– Low-Level Output Voltage – V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VOL
Figure 9
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
0 0.2 0.4 0.6 0.8 1 1.2 1.4
–40°C
0°C
25°C
70°C
125°C
VS = 2.7 V
IOH – High-Level Output Current – mA
– High-Level Output Voltage – V
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VOH
Figure 10
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
0 0.2 0.4 0.6 0.8 1 1.2 1.4
–40°C
0°C
25°C
125°C
VS = 2.7 V
70°C
IOL – Low-Level Output Current – mA
– Low-Level Output Voltage – V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VOL
Figure 11
0
1
2
3
4
5
6
7
8
0246810121416
VS – Supply Voltage – V
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
–40°C25°C
70°C
125°C
0°C
– Quiescent Currenr – AµI(Q)
Figure 12
0
1
2
3
4
5
6
7
8
–40 –25–10 5 20 35 50 65 80 95 110 125
16 V
5 V
2.7 V
TA – Free-Air Temperature – °C
– Quiescent Currenr –
QUIESCENT CURRENT
vs
FREE-AIR TEMPERATURE
AµI(Q)
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
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TYPICAL CHARACTERISTICS
Figure 13
0
5
10
15
0 5 10 15 20 25 300
5
10
15
40
t – Time – ms
– Supply Voltage – V/dc
SUPPLY VOLTAGE AND
SUPPLY CURRENT RAMP UP
– Supply Current –
VS
Aµ
ICC
VS
VO
IQ
VS = 0 to 15 V,
RL = 100 Ω,
CL = 10 pF,
TA = 25°C
Figure 14
–20
0
20
40
60
80
100
120
0.1 1 10 100 1 k 10 k 100 k 1 M
0°
30°
60°
90°
120°
150°
180°
VS = 5 V
RL = 100 kΩ
CL = 10 pF
TA = 25°C
f – Frequency – Hz
– Differential Voltage Gain – dB
DIFFERENTIAL VOLTAGE GAIN
AND PHASE SHIFT
vs
FREQUENCY
Phase Shift
AVD
Figure 15
100
110
120
130
140
150
160
170
–40 –25 –10 5 20 35 50 65 80 95 110 125
TA – Free-Air Temperature – °C
GBP – Gain-Bandwidth Product – kHz
GAIN-BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
VS = 2.7 V
VS = 5 V VS = 15 V
Figure 16
0
10
20
30
40
50
60
70
80
10 100 1000
CL – Load Capacitance – pF
Phase Margin – Degrees
PHASE MARGIN
vs
LOAD CAPACITANCE
VS = 5 V
RL = 100 kΩ
TA = 25°C
Figure 17
0
10
20
30
40
50
60
70
80
90
100
110
120
10 100 1 k 10 k 100 k 1 M
VS = 5 V
TA = 25°C
f – Frequency – Hz
CMRR – Common-Mode Rejection Ratio – dB
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
Figure 18
0
10
20
30
40
50
60
70
80
90
100
10 100 1 k 10 k 100 k 1 M
VS =±2.5 V
TA = 25°C
f – Frequency – Hz
PSRR – Power Supply Rejection Ratio – dB
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
Figure 19
0
50
100
150
200
250
1 10 100 1 k 10 k 100 k
VS = 5 V,
G = 2,
RF = 100 kΩ
f – Frequency – Hz
– Input Referred Noise Voltage –
INPUT REFERRED NOISE VOLTAGE
vs
FREQUENCY
nV/ Hz
Vn
Figure 20
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
–40 –25 –10 5 20 35 50 65 80 95 110 125
TA – Free-air Temperature – °C
SR – Slew Rate –
SLEW RATE
vs
FREE-AIR TEMPERATURE
s
µ
V/
SR+
SR–
VS = 5 V
Gain = 1
VO = 1
RL = 100 kΩ
CL = 50 pF
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
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TYPICAL CHARACTERISTICS
Figure 21
0
2
4
6
8
10
12
14
16
10 100 1000 1 k 10 k
VOPP
f – Frequency – Hz
– Output Voltage Peak-to-Peak – V
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
VS = 15 V
VS = 5 V
VS = 2.7 V
RL = 100 kΩ,
CL = 10 pF,
THD+N <= 5%
Figure 22
–2
–1.5
–1
–0.5
0
0.5
1
1.5
2
–100 0 100 200 300 400 500 600 700
VI = 3 VPP
VO = 3 VPP
t – Time – µs
Amplitude –
INVERTING SMALL-SIGNAL
RESPONSE
VPP
Gain = –1,
RL = 100 kΩ,
CL = 10 pF,
VS = 5 V,
VO = 3 VPP,
f = 1 kHz
Figure 23
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
–100 0 100 200 300 400 500 600 700
VI = 100 mVPP
VO = 100 mVPP
t – Time – µs
Amplitude –
INVERTING LARGE-SIGNAL
RESPONSE
VPP
Gain = –1,
RL = 100 kΩ,
CL = 10 pF,
VS = 5 V,
VO = 100 mVPP,
f = 1 kHz
Figure 24
–140
–120
–100
–80
–60
–40
–20
0
10 100 1 k 10 k 100 k
VS = 5 V
RL = 2 kΩ
CL = 10 pF
TA = 25°C
Channel 1 to 2
f – Frequency – Hz
Crosstalk – dB
CROSSTALK
vs
FREQUENCY
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SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
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APPLICATION INFORMATION
offset voltage
The output offset voltage (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times the
corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
VOO
+
VIO
ǒ
1
)ǒ
RF
RG
ǓǓ"
IIB
)
RS
ǒ
1
)ǒ
RF
RG
ǓǓ"
IIB– RF
+
–
VI+
RG
RS
RF
IIB–
VO
IIB+
Figure 25. Output Offset Voltage Model
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The
simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 26).
VIVO
C1
+
–
RGRF
R1
f–3dB
+
1
2
p
R1C1
VO
VI
+ǒ
1
)
RF
RG
Ǔǒ
1
1
)
sR1C1
Ǔ
VDD/2
Figure 26. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task.
For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure
to do this can result in phase shift of the amplifier.
VI
C2
R2R1
C1
RF
RG
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
(
=1
Q
2 – )
RGRF
_
+f–3dB
+
1
2
p
RC
VDD/2
Figure 27. 2-Pole Low-Pass Sallen-Key Filter
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
10 www.ti.com
APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high performance of the TLV238x, follow proper printed-circuit board design techniques. A
general set of guidelines is given in the following.
D
Ground planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D
Proper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D
Sockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
D
Short trace runs/compact part placements—Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier . Its length should be kept as short as possible. This will help to minimize stray capacitance at
the input of the amplifier.
D
Surface-mount passive components—Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
11
www.ti.com
APPLICATION INFORMATION
general power dissipation considerations
For a given θJA, the maximum power dissipation is shown in Figure 28 and is calculated by the following formula:
PD
+ǒ
TMAX–TA
q
JA
Ǔ
Where: PD= Maximum power dissipation of TLV238x IC (watts)
TMAX= Absolute maximum junction temperature (150°C)
TA= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
1
0.75
0.5
0
–55–40 –25 –10 5
Maximum Power Dissipation – W
1.25
1.5
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
1.75
20 35 50
0.25
TA – Free-Air Temperature – °C
2
65 80 95 110 125
MSOP Package
Low-K Test PCB
θJA = 260°C/W
TJ = 150°C
PDIP Package
Low-K Test PCB
θJA = 104°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
SOT -23 Package
Low-K Test PCB
θJA = 324°C/W
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 28. Maximum Power Dissipation vs Free-Air Temperature
3
2
4
5
(TOP VIEW)
1
OUT
GND
IN+
VDD
IN–
TLV2381
DBV PACKAGE
1
2
3
4
8
7
6
5
NC
IN–
IN+
GND
NC
VDD
OUT
NC
TLV2381
D PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN–
1IN+
GND
VDD
2OUT
2IN–
2IN+
TLV2382
D PACKAGE
(TOP VIEW)
NC – No internal connection
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLV2381ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2381IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2381IDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2381IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2381IDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2381IDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2381IDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2381IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2381IP PREVIEW PDIP P 8 TBD Call TI Call TI
TLV2382ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2382IDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2382IDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2382IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2382IP OBSOLETE PDIP P 8 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
PACKAGE OPTION ADDENDUM
www.ti.com 11-Dec-2006
Addendum-Page 1
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Dec-2006
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV2381IDBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TLV2381IDBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TLV2381IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV2382IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV2381IDBVR SOT-23 DBV 5 3000 182.0 182.0 20.0
TLV2381IDBVT SOT-23 DBV 5 250 182.0 182.0 20.0
TLV2381IDR SOIC D 8 2500 340.5 338.1 20.6
TLV2382IDR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 2
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