Single Ended Input To Differential
Output Operation
In many applications, it is required to drive a differential input
ADC from a single ended source. Traditionally, transformers
have been used to provide single to differential conversion,
but these are inherently bandpass by nature and cannot be
used for DC coupled applications. The LMH6554 provides
excellent performance as a single-ended input to differential
output converter down to DC. Figure 3 shows a typical appli-
cation circuit where an LMH6554 is used to produce a bal-
anced differential output signal from a single ended source.
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FIGURE 3. Single Ended Input with Differential Output
When using the LMH6554 in single-to-differential mode, the
complimentary output is forced to a phase inverted replica of
the driven output by the common mode feedback circuit as
opposed to being driven by its own complimentary input. Con-
sequently, as the driven input changes, the common mode
feedback action results in a varying common mode voltage at
the amplifier's inputs, proportional to the driving signal. Due
to the non-ideal common mode rejection of the amplifier's in-
put stage, a small common mode signal appears at the out-
puts which is superimposed on the differential output signal.
The ratio of the change in output common mode voltage to
output differential voltage is commonly referred to as output
balance error. The output balance error response of the
LMH6554 over frequency is shown in the Typical Perfor-
mance Characteristics section.
To match the input impedance of the circuit in Figure 3 to a
specified source resistance, RS, requries that RT || RIN = RS.
The equations governing RIN and AV for single-to-differential
operation are also provide in Figure 3. These equations, along
with the source matching condition, must be solved iteratively
to achieve the desired gain with the proper input termination.
Component values for several common gain configuration in
a 50Ω environment are given in Table 1.
Table 1. Gain Component Values for 50Ω System
Gain RFRGRTRM
0dB 200Ω 191Ω 62Ω 27.7Ω
6dB 200Ω 91Ω 76.8Ω 30.3Ω
12dB 200Ω 35.7Ω 147Ω 37.3Ω
Single Supply Operation
Single 5V supply operation is possible: however, as dis-
cussed earlier, AC input coupling is recommended due to
input common mode limitations. An example of an AC cou-
pled, single supply, single-to-differential circuit is shown in
Figure 4. Note that when AC coupling, both inputs need to be
AC coupled irrespective of single-to-differential or differential-
differential configuration. For higher supply voltages DC cou-
pling of the inputs may be possible provided that the output
common mode DC level is set high enough so that the
amplifier's inputs and outputs are within their specified oper-
ation ranges.
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FIGURE 4. AC Coupled for Single Supply Operation
Split Supply Operation
For optimum performance, split supply operation is recom-
mended using +2.5V and −2.5V supplies; however, operation
is possible on split supplies as low as +2.35V and −2.35V and
as high as +2.65V and −2.65V. Provided the total supply volt-
age does not exceed the 4.7V to 5.3V operating specification,
non-symmetric supply operation is also possible and in some
cases advantageous. For example, if a 5V DC coupled oper-
ation is required for low power dissipation but the amplifier
input common mode range prevents this operation, it is still
possible with split supplies of (V+) and (V-). Where (V+)-(V-)
= 5V and V+ and V- are selected to center the amplifier input
common mode range to suit the application.
Driving Analog To Digital
Converters
Analog-to-digital converters present challenging load condi-
tions. They typically have high impedance inputs with large
and often variable capacitive components. Figure 6 shows the
LMH6554 driving an ultra-high-speed Gigasample ADC the
ADC10D1500. The LMH6554 common mode voltage is set
by the ADC10D1500. The circuit in Figure 6 has a 2nd order
bandpass LC filter across the differential inputs of the AD-
C10D1500. The ADC10D1500 is a dual channel 10–bit ADC
with maximum sampling rate of 3 GSPS when operating in a
single channel mode and 1.5 GSPS in dual channel mode.
Figure 5 shows the SFDR and SNR performance vs. frequen-
cy for the LMH6554 and ADC10D1500 combination circuit
with the ADC input signal level at −1dBFS. In order to properly
match the input impedance seen at the LMH6554 amplifier
inputs, RM is chosen to match ZS || RT for proper input bal-
ance. The amplifier is configured to provide a gain of 2 V/V in
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LMH6554