ADSP2185NKSTZ320 - ANALOG DEVICES

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SHARC Processor

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E Document Feedback

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FEATURES

High performance 32-bit/40-bit floating-point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory—5 Mbits on-chip RAM, 4 Mbits on-chip

ROM

Up to 450 MHz operating frequency

Code compatible with all other members of the SHARC family

The ADSP-2148x processors are available with unique audio-

centric peripherals, such as the digital applications

interface, serial ports, precision clock generators, S/PDIF

transceiver, asynchronous sample rate converters, input

data port, and more

For complete ordering information, see Ordering Guide on

Page 66

Qualified for automotive applications

Figure 1. Functional Block Diagram

Internal Memory I/F

Block 0

RAM/ROM

B0D

64-BIT

Instruction

Cache

5 Stage

Sequencer

PEx PEy

PMD

64-BIT IOD0 32-BIT

EPD BUS 64-BIT

Core Bus

Cross Bar

DAI Routing/Pins

S/PDIF

Tx/Rx

PCG

DPI Routing/Pins

SPI/B UART

Block 1

RAM/ROM

Block 2

RAM

Block 3

RAM

AMI SDRAM

CTL

External Port Pin MUX

TIMER

SPORT

ASRC

PWM

DAG1/2 Core

Timer

PDAP/

IDP

TWI

IOD0 BUS DTCP/

MTM

PCG

PERIPHERAL BUS

32-BIT

CORE

FLAGS/

PWM3

JTAG

Internal Memory

DMD

64-BIT

PMD 64-BIT

CORE

FLAGS

IOD1

32-BIT

PERIPHERAL BUS

B1D

64-BIT

B2D

64-BIT

B3D

64-BIT

DPI Peripherals DAI Peripherals Peripherals External

Port

SIMD Core

THERMAL

DIODE

FFT

FIR

IIR

SPEP BUS

DMD

64-BIT

FLAGx/IRQx/

TMREXP

WDT

Rev. E | Page 2 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

TABLE OF CONTENTS

Features ................................................................. 1

Table of Contents ..................................................... 2

Revision History ...................................................... 2

General Description ................................................. 3

Family Core Architecture ........................................ 4

Family Peripheral Architecture ................................ 7

I/O Processor Features ......................................... 10

System Design .................................................... 11

Development Tools ............................................. 12

Additional Information ........................................ 13

Related Signal Chains .......................................... 13

Pin Function Descriptions ....................................... 14

Specifications ........................................................ 18

Operating Conditions .......................................... 18

Electrical Characteristics ....................................... 19

Absolute Maximum Ratings .................................. 21

ESD Sensitivity ................................................... 21

Maximum Power Dissipation ................................. 21

Package Information ............................................ 21

Timing Specifications ........................................... 22

Output Drive Currents ......................................... 55

Test Conditions .................................................. 55

Capacitive Loading .............................................. 55

Thermal Characteristics ........................................ 56

100-LQFP_EP Lead Assignment ................................ 58

176-Lead LQFP_EP Lead Assignment ......................... 60

Outline Dimensions ................................................ 64

Surface-Mount Design .......................................... 65

Automotive Products ........................................... 66

Ordering Guide .................................................. 66

REVISION HISTORY

6/2017—Rev. D to Rev. E

Added 266 MHz, Automotive Use Only Parameter Heading,

and Endnote 5 to Operating Conditions ....................... 18

Added 266 MHz to Electrical Characteristics ................. 19

Added 266 MHz Column to Clock Input ...................... 24

Changes to the Legend of Table 32 in AMI Read ............. 33

Changes to Ordering Guide ....................................... 66

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 3 of 68 | June 2017

GENERAL DESCRIPTION

The ADSP-2148x SHARC

processors are members of the

SIMD SHARC family of DSPs that feature Analog Devices’

Super Harvard Architecture. The processors are source code

compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x,

ADSP-2146x, ADSP-2147x and ADSP-2116x DSPs, as well as

with first generation ADSP-2106x SHARC processors in SISD

(single-instruction, single-data) mode. The ADSP-2148x pro-

cessors are 32-bit/40-bit floating point processors optimized for

high performance audio applications with large on-chip SRAM,

multiple internal buses to eliminate I/O bottlenecks, and an

innovative digital applications interface (DAI).

Table 1 shows performance benchmarks for the ADSP-2148x

processors. Table 2 shows the features of the individual product

offerings.

Table 1. Processor Benchmarks

Benchmark Algorithm

Speed

(at 400 MHz)

Speed

(at 450 MHz)

1024 Point Complex FFT

(Radix 4, with Reversal)

23 s 20.44 s

FIR Filter (per Tap)

1.25 ns 1.1 ns

IIR Filter (per Biquad)

5 ns 4.43 ns

Matrix Multiply (Pipelined)

[3 × 3] × [3 × 1]

[4 × 4] × [4 × 1]

11.25 ns

20 ns

10.0 ns

17.78 ns

Divide (y/×) 7.5 ns 6.67 ns

Inverse Square Root 11.25 ns 10.0 ns

Assumes two files in multichannel SIMD mode

Table 2. ADSP-2148x Family Features

Feature ADSP-21483 ADSP-21486 ADSP-21487 ADSP-21488 ADSP-21489

Maximum Instruction Rate 400 MHz 400 MHz 450 MHz 400 MHz 450 MHz

RAM 3 Mbits 5 Mbits 2/3 Mbits

5 Mbits

ROM 4 Mbits No

Audio Decoders in ROM

Yes No

Pulse-Width Modulation 4 Units (3 Units on 100-Lead Packages)

DTCP Hardware Accelerator Contact Analog Devices

External Port Interface (SDRAM, AMI)

Yes (16-bit) AMI Only Yes (16-bit)

Serial Ports 8

Direct DMA from SPORTs to External Port

(External Memory)

Yes

FIR, IIR, FFT Accelerator Yes

Watchdog Timer Yes (176-Lead Package Only)

MediaLB Interface Automotive Models Only

IDP/PDAP Yes

UART 1

DAI (SRU)/DPI (SRU2) Yes

S/PDIF Transceiver Yes

SPI Yes

TWI 1

SRC Performance

–128 dB

Thermal Diode Yes

VISA Support Yes

Package

176-Lead LQFP EPAD

100-Lead LQFP EPAD

176-Lead LQFP

EPAD

176-Lead LQFP EPAD

100-Lead LQFP EPAD

See Ordering Guide on Page 66.

ROM is factory programmed with latest multichannel audio decoding and post-processing algorithms from Dolby

Labs and DTS

. Decoder/post-processor algorithm

combination support varies depending upon the chip version and the system configurations. Please visit www.analog.com for complete information.

The 100-lead packages do not contain an external port. The SDRAM controller pins must be disabled when using this package. For more information, see Pin Function

Descriptions on Page 14. The ADSP-21486 processor in the 176-lead package also does not contain a SDRAM controller. For more information, see 176-Lead LQFP_EP

Lead Assignment on page 60.

Some models have –140 dB performance. For more information, see Ordering Guide on page 66.

Only available up to 400 MHz. See Ordering Guide on Page 66 for details.

Rev. E | Page 4 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

The diagram on Page 1 shows the two clock domains that make

up the ADSP-2148x processors. The core clock domain contains

the following features:

• Two processing elements (PEx, PEy), each of which com-

prises an ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting 2x64-bit data

transfers between memory and the core at every core pro-

cessor cycle

• One periodic interval timer with pinout

• On-chip SRAM (5 Mbit) and mask-programmable ROM

(4 Mbit)

• JTAG test access port for emulation and boundary scan.

The JTAG provides software debug through user break-

points which allows flexible exception handling.

The block diagram of the ADSP-2148x on Page 1 also shows the

peripheral clock domain (also known as the I/O processor)

which contains the following features:

•IOD0 (peripheral DMA) and IOD1 (external port DMA)

buses for 32-bit data transfers

• Peripheral and external port buses for core connection

• External port with an AMI and SDRAM controller

•4 units for PWM control

• 1 memory-to-memory (MTM) unit for internal-to-internal

memory transfers

• Digital applications interface that includes four precision

clock generators (PCG), an input data port (IDP/PDAP)

for serial and parallel interconnects, an S/PDIF

receiver/transmitter, four asynchronous sample rate con-

verters, eight serial ports, and a flexible signal routing unit

(DAI SRU).

• Digital peripheral interface that includes two timers, a

2-wire interface (TWI), one UART, two serial peripheral

interfaces (SPI), 2 precision clock generators (PCG), pulse

width modulation (PWM), and a flexible signal routing

unit (DPI SRU2).

As shown in the SHARC core block diagram on Page 5, the

processor uses two computational units to deliver a significant

performance increase over the previous SHARC processors on a

range of DSP algorithms. With its SIMD computational hard-

ware, the processors can perform 2.7 GFLOPS running at

450 MHz.

FAMILY CORE ARCHITECTURE

The ADSP-2148x is code compatible at the assembly level with

the ADSP-2147x, ADSP-2146x, ADSP-2137x, ADSP-2136x,

ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first

generation ADSP-2106x SHARC processors. The ADSP-2148x

shares architectural features with the ADSP-2126x, ADSP-

2136x, ADSP-2137x, ADSP-2146x and ADSP-2116x SIMD

SHARC processors, as shown in Figure 2 and detailed in the fol-

lowing sections.

SIMD Computational Engine

The ADSP-2148x contains two computational processing ele-

ments that operate as a single-instruction, multiple-data

(SIMD) engine. The processing elements are referred to as PEX

and PEY and each contains an ALU, multiplier, shifter, and reg-

ister file. PEx is always active, and PEy may be enabled by

setting the PEYEN mode bit in the MODE1 register. SIMD

mode allows the processor to execute the same instruction in

both processing elements, but each processing element operates

on different data. This architecture is efficient at executing math

intensive DSP algorithms.

SIMD mode also affects the way data is transferred between

memory and the processing elements because twice the data

bandwidth is required to sustain computational operation in the

processing elements. Therefore, entering SIMD mode also dou-

bles the bandwidth between memory and the processing

elements. When using the DAGs to transfer data in SIMD

mode, two data values are transferred with each memory or reg-

ister file access.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle and are arranged in parallel, maximizing

computational throughput. Single multifunction instructions

execute parallel ALU and multiplier operations. In SIMD mode,

the parallel ALU and multiplier operations occur in both pro-

cessing elements. These computation units support IEEE 32-bit

single-precision floating-point, 40-bit extended precision float-

ing-point, and 32-bit fixed-point data formats.

Timer

The processor contains a core timer that can generate periodic

software interrupts. The core timer can be configured to use

FLAG3 as a timer expired signal.

Data Register File

Each processing element contains a general-purpose data regis-

ter file. The register files transfer data between the computation

units and the data buses, and store intermediate results. These

10-port, 32-register (16 primary, 16 secondary) register files,

combined with the processor’s enhanced Harvard architecture,

allow unconstrained data flow between computation units and

internal memory. The registers in PEX are referred to as

R0–R15 and in PEY as S0–S15.

Context Switch

Many of the processor’s registers have secondary registers that

can be activated during interrupt servicing for a fast context

switch. The data registers in the register file, the DAG registers,

and the multiplier result registers all have secondary registers.

The primary registers are active at reset, while the secondary

registers are activated by control bits in a mode control register.

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 5 of 68 | June 2017

Universal Registers

These registers can be used for general-purpose tasks. The

USTAT (4) registers allow easy bit manipulations (Set, Clear,

Toggle, Test, XOR) for all peripheral registers (control/status).

The data bus exchange register (PX) permits data to be passed

between the 64-bit PM data bus and the 64-bit DM data bus, or

between the 40-bit register file and the PM/DM data bus. These

registers contain hardware to handle the data width difference.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-2148x features an enhanced Harvard architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data.

With the its separate program and data memory buses and on-

chip instruction cache, the processor can simultaneously fetch

four operands (two over each data bus) and one instruction

(from the cache), all in a single cycle.

Instruction Cache

The processor includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache allows full speed execution of core, looped operations

such as digital filter multiply-accumulates, and FFT butterfly

processing.

Data Address Generators With Zero-Overhead Hardware

Circular Buffer Support

The two data address generators (DAGs) are used for indirect

addressing and implementing circular data buffers in hardware.

Circular buffers allow efficient programming of delay lines and

other data structures required in digital signal processing, and

are commonly used in digital filters and Fourier transforms.

The two DAGs contain sufficient registers to allow the creation

of up to 32 circular buffers (16 primary register sets, 16 second-

ary). The DAGs automatically handle address pointer

wraparound, reduce overhead, increase performance, and sim-

plify implementation. Circular buffers can start and end at any

memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the

processor can conditionally execute a multiply, an add, and a

Figure 2. SHARC Core Block Diagram

SIMD Core CACHEINTERRUPT

5 STAGE

PROGRAM SEQUENCER

PM ADDRESS 32

DM ADDRESS 32

DM DATA 64

PM DATA 64

DAG1

16x32

MRF

80-BIT

ALU

MULTIPLIER SHIFTER

Rx/Fx

PEx

16x40-BIT

JTAG

DMD/PMD 64

PM DATA 48

ASTATx

STYKx

ASTATy

STYKy

TIMER

Sx/SFx

PEy

16x40-BIT

MRB

80-BIT

MSB

80-BIT

MSF

80-BIT

FLAG

SYSTEM

I/F

USTAT

4x32-BIT

64-BIT

DAG2

16x32

MULTIPLIER

DATA

SWAP

PM ADDRESS 24

ALU SHIFTER

Rev. E | Page 6 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

subtract in both processing elements while branching and fetch-

ing up to four 32-bit values from memory, all in a single

instruction.

Variable Instruction Set Architecture (VISA)

In addition to supporting the standard 48-bit instructions from

previous SHARC processors, the ADSP-2148x supports new

instructions of 16 and 32 bits. This feature, called Variable

Instruction Set Architecture (VISA), drops redundant/unused

bits within the 48-bit instruction to create more efficient and

compact code. The program sequencer supports fetching these

16-bit and 32-bit instructions from both internal and external

SDRAM memory. This support is not extended to the

asynchronous memory interface (AMI). Source modules need

to be built using the VISA option, in order to allow code genera-

tion tools to create these more efficient opcodes.

On-Chip Memory

The ADSP-21483 and the ADSP-21488 processors contain

3 Mbits of internal RAM (Table 3) and the ADSP-21486,

ADSP-21487, and ADSP-21489 processors contain 5 Mbits of

internal RAM (Table 4). Each memory block supports single-

cycle, independent accesses by the core processor and I/O

processor.

The processor’s SRAM can be configured as a maximum of

160k words of 32-bit data, 320k words of 16-bit data, 106.7k

words of 48-bit instructions (or 40-bit data), or combinations of

different word sizes up to 5 megabits. All of the memory can be

accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit

floating-point storage format is supported that effectively dou-

bles the amount of data that may be stored on-chip. Conversion

between the 32-bit floating-point and 16-bit floating-point

formats is performed in a single instruction. While each mem-

ory block can store combinations of code and data, accesses are

most efficient when one block stores data using the DM bus for

transfers, and the other block stores instructions and data using

the PM bus for transfers.

Using the DM bus and PM buses, with one bus dedicated to a

memory block, assures single-cycle execution with two data

transfers. In this case, the instruction must be available in the

cache.

The memory maps in Table 3 and Table 4 display the internal

memory address space of the processors. The 48-bit space sec-

tion describes what this address range looks like to an

Table 3. Internal Memory Space (3 MBits—ADSP-21483/ADSP-21488)

IOP Registers 0x0000 0000–0x0003 FFFF

Long Word (64 Bits)

Extended Precision Normal or

Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

Block 0 ROM (Reserved)

0x0004 0000–0x0004 7FFF

Block 0 ROM (Reserved)

0x0008 0000–0x0008 AAA9

Block 0 ROM (Reserved)

0x0008 0000–0x0008 FFFF

Block 0 ROM (Reserved)

0x0010 0000–0x0011 FFFF

Reserved

0x0004 8000–0x0004 8FFF

Reserved

0x0008 AAAA–0x0008 BFFF

Reserved

0x0009 0000–0x0009 1FFF

Reserved

0x0012 0000–0x0012 3FFF

Block 0 SRAM

0x0004 9000–0x0004 CFFF

Block 0 SRAM

0x0008 C000–0x0009 1554

Block 0 SRAM

0x0009 2000–0x0009 9FFF

Block 0 SRAM

0x0012 4000–0x0013 3FFF

Reserved

0x0004 D000–0x0004 FFFF

Reserved

0x0009 1555–0x0009 FFFF

Reserved

0x0009 A000–0x0009 FFFF

Reserved

0x0013 4000–0x0013 FFFF

Block 1 ROM (Reserved)

0x0005 0000–0x0005 7FFF

Block 1 ROM (Reserved)

0x000A 0000–0x000A AAA9

Block 1 ROM (Reserved)

0x000A 0000–0x000A FFFF

Block 1 ROM (Reserved)

0x0014 0000–0x0015 FFFF

Reserved

0x0005 8000–0x0005 8FFF

Reserved

0x000A AAAA–0x000A BFFF

Reserved

0x000B 0000–0x000B 1FFF

Reserved

0x0016 0000–0x0016 3FFF

Block 1 SRAM

0x0005 9000–0x0005 CFFF

Block 1 SRAM

0x000A C000–0x000B 1554

Block 1 SRAM

0x000B 2000–0x000B 9FFF

Block 1 SRAM

0x0016 4000–0x0017 3FFF

Reserved

0x0005 D000–0x0005 FFFF

Reserved

0x000B 1555–0x000B FFFF

Reserved

0x000B A000–0x000B FFFF

Reserved

0x0017 4000–0x0017 FFFF

Block 2 SRAM

0x0006 0000–0x0006 1FFF

Block 2 SRAM

0x000C 0000–0x000C 2AA9

Block 2 SRAM

0x000C 0000–0x000C 3FFF

Block 2 SRAM

0x0018 0000–0x0018 7FFF

Reserved

0x0006 2000– 0x0006 FFFF

Reserved

0x000C 2AAA–0x000D FFFF

Reserved

0x000C 4000–0x000D FFFF

Reserved

0x0018 8000–0x001B FFFF

Block 3 SRAM

0x0007 0000–0x0007 1FFF

Block 3 SRAM

0x000E 0000–0x000E 2AA9

Block 3 SRAM

0x000E 0000–0x000E 3FFF

Block 3 SRAM

0x001C 0000–0x001C 7FFF

Reserved

0x0007 2000–0x0007 FFFF

Reserved

0x000E 2AAA–0x000F FFFF

Reserved

0x000E 4000–0x000F FFFF

Reserved

0x001C 8000–0x001F FFFF

Some ADSP-2148x processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Please contact your Analog

Devices sales representative for additional details.

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 7 of 68 | June 2017

instruction that retrieves 48-bit memory. The 32-bit section

describes what this address range looks like to an instruction

that retrieves 32-bit memory.

ROM Based Security

The ADSP-2148x has a ROM security feature that provides

hardware support for securing user software code by preventing

unauthorized reading from the internal code. When using this

feature, the processor does not boot-load any external code, exe-

cuting exclusively from internal ROM. Additionally, the

processor is not freely accessible via the JTAG port. Instead, a

unique 64-bit key, which must be scanned in through the JTAG

or Test Access Port will be assigned to each customer. The

device will ignore a wrong key. Emulation features are available

after the correct key is scanned.

On-Chip Memory Bandwidth

The internal memory architecture allows programs to have four

accesses at the same time to any of the four blocks (assuming

there are no block conflicts). The total bandwidth is realized

using the DMD and PMD buses (2 × 64-bits, CCLK speed) and

the IOD0/1 buses (2 × 32-bit, PCLK speed).

FAMILY PERIPHERAL ARCHITECTURE

The ADSP-2148x family contains a rich set of peripherals that

support a wide variety of applications including high quality

audio, medical imaging, communications, military, test equip-

ment, 3D graphics, speech recognition, motor control, imaging,

and other applications.

External Memory

The external port interface supports access to the external mem-

ory through core and DMA accesses. The external memory

address space is divided into four banks. Any bank can be pro-

grammed as either asynchronous or synchronous memory. The

external ports are comprised of the following modules.

• An Asynchronous Memory Interface which communicates

with SRAM, FLASH, and other devices that meet the stan-

dard asynchronous SRAM access protocol. The AMI

supports 6M words of external memory in bank 0 and 8M

words of external memory in bank 1, bank 2, and bank 3.

• A SDRAM controller that supports a glueless interface with

any of the standard SDRAMs. The SDC supports 62M

words of external memory in bank 0, and 64M words of

external memory in bank 1, bank 2, and bank 3. NOTE:

This feature is not available on the ADSP-21486 product.

Table 4. Internal Memory Space (5 MBits—ADSP-21486/ADSP-21487/ADSP-21489)

IOP Registers 0x0000 0000–0x0003 FFFF

Long Word (64 Bits)

Extended Precision Normal or

Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

Block 0 ROM (Reserved)

0x0004 0000–0x0004 7FFF

Block 0 ROM (Reserved)

0x0008 0000–0x0008 AAA9

Block 0 ROM (Reserved)

0x0008 0000–0x0008 FFFF

Block 0 ROM (Reserved)

0x0010 0000–0x0011 FFFF

Reserved

0x0004 8000–0x0004 8FFF

Reserved

0x0008 AAAA–0x0008 BFFF

Reserved

0x0009 0000–0x0009 1FFF

Reserved

0x0012 0000–0x0012 3FFF

Block 0 SRAM

0x0004 9000–0x0004 EFFF

Block 0 SRAM

0x0008 C000–0x0009 3FFF

Block 0 SRAM

0x0009 2000–0x0009 DFFF

Block 0 SRAM

0x0012 4000–0x0013 BFFF

Reserved

0x0004 F000–0x0004 FFFF

Reserved

0x0009 4000–0x0009 FFFF

Reserved

0x0009 E000–0x0009 FFFF

Reserved

0x0013 C000–0x0013 FFFF

Block 1 ROM (Reserved)

0x0005 0000–0x0005 7FFF

Block 1 ROM (Reserved)

0x000A 0000–0x000A AAA9

Block 1 ROM (Reserved)

0x000A 0000–0x000A FFFF

Block 1 ROM (Reserved)

0x0014 0000–0x0015 FFFF

Reserved

0x0005 8000–0x0005 8FFF

Reserved

0x000A AAAA–0x000A BFFF

Reserved

0x000B 0000–0x000B 1FFF

Reserved

0x0016 0000–0x0016 3FFF

Block 1 SRAM

0x0005 9000–0x0005 EFFF

Block 1 SRAM

0x000A C000–0x000B 3FFF

Block 1 SRAM

0x000B 2000–0x000B DFFF

Block 1 SRAM

0x0016 4000–0x0017 BFFF

Reserved

0x0005 F000–0x0005 FFFF

Reserved

0x000B 4000–0x000B FFFF

Reserved

0x000B E000–0x000B FFFF

Reserved

0x0017 C000–0x0017 FFFF

Block 2 SRAM

0x0006 0000–0x0006 3FFF

Block 2 SRAM

0x000C 0000–0x000C 5554

Block 2 SRAM

0x000C 0000–0x000C 7FFF

Block 2 SRAM

0x0018 0000–0x0018 FFFF

Reserved

0x0006 4000– 0x0006 FFFF

Reserved

0x000C 5555–0x000D FFFF

Reserved

0x000C 8000–0x000D FFFF

Reserved

0x0019 0000–0x001B FFFF

Block 3 SRAM

0x0007 0000–0x0007 3FFF

Block 3 SRAM

0x000E 0000–0x000E 5554

Block 3 SRAM

0x000E 0000–0x000E 7FFF

Block 3 SRAM

0x001C 0000–0x001C FFFF

Reserved

0x0007 4000–0x0007 FFFF

Reserved

0x000E 5555–0x0000F FFFF

Reserved

0x000E 8000–0x000F FFFF

Reserved

0x001D 0000–0x001F FFFF

Some ADSP-2148x processors include a customer-definable ROM block and are not reserved as shown on this table. Please contact your Analog Devices sales representative

for additional details.

Rev. E | Page 8 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

• Arbitration logic to coordinate core and DMA transfers

between internal and external memory over the external

port.

Non-SDRAM external memory address space is shown in

Table 5.

External Port

The external port provides a high performance, glueless inter-

face to a wide variety of industry-standard memory devices. The

external port, available on the 176-lead LQFP, may be used to

interface to synchronous and/or asynchronous memory devices

through the use of its separate internal memory controllers. The

first is an SDRAM controller for connection of industry-stan-

dard synchronous DRAM devices while the second is an

asynchronous memory controller intended to interface to a

variety of memory devices. Four memory select pins enable up

to four separate devices to coexist, supporting any desired com-

bination of synchronous and asynchronous device types.

Asynchronous Memory Controller

The asynchronous memory controller provides a configurable

interface for up to four separate banks of memory or I/O

devices. Each bank can be independently programmed with dif-

ferent timing parameters, enabling connection to a wide variety

of memory devices including SRAM, flash, and EPROM, as well

as I/O devices that interface with standard memory control

lines. Bank 0 occupies a 6M word window and banks 1, 2, and 3

occupy a 8M word window in the processor’s address space but,

if not fully populated, these windows are not made contiguous

by the memory controller logic.

SDRAM Controller

The SDRAM controller provides an interface of up to four sepa-

rate banks of industry-standard SDRAM devices at speeds up to

SDCLK

. Fully compliant with the SDRAM standard, each bank has

its own memory select line (MS0–MS3), and can be configured

to contain between 4M bytes and 256M bytes of memory.

SDRAM external memory address space is shown in Table 6.

NOTE: this feature is not available on the ADSP-21486 model.

A set of programmable timing parameters is available to config-

ure the SDRAM banks to support slower memory devices. Note

that 32-bit wide devices are not supported on the SDRAM and

AMI interfaces.

The SDRAM controller address, data, clock, and control pins

can drive loads up to distributed 30 pF. For larger memory sys-

tems, the SDRAM controller external buffer timing should be

selected and external buffering should be provided so that the

load on the SDRAM controller pins does not exceed 30 pF.

Note that the external memory bank addresses shown are for

normal-word (32-bit) accesses. If 48-bit instructions as well as

32-bit data are both placed in the same external memory bank,

care must be taken while mapping them to avoid overlap.

SIMD Access to External Memory

The SDRAM controller on the processor supports SIMD access

on the 64-bit EPD (external port data bus) which allows access

to the complementary registers on the PEy unit in the normal

word space (NW). This removes the need to explicitly access the

complimentary registers when the data is in external SDRAM

memory.

VISA and ISA Access to External Memory

The SDRAM controller on the ADSP-2148x processors sup-

ports VISA code operation which reduces the memory load

since the VISA instructions are compressed. Moreover, bus

fetching is reduced because, in the best case, one 48-bit fetch

contains three valid instructions. Code execution from the tra-

ditional ISA operation is also supported. Note that code

execution is only supported from bank 0 regardless of

VISA/ISA. Table 7 shows the address ranges for instruction

fetch in each mode.

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM wave-

forms. In addition, it can generate complementary signals on

two outputs in paired mode or independent signals in non-

paired mode (applicable to a single group of four PWM

waveforms).

The entire PWM module has four groups of four PWM outputs

generating 16 PWM outputs in total. Each PWM group pro-

duces two pairs of PWM signals on the four PWM outputs.

Table 5. External Memory for Non-SDRAM Addresses

Bank

Size in

Words Address Range

Bank 0 6M 0x0020 0000–0x007F FFFF

Bank 1 8M 0x0400 0000–0x047F FFFF

Bank 2 8M 0x0800 0000–0x087F FFFF

Bank 3 8M 0x0C00 0000–0x0C7F FFFF

Table 6. External Memory for SDRAM Addresses

Bank

Size in

Words Address Range

Bank 0 62M 0x0020 0000–0x03FF FFFF

Bank 1 64M 0x0400 0000–0x07FF FFFF

Bank 2 64M 0x0800 0000–0x0BFF FFFF

Bank 3 64M 0x0C00 0000–0x0FFF FFFF

Table 7. External Bank 0 Instruction Fetch

Access Type

Size in

Words Address Range

ISA (NW) 4M 0x0020 0000–0x005F FFFF

VISA (SW) 10M 0x0060 0000–0x00FF FFFF

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 9 of 68 | June 2017

The PWM generator is capable of operating in two distinct

modes while generating center-aligned PWM waveforms:

single-update mode or double-update mode. In single-update

mode the duty cycle values are programmable only once per

PWM period. This results in PWM patterns that are symmetri-

cal about the midpoint of the PWM period. In double-update

mode, a second updating of the PWM registers is implemented

at the midpoint of the PWM period. In this mode, it is possible

to produce asymmetrical PWM patterns that produce lower

harmonic distortion in three-phase PWM inverters.

PWM signals can be mapped to the external port address lines

or to the DPI pins.

MediaLB

The automotive models of the ADSP-2148x processors have an

MLB interface which allows the processor to function as a

media local bus device. It includes support for both 3-pin as well

as 5-pin media local bus protocols. It supports speeds up to

1024 FS (49.25 Mbits/sec, FS = 48.1 kHz) and up to 31 logical

channels, with up to 124 bytes of data per media local bus frame.

For a list of automotive models, see Automotive Products on

Page 66.

Digital Applications Interface (DAI)

The digital applications interface (DAI) allows the connection

of various peripherals to any of the DAI pins (DAI_P20–1).

Programs make these connections using the signal routing unit

(SRU).

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the DAI

associated peripherals for a much wider variety of applications

by using a larger set of algorithms than is possible with noncon-

figurable signal paths.

The DAI includes eight serial ports, four precision clock genera-

tors (PCG), a S/PDIF transceiver, four ASRCs, and an input

data port (IDP). The IDP provides an additional input path to

the SHARC core, configurable as either eight channels of serial

data, or a single 20-bit wide synchronous parallel data acquisi-

tion port. Each data channel has its own DMA channel that is

independent from the processor’s serial ports.

Serial Ports (SPORTs)

The ADSP-2148x features eight synchronous serial ports that

provide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices such as Analog Devices’

AD183x family of audio codecs, ADCs, and DACs. The serial

ports are made up of two data lines, a clock, and frame sync. The

data lines can be programmed to either transmit or receive and

each data line has a dedicated DMA channel.

Serial ports can support up to 16 transmit or 16 receive DMA

channels of audio data when all eight SPORTs are enabled, or

four full duplex TDM streams of 128 channels per frame.

Serial port data can be automatically transferred to and from

on-chip memory/external memory via dedicated DMA chan-

nels. Each of the serial ports can work in conjunction with

another serial port to provide TDM support. One SPORT pro-

vides two transmit signals while the other SPORT provides the

two receive signals. The frame sync and clock are shared.

Serial ports operate in five modes:

• Standard serial mode

•Multichannel (TDM) mode

•I

S mode

•Packed I

S mode

• Left-justified mode

S/PDIF-Compatible Digital Audio Receiver/Transmitter

The S/PDIF receiver/transmitter has no separate DMA chan-

nels. It receives audio data in serial format and converts it

into a biphase encoded signal. The serial data input to the

receiver/transmitter can be formatted as left-justified, I

S or

right-justified with word widths of 16, 18, 20, or 24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF

receiver/transmitter are routed through the signal routing unit

(SRU). They can come from a variety of sources, such as the

SPORTs, external pins, or the precision clock generators

(PCGs), and are controlled by the SRU control registers.

Asynchronous Sample Rate Converter (SRC)

The asynchronous sample rate converter contains four SRC

blocks and is the same core as that used in the AD1896 192 kHz

stereo asynchronous sample rate converter and provides up to

128 dB SNR. The SRC block is used to perform synchronous or

asynchronous sample rate conversion across independent stereo

channels, without using internal processor resources. The four

SRC blocks can also be configured to operate together to

convert multichannel audio data without phase mismatches.

Finally, the SRC can be used to clean up audio data from jittery

clock sources such as the S/PDIF receiver.

Input Data Port

The IDP provides up to eight serial input channels—each with

its own clock, frame sync, and data inputs. The eight channels

are automatically multiplexed into a single 32-bit by eight-deep

FIFO. Data is always formatted as a 64-bit frame and divided

into two 32-bit words. The serial protocol is designed to receive

audio channels in I

S, left-justified sample pair, or right-justified

mode.

The IDP also provides a parallel data acquisition port (PDAP),

which can be used for receiving parallel data. The PDAP port

has a clock input and a hold input. The data for the PDAP can

be received from DAI pins or from the external port pins. The

PDAP supports a maximum of 20-bit data and four different

packing modes to receive the incoming data.

Precision Clock Generators

The precision clock generators (PCG) consist of four units, each

of which generates a pair of signals (clock and frame sync)

derived from a clock input signal. The units, A B, C, and D, are

identical in functionality and operate independently of each

other. The two signals generated by each unit are normally used

as a serial bit clock/frame sync pair.

Rev. E | Page 10 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

The outputs of PCG A and B can be routed through the DAI

pins and the outputs of PCG C and D can be driven on to the

DAI as well as the DPI pins.

Digital Peripheral Interface (DPI)

The ADSP-2148x SHARC processors have a digital peripheral

interface that provides connections to two serial peripheral

interface ports (SPI), one universal asynchronous receiver-

transmitter (UART), 12 flags, a 2-wire interface (TWI), three

PWM modules (PWM3–1), and two general-purpose timers.

Serial Peripheral (Compatible) Interface (SPI)

The SPI is an industry-standard synchronous serial link,

enabling the SPI-compatible port to communicate with other

SPI compatible devices. The SPI consists of two data pins, one

device select pin, and one clock pin. It is a full-duplex synchro-

nous serial interface, supporting both master and slave modes.

The SPI port can operate in a multimaster environment by

interfacing with up to four other SPI-compatible devices, either

acting as a master or slave device. The SPI-compatible periph-

eral implementation also features programmable baud rate and

clock phase and polarities. The SPI-compatible port uses open

drain drivers to support a multimaster configuration and to

avoid data contention.

UART Port

The processors provide a full-duplex Universal Asynchronous

Receiver/Transmitter (UART) port, which is fully compatible

with PC-standard UARTs. The UART port provides a simpli-

fied UART interface to other peripherals or hosts, supporting

full-duplex, DMA-supported, asynchronous transfers of serial

data. The UART also has multiprocessor communication capa-

bility using 9-bit address detection. This allows it to be used in

multidrop networks through the RS-485 data interface

standard. The UART port also includes support for 5 to 8 data

bits, 1 or 2 stop bits, and none, even, or odd parity. The UART

port supports two modes of operation:

• PIO (programmed I/O)—The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA (direct memory access)—The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

Timers

The ADSP-2148x has a total of three timers: a core timer that

can generate periodic software interrupts and two general-

purpose timers that can generate periodic interrupts and be

independently set to operate in one of three modes:

• Pulse waveform generation mode

• Pulse width count/capture mode

• External event watchdog mode

The core timer can be configured to use FLAG3 as a timer

expired signal, and the general-purpose timers have one bidirec-

tional pin and four registers that implement its mode of

operation: a 6-bit configuration register, a 32-bit count register,

a 32-bit period register, and a 32-bit pulse width register. A sin-

gle control and status register enables or disables the general-

purpose timer.

2-Wire Interface Port (TWI)

The TWI is a bidirectional 2-wire, serial bus used to move 8-bit

data while maintaining compliance with the I

C bus protocol.

The TWI master incorporates the following features:

• 7-bit addressing

• Simultaneous master and slave operation on multiple

device systems with support for multi master data

arbitration

• Digital filtering and timed event processing

• 100 kbps and 400 kbps data rates

• Low interrupt rate

I/O PROCESSOR FEATURES

The I/O processors provide up to 65 channels of DMA, as well

as an extensive set of peripherals.

DMA Controller

The processor’s on-chip DMA controller allows data transfers

without processor intervention. The DMA controller operates

independently and invisibly to the processor core, allowing

DMA operations to occur while the core is simultaneously exe-

cuting its program instructions. DMA transfers can occur

between the ADSP-2148x’s internal memory and its serial ports,

the SPI-compatible (serial peripheral interface) ports, the IDP

(input data port), the PDAP, or the UART. The DMA channel

summary is shown in Table 8.

Programs can be downloaded to the ADSP-2148x using DMA

transfers. Other DMA features include interrupt generation

upon completion of DMA transfers and DMA chaining for

automatic linked DMA transfers.

Table 8. DMA Channels

Peripheral DMA Channels

SPORTs 16

IDP/PDAP 8

SPI 2

UART 2

External Port 2

Accelerators 2

Memory-to-Memory 2

MLB

Automotive models only.

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 11 of 68 | June 2017

Delay Line DMA

The processor provides delay line DMA functionality. This

allows processor reads and writes to external delay line buffers

(and hence to external memory) with limited core interaction.

Scatter/Gather DMA

The processor provides scatter/gather DMA functionality. This

allows processor DMA reads/writes to/from non contiguous

memory blocks.

FFT Accelerator

The FFT accelerator implements a radix-2 complex/real input,

complex output FFT with no core intervention. The FFT accel-

erator runs at the peripheral clock frequency.

FIR Accelerator

The FIR (finite impulse response) accelerator consists of a 1024

word coefficient memory, a 1024 word deep delay line for the

data, and four MAC units. A controller manages the accelerator.

The FIR accelerator runs at the peripheral clock frequency.

IIR Accelerator

The IIR (infinite impulse response) accelerator consists of a

1440 word coefficient memory for storage of biquad coeffi-

cients, a data memory for storing the intermediate data, and one

MAC unit. A controller manages the accelerator. The IIR accel-

erator runs at the peripheral clock frequency.

Watchdog Timer

The watchdog timer is used to supervise the stability of the sys-

tem software. When used in this way, software reloads the

watchdog timer in a regular manner so that the downward

counting timer never expires. An expiring timer then indicates

that system software might be out of control.

The 32-bit watchdog timer that can be used to implement a soft-

ware watchdog function. A software watchdog can improve

system reliability by forcing the processor to a known state

through generation of a system reset, if the timer expires before

being reloaded by software. Software initializes the count value

of the timer, and then enables the timer. The watchdog timer

resets both the core and the internal peripherals. Note that this

feature is available on the 176-lead package only.

SYSTEM DESIGN

The following sections provide an introduction to system design

options and power supply issues.

Program Booting

The internal memory of the ADSP-2148x boots at system

power-up from an 8-bit EPROM via the external port, an SPI

master, or an SPI slave. Booting is determined by the boot con-

figuration (BOOT_CFG2–0) pins in Table 9 for the 176-lead

package and Table 10 for the 100-lead package.

The “Running Reset” feature allows a user to perform a reset of

the processor core and peripherals, but without resetting the

PLL and SDRAM controller, or performing a boot. The

functionality of the RESETOUT/RUNRSTIN pin has now been

extended to also act as the input for initiating a Running Reset.

For more information, see the hardware reference manual.

Power Supplies

The processors have separate power supply connections for the

internal (V

DD_INT

) and external (V

DD_EXT

) power supplies. The

internal supply must meet the V

DD_INT

specifications. The

external supply must meet the V

DD_EXT

specification. All exter-

nal supply pins must be connected to the same power supply.

To reduce noise coupling, the PCB should use a parallel pair of

power and ground planes for V

DD_INT

and GND.

Static Voltage Scaling (SVS)

Some models of the ADSP-2148x feature Static Voltage Scaling

(SVS) on the V

DD_INT

power supply. (See the Ordering Guide

on Page 66 for model details.) This voltage specification tech-

nique can provide significant performance benefits including

450 MHz core frequency operation without a significant

increase in power.

SVS optimizes the required V

DD_INT

voltage for each individual

device to enable enhanced operating frequency up to 450 MHz.

The optimized SVS voltage results in a reduction of maximum

DD_INT

which enables 450 MHz operation at the same or lower

maximum power than 400 MHz operation at a fixed voltage

supply. Implementation of SVS requires a specific voltage regu-

lator circuit design and initialization code.

Refer to the Engineer-to-Engineer Note Static Voltage Scaling

for ADSP-2148x SHARC Processors (EE-357) for further infor-

mation. The EE-Note details the requirements and process to

implement a SVS power supply system to enable operation up

to 450 MHz. This applies only to specific products within the

ADSP-2148x family which are capable of supporting 450 MHz

operation.

Table 9. Boot Mode Selection, 176-Lead Package

BOOT_CFG2–0 Booting Mode

000 SPI Slave Boot

001 SPI Master Boot

010 AMI User Boot (for 8-bit Flash Boot)

011 No boot (processor executes from internal

ROM after reset)

1xx Reserved

Table 10. Boot Mode Selection, 100-Lead Package

BOOT_CFG1–0 Booting Mode

00 SPI Slave Boot

01 SPI Master Boot

10 Reserved

11 No boot (processor executes from internal

ROM after reset)

Rev. E | Page 12 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Details on power consumption and Static and Dynamic current

consumption can be found at Total Power Dissipation on

Page 20. Also see Operating Conditions on Page 18 for more

information.

The following are SVS features.

• SVS is applicable only to 450 MHz models (not applicable

to 400 MHz or lower frequency models).

• Each individual SVS device includes a register (SVS_DAT)

containing the unique SVS voltage set at the factory, known

as SVS

NOM

•The SVS

NOM

value is the intended set voltage for the

DD_INT

voltage regulator.

• No dedicated pins are required for SVS. The TWI serial bus

is used to communicate SVS

NOM

to the voltage regulator.

• Analog Devices recommends a specific voltage regulator

design and initialization code sequence that optimizes the

power-up sequence.

The Engineer-to-Engineer Note Static Voltage Scaling for

ADSP-2148x SHARC Processors (EE-357) contains the

details of the regulator design and the initialization

requirements.

• Any differences from the Analog Devices recommended

programmable regulator design must be reviewed by Ana-

log Devices to ensure that it meets the voltage accuracy and

range requirements.

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-2148x pro-

cessors to monitor and control the target board processor

during emulation. Analog Devices DSP Tools product line of

JTAG emulators provides emulation at full processor speed,

allowing inspection and modification of memory, registers, and

processor stacks. The processor’s JTAG interface ensures that

the emulator will not affect target system loading or timing.

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate emulator hardware user’s guide.

DEVELOPMENT TOOLS

Analog Devices supports its processors with a complete line of

software and hardware development tools, including integrated

development environments (which include CrossCore

Embed-

ded Studio and/or VisualDSP++

), evaluation products,

emulators, and a wide variety of software add-ins.

Integrated Development Environments (IDEs)

For C/C++ software writing and editing, code generation, and

debug support, Analog Devices offers two IDEs.

CrossCore Embedded Studio is based on the Eclipse

frame-

work. Supporting most Analog Devices processor families, it is

the IDE of choice for future processors, including multicore

devices. CrossCore Embedded Studio seamlessly integrates

available software add-ins to support real time operating sys-

tems, file systems, TCP/IP stacks, USB stacks, algorithmic

software modules, and evaluation hardware board support

packages. For more information visit www.analog.com/cces.

The other Analog Devices IDE, VisualDSP++, supports proces-

sor families introduced prior to the release of CrossCore

Embedded Studio. This IDE includes the Analog Devices VDK

real time operating system and an open source TCP/IP stack.

For more information visit www.analog.com/visualdsp. Note

that VisualDSP++ will not support future Analog Devices

processors.

EZ-KIT Lite Evaluation Board

For processor evaluation, Analog Devices provides wide range

of EZ-KIT Lite

evaluation boards. Including the processor and

key peripherals, the evaluation board also supports on-chip

emulation capabilities and other evaluation and development

features. Also available are various EZ-Extenders

, which are

daughter cards delivering additional specialized functionality,

including audio and video processing. For more information

visit www.analog.com and search on “ezkit” or “ezextender”.

EZ-KIT Lite Evaluation Kits

For a cost-effective way to learn more about developing with

Analog Devices processors, Analog Devices offer a range of EZ-

KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT

Lite evaluation board, directions for downloading an evaluation

version of the available IDE(s), a USB cable, and a power supply.

The USB controller on the EZ-KIT Lite board connects to the

USB port of the user’s PC, enabling the chosen IDE evaluation

suite to emulate the on-board processor in-circuit. This permits

the customer to download, execute, and debug programs for the

EZ-KIT Lite system. It also supports in-circuit programming of

the on-board Flash device to store user-specific boot code,

enabling standalone operation. With the full version of Cross-

Core Embedded Studio or VisualDSP++ installed (sold

separately), engineers can develop software for supported EZ-

KITs or any custom system utilizing supported Analog Devices

processors.

Software Add-Ins for CrossCore Embedded Studio

Analog Devices offers software add-ins which seamlessly inte-

grate with CrossCore Embedded Studio to extend its capabilities

and reduce development time. Add-ins include board support

packages for evaluation hardware, various middleware pack-

ages, and algorithmic modules. Documentation, help,

configuration dialogs, and coding examples present in these

add-ins are viewable through the CrossCore Embedded Studio

IDE once the add-in is installed.

Board Support Packages for Evaluation Hardware

Software support for the EZ-KIT Lite evaluation boards and EZ-

Extender daughter cards is provided by software add-ins called

Board Support Packages (BSPs). The BSPs contain the required

drivers, pertinent release notes, and select example code for the

given evaluation hardware. A download link for a specific BSP is

located on the web page for the associated EZ-KIT or EZ-

Extender product. The link is found in the Product Download

area of the product web page.

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 13 of 68 | June 2017

Middleware Packages

Analog Devices separately offers middleware add-ins such as

real time operating systems, file systems, USB stacks, and

TCP/IP stacks. For more information see the following web

pages:

•www.analog.com/ucos3

•www.analog.com/ucfs

•www.analog.com/ucusbd

•www.analog.com/lwip

Algorithmic Modules

To speed development, Analog Devices offers add-ins that per-

form popular audio and video processing algorithms. These are

available for use with both CrossCore Embedded Studio and

VisualDSP++. For more information visit www.analog.com and

search on “Blackfin software modules” or “SHARC software

modules”.

Designing an Emulator-Compatible DSP Board (Target)

For embedded system test and debug, Analog Devices provides

a family of emulators. On each JTAG DSP, Analog Devices sup-

plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit

emulation is facilitated by use of this JTAG interface. The emu-

lator accesses the processor’s internal features via the

processor’s TAP, allowing the developer to load code, set break-

points, and view variables, memory, and registers. The

processor must be halted to send data and commands, but once

an operation is completed by the emulator, the DSP system is set

to run at full speed with no impact on system timing. The emu-

lators require the target board to include a header that supports

connection of the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, signal buffering, signal ter-

mination, and emulator pod logic, see Analog Devices JTAG

Emulation Technical Reference (EE-68). This document is

updated regularly to keep pace with improvements to emulator

support.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-2148x

architecture and functionality. For detailed information on the

ADSP-2148x family core architecture and instruction set, refer

to the programming reference manual.

RELATED SIGNAL CHAINS

A signal chain is a series of signal-conditioning electronic com-

ponents that receive input (data acquired from sampling either

real-time phenomena or from stored data) in tandem, with the

output of one portion of the chain supplying input to the next.

Signal chains are often used in signal processing applications to

gather and process data or to apply system controls based on

analysis of real-time phenomena.

Analog Devices eases signal processing system development by

providing signal processing components that are designed to

work together well. A tool for viewing relationships between

specific applications and related components is available on the

www.analog.com website.

The application signal chains page in the Circuits from the Lab

site (http:\\www.analog.com\circuits) provides:

• Graphical circuit block diagram presentation of signal

chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection

guides and application information

• Reference designs applying best practice design techniques

Rev. E | Page 14 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

PIN FUNCTION DESCRIPTIONS

Table 11. Pin Descriptions

Name Type

State

During/

After Reset Description

ADDR

23–0

I/O/T (ipu) High-Z/

driven low

(boot)

External Address. The processor outputs addresses for external memory and periph-

erals on these pins. The ADDR pins can be multiplexed to support the external memory

interface address, and FLAGS15–8 (I/O) and PWM (O). After reset, all ADDR pins are in

external memory interface mode and FLAG(0–3) pins are in FLAGS mode (default).

When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the ADDR

23–4

pins

for parallel input data.

DATA

15–0

I/O/T (ipu) High-Z External Data. The data pins can be multiplexed to support the external memory

interface data (I/O), and FLAGS

7–0

(I/O).

AMI_ACK I (ipu) Memory Acknowledge. External devices can deassert AMI_ACK (low) to add wait

states to an external memory access. AMI_ACK is used by I/O devices, memory

controllers, or other peripherals to hold off completion of an external memory access.

0–1

O/T (ipu) High-Z Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre-

sponding banks of external memory. The MS

1-0

lines are decoded memory address lines

that change at the same time as the other address lines. When no external memory

access is occurring the MS

1-0

lines are inactive; they are active however when a condi-

tional memory access instruction is executed, when the condition evaluates as true.

The MS1 pin can be used in EPORT/FLASH boot mode. For more information, see the

hardware reference manual.

AMI_RD O/T (ipu) High-Z AMI Port Read Enable. AMI_RD is asserted whenever the processor reads a word from

external memory.

AMI_WR O/T (ipu) High-Z AMI Port Write Enable. AMI_WR is asserted when the processor writes a word to

external memory.

FLAG0/IRQ0 I/O (ipu) FLAG[0]

INPUT

FLAG0/Interrupt Request0.

FLAG1/IRQ1 I/O (ipu) FLAG[1]

INPUT

FLAG1/Interrupt Request1.

FLAG2/IRQ2/MS2 I/O (ipu) FLAG[2]

INPUT

FLAG2/Interrupt Request2/Memory Select2.

FLAG3/TMREXP/MS3 I/O (ipu) FLAG[3]

INPUT

FLAG3/Timer Expired/Memory Select3.

The following symbols appear in the Type column of this table: A = asynchronous, I= input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot

be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The

range of an ipd resistor can be between 31 kΩ–85kΩ. The three-state voltage of ipu pads will not reach to the full V

DD_EXT

level; at typical

conditions the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 15 of 68 | June 2017

SDRAS O/T (ipu) High-Z/

driven high

SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other

SDRAM command pins, defines the operation for the SDRAM to perform.

SDCAS O/T (ipu) High-Z/

driven high

SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction with

other SDRAM command pins, defines the operation for the SDRAM to perform.

SDWE O/T (ipu) High-Z/

driven high

SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin. In conjunction with

other SDRAM command pins, defines the operation for the SDRAM to perform.

SDCKE O/T (ipu) High-Z/

driven high

SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK

signal. For details, see the data sheet supplied with the SDRAM device.

SDA10 O/T (ipu) High-Z/

driven high

SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-SDRAM

accesses. This pin replaces the DSP’s ADDR10 pin only during SDRAM accesses.

SDDQM O/T (ipu) High-Z/

driven high

DQM Data Mask. SDRAM Input mask signal for write accesses and output mask signal

for read accesses. Input data is masked when DQM is sampled high during a write cycle.

The SDRAM output buffers are placed in a High-Z state when DQM is sampled high

during a read cycle. SDDQM is driven high from reset de-assertion until SDRAM initial-

ization completes. Afterwards it is driven low irrespective of whether any SDRAM

accesses occur or not.

SDCLK O/T (ipd) High-Z/

driving

SDRAM Clock Output. Clock driver for this pin differs from all other clock drivers. See

Figure 41 on Page 55. For models in the 100-lead package, the SDRAM interface should

be disabled to avoid unnecessary power switching by setting the DSDCTL bit in SDCTL

DAI _P

20–1

I/O/T (ipu) High-Z Digital Applications Interface. These pins provide the physical interface to the DAI

SRU. The DAI SRU configuration registers define the combination of on-chip audio-

centric peripheral inputs or outputs connected to the pin and to the pin’s output enable.

The configuration registers of these peripherals then determines the exact behavior of

the pin. Any input or output signal present in the DAI SRU may be routed to any of these

pins.

DPI _P

14–1

I/O/T (ipu) High-Z Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.

The DPI SRU configuration registers define the combination of on-chip peripheral

inputs or outputs connected to the pin and to the pin’s output enable. The configu-

ration registers of these peripherals then determines the exact behavior of the pin. Any

input or output signal present in the DPI SRU may be routed to any of these pins.

WDT_CLKIN I Watchdog Timer Clock Input. This pin should be pulled low when not used.

WDT_CLKO O Watchdog Resonator Pad Output.

WDTRSTO O (ipu) Watchdog Timer Reset Out.

THD_P I Thermal Diode Anode. When not used, this pin can be left floating.

THD_M O Thermal Diode Cathode. When not used, this pin can be left floating.

Table 11. Pin Descriptions (Continued)

Name Type

State

During/

After Reset Description

The following symbols appear in the Type column of this table: A = asynchronous, I= input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot

be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The

range of an ipd resistor can be between 31 kΩ–85kΩ. The three-state voltage of ipu pads will not reach to the full V

DD_EXT

level; at typical

conditions the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

Rev. E | Page 16 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

MLBCLK

IMedia Local Bus Clock. This clock is generated by the MLB controller that is synchro-

nized to the MOST network and provides the timing for the entire MLB interface at

49.152 MHz at FS=48 kHz. When the MLB controller is not used, this pin should be

grounded.

MLBDAT

I/O/T in 3

pin mode. I

in 5 pin

mode.

High-Z Media Local Bus Data. The MLBDAT line is driven by the transmitting MLB device and

is received by all other MLB devices including the MLB controller. The MLBDAT line

carries the actual data. In 5-pin MLB mode, this pin is an input only. When the MLB

controller is not used, this pin should be grounded.

MLBSIG

I/O/T in 3

pin mode. I

in 5 pin

mode

High-Z Media Local Bus Signal. This is a multiplexed signal which carries the Channel/Address

generated by the MLB Controller, as well as the Command and RxStatus bytes from

MLB devices. In 5-pin mode, this pin is input only. When the MLB controller is not used,

this pin should be grounded.

MLBDO

O/T High-Z Media Local Bus Data Output (in 5 pin mode). This pin is used only in 5-pin MLB mode.

This serves as the output data pin in 5-pin mode. When the MLB controller is not used,

this pin should be connected to ground.

MLBSO

O/T High-Z Media Local Bus Signal Output (in 5 pin mode). This pin is used only in 5-pin MLB

mode. This serves as the output signal pin in 5-pin mode. When the MLB controller is

not used, this pin should be connected to ground.

TDI I (ipu) Test Data Input (JTAG). Provides serial data for the boundary scan logic.

TDO O/T High-Z Test Data Output (JTAG). Serial scan output of the boundary scan path.

TMS I (ipu) Test Mode Select (JTAG). Used to control the test state machine.

TCK I Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the device.

TRST I (ipu) Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)

after power-up or held low for proper operation of the processor.

EMU O (O/D, ipu) High-Z Emulation Status. Must be connected to the ADSP-2148x Analog Devices DSP Tools

product line of JTAG emulators target board connector only.

Table 11. Pin Descriptions (Continued)

Name Type

State

During/

After Reset Description

The following symbols appear in the Type column of this table: A = asynchronous, I= input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot

be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The

range of an ipd resistor can be between 31 kΩ–85kΩ. The three-state voltage of ipu pads will not reach to the full V

DD_EXT

level; at typical

conditions the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 17 of 68 | June 2017

CLK_CFG

1–0

ICore to CLKIN Ratio Control. These pins set the start up clock frequency.

Note that the operating frequency can be changed by programming the PLL multiplier

and divider in the PMCTL register at any time after the core comes out of reset. The

allowed values are:

00 = 8:1

01 = 32:1

10 = 16:1

11 = reserved

CLKIN I Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It configures

the processors to use either its internal clock generator or an external clock source.

Connecting the necessary components to CLKIN and XTAL enables the internal clock

generator. Connecting the external clock to CLKIN while leaving XTAL unconnected

configures the processors to use the external clock source such as an external clock

oscillator. CLKIN may not be halted, changed, or operated below the specified

frequency.

XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external

crystal.

RESET IProcessor Reset. Resets the processor to a known state. Upon deassertion, there is a

4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program

execution from the hardware reset vector address. The RESET input must be asserted

(low) at power-up.

RESETOUT/

RUNRSTIN

I/O (ipu) Reset Out/Running Reset In. The default setting on this pin is reset out. This pin also

has a second function as RUNRSTIN which is enabled by setting bit 0 of the RUNRSTCTL

BOOT_CFG

2–0

IBoot Configuration Select. These pins select the boot mode for the processor (see

Table 9). The BOOT_CFG pins must be valid before RESET (hardware and software) is

asserted.

The MLB pins are only available on the automotive models.

Table 12. Pin List, Power and Ground

Name Type Description

DD_INT

PInternal Power Supply

DD_EXT

PI/O Power Supply

GND

GGround

DD_THD

PThermal Diode Power Supply. When not used, this pin can be left floating.

The exposed pad is required to be electrically and thermally connected to GND. Implement this by soldering the exposed pad to a GND PCB land that is the same size as the

exposed pad. The GND PCB land should be robustly connected to the GND plane in the PCB for best electrical and thermal performance. No separate GND pins are provided

in the package.

Table 11. Pin Descriptions (Continued)

Name Type

State

During/

After Reset Description

The following symbols appear in the Type column of this table: A = asynchronous, I= input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot

be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The

range of an ipd resistor can be between 31 kΩ–85kΩ. The three-state voltage of ipu pads will not reach to the full V

DD_EXT

level; at typical

conditions the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

Rev. E | Page 18 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

SPECIFICATIONS

OPERATING CONDITIONS

266 MHz / 300 MHz / 350 MHz / 400 MHz 450 MHz

UnitParameter

Specifications subject to change without notice.

Description Min Nominal Max Min Nominal Max

DD_INT

SVS

NOM

refers to the nominal SVS voltage which is set between 1.0 V and 1.15 V at the factory for each individual device. Only the unique SVS

NOM

value in each chip may be used

for 401 MHz to 450 MHz operation of that chip. This spec lists the possible range of the SVS

NOM

values for all devices. The initial VDD_INT voltage at power on is 1.1 V nominal

and it transitions to SVS programmed voltage as outlined in Engineer-to-Engineer Note Static Voltage Scaling for ADSP-2148x SHARC Processors (EE-357).

Internal (Core) Supply Voltage 1.05 1.10 1.15 SVS

NOM

– 25 mV 1.00 – 1.15 SVS

NOM

+ 25 mV V

DD_EXT

External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 V

DD_THD

Thermal Diode Supply Voltage 3.13 3.47 3.13 3.47 V

Applies to input and bidirectional pins: ADDR23–0, DATA15–0, FLAG3–0, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RUNRSTIN, RESET, TCK, TMS, TDI, TRST, AMI_ACK,

MLBCLK, MLBDAT, MLBSIG.

High Level Input Voltage at

DD_EXT

= Max

2.0 3.6 2.0 3.6 V

Low Level Input Voltage at

DD_EXT

= Min

–0.3 +0.8 –0.3 +0.8 V

IH_CLKIN

Applies to input pins CLKIN, WDT_CLKIN.

High Level Input Voltage at

DD_EXT

= Max

2.2 V

DD_EXT

2.2 V

DD_EXT

IL_CLKIN

Low Level Input Voltage at

DD_EXT

= Min

–0.3 +0.8 –0.3 +0.8 V

Junction Temperature

100-Lead LQFP_EP at

AMBIENT

0°C to +70°C

0 110 0 115 °C

Junction Temperature

176-Lead LQFP_EP at

AMBIENT

0°C to +70°C

0 110 0 115 °C

AUTOMOTIVE USE ONLY 266 MHz / 300 MHz / 400 MHz

Junction Temperature

100-Lead LQFP_EP at

AMBIENT

–40°C to +85°C

(Automotive Grade)

–40 +125

Automotive application use profile only. Not supported for nonautomotive use. Contact Analog Devices for more information.

NA NA °C

Junction Temperature

176-Lead LQFP_EP at

AMBIENT

–40°C to +85°C

(Automotive Grade)

–40 +125

NA NA °C

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 19 of 68 | June 2017

ELECTRICAL CHARACTERISTICS

266 MHz / 300 MHz / 350 MHz / 400 MHz / 450 MHz

Parameter

Description Conditions Min Typ Max Unit

High Level Output

Voltage

@ V

DD_EXT

= Min,

= –1.0 mA

2.4 V

Low Level Output

Voltage

@ V

DD_EXT

= Min,

= 1.0 mA

0.4 V

4, 5

High Level Input Current @ V

DD_EXT

= Max,

= V

DD_EXT

Max

10 µA

Low Level Input Current @ V

DD_EXT

= Max, V

= 0 V 10 µA

ILPU

Low Level Input Current

Pull-up

@ V

DD_EXT

= Max, V

= 0 V 200 µA

OZH

6, 7

Three-State Leakage

Current

@ V

DD_EXT

= Max,

= V

DD_EXT

Max

10 µA

OZL

Three-State Leakage

Current

@ V

DD_EXT

= Max, V

= 0 V 10 µA

OZLPU

Three-State Leakage

Current Pull-up

@ V

DD_EXT

= Max, V

= 0 V 200 µA

OZHPD

Three-State Leakage

Current Pull-down

@ V

DD_EXT

= Max,

= V

DD_EXT

Max

200 µA

DD_INT

Supply Current (Internal) f

CCLK

> 0 MHz Table 14 + Table 15

× ASF

DD_INT

Supply Current (Internal) V

DDINT

= 1.1 V, ASF = 1,

= 25°C

385 / 410 / 450 / 500 / 550 mA

10,

Input Capacitance T

CASE

= 25°C 5 pF

Specifications subject to change without notice.

Applies to output and bidirectional pins: ADDR23–0, DATA15–0, AMI_RD, AMI_WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, RESETOUT MLBSIG, MLBDAT, MLBDO,

MLBSO, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, MS0-1.

See Output Drive Currents on Page 55 for typical drive current capabilities.

Applies to input pins: BOOT_CFGx, CLK_CFGx, TCK, RESET, CLKIN.

Applies to input pins with internal pull-ups: TRST, TMS, TDI.

Applies to three-statable pin: TDO.

Applies to three-statable pins with pull-ups: DAI_Px, DPI_Px, EMU.

Applies to three-statable pin with pull-down: SDCLK.

See Engineer-to-Engineer Note Estimating Power for ADSP-214xx SHARC Processors (EE-348) for further information.

Applies to all signal pins.

Guaranteed, but not tested.

Rev. E | Page 20 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Total Power Dissipation

The information in this section should be augmented with the

Engineer-to-Engineer Note Estimating Power for ADSP-214xx

SHARC Processors (EE-348).

Total power dissipation has two components:

1. Internal power consumption is additionally comprised of

two components:

• Static current due to leakage. Table 14 shows the static

current consumption (I

DD_INT_STATIC

) as a function of

junction temperature (T

) and core voltage (V

DD_INT

• Dynamic current (I

DD_INT_DYNAMIC

), due to transistor

switching characteristics and activity level of the pro-

cessor. The activity level is reflected by the Activity

Scaling Factor (ASF), which represents the activity

level of the application code running on the processor

core and having various levels of peripheral and exter-

nal port activity (Table 13).

Dynamic current consumption is calculated by select-

ing the ASF that corresponds most closely with the

user application and then multiplying that with the

dynamic current consumption (Table 15).

2. External power consumption is due to the switching activ-

ity of the external pins.

Table 13. Activity Scaling Factors (ASF)

Activity Scaling Factor (ASF)

Idle 0.29

Low 0.53

Medium Low 0.61

Medium High 0.77

Peak Typical (50:50)

0.85

Peak Typical (60:40)

0.93

Peak Typical (70:30)

1.00

High Typical 1.16

High 1.25

Peak 1.31

See the Engineer-to-Engineer Note Estimating Power for ADSP-214xx SHARC

Processors (EE-348) for more information on the explanation of the power

vectors specific to the ASF table.

Ratio of continuous instruction loop (core) to SDRAM control code reads and

writes.

Table 14. Static Current—I

DD_INT_STATIC

(mA)

(°C)

DD_INT

(V)

0.975 V 1.0 V 1.025 V 1.05 V 1.075 V 1.10 V 1.125 V 1.15 V 1.175 V

–45 68 77 86 96 107 118 131 144 159

–35 74 83 92 103 114 126 140 154 170

–25 82 92 101 113 125 138 153 168 185

–15 94 104 115 127 140 155 171 187 205

–5 109 121 133 147 161 177 194 212 233

+5 129 142 156 171 188 206 225 245 268

+15 152 168 183 201 219 240 261 285 309

+25 182 199 216 237 257 280 305 331 360

+35 217 237 256 279 303 329 358 388 420

+45 259 282 305 331 359 389 421 455 492

+55 309 334 361 391 423 458 495 533 576

+65 369 398 429 464 500 539 582 626 675

+75 437 471 506 547 588 633 682 731 789

+85 519 559 599 645 693 746 802 860 926

+95 615 662 707 761 816 877 942 1007 1083

+105 727 779 833 897 958 1026 1103 1179 1266

+115 853 914 975 1047 1119 1198 1285 1372 1473

+125 997 1067 1138 1219 1305 1397 1498 1601 1716

Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 18.

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 21 of 68 | June 2017

ABSOLUTE MAXIMUM RATINGS

Stresses at or above those listed in Table 16 may cause perma-

nent damage to the product. This is a stress rating only;

functional operation of the product at these or any other condi-

tions above those indicated in the operational section of this

specification is not implied. Operation beyond the maximum

operating conditions for extended periods may affect product

reliability.

ESD SENSITIVITY

MAXIMUM POWER DISSIPATION

See Engineer-to-Engineer Note Estimating Power for ADSP-

214xx SHARC Processors (EE-348) for detailed thermal and

power information regarding maximum power dissipation. For

information on package thermal specifications, see Thermal

Characteristics on Page 56.

PACKAGE INFORMATION

The information presented in Figure 3 provides details about

the package branding for the ADSP-2148x processors. For a

complete listing of product availability, see Ordering Guide on

Page 66.

Table 15. Dynamic Current in CCLK Domain—I

DD_INT_DYNAMIC

(mA, with ASF = 1.0)

CCLK

(MHz)

DD_INT

(V)

0.975 V 1.0 V 1.025 V 1.05 V 1.075 V 1.10 V 1.125 V 1.15 V 1.175 V

100 767781848788909295

150 117 119 123 126 130 133 136 139 144

200 153 156 161 165 170 174 179 183 188

250 190 195 201 207 212 217 223 229 235

300 227 233 240 246 253 260 266 273 280

350 263 272 278 286 294 302 309 318 325

400 300 309 317 326 335 344 352 361 370

450 339 349 356 365 374 385 394 405 415

The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 19.

Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 18.

Table 16. Absolute Maximum Ratings

Parameter Rating

Internal (Core) Supply Voltage (V

DD_INT

) –0.3 V to +1.32 V

External (I/O) Supply Voltage (V

DD_EXT

)–0.3 V to +3.6 V

Thermal Diode Supply Voltage

DD_THD

)

–0.3 V to +3.6 V

Input Voltage –0.5 V to +3.6 V

Output Voltage Swing –0.5 V to V

DD_EXT

+0.5 V

Storage Temperature Range –65°C to +150°C

Junction Temperature While Biased 125°C

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid

performance degradation or loss of functionality.

Figure 3. Typical Package Brand

Table 17. Package Brand Information

Non automotive only. For branding information specific to automotive products,

contact Analog Devices Inc.

Brand Key Field Description

t Temperature Range

pp Package Type

Z RoHS Compliant Option

cc See Ordering Guide

vvvvvv.x Assembly Lot Code

n.n Silicon Revision

# RoHS Compliant Designation

yyww Date Code

vvvvvv.x n.n

tppZ-cc

ADSP-2148x

#yyww country_of_origin

Rev. E | Page 22 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

TIMING SPECIFICATIONS

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 43 on Page 55 for voltage reference levels.

Switching characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

Timing requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

Core Clock Requirements

The processor’s internal clock (a multiple of CLKIN) provides

the clock signal for timing internal memory, the processor core,

and the serial ports. During reset, program the ratio between the

processor’s internal clock frequency and external (CLKIN)

clock frequency with the CLK_CFG1–0 pins.

The processor’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL,

see Figure 4). This PLL-based clocking minimizes the skew

between the system clock (CLKIN) signal and the processor’s

internal clock.

Voltage Controlled Oscillator (VCO)

In application designs, the PLL multiplier value should be

selected in such a way that the VCO frequency never exceeds

VCO

specified in Table 20.

• The product of CLKIN and PLLM must never exceed 1/2 of

VCO

(max) in Table 20 if the input divider is not enabled

(INDIV = 0).

• The product of CLKIN and PLLM must never exceed f

VCO

(max) in Table 20 if the input divider is enabled

(INDIV = 1).

The VCO frequency is calculated as follows:

VCO

= 2 × PLLM × f

INPUT

CCLK

= (2 × PLLM × f

INPUT

) ÷ PLLD

where:

VCO

= VCO output

PLLM = Multiplier value programmed in the PMCTL register.

During reset, the PLLM value is derived from the ratio selected

using the CLK_CFG pins in hardware.

PLLD = 2, 4, 8, or 16 based on the divider value programmed on

the PMCTL register. During reset this value is 2.

INPUT

= is the input frequency to the PLL.

INPUT

= CLKIN when the input divider is disabled or

INPUT

= CLKIN ÷ 2 when the input divider is enabled

Figure 4. Core Clock and System Clock Relationship to CLKIN

LOOP

FILTER

CLKIN

PCLK

SDRAM

DIVIDER

BYPASS

MUX

PMCTL

(SDCKR)

CCLK

PLL

XTAL

CLKIN

DIVIDER

RESET

VCO

÷ (2 × PLLM)

BUF

VCO

BUF

PMCTL

(INDIV)

PLL

DIVIDER

RESETOUT

CLKOUT (TEST ONLY)*

DELAY OF

4096 CLKIN

CYCLES

PCLK

PMCTL

(PLLBP)

PMCTL

(PLLD)

VCO

fCCLK

INPUT

*CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS f

INPUT.

THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN.

CLK_CFGx/

PMCTL (2 × PLLM) DIVIDE

BY 2

MUX

PMCTL

(PLLBP)

CCLK

RESETOUT

CORESRST

SDCLK

BYPASS

MUX

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 23 of 68 | June 2017

Note the definitions of the clock periods that are a function of

CLKIN and the appropriate ratio control shown in Table 18. All

of the timing specifications for the ADSP-2148x peripherals are

defined in relation to t

PCLK

. See the peripheral specific section

for each peripheral’s timing information.

Figure 4 shows core to CLKIN relationships with external oscil-

lator or crystal. The shaded divider/multiplier blocks denote

where clock ratios can be set through hardware or software

using the power management control register (PMCTL). For

more information, see the hardware reference manual.

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 19. While no specific power-up sequencing is required

between V

DD_EXT

and V

DD_INT

, there are some considerations

that system designs should take into account.

• No power supply should be powered up for an extended

period of time (> 200 ms) before another supply starts to

ramp up.

•If the V

DD_INT

power supply comes up after V

DD_EXT

, any

pin, such as RESETOUT and RESET, may actually drive

momentarily until the V

DD_INT

rail has powered up.

Systems sharing these signals on the board must determine

if there are any issues that need to be addressed based on

this behavior.

Note that during power-up, when the V

DD_INT

power supply

comes up after V

DD_EXT

, a leakage current of the order of three-

state leakage current pull-up, pull-down may be observed on

any pin, even if that is an input only (for example the RESET

pin) until the V

DD_INT

rail has powered up.

Table 18. Clock Periods

Timing

Requirements Description

CLKIN Clock Period

CCLK

Processor Core Clock Period

PCLK

Peripheral Clock Period = 2 × t

CCLK

SDCLK

SDRAM Clock Period = (t

CCLK

) × SDCKR

Table 19. Power Up Sequencing Timing Requirements (Processor Startup)

Parameter Min Max Unit

Timing Requirements

RSTVDD

RESET Low Before V

DD_EXT

or V

DD_INT

On 0 ms

IVDDEVDD

DD_INT

On Before V

DD_EXT

–200 +200 ms

CLKVDD

CLKIN Valid After V

DD_INT

and V

DD_EXT

Valid 0 200 ms

CLKRST

CLKIN Valid Before RESET Deasserted 10

µs

PLLRST

PLL Control Setup Before RESET Deasserted 20

µs

Switching Characteristic

CORERST

Core Reset Deasserted After RESET Deasserted 4096 × t

+ 2 × t

CCLK

Valid V

DD_INT

and V

DD_EXT

assumes that the supplies are fully ramped to their nominal values (it does not matter which supply comes up first). Voltage ramp rates can vary

from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem.

Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for startup time. Assume

a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

Based on CLKIN cycles.

Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

The 4096 cycle count depends on t

SRST

specification in Table 21. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097

cycles maximum.

Rev. E | Page 24 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Clock Input

Figure 5. Power-Up Sequencing

Table 20. Clock Input

Parameter

266 MHz 300 MHz 350 MHz 400 MHz 450 MHz

UnitMin Max Min Max Min Max Min Max Min Max

Timing Requirements

CLKIN Period 30

Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.

100

Applies only for CLK_CFG1–0 = 01 and default values for PLL control bits in PMCTL.

26.66

100

22.8

100

17.75

100

CKL

CLKIN Width Low 15451345114510458.87545ns

CKH

CLKIN Width High 15 45 13 45 11 45 10 45 8.875 45 ns

CKRF

Guaranteed by simulation but not tested on silicon.

CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 3 3 3 ns

CCLK

Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t

CCLK

CCLK Period 3.75 10 3.33 10 2.85 10 2.5 10 2.22 10 ns

VCO

See Figure 4 on Page 22 for VCO diagram.

VCO Frequency 200 800 200 800 200 800 200 800 200 900 MHz

CKJ

6, 7

Actual input jitter should be combined with ac specifications for accurate timing analysis.

Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

CLKIN Jitter Tolerance –250 +250 –250 +250 –250 +250 –250 +250 –250 +250 ps

Figure 6. Clock Input

tRSTVDD

tCLKVDD

tCLKRST

tCORERST

tPLLRST

VDDEXT

VDDINT

CLKIN

CLK_CFG1–0

RESET

RESETOUT

tIVDDEVDD

CLKIN

tCK

tCKL

tCKH

tCKJ

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 25 of 68 | June 2017

Clock Signals

The ADSP-2148x can use an external clock or a crystal. See the

CLKIN pin description in Table 11 on Page 14. Programs can

configure the processor to use its internal clock generator by

connecting the necessary components to CLKIN and XTAL.

Figure 7 shows the component connections used for a crystal

operating in fundamental mode. Note that the clock rate is

achieved using a 25 MHz crystal and a PLL multiplier ratio 16:1

(CCLK:CLKIN achieves a clock speed of 400 MHz). To achieve

the full core clock rate, programs need to configure the multi-

plier bits in the PMCTL register.

Figure 7. Recommended Circuit for

Fundamental Mode Crystal Operation

2pF Y1

0ȍ

XTAL

CLKIN

22pF

25MHz

47ȍ

TYPICAL VALUES

ADSP-2148x

CHOOSE C1 AND C2 BASED ON THE CRYSTAL Y1.

R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE

POWER. REFER TO CRYSTAL MANUFACTURER’S

SPECIFICATIONS.

Rev. E | Page 26 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Reset

Running Reset

The following timing specification applies to

RESETOUT/RUNRSTIN pin when it is configured as

RUNRSTIN.

Table 21. Reset

Parameter Min Max Unit

Timing Requirements

WRST

RESET Pulse Width Low 4 × t

SRST

RESET Setup Before CLKIN Low 8 ns

Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μ while RESET is low, assuming stable

and CLKIN (not including start-up time of external clock oscillator).

Figure 8. Reset

CLKIN

RESET

tSRST

tWRST

Table 22. Running Reset

Parameter Min Max Unit

Timing Requirements

WRUNRST

Running RESET Pulse Width Low 4 × t

SRUNRST

Running RESET Setup Before CLKIN High 8 ns

Figure 9. Running Reset

CLKIN

RUNRSTIN

tWRUNRST tSRUNRST

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 27 of 68 | June 2017

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts, as well as the DAI_P20–1 and

DPI_P14–1 pins when they are configured as interrupts.

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (TMREXP).

Table 23. Interrupts

Parameter Min Max Unit

Timing Requirement

IPW

IRQx Pulse Width 2 × t

PCLK

+2 ns

Figure 10. Interrupts

INTERRUPT

INPUTS

tIPW

Table 24. Core Timer

Parameter Min Max Unit

Switching Characteristic

WCTIM

TMREXP Pulse Width 4 × t

PCLK

– 1 ns

Figure 11. Core Timer

FLAG3

(TMREXP)

tWCTIM

Rev. E | Page 28 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Timer PWM_OUT Cycle Timing

The following timing specification applies to timer0 and timer1

in PWM_OUT (pulse-width modulation) mode. Timer signals

are routed to the DPI_P14–1 pins through the DPI SRU. There-

fore, the timing specifications provided below are valid at the

DPI_P14–1 pins.

Timer WDTH_CAP Timing

The following timing specification applies to timer0 and timer1,

and in WDTH_CAP (pulse-width count and capture) mode.

Timer signals are routed to the DPI_P14–1 pins through the

SRU. Therefore, the timing specification provided below is valid

at the DPI_P14–1 pins.

Table 25. Timer PWM_OUT Timing

Parameter Min Max Unit

Switching Characteristic

PWMO

Timer Pulse Width Output 2 × t

PCLK

– 1.2 2 × (2

– 1) × t

PCLK

Figure 12. Timer PWM_OUT Timing

PWM

OUTPUTS

tPWMO

Table 26. Timer Width Capture Timing

Parameter Min Max Unit

Timing Requirement

PWI

Timer Pulse Width 2 × t

PCLK

2 × (2

– 1) × t

PCLK

Figure 13. Timer Width Capture Timing

TIMER

CAPTURE

INPUTS

tPWI

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 29 of 68 | June 2017

Watchdog Timer Timing

Pin to Pin Direct Routing (DAI and DPI)

For direct pin connections only (for example DAI_PB01_I to

DAI_PB02_O).

Table 27. Watchdog Timer Timing

Parameter Min Max Unit

Timing Requirement

WDTCLKPER

100 1000 ns

Switching Characteristics

RST

WDT Clock Rising Edge to Watchdog Timer

RESET Falling Edge

36.4 ns

RSTPW

Reset Pulse Width 64 × t

WDTCLKPER

Figure 14. Watchdog Timer Timing

WDT_CLKIN

WDTRSTO

tWDTCLKPER

tRST

tRSTPW

Table 28. DAI/DPI Pin to Pin Routing

Parameter Min Max Unit

Timing Requirement

DPIO

Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid 1.5 12 ns

Figure 15. DAI Pin to Pin Direct Routing

DAI_Pn

DPI_Pn

DAI_Pm

DPI_Pm

tDPIO

Rev. E | Page 30 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that

the precision clock generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

inputs and outputs are not directly routed to/from DAI pins (via

pin buffers), there is no timing data available. All timing param-

eters and switching characteristics apply to external DAI pins

(DAI_P01 – DAI_P20).

Table 29. Precision Clock Generator (Direct Pin Routing)

Parameter Min Max Unit

Timing Requirements

PCGIW

Input Clock Period t

PCLK

× 4 ns

STRIG

PCG Trigger Setup Before Falling Edge of PCG Input

Clock

4.5 ns

HTRIG

PCG Trigger Hold After Falling Edge of PCG Input

Clock

3ns

Switching Characteristics

DPCGIO

PCG Output Clock and Frame Sync Active Edge

Delay After PCG Input Clock

2.5 10 ns

DTRIGCLK

PCG Output Clock Delay After PCG Trigger 2.5 + (2.5 × t

PCGIP

) 10 + (2.5 × t

PCGIP

)ns

DTRIGFS

PCG Frame Sync Delay After PCG Trigger 2.5 + ((2.5 + D – PH) × t

PCGIP

) 10 + ((2.5 + D – PH) × t

PCGIP

)ns

PCGOW

Output Clock Period 2 × t

PCGIP

– 1 ns

D = FSxDIV, PH = FSxPHASE. For more information, see the “Precision Clock Generators” chapter in the hardware reference manual.

Normal mode of operation.

Figure 16. Precision Clock Generator (Direct Pin Routing)

DAI_Pn

DPI_Pn

PCG_TRIGx_I

DAI_Pm

DPI_Pm

PCG_EXTx_I

(CLKIN)

DAI_Py

DPI_Py

PCG_CLKx_O

DAI_Pz

DPI_Pz

PCG_FSx_O

tDTRIGFS

tDTRIGCLK

tDPCGIO

tSTRIG tHTRIG

tPCGOW

tDPCGIO

tPCGIP

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 31 of 68 | June 2017

Flags

The timing specifications provided below apply to the

DPI_P14–1, ADDR7–0, ADDR23–8, DATA7–0, and FLAG3–0

pins when configured as FLAGS. See Table 11 on Page 14 for

more information on flag use.

Table 30. Flags

Parameter Min Max Unit

Timing Requirement

FIPW

FLAGs IN Pulse Width 2 × t

PCLK

+ 3 ns

Switching Characteristic

FOPW

FLAGs OUT Pulse Width 2 × t

PCLK

– 3 ns

This is applicable when the Flags are connected to DPI_P14–1, ADDR7–0, ADDR23–8, DATA7–0 and FLAG3–0 pins.

Figure 17. Flags

FLAG

INPUTS

FLAG

OUTPUTS

tFOPW

tFIPW

Rev. E | Page 32 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

SDRAM Interface Timing (166 MHz SDCLK)

The maximum frequency for SDRAM is 166 MHz. For informa-

tion on SDRAM frequency and programming, see the hardware

reference manual, Engineer-to-Engineer Note Interfacing

SDRAM Memories to SHARC Processors (EE-286), and the

SDRAM vendor data sheet.

Table 31. SDRAM Interface Timing

Parameter Min Max Unit

Timing Requirements

SSDAT

DATA Setup Before SDCLK 0.7 ns

HSDAT

DATA Hold After SDCLK 1.23 ns

Switching Characteristics

SDCLK

SDCLK Period 6 ns

SDCLKH

SDCLK Width High 2.2 ns

SDCLKL

SDCLK Width Low 2.2 ns

DCAD

Command, ADDR, Data Delay After SDCLK 4 ns

HCAD

Command, ADDR, Data Hold After SDCLK 1 ns

DSDAT

Data Disable After SDCLK 5.3 ns

ENSDAT

Data Enable After SDCLK 0.3 ns

Systems should use the SDRAM model with a speed grade higher than the desired SDRAM controller speed. For example, to run the SDRAM controller at 166 MHz the

SDRAM model with a speed grade of 183 MHz or above should be used. See Engineer-to-Engineer Note Interfacing SDRAM Memories to SHARC Processors (EE-286) for

more information on hardware design guidelines for the SDRAM interface.

Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE.

Figure 18. SDRAM Interface Timing

SDCLK

DATA (IN)

DATA (OUT)

COMMAND/ADDR

(OUT)

tSDCLKH

tSDCLKL

tHSDAT

tSSDAT

tHCAD

tDCAD

tENSDAT

tDCAD tDSDAT

tHCAD

tSDCLK

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 33 of 68 | June 2017

AMI Read

Use these specifications for asynchronous interfacing to memo-

ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD,

AMI_WR, and strobe timing parameters only apply to asyn-

chronous access mode.

Table 32. AMI Read

Parameter Min Max Unit

Timing Requirements

DAD

1, 2,

Address Selects Delay to Data Valid W + t

SDCLK

–5.4 ns

DRLD

AMI_RD Low to Data Valid W – 3.2 ns

SDS

Data Setup to AMI_RD High 2.5 ns

HDRH

Data Hold from AMI_RD High 0 ns

DAAK

2, 6

AMI_ACK Delay from Address, Selects t

SDCLK

–9.5 + W ns

DSAK

AMI_ACK Delay from AMI_RD Low W – 7 ns

Switching Characteristics

DRHA

Address Selects Hold After AMI_RD High RHC + 0.20 ns

DARL

Address Selects to AMI_RD Low t

SDCLK

– 3.8 ns

AMI_RD Pulse Width W – 1.4 ns

RWR

AMI_RD High to AMI_RD Low HI + t

SDCLK

– 1 ns

W = (number of wait states specified in AMICTLx register) × t

SDCLK

RHC = (number of Read Hold Cycles specified in AMICTLx register) × t

SDCLK

Where PREDIS = 0

HI = RHC (if IC=0): Read to Read from same bank

HI = RHC + t

SDCLK

(if IC>0): Read to Read from same bank

HI = RHC + IC: Read to Read from different bank

HI = RHC + Max (IC, (4 × t

SDCLK

)): Read to Write from same or different bank

Where PREDIS = 1

HI = RHC + Max (IC, (4 × t

SDCLK

)): Read to Write from same or different bank

HI = RHC + (3 × t

SDCLK

): Read to Read from same bank

HI = RHC + Max (IC, (3 × t

SDCLK

): Read to Read from different bank

IC = (number of idle cycles specified in AMICTLx register) × t

SDCLK

H = (number of hold cycles specified in AMICTLx register) × tSDCLK

Data delay/setup: System must meet t

DAD

, t

DRLD

, or t

SDS.

The falling edge of MSx, is referenced.

The maximum limit of timing requirement values for t

DAD

and t

DRLD

parameters are applicable for the case where AMI_ACK is always high and when the ACK feature is not

used.

Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode.

Data hold: User must meet t

HDRH

in asynchronous access mode. See Test Conditions on Page 55 for the calculation of hold times given capacitive and dc loads.

AMI_ACK delay/setup: User must meet t

DAAK

, or t

DSAK

, for deassertion of AMI_ACK (low).

Rev. E | Page 34 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Figure 19. AMI Read

AMI_ACK

AMI_DATA

tDRHA

tRW

tHDRH

tRWR

tDAD

tDARL

tDRLD tSDS

tDSAK

tDAAK

AMI_WR

AMI_RD

AMI_ADDR

AMI_MSx

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 35 of 68 | June 2017

AMI Write

Use these specifications for asynchronous interfacing to memo-

ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD,

AMI_WR, and strobe timing parameters only apply to asyn-

chronous access mode.

Table 33. AMI Write

Parameter Min Max Unit

Timing Requirements

DAAK

1, 2

AMI_ACK Delay from Address, Selects t

SDCLK

– 9.7 + W ns

DSAK

1, 3

AMI_ACK Delay from AMI_WR Low W – 6 ns

Switching Characteristics

DAWH

Address Selects to AMI_WR Deasserted t

SDCLK

–3.1+ W ns

DAWL

Address Selects to AMI_WR Low t

SDCLK

–3 ns

AMI_WR Pulse Width W – 1.3 ns

DDWH

Data Setup Before AMI_WR High t

SDCLK

–3.7+ W ns

DWHA

Address Hold After AMI_WR Deasserted H + 0.15 ns

DWHD

Data Hold After AMI_WR Deasserted H ns

DATRWH

Data Disable After AMI_WR Deasserted t

SDCLK

– 4.3 + H t

SDCLK

+ 4.9 + H ns

WWR

AMI_WR High to AMI_WR Low t

SDCLK

–1.5+ H ns

DDWR

Data Disable Before AMI_RD Low 2 × t

SDCLK

– 6 ns

WDE

Data Enabled to AMI_WR Low t

SDCLK

– 3.7 ns

W = (number of wait states specified in AMICTLx register) × t

SDCLK

H = (number of hold cycles specified in AMICTLx register) × t

SDCLK

AMI_ACK delay/setup: System must meet t

DAAK

, or t

DSAK

, for deassertion of AMI_ACK (low).

The falling edge of MSx is referenced.

Note that timing for AMI_ACK, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode.

See Test Conditions on Page 55 for calculation of hold times given capacitive and dc loads.

For Write to Write: t

SDCLK

+ H, for both same bank and different bank. For Write to Read: 3 × t

SDCLK

+ H, for the same bank and different banks.

Figure 20. AMI Write

AMI_ACK

AMI_DATA

tDAWH tDWHA

tWWR

tDATRWH

tDWHD

tWW

tDDWR

tDDWH

tDAWL

tWDE

tDSAK

tDAAK

AMI_RD

AMI_WR

AMI_ADDR

AMI_MSx

Rev. E | Page 36 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Serial Ports

In slave transmitter mode and master receiver mode, the maxi-

mum serial port frequency is f

PCLK

/8. In master transmitter

mode and slave receiver mode, the maximum serial port clock

frequency is f

PCLK

/4. To determine whether communication is

possible between two devices at clock speed n, the following

specifications must be confirmed: 1) frame sync delay and frame

sync setup and hold; 2) data delay and data setup and hold; and

3) SCLK width.

Serial port signals (SCLK, frame sync, Data Channel A, Data

Channel B) are routed to the DAI_P20–1 pins using the SRU.

Therefore, the timing specifications provided below are valid at

the DAI_P20–1 pins.

Table 34. Serial Ports—External Clock

Parameter Min Max Unit

Timing Requirements

SFSE

Frame Sync Setup Before SCLK

(Externally Generated Frame Sync in either Transmit or Receive

Mode)

2.5

HFSE

Frame Sync Hold After SCLK

(Externally Generated Frame Sync in either Transmit or Receive

Mode)

2.5

SDRE

Receive Data Setup Before Receive SCLK 1.9 ns

HDRE

Receive Data Hold After SCLK 2.5 ns

SCLKW

SCLK Width (t

PCLK

× 4) ÷ 2 – 1.5 ns

SCLK

SCLK Period t

PCLK

× 4 ns

Switching Characteristics

DFSE

Frame Sync Delay After SCLK

(Internally Generated Frame Sync in either Transmit or Receive Mode)

10.25

HOFSE

Frame Sync Hold After SCLK

(Internally Generated Frame Sync in either Transmit or Receive Mode)

DDTE

Transmit Data Delay After Transmit SCLK 9 ns

HDTE

Transmit Data Hold After Transmit SCLK 2 ns

Referenced to sample edge.

Referenced to drive edge.

Table 35. Serial Ports—Internal Clock

Parameter Min Max Unit

Timing Requirements

SFSI

Frame Sync Setup Before SCLK

(Externally Generated Frame Sync in either Transmit or Receive Mode)

HFSI

Frame Sync Hold After SCLK

(Externally Generated Frame Sync in either Transmit or Receive Mode)

2.5

SDRI

Receive Data Setup Before SCLK 7 ns

HDRI

Receive Data Hold After SCLK 2.5 ns

Switching Characteristics

DFSI

Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode) 4 ns

HOFSI

Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode) –1 ns

DFSIR

Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode) 9.75 ns

HOFSIR

Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode) –1 ns

DDTI

Transmit Data Delay After SCLK 3.25 ns

HDTI

Transmit Data Hold After SCLK –2 ns

SCKLIW

Transmit or Receive SCLK Width 2 × t

PCLK

– 1.5 2 × t

PCLK

+ 1.5 ns

Referenced to the sample edge.

Referenced to drive edge.

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 37 of 68 | June 2017

Figure 21. Serial Ports

DRIVE EDGE SAMPLE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(FS)

DAI_P20–1

(SCLK)

tHOFSI tHFSI

tHDRI

DATA RECEIVE—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(FS)

DAI_P20–1

(SCLK)

tHFSI

tDDTI

DATA TRANSMIT—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(FS)

DAI_P20–1

(SCLK)

tHOFSE

tHOFSI

tHDTI

tHFSE

tHDTE

tDDTE

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(FS)

DAI_P20–1

(SCLK)

tHOFSE tHFSE

tHDRE

DATA RECEIVE—EXTERNAL CLOCK

tSCLKIW

tDFSI

tSFSI

tSDRI

tSCLKW

tDFSE

tSFSE

tSDRE

tDFSE

tSFSE

tSFSI

tDFSI

tSCLKIW tSCLKW

Rev. E | Page 38 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Table 36. Serial Ports—External Late Frame Sync

Parameter Min Max Unit

Switching Characteristics

DDTLFSE

Data Delay from Late External Transmit Frame Sync or External

Receive Frame Sync with MCE = 1, MFD = 0

8.5

DDTENFS

Data Enable for MCE = 1, MFD = 0 0.5 ns

The t

DDTLFSE

and t

DDTENFS

parameters apply to left-justified, as well as DSP serial mode, and MCE = 1, MFD = 0.

Figure 22. External Late Frame Sync

This figure reflects changes made to support left-justified mode.

DRIVE SAMPLE

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

2ND BIT

DAI_P20–1

(SCLK)

DAI_P20–1

(FS)

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

DRIVE

tDDTE/I

tHDTE/I

tDDTLFSE

tDDTENFS

tSFSE/I

DRIVE SAMPLE

LATE EXTERNAL TRANSMIT FS

2ND BIT

DAI_P20–1

(SCLK)

DAI_P20–1

(FS)

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

DRIVE

tDDTE/I

tHDTE/I

tDDTENFS

tSFSE/I

tHFSE/I

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 39 of 68 | June 2017

Table 37. Serial Ports—Enable and Three-State

Parameter Min Max Unit

Switching Characteristics

DDTEN

Data Enable from External Transmit SCLK 2 ns

DDTTE

Data Disable from External Transmit SCLK 11.5 ns

DDTIN

Data Enable from Internal Transmit SCLK –1.5 ns

Referenced to drive edge.

Figure 23. Serial Ports—Enable and Three-State

DRIVE EDGE

tDDTIN

tDDTEN tDDTTE

DAI_P20–1

(SCLK, INT)

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(SCLK, EXT)

DAI_P20–1

(DATA

CHANNEL A/B)

Rev. E | Page 40 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

The SPORTx_TDV_O output signal (routing unit) becomes

active in SPORT multichannel mode. During transmit slots

(enabled with active channel selection registers) the SPORTx-

_TDV_O is asserted for communication with external devices.

Table 38. Serial Ports—TDV (Transmit Data Valid)

Parameter Min Max Unit

Switching Characteristics

DRDVEN

TDV Assertion Delay from Drive Edge of External Clock 3 ns

DFDVEN

TDV Deassertion Delay from Drive Edge of External Clock 8 ns

DRDVIN

TDV Assertion Delay from Drive Edge of Internal Clock –1 ns

DFDVIN

TDV Deassertion Delay from Drive Edge of Internal Clock 2 ns

Referenced to drive edge.

Figure 24. Serial Ports—TDM Internal and External Clock

DRIVE EDGE DRIVE EDGE

DAI_P20–1

(SCLK, EXT)

tDRDVEN

tDFDVEN

DRIVE EDGE DRIVE EDGE

DAI_P20–1

(SCLK, INT)

tDRDVIN

tDFDVIN

TDVx

DAI_P20-1

TDVx

DAI_P20-1

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 41 of 68 | June 2017

Input Data Port (IDP)

The timing requirements for the IDP are given in Table 39. IDP

signals are routed to the DAI_P20–1 pins using the SRU. There-

fore, the timing specifications provided below are valid at the

DAI_P20–1 pins.

Table 39. Input Data Port (IDP)

Parameter Min Max Unit

Timing Requirements

SISFS

Frame Sync Setup Before Serial Clock Rising Edge 3.8 ns

SIHFS

Frame Sync Hold After Serial Clock Rising Edge 2.5 ns

SISD

Data Setup Before Serial Clock Rising Edge 2.5 ns

SIHD

Data Hold After Serial Clock Rising Edge 2.5 ns

IDPCLKW

Clock Width (t

PCLK

× 4) ÷ 2 – 1 ns

IDPCLK

Clock Period t

PCLK

× 4 ns

The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG's input can

be either CLKIN or any of the DAI pins.

Figure 25. IDP Master Timing

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

tIDPCLK

tIDPCLKW

tSISFS tSIHFS

tSIHD

tSISD

Rev. E | Page 42 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 40. PDAP is the parallel mode operation of Channel 0 of

the IDP. For details on the operation of the PDAP, see the

PDAP chapter of the hardware reference manual. Note that the

20 bits of external PDAP data can be provided through the

ADDR23–4 pins or over the DAI pins.

Table 40. Parallel Data Acquisition Port (PDAP)

Parameter Min Max Unit

Timing Requirements

SPHOLD

PDAP_HOLD Setup Before PDAP_CLK Sample Edge 2.5 ns

HPHOLD

PDAP_HOLD Hold After PDAP_CLK Sample Edge 2.5 ns

PDSD

PDAP_DAT Setup Before PDAP_CLK Sample Edge 3.85 ns

PDHD

PDAP_DAT Hold After PDAP_CLK Sample Edge 2.5 ns

PDCLKW

Clock Width (t

PCLK

× 4) ÷ 2 – 3 ns

PDCLK

Clock Period t

PCLK

× 4 ns

Switching Characteristics

PDHLDD

Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × t

PCLK

+ 3 ns

PDSTRB

PDAP Strobe Pulse Width 2 × t

PCLK

– 1.5 ns

Source pins of PDAP_DATA are ADDR23–4 or DAI pins. Source pins for PDAP_CLK and PDAP_HOLD are 1) DAI pins; 2) CLKIN through PCG; 3) DAI pins through

PCG; or 4) ADDR3–2 pins.

Figure 26. PDAP Timing

DAI_P20–1

(PDAP_CLK)

SAMPLE EDGE

DAI_P20–1

(PDAP_HOLD)

DAI_P20–1

(PDAP_STROBE)

tPDSTRB

tPDHLDD

tPDHD

tPDSD

tSPHOLD tHPHOLD

tPDCLK

tPDCLKW

DAI_P20–1/

ADDR23–4

(PDAP_DATA)

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 43 of 68 | June 2017

Sample Rate Converter—Serial Input Port

The ASRC input signals are routed from the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided in

Table 41 are valid at the DAI_P20–1 pins.

Table 41. ASRC, Serial Input Port

Parameter Min Max Unit

Timing Requirements

SRCSFS

Frame Sync Setup Before Serial Clock Rising Edge 4 ns

SRCHFS

Frame Sync Hold After Serial Clock Rising Edge 5.5 ns

SRCSD

Data Setup Before Serial Clock Rising Edge 4 ns

SRCHD

Data Hold After Serial Clock Rising Edge 5.5 ns

SRCCLKW

Clock Width (t

PCLK

× 4) ÷ 2 – 1 ns

SRCCLK

Clock Period t

PCLK

× 4 ns

The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input

can be either CLKIN or any of the DAI pins.

Figure 27. ASRC Serial Input Port Timing

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

tSRCCLK

tSRCCLKW

tSRCSFS tSRCHFS

tSRCHD

tSRCSD

Rev. E | Page 44 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Sample Rate Converter—Serial Output Port

For the serial output port, the frame sync is an input, and it

should meet setup and hold times with regard to SCLK on the

output port. The serial data output has a hold time and delay

specification with regard to serial clock. Note that serial clock

rising edge is the sampling edge, and the falling edge is the

drive edge.

Table 42. ASRC, Serial Output Port

Parameter Min Max Unit

Timing Requirements

SRCSFS

Frame Sync Setup Before Serial Clock Rising Edge 4 ns

SRCHFS

Frame Sync Hold After Serial Clock Rising Edge 5.5 ns

SRCCLKW

Clock Width (t

PCLK

× 4) ÷ 2 – 1 ns

SRCCLK

Clock Period t

PCLK

× 4 ns

Switching Characteristics

SRCTDD

Transmit Data Delay After Serial Clock Falling Edge 9.9 ns

SRCTDH

Transmit Data Hold After Serial Clock Falling Edge 1 ns

The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input

can be either CLKIN or any of the DAI pins.

Figure 28. ASRC Serial Output Port Timing

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

tSRCCLK

tSRCCLKW

tSRCSFS tSRCHFS

tSRCTDD

tSRCTDH

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 45 of 68 | June 2017

Pulse-Width Modulation Generators (PWM)

The following timing specifications apply when the

ADDR23–8/DPI_14–1 pins are configured as PWM.

S/PDIF Transmitter

Serial data input to the S/PDIF transmitter can be formatted as

left-justified, I

S, or right-justified with word widths of 16, 18,

20, or 24 bits. The following sections provide timing for the

transmitter.

S/PDIF Transmitter-Serial Input Waveforms

Figure 30 shows the right-justified mode. Frame sync is high for

the left channel and low for the right channel. Data is valid on

the rising edge of serial clock. The MSB is delayed the minimum

in 24-bit output mode or the maximum in 16-bit output mode

from a frame sync transition, so that when there are 64 serial

clock periods per frame sync period, the LSB of the data is right-

justified to the next frame sync transition.

Table 43. Pulse-Width Modulation (PWM) Timing

Parameter Min Max Unit

Switching Characteristics

PWMW

PWM Output Pulse Width t

PCLK

– 2 (2

– 2) × t

PCLK

PWMP

PWM Output Period 2 × t

PCLK

– 1.5 (2

– 1) × t

PCLK

Figure 29. PWM Timing

PWM

OUTPUTS

tPWMW

tPWMP

Table 44. S/PDIF Transmitter Right-Justified Mode

Parameter Nominal Unit

Timing Requirement

RJD

Frame Sync to MSB Delay in Right-Justified Mode

16-Bit Word Mode

18-Bit Word Mode

20-Bit Word Mode

24-Bit Word Mode

SCLK

Figure 30. Right-Justified Mode

MSB

LEFT/RIGHT CHANNEL

LSB LSBMSB–1 MSB–2 LSB+2 LSB+1

DAI_P20–1

SCLK

DAI_P20–1

SDATA

tRJD

Rev. E | Page 46 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Figure 31 shows the default I

S-justified mode. The frame sync

is low for the left channel and HI for the right channel. Data is

valid on the rising edge of serial clock. The MSB is left-justified

to the frame sync transition but with a delay.

Figure 32 shows the left-justified mode. The frame sync is high

for the left channel and low for the right channel. Data is valid

on the rising edge of serial clock. The MSB is left-justified to the

frame sync transition with no delay.

Table 45. S/PDIF Transmitter I

S Mode

Parameter Nominal Unit

Timing Requirement

I2SD

Frame Sync to MSB Delay in I

S Mode 1 SCLK

Figure 31. I

S-Justified Mode

MSB

LEFT/RIGHT CHANNEL

LSBMSB–1 MSB–2 LSB+2 LSB+1

DAI_P20–1

SCLK

DAI_P20–1

SDATA

tI2SD

Table 46. S/PDIF Transmitter Left-Justified Mode

Parameter Nominal Unit

Timing Requirement

LJD

Frame Sync to MSB Delay in Left-Justified Mode 0 SCLK

Figure 32. Left-Justified Mode

MSB

LEFT/RIGHT CHANNEL

LSBMSB–1 MSB–2 LSB+2 LSB+1

DAI_P20–1

SCLK

DAI_P20–1

SDATA

tLJD

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 47 of 68 | June 2017

S/PDIF Transmitter Input Data Timing

The timing requirements for the S/PDIF transmitter are given

in Table 47. Input signals are routed to the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided

below are valid at the DAI_P20–1 pins.

Oversampling Clock (TxCLK) Switching Characteristics

The S/PDIF transmitter requires an oversampling clock input.

This high frequency clock (TxCLK) input is divided down to

generate the internal biphase clock.

Table 47. S/PDIF Transmitter Input Data Timing

Parameter Min Max Unit

Timing Requirements

SISFS

Frame Sync Setup Before Serial Clock Rising Edge 3 ns

SIHFS

Frame Sync Hold After Serial Clock Rising Edge 3 ns

SISD

Data Setup Before Serial Clock Rising Edge 3 ns

SIHD

Data Hold After Serial Clock Rising Edge 3 ns

SITXCLKW

Transmit Clock Width 9 ns

SITXCLK

Transmit Clock Period 20 ns

SISCLKW

Clock Width 36 ns

SISCLK

Clock Period 80 ns

The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can

be either CLKIN or any of the DAI pins.

Figure 33. S/PDIF Transmitter Input Timing

SAMPLE EDGE

DAI_P20–1

(TxCLK)

DAI_P20–1

(SCLK)

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

tSITXCLKW tSITXCLK

tSISCLKW

tSISCLK

tSISFS tSIHFS

tSISD tSIHD

Table 48. Oversampling Clock (TxCLK) Switching Characteristics

Parameter Max Unit

Frequency for TxCLK = 384 × Frame Sync Oversampling Ratio × Frame Sync ≤ 1/t

SITXCLK

MHz

Frequency for TxCLK = 256 × Frame Sync 49.2 MHz

Frame Rate (FS) 192.0 kHz

Rev. E | Page 48 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

S/PDIF Receiver

The following section describes timing as it relates to the

S/PDIF receiver.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL

(digital PLL) generates the 512 × FS clock.

Table 49. S/PDIF Receiver Internal Digital PLL Mode Timing

Parameter Min Max Unit

Switching Characteristics

DFSI

Frame Sync Delay After Serial Clock 5 ns

HOFSI

Frame Sync Hold After Serial Clock –2 ns

DDTI

Transmit Data Delay After Serial Clock 5 ns

HDTI

Transmit Data Hold After Serial Clock –2 ns

SCLKIW

Transmit Serial Clock Width 8 × t

PCLK

– 2 ns

SCLK frequency is 64 × FS where FS = the frequency of frame sync.

Figure 34. S/PDIF Receiver Internal Digital PLL Mode Timing

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(DATA CHANNEL

A/B)

DRIVE EDGE

tSCLKIW

tDFSI

tHOFSI

tDDTI

tHDTI

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 49 of 68 | June 2017

SPI Interface—Master

The ADSP-2148x contains two SPI ports. Both primary and sec-

ondary are available through DPI only. The timing provided in

Table 50 and Table 51 applies to both.

Table 50. SPI Interface Protocol—Master Switching and Timing Specifications

Parameter Min Max Unit

Timing Requirements

SSPIDM

Data Input Valid to SPICLK Edge (Data Input Setup Time) 8.2 ns

HSPIDM

SPICLK Last Sampling Edge to Data Input Not Valid 2 ns

Switching Characteristics

SPICLKM

Serial Clock Cycle 8 × t

PCLK

– 2 ns

SPICHM

Serial Clock High Period 4 × t

PCLK

– 2 ns

SPICLM

Serial Clock Low Period 4 × t

PCLK

– 2 ns

DDSPIDM

SPICLK Edge to Data Out Valid (Data Out Delay Time) 2.5 ns

HDSPIDM

SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 4 × t

PCLK

– 2 ns

SDSCIM

DPI Pin (SPI Device Select) Low to First SPICLK Edge 4 × t

PCLK

– 2 ns

HDSM

Last SPICLK Edge to DPI Pin (SPI Device Select) High 4 × t

PCLK

– 2 ns

SPITDM

Sequential Transfer Delay 4 × t

PCLK

– 1.2 ns

Figure 35. SPI Master Timing

tSPICHM

tSDSCIM tSPICLM tSPICLKM tHDSM tSPITDM

tDDSPIDM

tHSPIDM

tSSPIDM

DPI

(OUTPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

CPHASE = 1

CPHASE = 0

tHDSPIDM

tHSPIDM

tSSPIDM tSSPIDM

tDDSPIDM

tHDSPIDM

SPICLK

(CP = 0,

CP = 1)

(OUTPUT)

Rev. E | Page 50 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

SPI Interface—Slave

Table 51. SPI Interface Protocol—Slave Switching and Timing Specifications

Parameter Min Max Unit

Timing Requirements

SPICLKS

Serial Clock Cycle 4 × t

PCLK

– 2 ns

SPICHS

Serial Clock High Period 2 × t

PCLK

– 2 ns

SPICLS

Serial Clock Low Period 2 × t

PCLK

– 2 ns

SDSCO

SPIDS Assertion to First SPICLK Edge

CPHASE = 0

CPHASE = 1

2 × t

PCLK

HDS

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 2 × t

PCLK

SSPIDS

Data Input Valid to SPICLK edge (Data Input Set-up Time) 2 ns

HSPIDS

SPICLK Last Sampling Edge to Data Input Not Valid 2 ns

SDPPW

SPIDS Deassertion Pulse Width (CPHASE=0) 2 × t

PCLK

Switching Characteristics

DSOE

SPIDS Assertion to Data Out Active 0 7.5 ns

DSOE

SPIDS Assertion to Data Out Active (SPI2) 0 7.5 ns

DSDHI

SPIDS Deassertion to Data High Impedance 0 10.5 ns

DSDHI

SPIDS Deassertion to Data High Impedance (SPI2) 0 10.5 ns

DDSPIDS

SPICLK Edge to Data Out Valid (Data Out Delay Time) 9.5 ns

HDSPIDS

SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × t

PCLK

DSOV

SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × t

PCLK

The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the “Serial Peripheral Interface Port” chapter of

the hardware reference manual.

Figure 36. SPI Slave Timing

tSPICHS tSPICLS tSPICLKS tHDS tSDPPW

tSDSCO

tDSOE

tDDSPIDS

tDSDHI

tHDSPIDS

tHSPIDS

tSSPIDS

tDSDHI

tDSOV

tHSPIDS

tHDSPIDS

SPIDS

(INPUT)

MISO

(OUTPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

MOSI

(INPUT)

CPHASE = 1

CPHASE = 0

SPICLK

(CP = 0,

CP = 1)

(INPUT)

tSSPIDS

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 51 of 68 | June 2017

Media Local Bus

All the numbers given are applicable for all speed modes

(1024 FS, 512 FS and 256 FS for 3-pin; 512 FS and 256 FS for

5-pin), unless otherwise specified. Please refer to the MediaLB

specification document revision 3.0 for more details.

Table 52. MLB Interface, 3-Pin Specifications

Parameter Min Typ Max Unit

3-Pin Characteristics

MLBCLK

MLB Clock Period

1024 FS

512 FS

256 FS

20.3

MCKL

MLBCLK Low Time

1024 FS

512 FS

256 FS

6.1

MCKH

MLBCLK High Time

1024 FS

512 FS

256 FS

9.3

MCKR

MLBCLK Rise Time (V

to V

)

1024 FS

512 FS/256 FS

MCKF

MLBCLK Fall Time (V

to V

)

1024 FS

512 FS/256 FS

MPWV

MLBCLK Pulse Width Variation

1024 FS

512 FS/256

0.7

2.0

nspp

DSMCF

DAT/SIG Input Setup Time 1 ns

DHMCF

DAT/SIG Input Hold Time 2 ns

MCFDZ

DAT/SIG Output Time to Three-state 0 15 ns

MCDRV

DAT/SIG Output Data Delay From MLBCLK Rising Edge 8 ns

MDZH

Bus Hold Time

1024 FS

512 FS/256

MLB

DAT/SIG Pin Load

1024 FS

512 FS/256

Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp).

The board must be designed to ensure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be

minimized while meeting the maximum capacitive load listed.

Rev. E | Page 52 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Figure 37. MLB Timing (3-Pin Interface)

Table 53. MLB Interface, 5-Pin Specifications

Parameter Min Typ Max Unit

5-Pin Characteristics

MLBCLK

MLB Clock Period

512 FS

256 FS

MCKL

MLBCLK Low Time

512 FS

256 FS

MCKH

MLBCLK High Time

512 FS

256 FS

MCKR

MLBCLK Rise Time (V

to V

)6ns

MCKF

MLBCLK Fall Time (V

to V

)6ns

MPWV

MLBCLK Pulse Width Variation 2 nspp

DSMCF

DAT/SIG Input Setup Time 3 ns

DHMCF

DAT/SIG Input Hold Time 5 ns

MCDRV

DS/DO Output Data Delay From MLBCLK Rising Edge 8 ns

MCRDL

DO/SO Low From MLBCLK High

512 FS

256 FS

MLB

DS/DO Pin Load 40 pf

Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp).

Gate Delays due to OR'ing logic on the pins must be accounted for.

When a node is not driving valid data onto the bus, the MLBSO and MLBDO output lines shall remain low. If the output lines can float at anytime, including while in reset,

external pull-down resistors are required to keep the outputs from corrupting the MediaLB signal lines when not being driven.

tMCKH

MLBSIG/

MLBDAT

(Rx, Input)

tMCKL

tMCKR

MLBSIG/

MLBDAT

(Tx, Output)

tMCFDZ

tDSMCF

MLBCLK

tMLBCLK

VALID

tDHMCF

tMCKF

tMCDRV

VALID

tMDZH

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 53 of 68 | June 2017

Universal Asynchronous Receiver-Transmitter

(UART) Ports—Receive and Transmit Timing

For information on the UART port receive and transmit opera-

tions, see the hardware reference manual.

2-Wire Interface (TWI)—Receive and Transmit Timing

For information on the TWI receive and transmit operations,

see the hardware reference manual.

Figure 38. MLB Timing (5-Pin Interface)

Figure 39. MLB 3-Pin and 5-Pin MLBCLK Pulse Width Variation Timing

tMCKH

MLBSIG/

MLBDAT

(Rx, Input)

tMCKL

tMCKR

MLBSO/

MLBDO

(Tx, Output)

tMCRDL

tDSMCF

MLBCLK

tMLBCLK

VALID

tDHMCF

tMCKF

tMCDRV

tMPWV tMPWV

MLBCLK

Rev. E | Page 54 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

JTAG Test Access Port and Emulation

Table 54. JTAG Test Access Port and Emulation

Parameter Min Max Unit

Timing Requirements

TCK

TCK Period 20 ns

STAP

TDI, TMS Setup Before TCK High 5 ns

HTAP

TDI, TMS Hold After TCK High 6 ns

SSYS

System Inputs = DATA15–0, CLK_CFG1–0, RESET, BOOT_CFG2–0, DAI_Px, DPI_Px, and FLAG3–0.

System Inputs Setup Before TCK High 7 ns

HSYS

System Inputs Hold After TCK High 18 ns

TRSTW

TRST Pulse Width 4t

Switching Characteristics

DTDO

TDO Delay from TCK Low 10 ns

DSYS

System Outputs = DAI_Px, DPI_Px ADDR23–0, AMI_RD, AMI_WR, FLAG3–0, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, SDCLK and EMU.

System Outputs Delay After TCK Low t

TCK

÷ 2 + 7 ns

Figure 40. IEEE 1149.1 JTAG Test Access Port

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

tTCK

tSTAP tHTAP

tDTDO

tSSYS tHSYS

tDSYS

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 55 of 68 | June 2017

OUTPUT DRIVE CURRENTS

Figure 41 shows typical I-V characteristics for the output driv-

ers of the ADSP-2148x, and Table 55 shows the pins associated

with each driver. The curves represent the current drive capabil-

ity of the output drivers as a function of output voltage.

TEST CONDITIONS

The ac signal specifications (timing parameters) appear in

Table 21 on Page 26 through Table 54 on Page 54. These include

output disable time, output enable time, and capacitive loading.

The timing specifications for the SHARC apply for the voltage

reference levels in Figure 42.

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 43. All delays (in nanoseconds) are mea-

sured between the point that the first signal reaches 1.5 V and

the point that the second signal reaches 1.5 V.

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 42). Figure 46 and Figure 47 show

graphically how output delays and holds vary with load capaci-

tance. The graphs of Figure 44 through Figure 47 may not be

linear outside the ranges shown for Typical Output Delay vs.

Load Capacitance and Typical Output Rise Time (20% to 80%,

V = Min) vs. Load Capacitance.

Table 55. Driver Types

Driver Type Associated Pins

A FLAG[0–3], AMI_ADDR[0–23], DATA[0–15],

AMI_RD, AMI_WR, AMI_ACK, MS[1-0], SDRAS,

SDCAS, SDWE, SDDQM, SDCKE, SDA10, EMU, TDO,

RESETOUT, DPI[1–14], DAI[1–20], WDTRSTO,

MLBDAT, MLBSIG, MLBSO, MLBDO, MLBCLK

BSDCLK

Figure 41. Typical Drive at Junction Temperature

Figure 43. Voltage Reference Levels for AC Measurements

SWEEP (VDDEXT) VOLTAGE (V)

03.50.5 1.0 1.5 2.0 2.5 3.0

100

200

SOURCE/SINK (V

DDEXT

) CURRENT (mA)

150

100

200

150

VOH 3.13 V, 125 °C

VOL 3.13 V, 125 °C

TYPE A

TYPE B

INPUT

OUTPUT

1.5V 1.5V

Figure 42. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

Figure 44. Typical Output Rise/Fall Time

(20% to 80%, V

DD_EXT

= Max)

ZO = 50:(impedance)

TD = 4.04 r 1.18 ns

2pF

TESTER PIN ELECTRONICS

50:

0.5pF

70:

400:

45:

4pF

NOTES:

THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

VLOAD

DUT

OUTPUT

50:

LOAD CAPACITANCE (pF)

RISE AND FALL TIMES (ns)

125 20010025 17550 75 150

5y = 0.0341x + 0.3093

y = 0.0153x + 0.2131

y = 0.0414x + 0.2661

y = 0.0152x + 0.1882

TYPE A DRIVE FALL

TYPE A DRIVE RISE

TYPE B DRIVE FALL

TYPE B DRIVE RISE

Rev. E | Page 56 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

THERMAL CHARACTERISTICS

The ADSP-2148x processor is rated for performance over the

temperature range specified in Operating Conditions on

Page 18.

Table 57 airflow measurements comply with JEDEC standards

JESD51-2 and JESD51-6, and the junction-to-board measure-

ment complies with JESD51-8. Test board design complies with

JEDEC standards JESD51-7 (LQFP_EP). The junction-to-case

measurement complies with MIL- STD-883. All measurements

use a 2S2P JEDEC test board.

To determine the junction temperature of the device while on

the application PCB, use:

where:

= junction temperature °C

CASE

= case temperature (°C) measured at the top center of the

package



= junction-to-top (of package) characterization parameter

is the Typical value from Table 57.

= power dissipation

Values of 

are provided for package comparison and PCB

design considerations. 

can be used for a first order approxi-

mation of T

by the equation:

where:

= ambient temperature °C

Values of 

are provided for package comparison and PCB

design considerations when an external heatsink is required.

Figure 45. Typical Output Rise/Fall Time

(20% to 80%, V

DD_EXT

= Min)

Figure 46. Typical Output Rise/Fall Delay

DD_EXT

= Max)

LOAD CAPACITANCE (pF)

RISE AND FALL TIMES (ns)

25 20015050 75 100 125 175

y = 0.0571x + 0.5558

y = 0.0278x + 0.3138

y = 0.0258x + 0.3684

TYPE A DRIVE FALL

TYPE A DRIVE RISE

TYPE B DRIVE RISE

TYPE B DRIVE FALL

y = 0.0747x + 0.5154

LOAD CAPACITANCE (pF)

3.5

0.5

1.5

RISE AND FALL DELAY (ns)

2.5

y = 0.0152x + 1.7607

y = 0.0068x + 1.7614

y = 0.0196x + 1.2945

y = 0.0074x + 1.421

0 25 20015050 75 100 125 175

TYPE A DRIVE FALL

TYPE A DRIVE RISE

TYPE B DRIVE RISE

TYPE B DRIVE FALL

4.5

Figure 47. Typical Output Rise/Fall Delay

DD_EXT

= Min)

LOAD CAPACITANCE (pF)

RISE AND FALL TIMES DELAY (ns)

125 20010025 17550 75 150

y = 0.0256x + 3.5859

y = 0.0116x + 3.5697

y = 0.0359x + 2.924

y = 0.0136x + 3.1135

TYPE A DRIVE FALL TYPE A DRIVE RISE

TYPE B DRIVE FALL

TYPE B DRIVE RISE

TJTCASE



JT PD

+=

TJTA



JA PD

+=

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 57 of 68 | June 2017

Note that the thermal characteristics values provided in

Table 56 and Table 57 are modeled values.

Thermal Diode

The ADSP-2148x processors incorporate thermal diode/s to

monitor the die temperature. The thermal diode of is a

grounded collector, PNP Bipolar Junction Transistor (BJT). The

THD_P pin is connected to the emitter and the THD_M pin is

connected to the base of the transistor. These pins can be used

by an external temperature sensor (such as ADM 1021A or

LM86 or others) to read the die temperature of the chip.

The technique used by the external temperature sensor is to

measure the change in VBE when the thermal diode is operated

at two different currents. This is shown in the following

equation:

where:

n = multiplication factor close to 1, depending on process

variations

k = Boltzmann’s constant

T = temperature (°C)

q = charge of the electron

N = ratio of the two currents

The two currents are usually in the range of 10 micro Amperes

to 300 micro Amperes for the common temperature sensor

chips available.

Table 58 contains the thermal diode specifications using the

transistor model.

Table 56. Thermal Characteristics for 100-Lead LQFP_EP

Parameter Condition Typical Unit



Airflow = 0 m/s 17.8 °C/W



JMA

Airflow = 1 m/s 15.4 °C/W



JMA

Airflow = 2 m/s 14.6 °C/W



2.4 °C/W



Airflow = 0 m/s 0.24 °C/W



JMT

Airflow = 1 m/s 0.37 °C/W



JMT

Airflow = 2 m/s 0.51 °C/W

Table 57. Thermal Characteristics for 176-Lead LQFP_EP

Parameter Condition Typical Unit



Airflow = 0 m/s 16.9 °C/W



JMA

Airflow = 1 m/s 14.6 °C/W



JMA

Airflow = 2 m/s 13.8 °C/W



2.3 °C/W



Airflow = 0 m/s 0.21 °C/W



JMT

Airflow = 1 m/s 0.32 °C/W



JMT

Airflow = 2 m/s 0.41 °C/W

VBE nkT

------ In(N)=

Table 58. Thermal Diode Parameters – Transistor Model

Symbol Parameter Min Typ Max Unit

Forward Bias Current 10 300 A

Emitter Current 10 300 A

Transistor Ideality 1.012 1.015 1.017

Series Resistance 0.12 0.2 0.28 

See Engineer-to-Engineer Note Using the On-Chip Thermal Diode on Analog Devices Processors (EE-346).

Analog Devices does not recommend operation of the thermal diode under reverse bias.

Specified by design characterization.

The ideality factor, nQ, represents the deviation from ideal diode behavior as exemplified by the diode equation: I

= I

× (e

qVBE/nqkT

–1) where I

= saturation current,

q = electronic charge, V

= voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin).

The series resistance (R

) can be used for more accurate readings as needed.

Rev. E | Page 58 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

100-LQFP_EP LEAD ASSIGNMENT

Table 59. 100-Lead LQFP_EP Lead Assignments (Numerical by Lead Number)

Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No.

DD_INT

DD_EXT

26 DAI_P10 51 V

DD_INT

CLK_CFG1 2 DPI_P08 27 V

DD_INT

52 FLAG0 77

BOOT_CFG0 3 DPI_P07 28 V

DD_EXT

53 V

DD_INT

DD_EXT

DD_INT

29 DAI_P20 54 V

DD_INT

5 DPI_P09 30 V

DD_INT

55 FLAG1 80

BOOT_CFG1 6 DPI_P10 31 DAI_P08 56 FLAG2 81

GND 7 DPI_P11 32 DAI_P04 57 FLAG3 82

NC 8 DPI_P12 33 DAI_P14 58 MLBCLK 83

NC 9 DPI_P13 34 DAI_P18 59 MLBDAT 84

CLK_CFG0 10 DAI_P03 35 DAI_P17 60 MLBDO 85

DD_INT

11 DPI_P14 36 DAI_P16 61 V

DD_EXT

CLKIN 12 V

DD_INT

37 DAI_P15 62 MLBSIG 87

XTAL 13 V

DD_INT

38 DAI_P12 63 V

DD_INT

DD_EXT

14 V

DD_INT

39 V

DD_INT

64 MLBSO 89

DD_INT

15 DAI_P13 40 DAI_P11 65 TRST 90

DD_INT

16 DAI_P07 41 V

DD_INT

66 EMU 91

RESETOUT/RUNRSTIN 17 DAI_P19 42 V

DD_INT

67 TDO 92

DD_INT

18 DAI_P01 43 GND 68 V

DD_EXT

DPI_P01 19 DAI_P02 44 THD_M 69 V

DD_INT

DPI_P02 20 V

DD_INT

45 THD_P 70 TDI 95

DPI_P03 21 V

DD_EXT

46 V

DD_THD

71 TCK 96

DD_INT

22 V

DD_INT

47 V

DD_INT

72 V

DD_INT

DPI_P05 23 DAI_P06 48 V

DD_INT

73 RESET 98

DPI_P04 24 DAI_P05 49 V

DD_INT

74 TMS 99

DPI_P06 25 DAI_P09 50 V

DD_INT

75 V

DD_INT

100

GND 101*

MLB pins (pins 83, 84, 85, 87, and 89) are available for automotive models only. For non-automotive models, these pins should be connected

to ground (GND).

* Pin no. 101 (exposed pad) is the GND supply (see Figure 48 and Figure 49) for the processor; this pad must be robustly connected to GND.

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 59 of 68 | June 2017

Figure 48 shows the top view of the 100-lead LQFP_EP lead

configuration. Figure 49 shows the bottom view of the 100-lead

LQFP_EP lead configuration.

Figure 48. 100-Lead LQFP_EP Lead Configuration (Top View)

LEAD 1

LEAD 25

LEAD 75

LEAD 51

LEAD 100 LEAD 76

LEAD 26 LEAD 50

LEAD 1 INDICATOR

ADSP-2148x

100-LEAD LQFP_EP

TOP VIEW

Figure 49. 100-Lead LQFP_EP Lead Configuration (Bottom View)

LEAD 75

LEAD 51

LEAD 1

LEAD 25

LEAD 76 LEAD 100

LEAD 50 LEAD 26

LEAD 1 INDICATOR

GND PAD

(LEAD 101)

ADSP-2148x

100-LEAD LQFP_EP

BOTTOM VIEW

Rev. E | Page 60 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

176-LEAD LQFP_EP LEAD ASSIGNMENT

Table 60. ADSP-21486 176-Lead LQFP_EP Lead Assignment (Numerical by Lead Number)

Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No.

NC 1 V

DD_EXT

45 DAI_P10 89 V

DD_INT

133

MS0 2DPI_P08 46V

DD_INT

90 FLAG0 134

NC 3 DPI_P07 47 V

DD_EXT

91 FLAG1 135

DD_INT

48 DAI_P20 92 FLAG2 136

CLK_CFG1 5 DPI_P09 49 V

DD_INT

93 GND 137

ADDR0 6 DPI_P10 50 DAI_P08 94 FLAG3 138

BOOT_CFG0 7 DPI_P11 51 DAI_P14 95 GND 139

DD_EXT

8 DPI_P12 52 DAI_P04 96 GND 140

ADDR1 9 DPI_P13 53 DAI_P18 97 V

DD_EXT

141

ADDR2 10 DPI_P14 54 DAI_P17 98 GND 142

ADDR3 11 DAI_P03 55 DAI_P16 99 V

DD_INT

143

ADDR4 12 NC 56 DAI_P12 100 TRST 144

ADDR5 13 V

DD_EXT

57 DAI_P15 101 GND 145

BOOT_CFG1 14 NC 58 V

DD_INT

102 EMU 146

GND 15 NC 59 DAI_P11 103 DATA0 147

ADDR6 16 NC 60 V

DD_EXT

104 DATA1 148

ADDR7 17 NC 61 V

DD_INT

105 DATA2 149

NC 18 V

DD_INT

62 BOOT_CFG2 106 DATA3 150

NC 19 NC 63 V

DD_INT

107 TDO 151

ADDR8 20 NC 64 AMI_ACK 108 DATA4 152

ADDR9 21 V

DD_INT

65 GND 109 V

DD_EXT

153

CLK_CFG0 22 NC 66 THD_M 110 DATA5 154

DD_INT

23 NC 67 THD_P 111 DATA6 155

CLKIN 24 V

DD_INT

68 V

DD_THD

112 V

DD_INT

156

XTAL 25 NC 69 V

DD_INT

113 DATA7 157

ADDR10 26 WDTRSTO 70 V

DD_INT

114 TDI 158

NC 27 NC 71 MS1 115 NC 159*

DD_EXT

28 V

DD_EXT

72 V

DD_INT

116 V

DD_EXT

160

DD_INT

29 DAI_P07 73 WDT_CLKO 117 DATA8 161

ADDR11 30 DAI_P13 74 WDT_CLKIN 118 DATA9 162

ADDR12 31 DAI_P19 75 V

DD_EXT

119 DATA10 163

ADDR17 32 DAI_P01 76 ADDR23 120 TCK 164

ADDR13 33 DAI_P02 77 ADDR22 121 DATA11 165

DD_INT

34 V

DD_INT

78 ADDR21 122 DATA12 166

ADDR18 35 NC 79 V

DD_INT

123 DATA14 167

RESETOUT/RUNRSTIN 36 NC 80 ADDR20 124 DATA13 168

DD_INT

37 NC 81 ADDR19 125 V

DD_INT

169

DPI_P01 38 NC 82 V

DD_EXT

126 DATA15 170

DPI_P02 39 NC 83 ADDR16 127 NC 171

DPI_P03 40 V

DD_EXT

84 ADDR15 128 NC 172

DD_INT

41 V

DD_INT

85 V

DD_INT

129 RESET 173

DPI_P05 42 DAI_P06 86 ADDR14 130 TMS 174

DPI_P04 43 DAI_P05 87 AMI_WR 131 NC 175

DPI_P06 44 DAI_P09 88 AMI_RD 132 V

DD_INT

176

GND 177**

*No external connection should be made to this pin. Use as NC only.

** Lead no. 177 (exposed pad) is the GND supply (see Figure 50 and Figure 51) for the processor; this pad must be robustly connected to GND.

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 61 of 68 | June 2017

Table 61. ADSP-21483, ADSP-21487, ADSP-21488, and ADSP-21489 176-Lead LQFP_EP Lead Assignment

(Numerical by Lead Number)

Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No.

SDDQM 1 V

DD_EXT

45 DAI_P10 89 V

DD_INT

133

MS0 2DPI_P08 46V

DD_INT

90 FLAG0 134

SDCKE 3 DPI_P07 47 V

DD_EXT

91 FLAG1 135

DD_INT

48 DAI_P20 92 FLAG2 136

CLK_CFG1 5 DPI_P09 49 V

DD_INT

93 GND 137

ADDR0 6 DPI_P10 50 DAI_P08 94 FLAG3 138

BOOT_CFG0 7 DPI_P11 51 DAI_P14 95 GND 139

DD_EXT

8 DPI_P12 52 DAI_P04 96 GND 140

ADDR1 9 DPI_P13 53 DAI_P18 97 V

DD_EXT

141

ADDR2 10 DPI_P14 54 DAI_P17 98 GND 142

ADDR3 11 DAI_P03 55 DAI_P16 99 V

DD_INT

143

ADDR4 12 NC 56 DAI_P12 100 TRST 144

ADDR5 13 V

DD_EXT

57 DAI_P15 101 GND 145

BOOT_CFG1 14 NC 58 V

DD_INT

102 EMU 146

GND 15 NC 59 DAI_P11 103 DATA0 147

ADDR6 16 NC 60 V

DD_EXT

104 DATA1 148

ADDR7 17 NC 61 V

DD_INT

105 DATA2 149

NC 18 V

DD_INT

62 BOOT_CFG2 106 DATA3 150

NC 19 NC 63 V

DD_INT

107 TDO 151

ADDR8 20 NC 64 AMI_ACK 108 DATA4 152

ADDR9 21 V

DD_INT

65 GND 109 V

DD_EXT

153

CLK_CFG0 22 NC 66 THD_M 110 DATA5 154

DD_INT

23 NC 67 THD_P 111 DATA6 155

CLKIN 24 V

DD_INT

68 V

DD_THD

112 V

DD_INT

156

XTAL 25 NC 69 V

DD_INT

113 DATA7 157

ADDR10 26 WDTRSTO 70 V

DD_INT

114 TDI 158

SDA10 27 NC 71 MS1 115 SDCLK 159

DD_EXT

28 V

DD_EXT

72 V

DD_INT

116 V

DD_EXT

160

DD_INT

29 DAI_P07 73 WDT_CLKO 117 DATA8 161

ADDR11 30 DAI_P13 74 WDT_CLKIN 118 DATA9 162

ADDR12 31 DAI_P19 75 V

DD_EXT

119 DATA10 163

ADDR17 32 DAI_P01 76 ADDR23 120 TCK 164

ADDR13 33 DAI_P02 77 ADDR22 121 DATA11 165

DD_INT

34 V

DD_INT

78 ADDR21 122 DATA12 166

ADDR18 35 NC 79 V

DD_INT

123 DATA14 167

RESETOUT/RUNRSTIN 36 NC 80 ADDR20 124 DATA13 168

DD_INT

37 NC 81 ADDR19 125 V

DD_INT

169

DPI_P01 38 NC 82 V

DD_EXT

126 DATA15 170

DPI_P02 39 NC 83 ADDR16 127 SDWE 171

DPI_P03 40 V

DD_EXT

84 ADDR15 128 SDRAS 172

DD_INT

41 V

DD_INT

85 V

DD_INT

129 RESET 173

DPI_P05 42 DAI_P06 86 ADDR14 130 TMS 174

DPI_P04 43 DAI_P05 87 AMI_WR 131 SDCAS 175

DPI_P06 44 DAI_P09 88 AMI_RD 132 V

DD_INT

176

GND 177*

* Lead no. 177 (exposed pad) is the GND supply (see Figure 50 and Figure 51) for the processor; this pad must be robustly connected to GND.

Rev. E | Page 62 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Table 62. Automotive Models ADSP-21488, and ADSP-21489 176-Lead LQFP_EP Lead Assignment (Numerical by Lead Number)

Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No.

SDDQM 1 V

DD_EXT

45 DAI_P10 89 V

DD_INT

133

MS0 2DPI_P08 46V

DD_INT

90 FLAG0 134

SDCKE 3 DPI_P07 47 V

DD_EXT

91 FLAG1 135

DD_INT

48 DAI_P20 92 FLAG2 136

CLK_CFG1 5 DPI_P09 49 V

DD_INT

93 MLBCLK 137

ADDR0 6 DPI_P10 50 DAI_P08 94 FLAG3 138

BOOT_CFG0 7 DPI_P11 51 DAI_P14 95 MLBDAT 139

DD_EXT

8 DPI_P12 52 DAI_P04 96 MLBDO 140

ADDR1 9 DPI_P13 53 DAI_P18 97 V

DD_EXT

141

ADDR2 10 DPI_P14 54 DAI_P17 98 MLBSIG 142

ADDR3 11 DAI_P03 55 DAI_P16 99 V

DD_INT

143

ADDR4 12 NC 56 DAI_P12 100 TRST 144

ADDR5 13 V

DD_EXT

57 DAI_P15 101 MLBSO 145

BOOT_CFG1 14 NC 58 V

DD_INT

102 EMU 146

GND 15 NC 59 DAI_P11 103 DATA0 147

ADDR6 16 NC 60 V

DD_EXT

104 DATA1 148

ADDR7 17 NC 61 V

DD_INT

105 DATA2 149

NC 18 V

DD_INT

62 BOOT_CFG2 106 DATA3 150

NC 19 NC 63 V

DD_INT

107 TDO 151

ADDR8 20 NC 64 AMI_ACK 108 DATA4 152

ADDR9 21 V

DD_INT

65 GND 109 V

DD_EXT

153

CLK_CFG0 22 NC 66 THD_M 110 DATA5 154

DD_INT

23 NC 67 THD_P 111 DATA6 155

CLKIN 24 V

DD_INT

68 V

DD_THD

112 V

DD_INT

156

XTAL 25 NC 69 V

DD_INT

113 DATA7 157

ADDR10 26 WDTRSTO 70 V

DD_INT

114 TDI 158

SDA10 27 NC 71 MS1 115 SDCLK 159

DD_EXT

28 V

DD_EXT

72 V

DD_INT

116 V

DD_EXT

160

DD_INT

29 DAI_P07 73 WDT_CLKO 117 DATA8 161

ADDR11 30 DAI_P13 74 WDT_CLKIN 118 DATA9 162

ADDR12 31 DAI_P19 75 V

DD_EXT

119 DATA10 163

ADDR17 32 DAI_P01 76 ADDR23 120 TCK 164

ADDR13 33 DAI_P02 77 ADDR22 121 DATA11 165

DD_INT

34 V

DD_INT

78 ADDR21 122 DATA12 166

ADDR18 35 NC 79 V

DD_INT

123 DATA14 167

RESETOUT/RUNRSTIN 36 NC 80 ADDR20 124 DATA13 168

DD_INT

37 NC 81 ADDR19 125 V

DD_INT

169

DPI_P01 38 NC 82 V

DD_EXT

126 DATA15 170

DPI_P02 39 NC 83 ADDR16 127 SDWE 171

DPI_P03 40 V

DD_EXT

84 ADDR15 128 SDRAS 172

DD_INT

41 V

DD_INT

85 V

DD_INT

129 RESET 173

DPI_P05 42 DAI_P06 86 ADDR14 130 TMS 174

DPI_P04 43 DAI_P05 87 AMI_WR 131 SDCAS 175

DPI_P06 44 DAI_P09 88 AMI_RD 132 V

DD_INT

176

GND 177*

* Lead no. 177 (exposed pad) is the GND supply (see Figure 50 and Figure 51) for the processor; this pad must be robustly connected to GND.

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 63 of 68 | June 2017

Figure 50 shows the top view of the 176-lead LQFP_EP lead

configuration. Figure 51 shows the bottom view of the 176-lead

LQFP_EP lead configuration.

Figure 50. 176-Lead LQFP_EP Lead Configuration (Top View)

LEAD 1

LEAD 44

LEAD 132

LEAD 89

LEAD 176 LEAD 133

LEAD 45 LEAD 88

LEAD 1 INDICATOR

ADSP-2148x

176-LEAD LQFP_EP

TOP VIEW

Figure 51. 176-Lead LQFP_EP Lead Configuration (Bottom View)

LEAD 132

LEAD 89

LEAD 1

LEAD 44

LEAD 133 LEAD 176

LEAD 88 LEAD 45

LEAD 1 INDICATOR

GND PAD

(LEAD 177)

ADSP-2148x

176-LEAD LQFP_EP

BOTTOM VIEW

Rev. E | Page 64 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

OUTLINE DIMENSIONS

The ADSP-2148x processors are available in 100-lead and

176-lead LQFP_EP RoHS compliant packages.

Figure 52. 100-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]

(SW-100-2)

Dimensions shown in millimeters

For information relating to the exposed pad on the SW-100-2 package, see the table endnote on Page 58.

COMPLIANT TO JEDEC STANDARDS MS-026-BED-HD

TOP VIEW

(PINS DOWN)

BOTTOM VIEW

(PINS UP)

EXPOSED

PAD

25 25

26 26

50 50

76 76100 100

75 75

51 51

0.27

0.22

0.17

0.50

BSC

LEAD PITCH

PIN 1

16.20

16.00 SQ

15.80 14.20

14.00 SQ

13.80

6.00 BSC

12.00 REF

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

“SURFACE-MOUNT DESIGN” IN

THIS DATA SHEET.

0.15

0.05 0.08

COPLANARITY

7°

0°

0.20

0.09

VIEW A

ROTATED 90° CCW

1.45

1.40

1.35

VIEW A

1.60

MAX

SEATING

PLANE

0.75

0.60

0.45

1.00 REF

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 65 of 68 | June 2017

SURFACE-MOUNT DESIGN

The exposed pad is required to be electrically and thermally

connected to GND. Implement this by soldering the exposed

pad to a GND PCB land that is the same size as the exposed pad.

The GND PCB land should be robustly connected to the GND

plane in the PCB for best electrical and thermal performance.

No separate GND pins are provided in the package.

Figure 53. 176-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]

(SW-176-2)

Dimensions shown in millimeters

For information relating to the exposed pad on the SW-176-2 package, see the table endnote on Page 60.

COMPLIANT TO JEDEC STANDARDS MS-026-BGA-HD

0.15

0.10

0.05 0.08

COPLANARITY

0.20

0.15

0.09

1.45

1.40

1.35

7°

3.5°

0°

VIEW A

ROTATED 90° CCW

0.27

0.22

0.17

0.75

0.60

0.45

0.50

BSC

LEAD PITCH

24.10

24.00 SQ

23.90

26.20

26.00 SQ

25.80

TOP VIEW

(PINS DOWN)

BOTTOM VIEW

(PINS UP)

EXPOSED

PAD

132

176 133 176

133

PIN 1

1.60 MAX

1.00 REF

SEATING

PLANE

VIEW A

6.00 BSC

21.50 REF

FOR PROPER CONNECTION

OF THE EXPOSED PAD, REFER

TO “SURFACE-MOUNT DESIGN”

IN THIS DATA SHEET.

Rev. E | Page 66 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

AUTOMOTIVE PRODUCTS

The following models are available with controlled manufactur-

ing to support the quality and reliability requirements of

automotive applications. Note that these automotive models

may have specifications that differ from the commercial models

and designers should review the product Specifications on

Page 18 section of this data sheet carefully. Only the automotive

grade products shown in Table 63 are available for use in auto-

motive applications. Contact your local ADI account

representative for specific product ordering information and to

obtain the specific Automotive Reliability reports for these

models.

ORDERING GUIDE

Table 63. Automotive Products

Model

1, 2,

3, 4

Notes Temperature Range

RAM

Processor

Instruction

Rate (Max) Package Description Package Option

AD21486WBSWZ4Axx

–40°C to +85°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2

AD21487WBSWZ4Axx

–40°C to +85°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2

AD21487WBSWZ4Bxx

–40°C to +85°C 5 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2

AD21488WBSWZ1Axx –40°C to +85°C 3 Mbit 266 MHz 100-Lead LQFP_EP SW-100-2

AD21488WBSWZ2Axx –40°C to +85°C 3 Mbit 300 MHz 100-Lead LQFP_EP SW-100-2

AD21488WBSWZ1Bxx –40°C to +85°C 2 Mbit 266 MHz 176-Lead LQFP_EP SW-176-2

AD21488WBSWZ2Bxx –40°C to +85°C 3 Mbit 266 MHz 176-Lead LQFP_EP SW-176-2

AD21488WBSWZ4Bxx –40°C to +85°C 3 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2

AD21489WBSWZ4xx –40°C to +85°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2

AD21489WBSWZ4xxRL –40°C to +85°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2

AD21489WBSWZ4Bxx –40°C to +85°C 5 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2

Z =RoHS Compliant Part.

W = automotive applications.

xx denotes the current die revision.

RL = Tape and Reel.

Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 18 for junction temperature (T

)

specification which is the only temperature specification.

This product contains IP from Dolby, DTS and DTLA. Proper software licenses required. Contact Analog Devices, Inc. for information.

Model

Notes Temperature Range

RAM

Processor

Instruction

Rate (Max) Package Description Package Option

ADSP-21483KSWZ-2B

0°C to +70°C 3 Mbit 300 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21483KSWZ-3B

0°C to +70°C 3 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21483KSWZ-3AB

0°C to +70°C 3 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21483KSWZ-4B

0°C to +70°C 3 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21483KSWZ-4AB

0°C to +70°C 3 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21486KSWZ-2A

0°C to +70°C 5 Mbit 300 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21486KSWZ-2B

0°C to +70°C 5 Mbit 300 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21486KSWZ-2AB

0°C to +70°C 5 Mbit 300 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21486KSWZ-2BB

0°C to +70°C 5 Mbit 300 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21486KSWZ-3A

0°C to +70°C 5 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21486KSWZ-3B

0°C to +70°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21486KSWZ-3AB

0°C to +70°C 5 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2

ADSP21486KSWZ3ABRL

0°C to +70°C 5 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21486KSWZ-3BB

0°C to +70°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21486KSWZ-4A

0°C to +70°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21486KSWZ-4AB

0°C to +70°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. E | Page 67 of 68 | June 2017

ADSP-21487KSWZ-2B

0°C to +70°C 5 Mbit 300 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21487KSWZ-2BB

0°C to +70°C 5 Mbit 300 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21487KSWZ-3B

0°C to +70°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21487KSWZ-3BB

0°C to +70°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21487KSWZ-4B

0°C to +70°C 5 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21487KSWZ-4BB

0°C to +70°C 5 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21487KSWZ-5B

0°C to +70°C 5 Mbit 450 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21487KSWZ-5BB

0°C to +70°C 5 Mbit 450 MHz 176-Lead LQFP_EP SW-176-2

ADSP21487KSWZ5BBRL 0°C to +70°C 5 Mbit 450 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21488BSWZ-3A –40°C to +85°C 3 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21488KSWZ-3A 0°C to +70°C 3 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21488KSWZ-3A1

0°C to +70°C 3 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21488KSWZ-3B 0°C to +70°C 3 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21488BSWZ-3B –40°C to +85°C 3 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21488KSWZ-4A 0°C to +70°C 3 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21488BSWZ-4A –40°C to +85°C 3 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21488KSWZ-4B 0°C to +70°C 3 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21488BSWZ-4B –40°C to +85°C 3 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21488KSWZ-4B1

0°C to +70°C 3 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21489KSWZ-3A 0°C to +70°C 5 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21489BSWZ-3A –40°C to +85°C 5 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21489KSWZ-3B 0°C to +70°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21489BSWZ-3B –40°C to +85°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21489KSWZ-4A 0°C to +70°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21489BSWZ-4A –40°C to +85°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21489KSWZ-4B 0°C to +70°C 5 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21489BSWZ-4B –40°C to +85°C 5 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2

ADSP-21489KSWZ-5B

0°C to +70°C 5 Mbit 450 MHz 176-Lead LQFP_EP SW-176-2

Z = RoHS compliant part.

RL = Tape and Reel.

Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 18 for junction temperature (T

)

specification, which is the only temperature specification.

The ADSP-21483, ADSP-21486, and ADSP-21487 models are available with factory programmed ROM including the latest multichannel audio decoding and post-processing

algorithms from Dolby Labs and DTS. ROM contents may vary depending on chip version and silicon revision. Please visit www.analog.com for complete information.

See Engineer-to-Engineer Note Static Voltage Scaling for ADSP-2148x SHARC Processors (EE-357) for operating ADSP-2148x processors at 450 MHz.

This product contains a –140 dB sample rate converter.

Model

Notes Temperature Range

RAM

Processor

Instruction

Rate (Max) Package Description Package Option

Rev. E | Page 68 of 68 | June 2017

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

registered trademarks are the property of their respective owners.

D09018-0-6/17(E)