TEA1751LT/N1,518 - NXP Semiconductors / Philips Semiconductors

1. General description

The GreenChip III is the third generation of gre en Switched Mode Power Supply (SMPS)

controller ICs. The TEA1751(L)T (TEA1751T and TEA1751LT) combines a controller for

Power Factor Correction (PFC) and a flyba ck controller. Its high level of integration allows

the design of a cost-effective power supply with a very low number of external

components.

The special built-in green functions provide high efficiency at all power levels. This applies

to quasi-resonant operation at high power levels, quasi-resonant operation with valley

skipping, as well as to reduced frequency operation at lower power levels. At low power

levels, the PFC switches off to maintain high efficiency.

During low power conditions, the flyback controller switches to frequency reduction mode

and limits the peak current to 25 % of its maximum value. This will ensure high efficiency

at low power and good standby power performance while minimizing audible noise from

the transformer.

The TEA1751(L)T is a MultiChip Module, (MCM), containing two chips. The proprietary

high voltage BCD800 process which makes direct start-up possible from th e rectified

universal mains volt age in an ef fective and g reen way. The second low vo lt age SIlicon On

Insulator (SIOI) is used for accurate, high speed protection functions and control.

The TEA1751(L)T enables highly efficient and reliable supplies with power requirements

up to 250 W, to be de sign e d easily an d with a minimum number of external component s.

2. Features

2.1 Distinctive features

Integrated PFC and flyback controller.

Universal mains supply operation (70 V (AC) to 276 V (AC)).

Dual boost PFC with accurate maximum output voltage (NXP patented).

High level of integration, resulting in a very low external component count and a

cost-effective design.

2.2 Green features

On-chip start-up current source.

TEA1751T; TEA1751LT

GreenChip III SMPS control IC

Rev. 02 — 23 December 2009 Product data sheet

Product data sheet Rev. 02 — 23 December 2009 2 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

2.3 PFC green features

Valley/zero voltage switching for minimum switching losses (NXP patented).

Frequency limitation to reduce switching losses.

PFC is switched off when a low load is detected at the flyback output.

2.4 Flyback green features

Valley switching for minimum switching losses (NXP patented).

Frequency reduction with fixed minimum peak current at low power operation to

maintain high efficiency at low output power levels.

2.5 Protection features

Safe restart mode for system fault conditions.

Continuous mode protection by means of demagnetization detection for both

converters (N XP patented) .

UnderVoltage Protection (UVP) (foldback during overload).

Accurate OverVoltage Protection (OVP) for both converters (adjustable for flyback

converter).

Mains voltage independent OverPower Protection (OPP)

Open control loop protection for both converters. The open loop protection on the

flyback converter is latched on the TEA1751L and safe restart on the TEA1751.

IC overtemperature protection.

Low and adjustable OverCurrent Protection (OCP) trip level for both conve rters.

General purpose input for latched protection, e.g. to be used for system

OverTemperature Protection (OTP).

3. Applications

The device can be use d in all applications that require an efficient and cost-effective

power supply solution up to 250 W. Notebook adapters in particular can benefit from

the high level of integr atio n .

4. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

TEA1751T SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

TEA1751LT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 02 — 23 December 2009 3 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

5. Block diagram

Remark:

For the TEA1751L the time-out is latched.

For the TEA1751 the time-out is safe restart.

Fig 1. Block diagram

LOW

VIN

TIMER 50 μs

TIMER 4 μs

PFC

PROT

VoOVP

VoSTART FB

VoSHORT

LOW VIN

OCP

PFC DRIVER

ENABLE PFC

START STOP PFC

500 mV

SOFT START

PFCGATE

VALLEY

DETECT

ZCS

BLANK

2.50 V

2.7 V

1.25 V

MAX

TIMEOUT

EXT PROT

OTP

OvpFB

LATCH RESET

PROT

EXT PROT

Vstartup

Vth(UVLO)

LATCHED

PROTECTION

CHARGE

CONTROL

STARTFB

START STOP

PFC

PROT

VCC GOOD

CHARGE

PFC

OSC

PFC PROT

PROT

LATCH

RESET

ENABLE PFC

VCC GOOD

VoSTART FB

LOW POWER

EXT PROT

SMPS

CONTROL

START

SOFT

START FB

ENABLE FB

BLANK

OSC

TON MAX

Freq

Red.

EXT PROT

LOW

POWER

TIME

OUT

FB DRIVER

FB GATE

DRV

12 13

PFC DRIVER

PFC GATE

VINSENSE

PFCCOMP

VOSENSE

PFCSENSE

PFCAUX OTP

CHARGE

VALLEY

DETECT

OTP

INTERNAL

SUPPLY

ZCS FB GATE

FBAUX

FBSENSE

COUNTER

OVP

OvpFB

1.12 V 3.5 V

HV VCC

16 1

GND

FBCTRL

LATCH

80 mV

PFCDRIVER FBDRIVER

Vstartup

Vth(UVLO)

014aaa299

DRV

PROT

ENABLE

80 μA

60 μA

30 μA

60 μA

3.7 V

LOW

POWER

OCP

Freq. Red.

1.25 V

DRIVER

2.5 V 3.5 V

TEMP

100 mV

15 μA

BOOST

TIMEOUT

TON MAX

VoSHORT

VUVLO

SAFE

RESTART

PROTECTION

S (TEA1751 only)

OPP

OPP MIN

S (TEA1751L only)

Product data sheet Rev. 02 — 23 December 2009 4 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 2. Pin configuration: TEA1751(L)T (SOT109-1)

TEA1751(L)T

VCC HV

GND HVS

FBCTRL HVS

FBAUX FBDRIVER

LATCH PFCDRIVER

PFCCOMP PFCSENSE

VINSENSE FBSENSE

PFCAUX VOSENSE

014aaa300

Table 2. Pin description

Symbol Pin Description

VCC 1 supply voltage

GND 2 ground

FBCTRL 3 control input for flyback

FBAUX 4 input from auxiliary winding for demagnetiza tion timing and

overvoltage protection for flyback

LATCH 5 general purpose protection input

PFCCOMP 6 freq uency compensation pin for PFC

VINSENSE 7 sense input for mains voltage

PFCAUX 8 input from auxiliary winding for de magnetization timing for PFC

VOSENSE 9 sense input for PFC output voltage

FBSENSE 10 programmable current sense input for flyback

PFCSENSE 11 programmable current sense input for PFC

PFCDRIVER 12 gate driver output for PFC

FBDRIVER 13 gate driver output for flyback

HVS 14, 15 high voltage safety spacer, not connected

HV 16 high voltage start-up and valley sensing of flyback part

Product data sheet Rev. 02 — 23 December 2009 5 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

7. Functional description

7.1 General control

The TEA1751(L)T contains a controller for a power factor correction circuit as well as a

controller for a flyback circuit. A typical configuration is shown in Figure 3.

7.1.1 Start-up and UnderVoltage LockOut (UVLO)

Initially the capacitor on the VCC pin is charged from the high voltag e mains via the HV pin.

As long as VCC is below Vtrip, the charge current is low. This protects the IC if the VCC pin

is shorted to ground. For a short start-up time the charge current above Vtrip is increased

until VCC reaches Vth(UVLO). If VCC is between Vth(UVLO) and Vstartup, the charge current is

low again, ensuring a low duty cycle during fault conditions.

The control logic activates the inte rnal circuitry and switches off the HV charge current

when the voltage on pin VCC p asses the Vstartup level. First, the LATCH pin current source

is activated and the soft start capacitors on the PFCSENSE and FBSENSE pins are

charged. When the LATCH pin voltage exceeds the Ven(LATCH) voltage and the soft start

capacitor on the PFCSENSE pin is charged, the PFC circuit is activated. Also the flyback

converter is activated (providing the soft start capacitor on the FBSENSE pin is charged).

The output voltag e of the flyback converter is then r egulated to its no minal output volt ag e.

The IC supply is taken over by the auxiliary winding of the flyback converter. See Figure 4.

If during start-up the LATCH pin does not reach the Ven(LATCH) lev el before VCC reaches

Vth(UVLO), the LATCH pin output is deactivated and the charge current is switched on

again.

Fig 3. Typical configuration

12 11 9 16 13

TEA1751(L)T

014aaa301

Product data sheet Rev. 02 — 23 December 2009 6 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

As soon as the flyback con verter is started, the volt age on the FBCTRL pin is monitor ed. If

the output volt age of the flyba ck converter do es not reach it s intended regulation level in a

predefined time, the volt age on the FBCTRL pin reache s the Vto(FBCTRL) level and an error

is assumed. The TEA1751 then initiates a sa fe restart, while in the TEA1751L the

protection is latched.

When one of the protection functions is activated, both converters stop switching and the

VCC voltage drops to Vth(UVLO). A latched protection recharges the capacitor CVCC via the

HV pin, but does not restart the converters. For a safe restart protection, the capacitor is

recharged via the HV pin and the device restarts (see block diagram, Figure 1).

In the event of an overvoltage protection of the PFC circuit, VVOSENSE >Vovp(VOSENSE),

only the PFC controlle r sto ps switching until the VOSEN SE pin vo ltage drops below

VOVP(VOSENSE) again. Also, if a mains undervoltage is detected

VVINSENSE <Vstop(VINSENSE), only the PFC controller stops switching until

VVINSENSE >Vstart(VINSENSE) again.

When the voltage on pin VCC drops below the undervoltage lockout level, b oth controllers

stop switching and reenter the safe restart mode. In the safe restart mode the driver

outputs are disabled and the VCC pin voltage is recharged via the HV pin.

Product data sheet Rev. 02 — 23 December 2009 7 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

7.1.2 Supply management

All internal refere nce voltages are der ive d fro m a temper atur e comp en sate d an d trim med

on-chip band gap cir cuit. Internal reference currents are derived from a temperature

compensated and trimmed on-chip current reference circuit.

7.1.3 Latch input

Pin LATCH is a general purpose input pin, which can be used to switch off both

converters. The pin sources a current IO(LATCH) (80 μA typical). Switching off both

converters is stopped as soon as the voltage on this pin drops below 1.25 V.

At initial start-up the switching is inhibited un til the capacitor on th e LATCH pin is charged

above 1.35 V (typical). No internal filtering is done on this pin. An internal zener clamp of

2.9 V (typical) protects this pin from excessive voltages.

Fig 4. Start-up sequence, normal operation and restart sequence

VCC

LATCH

PROTECTION

PFCSENSE

PFCDRIVER

FBSENSE

FBDRIVER

FBCTRL

VOSENSE

charging VCC

capacitor

starting

converters

normal

operation

protection restart

soft start

IHV

Vstart(VINSENSE)

Vto(FBCTRL)

Vstartup

Vth(UVLO)

Vtrip

VEN(LATCH)

Vstart(fb)

VINSENSE

014aaa156

Product data sheet Rev. 02 — 23 December 2009 8 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

7.1.4 Fast latch reset

In a typical application the mains can be interrupted briefly to rese t the la tched p rotection.

The PFC bus capacitor, Cbus, does not have to discharge for this latched protection to

reset.

Typically the PFC bus capacitor, Cbus, has to discharge for the VCC to drop to this reset

level. When the latched protection is set, the clamping circuit of the VINSENSE circuit is

disabled. (see also Section 7.2.9) As soon as the VINSENSE voltage drops below

750 mV (typical) and afte r that is raised to 870 mV (typical), the latched protection is reset.

The latched protection is also reset by removing both the voltage on pin VCC and on

pin HV.

7.1.5 Overtemperature protection

An accurate internal temperature protection is provided in the circuit. When the junction

temperature exceeds the thermal shutdown temperature, the IC stops switching. As long

as OTP is active, the capacitor CVCC is not recharged from the HV mains. The OTP circuit

is supplied from the HV pin if the VCC supply voltage is not sufficient.

OTP is a latched protection. It can be reset by removing both the voltage on pin VCC and

on pin HV or by the fast latch reset function. (See Section 7.1.4)

7.2 Power factor correction circuit

The power factor correction circuit operates in quasi-resonant or discontinuous

conduction mode with valley switching. The next primary stroke is only started when the

previous secondary stroke has ended and the voltage across the PFC MOSFET has

reached a minimum value. The voltage on the PFCAUX pin is used to detect transformer

demagnetization and the minimu m voltage across the external PFC MOSFET switch.

7.2.1 ton control

The power factor corr ection circuit is operate d in ton control. The resulting mains harmonic

reduction of a typical application is well within the class-D requirements.

7.2.2 Valley switching and demagnetization (PFCAUX pin)

The PFC MOSFET is switched on af ter the trans former is dem agnetized. Internal circuitr y

connected to the PFCAUX pin detect s the en d of the secondary stroke. It also detect s the

voltage across the PFC MOSFET. The next stroke is started when the voltage across the

PFC MOSFET is at its minimum in order to reduce switching losses and ElectroMagnetic

Interference (EMI) (valley switching).

If no demagnetization signal is detected on the PFCAUX pin, the contr oller ge ne ra te s a

zero current signal (ZCS), 50 μs (typical) after the last PFCGATE signal.

If no valley signal is detected on the PFCAUX pin, the controller genera tes a va lley sign al

4μs (typical) after demagnetization was detected.

To protect the interna l circuitry during lightning event s, for example, it is advisable to add a

5kΩ series resistor to this pin. To preven t incorrect switching du e to external distur bance,

the resistor should be placed close to the IC on the printed -circuit board.

Product data sheet Rev. 02 — 23 December 2009 9 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

7.2.3 Frequency limitation

To optimi ze the transformer and minimize switching losses, the switching frequency is

limited to fsw(PFC)max. If the frequency for quasi -resonant op eration is above the fsw(PFC)max

limit, the system switches over to discontinuous conduction mode. Also here, the PFC

MOSFET is only switched on at a minimum voltage across the switch (valley switching).

7.2.4 Mains voltage compensation (VINSENSE pin)

The mathematical equation for the transfer function of a power factor corrector contains

the square of the mains input voltage. In a typical application this results in a low

bandwidth for low mains input voltages, while at high mains input voltages the Mains

Harmonic Reduction (MHR) requirements may be har d to meet.

To compensate for th e mains input voltage influence, the TEA1751(L)T contains a

correction circuit. Via the VINSENSE pin the average input voltage is measured and the

information is fed to an internal compensation circuit. With this compensation it is possible

to keep the regulation loop bandwidth constant over the full mains input range, yielding a

fast transient response on load steps, while still complying with class-D MHR

requirements.

In a typical application, the bandwidth of the regulation loop is set by a resistor and two

capacitors on the PFCCOMP pin.

7.2.5 Soft start-up (pin PFCSENSE)

To prevent audible transformer noise at start-up or during hiccup, the transformer peak

current, IDM, is increased slowly by the soft start function. This can be achieved by

inserting RSS1 and CSS1 between pin PFCSENSE and current sense resistor RSENSE1.

An internal current source charges the capacitor to VPFCSENSE =I

start(soft)PFC ×RSS1. The

voltage is limited to Vstart(soft)PFC.

The start level and the time constant of the increasing primary current level can be

adjusted externally by changing the values of RSS1 and CSS1.

The charging current Istart(soft)PFC flows as long as the voltage on pin PFCSENSE is

below 0.5 V (typ). If the voltage on pin PFCSENSE exceeds 0.5 V, the soft start current

source starts limiting current Istart(soft)PFC. As soon as the PFC starts switching, the

Istart(soft)PFC current source is switched off; see Figure 5.

τsoftstart 3 RSS1 CSS1

××=

Product data sheet Rev. 02 — 23 December 2009 10 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

7.2.6 Low power mode

When the output power of the flyback converter (see Section 7.3) is low, the flyback

converter switches over to frequency reduction mod e. When frequency reduction mode is

entered by the flyback controller, the power factor correction circuit is switch ed off to

mainta in high efficiency.

During low power mode operation the PFCCOMP pin is clamped to a minimal voltage of

2.7 V (typical) and a maximum voltage of 3.9 V (typical). The lower clamp voltage limits

the maximum power that is delivered when the PFC is switched on again. The upper

clamp volt age ensures that the PFC can return to its normal regulation point in a limited

amount of time when returning from low power mode.

As soon as the flyback converter leaves the frequency reduction mode, the power factor

correction circuit restores normal op eration. To prevent continuous switching on and of f of

the PFC circuit, a small hysteresis is build in, (60 mV (typical) on the FBCTRL pin).

7.2.7 Dual boost PFC

The PFC output volt age is m odulated by the main s input volt age. Th e mains input volt age

is measured via the VINSENSE pin. The current is sourced from the VOSENSE pin if the

voltage on the VINSENSE pin drops below 2.2 V (typical). To ensure the stability of the

switch-over 200 mV is inserted around the 2.2 V, see Figure 6.

For low VINSENSE input voltages, the output current is 15 μA (typical). This output

current, in combination with the resistors on the VOSENSE pin , sets the lower PFC output

voltage level at low mains volt ages. At high mains input volt ages the current is switched to

zero. The PFC output voltage will then be at its maximum. As this current is zero in this

situation, it does not effect the ac curacy of the PFC output voltage.

For proper switch-off behavior, the VOSENSE current is switched to its maximum value,

(15 μA (typical)), as soon as the voltage on pin VOSENSE drops below 2.1 V (typical).

Fig 5. Soft start-up of PFC

SOFT START

CONTROL

OCP

PFCSENSE

0.5 V

Istartup(soft)PFC ≤ 60 μA

RSS1

CSS1

RSENSE1

014aaa15

Product data sheet Rev. 02 — 23 December 2009 11 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

7.2.8 Overcurrent protection (PFCSENSE pin)

The maximum peak current is limited cycle-by-cycle by sensing the voltage across an

external sense resistor, RSENSE1, on the source of the external MOSFET. The voltage is

measured via the PFCSENSE pin.

7.2.9 Mains undervoltage lockout / brownout protection (VINSENSE pin)

To prevent the PFC from operating at very low mains input voltages, the voltage on the

VINSENSE pin is sensed continuously. As soon as the voltage on this pin drops below the

Vstop(VINSENSE) level, switching of the PFC is stopped.

The voltag e on pin VINSENSE is clamped to a minimum value,

Vstart(VINSENSE) +ΔVpu(VINSENSE), for a fast restart as soon as the mains input voltage is

restored after a mains dropout.

7.2.10 Overvoltage protection (VOSENSE pin)

To prevent output overvoltage during load steps and mains transients, an overvoltage

protection circuit is built in.

As soon as the voltage on the VOSENSE pin exceeds the Vovp(VOSENSE) level, switching

of the power factor correction circuit is inhibited. Switching of the PFC recommences as

soon as the VOSENSE pin voltage drops below the V ovp(VOSENSE) level again.

When the resistor between pin VOSENSE and ground is open, the overvoltag e protection

is also triggered.

7.2.11 PFC open loop protection (VOSENSE pin)

The power factor correction circui t does not start switching until the voltage on the

VOSENSE pin is above the Vth(ol)(VOSENSE) level. This protects the circuit from open loop

and VOSENSE short situations.

7.2.12 Driver (pin PFCDRIVER)

The driver circuit to the gate of the power MOSFET has a current sourcing capability of

typically −500 mA and a current sink capability of typically 1.2 A. This permits fast turn-on

and turn-off of the power MOSFET for efficient operation.

Fig 6. Voltage to current transfer function for dual boost PFC

VVINSENSE

II(VOSENSE)

014aaa09

−15 μA

2.2 V

Product data sheet Rev. 02 — 23 December 2009 12 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

7.3 Flyback controller

The TEA1751(L)T includes a controller for a flyback converter. The flyback converter

operates in quasi-resonant or di scontinuous conduction mode with valley switching. The

auxiliary winding of the flyback transformer provides demagnetization detection and

powers the IC afte r start-up.

7.3.1 Multimode operation

The TEA1751(L)T flyback controller can operate in several modes; see Figure 7.

At high output power the converter switches to quasi-resonant mode. The next converter

stroke is started af ter demagnetization of the transformer cur rent. In quasi-re sonant mode

switching losses are minimized as the converter on ly switches on when the voltage across

the external MO SFET is at its minimum (valley switching, see also Section 7.3.2).

To prevent hig h frequency operation at lower loads, th e quasi-resonant operation chang es

to discontinuous mode operation with valley skipping in which the switching frequency is

limited for EMI to fsw(fb)max (125 kHz typical). Again, the external MOSFET is only switched

on when the voltage across th e MO SFET is at its minimum.

At very low power and standby levels the frequency is controlled down by a Voltage

Controlled Oscillator (VCO). The minimum frequency can be reduced to zero. During

frequency reduction mo de, the p rimary peak cu rrent is kept at a min imal level of Ipkmax/4

to maintain a high efficiency. (Ipkmax is the maximum primary peak current set by the

sense resistor and the maximum sense voltage.) As the primary peak cu rrent is low in

frequency reduction operation (Ipk = Ipkmax/4), no audible noise is noticeable at

switching frequencies in the audible range. Valley switching is also active in this mode.

In frequency reduction mode the PFC controller is switched off and the flyback maximum

frequency changes linearly with the control voltage on the FBCTRL pin (see Figure 8 ).

For stable on and off switching of the PFC, the FBCTRL pin has a 50 mV (typical)

hysteresis. At no load operation the switching frequency can be reduced to (almost) zero.

Fig 7. Multimode operation flyback

discontinuous

with valley

switching quasi resonant

PFC off

frequency

reduction

fsw(fb)max

output power

switching frequency

014aaa15

PFC on

Product data sheet Rev. 02 — 23 December 2009 13 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

7.3.2 Valley switching (HV pin)

Refer to Figure 9. A new cycle starts when the external MOSFET is activated. After the

on-time (determined by the FBSENSE voltage and the FBCTRL volt age), the MOSFET is

switched off an d the secondary stro ke star ts. Af ter the secondary str oke, the drain volta ge

shows an oscillation with a frequency of approximately where Lp is

the primary self-inductance of the flyback transformer and Cd is the capacitance on the

drain node.

As soon as the internal oscillator voltage is high again and the secondary stroke has

ended, the circuit waits for the lowest drain voltage before starting a new primary stroke.

Figure 9 shows the drain voltage, valley signal, secondary stroke signal and the internal

oscillator signal.

Valley switching allows high frequency operation as capacitive switching losses are

reduced, see Equation 1. High fre quency operation makes small and cost-effective

magnetics possible.

(1)

Fig 8. Frequency control of flyback part

fsw(fb)max

VFBCTRL

1.5 V

discontinuous

with valley

switching quasi resonant

frequency

reduction

PFC off

switching frequency

014aaa15

PFC on

2π× LpCd

×()×()

---------------------------------------------------

---CdV2

×f××=

⎝⎠

⎛⎞

Product data sheet Rev. 02 — 23 December 2009 14 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

7.3.3 Current mode control (FBSENSE pin)

Current mode control is used for the flyback converter for its good line regulation.

The primary current is sensed by the FBSENSE pin across an external resistor and

compared with an internal control voltage.The internal control voltage is proportional to

the FBCTRL pin voltage, see Figure 10.

(1) Start of ne w cycle at lowest drain voltage.

(2) Start of new cycle in a classical Pulse Width Modulation (PWM) system without valley detection.

Fig 9. Signals for valley switching

drain

secondary

stroke

014aaa02

secondary

ringing

primary

stroke

valley

(2) (1)

secondary

stroke

oscillator

Product data sheet Rev. 02 — 23 December 2009 15 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

The driver output is latched in th e logic, preventing multiple switch-on.

7.3.4 Demagnetization (FBAUX pin)

The system is always in quasi-resonant or discontinuous conduction mode. The internal

oscillator does not start a new primary stroke until the previous secondary stroke has

ended.

Demagnetization features a cycle-by-cycle output short circuit protection by immedi ately

lowering the frequency (longer off-time), thereby reducing the power level.

Demagnetization recognition is suppressed during the first tsup(xfmr_ring) time (2 μs typical).

This suppression may be necessary at low output voltages and at start-up and in

applications where the transformer has a large leakage inductance.

If pin FBAUX is open circuit or not connected, a fault condition is assumed and the

converter stops operating immediately. Operation restart s as soon as the fault condition is

removed.

7.3.5 Flyback control / time-out (FBCTRL pin)

The pin FBCTRL is connected to an internal voltage source of 3.5 V via an internal

resistor (typical resistance is 3 kΩ). As soon as the voltage on this pin is above

2.5 V (typical), this connection is disabled. Above 2.5 V the pin is biased with a small

current. When the voltage on this pin rises above 4.5 V (typical), a fault is assumed and

switching is inhibited. In the TEA1751 a restart will then be made, while in the TEA1751L

the protection will be latched.

When a small capacitor is connected to this pin, a time-out function can be created to

protect against an open control loop situatio n. (see Figure 11 and Figure 12) T he time-out

function can be disabled by connecting a re sistor (1 00 k Ω) to groun d on the FBCTRL pin.

If the pin is shorted to ground, switching of the flyback controller is inhibited.

Fig 10. Peak current control of flyback part

sense(fb)max

(V)

FBCTRL

(V)1.5 V 2.0 V

0.52 V

flyback

frequency

reduction

PFC off

FBSENSE peak voltage

014aaa16

PFC on

flyback

discontinuous

or QR

flyback

cycle skip

mode

1.4 V

0.13 V

Product data sheet Rev. 02 — 23 December 2009 16 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

In normal operating conditions, when the converter is regulating the output voltage, the

voltage on the FBCTRL pin is between 1.4 V and 2.0 V (typical values) from minimum to

maximum output powe r.

Fig 11. Time-out protection circuit

Fig 12. Time-out protection (signals), safe restart in the TEA1751

Fig 13. Time-out protection (signals), latched in the TEA1751L

014aaa049

FBCTRL

2.5 V

4.5 V

30 μA

3 kΩ

3.5 V

TIME-OUT

014aaa05

4.5 V

2.5 V

FBCTRL

output

voltage

intended output

voltage not

reached within

time-out time.

intended output voltage

reached within time-out

time.

restart

014aaa29

4.5 V

2.5 V

FBCTRL

output

voltage

intended output

voltage not

reached within

time−out time.

latched

Product data sheet Rev. 02 — 23 December 2009 17 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

7.3.6 Soft start-up (pin FBSENSE)

To prevent audible transformer noise during start-up, the transformer peak current, IDM is

slowly increased by the soft start function. This can be achieved by inserting a resistor and

a capacitor between pin 10, F BSENSE , and the current sense resistor.

An internal current source charges the capacitor to V = Istart(soft)fb ×RSS2, with a maximum

of approximately 0.5 V.

The start level and the time constant of the increasing primary current level can be

adjusted externally by changing the values of RSS2 and CSS2.

The soft start current Istart(soft)fb is switched on as soon as VCC reaches Vstartup. When the

voltage on pin FBSENSE has reached 0.5 V, the flyback converter starts switching.

The charging current Istart(soft)(PFC) flows as long as the voltage on pin FBSENSE is below

approximately 0.5 V. If the voltage on pin FBSENSE exceeds 0.5 V, the soft start current

source starts limiting the current. After the flyback co nv er te r ha s started, th e so ft start

current source is switched off.

7.3.7 Maximum on-time

The flyback controller limit s the ‘on-time’ of the external MOSFET to 40 μs (typical). When

the ‘on-time’ is longer than 40 μs, the IC stops switching and enters the safe rest ar t mode.

7.3.8 Overvoltage protection (FBAUX pin)

An output overvoltage protection is implemented in th e GreenChip III series. This works

for the TEA1751(L)T by sensing the auxiliary voltage via the current flowing into

pin FBAUX during the secondary stroke. The auxiliary winding voltage is a well-defined

replica of the output voltage. Voltage spikes are averaged by an intern a l filter.

If the output voltage exceeds the OVP trip level, an internal counter starts counting

subsequent OVP event s. The counter has been added to pr event incorrect OVP detection

which might occur during ESD or lightning events. If the output voltage exceeds the OVP

trip level a few times and not again in a subsequent cycle, the internal counter counts

down at twice the speed it uses when counting up. However , when typically eight cycles of

Fig 14. Soft start-up of flyback.

τsoftstart 3 RSS2 CSS2

××=

014aaa02

SOFT START

CONTROL

OCP

FBSENSE

0.5 V

Istart(soft)fb ≤ 60 μA

RSS2

CSS2

RSENSE2

Product data sheet Rev. 02 — 23 December 2009 18 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

subsequent OVP events are detected, the IC assumes a true OVP and the OVP circuit

switches the power MOSFET off. As the protection is latched, the converter only restarts

after the internal latch is reset. In a typical application the mains should be interrupted to

reset the internal latch.

The output voltage Vo(OVP) at which the OVP function trips, can be set by the

demagnetization resistor, RFBAUX :

where Ns is the number of secondary turns an d Naux is the number of auxiliary turns of the

transformer. Current Iovp(FBAUX) is internally trimmed.

The value of RFBAUX can be adjusted to the turns ratio of the transformer, thus making an

accurate OVP detection possible.

7.3.9 Overcurrent protection (FBSENSE pin)

The primary peak current in the transformer is measured accurately cycle-by-cycle using

the external sense resistor Rsense2. The OCP circuit limits the voltage on pin FBSENSE to

an internal level (see also Section 7.3.3). The OCP detection is suppressed during the

leading edge blanking period, tleb, to prevent false triggering caused by switch-on spikes.

7.3.10 Overpower protection

During the primary stroke of the flyback converter the input voltage of the flyback

converter is measured by sensing the current that is drawn from the pin FBAUX.

The current informa tion is used to adjust the peak drain current of the flyback converter,

which is measured via pin FBSENSE. The internal compensation is such that an almost

input volt age independent maximum output power can be realized.

The OPP curve is given in Figure 16.

VoOVP() Ns

Naux

----------- Iovp FBaux()

RFBaux

×Vclamp FBAUX()

+()=

Fig 15. OCP leadin g ed ge blanking

LEB (t

leb

)

OCP LEVEL

FBSENSE

014aaa02

Product data sheet Rev. 02 — 23 December 2009 19 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

7.3.11 Driver (pin FBDRIVER)

The driver circuit to the gate of the e xter nal power MOSFET has a current sourcing

capability of typically −500 mA and a current sink capability of typically 1.2 A. This permits

fast turn-on and turn-of f of the power MOSFET for efficient operation.

8. Limiting values

Fig 16. Overpower prote ction curve

IFBAUX (μA)

−400

−360

0−100−300 −200

014aaa096

0.4

0.5

0.6

VFBSENSE

(V)

0.3

0.52

0.37

Table 3. Limiting va lues

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

Voltages

VCC supply voltage −0.4 +38 V

VLATCH voltage on pin LATCH current limited −0.4 +5 V

VFBCTRL voltage on pin FBCTRL −0.4 +5 V

VPFCCOMP voltage on pin PFCCOMP −0.4 +5 V

VVINSENSE voltage on pin VINSENSE −0.4 +5 V

VVOSENSE voltage on pin VOSENSE −0.4 +5 V

VPFCAUX voltage on pin PFCAUX −25 +25 V

VFBSENSE voltage on pin FBSENSE current limited −0.4 +5 V

VPFCSENSE voltage on pin PFCSENSE current limited −0.4 +5 V

VHV voltage on pin HV −0.4 +650 V

Currents

IFBCTRL current on pin FBCTRL −30 mA

IFBAUX current on pin FBAUX −1+1mA

IPFCSENSE current on pin PFCSENSE −1+10mA

IFBSENSE current on pin FBSENSE −1+10mA

IFBDRIVER current on pin FBDRIVER duty cycle <10 %−0.8 +2 A

Product data sheet Rev. 02 — 23 December 2009 20 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

[1] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

[2] Equivalent to discharging a 200 pF capacitor through a 0.75 μH coil and a 10 Ω resistor.

9. Thermal characteristics

10. Characteristics

IPFCDRIVER current on pin PFCDRIVER duty cycle <10 %−0.8 +2 A

IHV current on pin HV - 5 mA

General

Ptot total power dissipation Tamb <75 °C-0.6W

Tstg storage temperature −55 +150 °C

Tjjunction temperature −40 +150 °C

ESD

VESD electrostatic discharge

voltage class 1

human body

model

pins 1 to 13 [1] -2000V

pin 16 (HV) [1] -1500V

machine mode l [2] -200V

charged device

model -500V

Table 3. Limiting va lues …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

Table 4. Thermal characteristics

Symbol Parameter Conditions Typ Unit

Rth(j-a) thermal resistance from

junction to ambient in free air; JEDEC test

board 124 K/W

Table 5. Chara cteristics

Tamb =25

C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into

the IC; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Start-up current source (pin HV)

IHV current on pin HV VHV > 80 V

VCC < Vtrip;

Vth(UVLO) <VCC <Vstartup

-1.0-mA

Vtrip < VCC < Vth(UVLO) -5.4-mA

with auxiliary supply 8 20 40 μA

VBR breakdown voltage 650 - - V

Supply voltage management (pin VCC)

Vtrip trip voltage 0.55 0.65 0.75 V

Vstartup start-up voltage 212223V

Product data sheet Rev. 02 — 23 December 2009 21 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

Vth(UVLO) undervoltage lockout threshold

voltage 14 15 16 V

Vstart(hys) hysteresis of start volt age during start-up phase - 300 - mV

Vhys hysteresis voltage Vstartup −Vth(UVLO) 6.3 7 7.7 V

Ich(low) low charging current VHV > 80 V; VCC <Vtrip or

Vth(UVLO) <VCC <Vstartup

−1.2 −1.0 −0.8 mA

Ich(high) high charging current VHV >80 V; Vtrip <VCC < Vth(UVLO) −4.6 −5.4 −6.3 mA

ICC(oper) operating supply current no load on pin FBDRIVER and

PFCDRIVER 2.25 3 3.75 mA

Input voltage sensing PFC (pin VINSENSE)

Vstop(VINSENSE) stop voltage on pin VINSENSE 0.86 0.89 0.92 V

Vstart(VINSENSE) start voltage on pin VINSENSE 1.11 1.15 1.19 V

ΔVpu(VINSENSE) pull-up voltage difference on

pin VINSENSE active after Vstop(VINSENSE) is

detected -−100 - mV

Ipu(VINSENSE) pull-up current on pin

VINSENSE active after Vstop(VINSENSE) is

detected −55 −47 −40 μA

Vmvc(VINSENSE)max maximum mains voltage

compensation voltage on pin

VINSENSE

4.0--V

Vflr fast latch reset voltage active after Vth(UVLO) is detected - 0.75 - V

Vflr(hys) hysteresis of fast latch reset

voltage -0.12-V

II(VINSENSE) input current on pin VINSENSE VVINSENSE > Vstop(VINSENSE) after

Vstart(VINSENSE) is detected 533100nA

Vbst(dual) dual boo st voltage current switch-over point - 2.2 - V

switch-over region - 200 - mV

Loop compensation PFC (pin PFCCOMP)

gmtransconductance VVOSENSE to IO(PFCCOMP) 60 80 100 μA/V

IO(PFCCOMP) output current on pin

PFCCOMP VVOSENSE = 3.3 V 33 39 45 μA

VVOSENSE = 2.0 V −45 −39 −33 μA

Vclamp(PFCCOMP) clamp voltage on pin

PFCCOMP Low power mode; PFC off; lower

clamp voltage [1] 2.5 2.7 2.9 V

Upper clamp voltage [1] -3.9-V

Vton(PFCCOMP)zero zero on-time voltage on pin

PFCCOMP 3.4 3.5 3.6 V

Vton(PFCCOMP)max maximum on-time voltage on

pin PFCCOMP 1.20 1.25 1.30 V

Pulse width modulator PFC

ton(PFC) PFC on-time VVINSENSE = 3.3 V;

VPFCCOMP =Vton(PFCCOMP)max

3.6 4.5 5.0 μs

VVINSENSE = 0.9 V;

VPFCCOMP =Vton(PFCCOMP)max

30 40 53 μs

Table 5. Chara cteristics …continued

Tamb =25

C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into

the IC; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 02 — 23 December 2009 22 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

Output voltage sensing PFC (pin VOSENSE)

Vth(ol)(VOSENSE) open-loop threshold voltage on

pin VOSENSE -1.15-V

Vreg(VOSENSE) regulation voltage on pin

VOSENSE for IO(PFCCOMP) = 0 2.475 2.500 2.525 V

Vovp(VOSENSE) overvoltage protection voltage

on pin VOSENSE 2.60 2.63 2.67 V

Ibst(dual) dual boost current VVINSENSE < Vbst(dual) or

VVOSENSE <2.1 V --15-μA

VVINSENSE > Vbst(dual) --30-nA

Overcurrent protection PFC (pin PFCSENSE)

Vsense(PFC)max maximum PFC sense voltage ΔV/Δt = 50 mV/μs 0.49 0.52 0.55 V

ΔV/Δt = 200 mV/μs 0.52 0.55 0.57 V

tleb(PFC) PFC leading edge blanking

time 250 310 370 ns

Iprot(PFCSENSE) protection current on pin

PFCSENSE −50 - −5nA

Soft start PFC (pin PFCSENSE)

Istart(soft)PFC PFC soft start current −75 −60 −45 μA

Vstart(soft)PFC PFC sof t st art voltage enabling voltage 0.46 0.50 0.54 V

Rstart(soft)PFC PFC soft start resist ance 12 - - kΩ

Oscillator PFC

fsw(PFC)max maximum PFC switching

frequency 100 125 150 kHz

toff(PFC)min minimum PFC off-time 1.1 1.4 1.7 μs

Valley switching PFC (pin PFCAUX)

(ΔV/Δt)vrec(PFC) PFC valley recognition voltage

change with time --1.7V/μs

tvrec(PFC) PFC valley recogniti on time VPFCAUX = 1 V peak-to-peak [2] --300ns

demagnetization to ΔV/Δt = 0 [3] --50ns

tto(vrec)PFC PFC valley recognition time-out

time 346μs

Demagnetization manag ement PFC (pin PFCAUX)

Vth(comp)PFCAUX comparator threshold voltage

on pin PFCAUX −150 −100 −50 mV

tto(demag)PFC PFC demagnetization time-out

time 40 50 60 μs

Iprot(PFCAUX) protection current on pin

PFCAUX VPFCAUX = 50 mV −75 - −5nA

Driver (pin PFCDRIVER)

Isrc(PFCDRIVER) source current on pin

PFCDRIVER VPFCDRIVER = 2V - −0.5 - A

Table 5. Chara cteristics …continued

Tamb =25

C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into

the IC; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 02 — 23 December 2009 23 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

Isink(PFCDRIVER) sink current on pin

PFCDRIVER VPFCDRIVER = 2 V - 0.7 - A

VPFCDRIVER = 10 V - 1.2 - A

VO(PFCDRIVER)max maximum output voltage on pin

PFCDRIVER -1112V

Overvoltage protection flyback (pin FBAUX)

Iovp(FBAUX) overvoltage protection current

on pin FBAUX 279 300 321 μA

Ncy(ovp) number of overvoltage

protection cycles 6812

Demagnetization management flyback (pin FBAUX)

Vth(comp)FBAUX comparator threshold voltage

on pin FBAUX 60 80 110 mV

Iprot(FBAUX) protection current on pin

FBAUX VFBAUX =50 mV −50 - −5nA

Vclamp(FBAUX) clamp voltage on pin FBAUX IFBAUX = −500 μA−1.0 −0.8 −0.6 V

IFBAUX =500 μA 0.5 0.7 0.9 V

tsup(xfmr_ring) transformer ringing

suppression time 1.5 2 2.5 μs

Pulse width modulator flyback

ton(fb)min minimum flyback on-time - tleb -ns

ton(fb)max maximum flyback on-time 32 40 48 μs

Oscillator flyback

fsw(fb)max maximum flyback switching

frequency 100 125 150 kHz

Vstart(VCO)FBCTRL VCO start voltage on pin

FBCTRL 1.3 1.5 1.7 V

Vhys(FBCTRL) hysteresis voltage on pin

FBCTRL [4] -60-mV

ΔVVCO(FBCTRL) VCO voltage difference on pin

FBCTRL --0.1-V

Peak current contro l flyback (pin FBCTRL)

VFBCTRL voltage on pin FBCTRL for maximum flyback peak current 1.85 2.0 2.15 V

Vto(FBCTRL) time-out voltage on pin

FBCTRL enable voltage - 2.5 - V

trip voltage 4.2 4.5 4.8 V

Rint(FBCTRL) internal resistance on pin

FBCTRL -3-kΩ

IO(FBCTRL) output current on pin FBCTRL VFBCTRL = 0 V −1.4 −1.19 −0.93 mA

VFBCTRL = 2 V −0.6 −0.5 −0.4 mA

Ito(FBCTRL) time-out current on pin

FBCTRL VFBCTRL =2.6 V −36 −30 −24 μA

VFBCTRL =4.1 V −34.5 −28.5 −22.5 μA

Valley switching flyback (pin HV)

(ΔV/Δt)vrec(fb) flyback valley recognition

voltage change with time −75 - +75 V/μs

Table 5. Chara cteristics …continued

Tamb =25

C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into

the IC; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 02 — 23 December 2009 24 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

[1] For a typical application with a compensation network on pin PFCCOMP, like the example in Figure 3.

[2] Minimum required voltage change time for valley recognition on pin PFCAUX.

[3] Minimum time required between demagnetization detection and ΔV/Δt = 0 on pin PFCAUX.

[4] Hysteresis for PFC on/off control.

[5] Guaranteed by design.

td(vrec-swon) valley recognition to switch-on

delay time [5] -150-ns

Soft start flyback (pin FBSENSE)

Istart(soft)fb flyback soft start current −75 −60 −45 μA

Vstart(soft)fb flyback soft start voltage enable voltage 0.43 0.49 0.54 V

Rstart(soft)fb flyback soft start resistance 12 - - kΩ

Overcurrent protection flyback (pin FBSENSE)

Vsense(fb)max maximum flyback sense

voltage ΔV/Δt = 50 mV/μs 0.49 0.52 0.55 V

ΔV/Δt = 200 mV/μs 0.52 0.55 0.58 V

tleb(fb) flyback leading edge blanking

time 255 305 355 ns

Istart(OPP)FBAUX OPP start current on pin

FBAUX -−100 - μA

Iopp(red)(FBAUX) reduced overpower protection

current on pin FBAUX Vsense(fb)max has reduced to

0.37 V -−360 - μA

Driver (pin FBDRIVER)

Isrc(FBDRIVER) source current on pin

FBDRIVER VFBDRIVER =2V - −0.5 - A

Isink(FBDRIVER) sink current on pin FBDRIVER VFBDRIVER =2V -0.7-A

VFBDRIVER = 10 V - 1.2 - A

VO(FBDRIVER)(max) maximum output voltage on pin

FBDRIVER -1112V

LATCH input (pin LATCH)

Vprot(LATCH) protection voltage on pin

LATCH 1.23 1.25 1.27 V

IO(LATCH) output curren t on pin LATCH Vprot(LATCH) <VLATCH <Voc(LATCH) −85 −80 −75 μA

Ven(LATCH) enable voltage on pin LATCH at start-up 1.30 1.35 1.40 V

Vhys(LATCH) hysteresis voltage on pin

LATCH Ven(LATCH) −Vprot(LATCH) 80 100 140 mV

Voc(LATCH) open-circuit voltage on pin

LATCH 2.65 2.9 3.15 V

Temperature protection

Tpl(IC) IC protection le ve l te mp erature 130 140 150 °C

Tpl(IC)hys hysteresis of IC protection level

temperature -10-°C

Table 5. Chara cteristics …continued

Tamb =25

C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into

the IC; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 02 — 23 December 2009 25 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

11. Application information

A power supply with the TEA1751(L)T consists of a power factor correction circuit

followed by a flyback converter. See Figure 16.

Capacitor CVCC buffers the IC supply volta ge, which is powered via the high voltage

rectified mains during start-up and via the auxiliary winding of the flyback converter during

operation. Sense resistors RSENSE1 and RSENSE2 convert the current thro ugh the

MOSFETs S1 and S2 into a voltage at pins PFCSENSE and FBSENSE. The values of

RSENSE1 and RSENSE2 de fine the maximum primary pe ak current in MOSFETs S1 and S2.

In the example given, the LATCH pin is connected to a Ne ga tive Temperature Coefficient

(NTC) resistor. When the resistance drops below (typ), the

protection is activated. A capacitor CTIMEOUT is connected to the FBCTRL pin. For a

120 nF capacitor , typically after 10 ms the time-out protection is activated. RLOOP is adde d

so that the time-out capacitor does not interfere with the normal regulation loop.

RS1 and RS2 are added to prevent the soft start capacitor s from being charged during

normal operation due to negative voltage spikes across the sense resistors.

Resistor RAUX1 is added to protect the IC from damage during lightning events.

Fig 17. Typical application diagram TEA17 51(L)T

Vprot LATCH()

IOLATCH()

------------------------------- 15.6 kΩ=

12 11 9 16 13

TEA1751(L)T

014aaa30

RS2 RSS2

CSS2

COUT

RAUX2

RSENSE2

CVCC

RS1

Cbus

CSS1 RSS1

RSENSE1

CTIMEOUT

RLOOP

COMPENSATION

RAUX1

Product data sheet Rev. 02 — 23 December 2009 26 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

12. Package outline

Fig 18. Package outline SOT109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10

1.45

1.25 0.25 0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8 1.27 6.2

5.8

0.7

0.6

0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004

0.057

0.049 0.01 0.019

0.014

0.0100

0.0075

0.39

0.38

0.16

0.15 0.05

1.05

0.041

0.244

0.228

0.028

0.020

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

O16: plastic small outline package; 16 leads; body width 3.9 mm SOT109

-1

Product data sheet Rev. 02 — 23 December 2009 27 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

13. Revision history

Table 6. Revision history

Document ID Release date Data sheet statu s Change notice Supersedes

TEA1751T_LT_2 20091223 Product data sheet - TEA1751T_LT_1

Modifications: •Value for junction temperature (Tj) changed in Table 3.

TEA1751T_LT_1 20090210 Product data sheet - -

Product data sheet Rev. 02 — 23 December 2009 28 of 29

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

14. Legal information

14.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product st atus of device (s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

14.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warrant ies as to t he accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short dat a sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict wit h the short data sheet, the

full data sheet shall pre va il.

14.3 Disclaimers

General — In formation in this document is beli eved to be accurate and

reliable. However, NXP Semiconductors d oes not give an y represent ations or

warranties, expressed or impli ed, as to the accuracy or completeness of such

information and shall have no liability for th e co nsequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are no t designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applicat ions where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environme ntal

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ra tings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other co nditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may af fect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between inf ormation in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Not hing in this document may be interpret ed or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

14.4 Trademarks

Notice: All refe renced brands, produc t names, service names and trademarks

are the property of their respective ow ners.

GreenChip — is a trademark of NXP B.V.

15. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to : salesaddresses@nxp.com

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contain s data from the objective specification for product development .

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

NXP Semiconductors TEA1751T; TEA1751LT

GreenChip III SMPS control IC

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 23 December 2009

Document identifier: TEA1751T_LT_2

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

16. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1 Distinctive features . . . . . . . . . . . . . . . . . . . . . . 1

2.2 Green features . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.3 PFC green features . . . . . . . . . . . . . . . . . . . . . 2

2.4 Flyback green features. . . . . . . . . . . . . . . . . . . 2

2.5 Protection features . . . . . . . . . . . . . . . . . . . . . . 2

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 5

7.1 General control. . . . . . . . . . . . . . . . . . . . . . . . . 5

7.1.1 Start-up and UnderVoltage LockOut

(UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

7.1.2 Supply management. . . . . . . . . . . . . . . . . . . . . 7

7.1.3 Latch input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.1.4 Fast latch reset. . . . . . . . . . . . . . . . . . . . . . . . . 8

7.1.5 Overtemperature protection . . . . . . . . . . . . . . . 8

7.2 Power factor correction circuit . . . . . . . . . . . . . 8

7.2.1 ton control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.2.2 Valley switchin g and demagnetization

(PFCAUX pin). . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.2.3 Frequency limitation . . . . . . . . . . . . . . . . . . . . . 9

7.2.4 Mains voltage compensation

(VINSENSE pin) . . . . . . . . . . . . . . . . . . . . . . . . 9

7.2.5 Soft start-up (pin PFCSENSE) . . . . . . . . . . . . . 9

7.2.6 Low power mode . . . . . . . . . . . . . . . . . . . . . . 10

7.2.7 Dual boost PFC . . . . . . . . . . . . . . . . . . . . . . . 10

7.2.8 Overcurrent protection (PFCSENSE pin) . . . . 11

7.2.9 Mains undervoltage lockout / brownout

protection (VINSENSE pin) . . . . . . . . . . . . . . 11

7.2.10 Overvoltage protection (VOSENSE pin). . . . . 11

7.2.11 PFC open loop protection (VOSENSE pin) . . 11

7.2.12 Driver (pin PFCDRIVER) . . . . . . . . . . . . . . . . 11

7.3 Flyback controller . . . . . . . . . . . . . . . . . . . . . . 12

7.3.1 Multimode operation. . . . . . . . . . . . . . . . . . . . 12

7.3.2 Valley switching (HV pin) . . . . . . . . . . . . . . . . 13

7.3.3 Current mode control (FBSENSE pin) . . . . . . 14

7.3.4 Demagnetization (FBAUX pin) . . . . . . . . . . . . 15

7.3.5 Flyback control / time-out (FBCTRL pin) . . . . 15

7.3.6 Soft start-up (pin FBSENSE) . . . . . . . . . . . . . 17

7.3.7 Maximum on-time. . . . . . . . . . . . . . . . . . . . . . 17

7.3.8 Overvoltage protection (FBAUX pin) . . . . . . . 17

7.3.9 Overcurrent protection (FBSENSE pin) . . . . . 18

7.3.10 Overpower protection. . . . . . . . . . . . . . . . . . . 18

7.3.11 Driver (pin FBDRIVER) . . . . . . . . . . . . . . . . . 19

8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 19

9 Thermal characteristics . . . . . . . . . . . . . . . . . 20

10 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20

11 Application information . . . . . . . . . . . . . . . . . 25

12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 26

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . 27

14 Legal information . . . . . . . . . . . . . . . . . . . . . . 28

14.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 28

14.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

14.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 28

14.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 28

15 Contact information . . . . . . . . . . . . . . . . . . . . 28

16 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29