2011 Microchip Technology Inc. DS80502C-page 1
PIC12(L)F1822/PIC16(L)F1823
The PIC12(L)F1822/PIC16(L)F1823 family devices that
you have received conform functionally to the current
Device Data Sheet (DS41413B), except for the
anomalies describe d in this doc ument.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
The errata describ ed in this document will be addressed
in future revisions of the PIC12(L)F1822/PIC16(L)F1823
silicon.
Data Sheet clarifications and corrections st art on page 7,
following the discu ssion of silicon issues .
The silicon revision level can be identified using the
current version of MPLAB® IDE and Microchip’s
programmers, debuggers, and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
For example, to identify the silicon revision level using
MPLAB IDE in conjunction with MPLAB ICD 2 or
PICkit™ 3:
1. Using the appropriate interface, connect the
device to the MPLAB ICD 2 programmer/
debugger or PICkit™ 3.
2. From the main menu in MPLAB IDE, select
Configure>Select Device, and then select the
target part number in the dialog box.
3. Select the MPLAB hardware tool
(Debugger>Select Tool).
4. Perform a “Connect” operation to the device
(Debugger>Connect). Depending on the
development tool used, the part number and
Device Revision ID value appear in the Output
window.
The DEVREV values for the various PIC12(L)F1822/
PIC16(L)F1823 silicon revisions are shown in Table 1.
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2 apply to the current silicon
revision (A8). Note: If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
TABLE 1: SILICON DEVREV VALUES
Part Number Device ID(1) Revision ID for Silicon Revision(2)
A6 A8
PIC12F1822 10 0111 000x xxxx 06h 08h
PIC12LF1822 10 1000 000x xxxx 06h 08h
PIC16F1823 10 0111 001x xxxx 06h 08h
PIC16LF1823 10 1000 001x xxxx 06h 08h
Note 1: The Device ID is located in the last configuration memor y space.
2: Refer to the “PIC16F/LF182X/PIC16F/LF1822 Memory Programming Specification” (DS41390) for
detailed information on Device and Revision IDs for your specific device.
PIC12(L)F1822/PIC16(L)F1823 Family
Silicon Errata and Data Sheet Clarification
PIC12(L)F1822/PIC16(L)F1823
DS80502C-page 2 2011 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature Item
Number Issue Summary
Affected
Revisions(1)
A6 A8
Oscillator HS Oscillator 1.1 HS Osci llator min. VDD.X
ADC Analog-to-Digital Converter 2.1 ADC conversion does not
complete. X
APFCON Remappable T1Gate 3.1 T1Gate is not remappable. X
Enhanced Capture Compare
PWM (ECCP) Enhance d PWM 4.1 PWM 0% duty cycle direction
change. X
Enhanced Capture Compare
PWM (ECCP) Enhance d PWM 4.2 PWM 0% duty cycle port
steering. X
Clock Switching OSTS Status Bit 5.1 Remai ns clear when 4xPLL
enabled. XX
Timer1 Gate T1Gate Toggle mode 6.1 T1Gate Flip-Flop does not
clear. XX
In-Circuit Serial Program-
ming™ (ICSP™) Low-Voltage Programming 7.1 Bulk Erase not available with
LVP. X
BOR Wake-up from Sleep 8.1 Device may BOR Reset when
waking-up from Sleep. XX
Note 1: Only those issues indicated in the last column apply to the current silicon revision.
2011 Microchip Technology Inc. DS80502C-page 3
PIC12(L)F1822/PIC16(L)F1823
Silicon Errata Issues
1. Module: Oscillator
1.1 HS Oscillator
The HS oscillator requires a minimum voltage of
3.0 volts (at 65°C or less) to operate at 20 MHz.
Work around
None.
Affected Silicon Revisions
2. Module: ADC
2.1 Analog-to-Digital Converter (ADC)
Under certain device operating conditions, the
ADC conversion may not complete properly . When
this occurs, the ADC Interrupt Flag (ADIF) does
not get set, th e GO/DO NE bit d oes not g et cl eared
and the c onv ers io n re sul t does not get loaded in to
the ADRESH and ADRESL result registers.
Work around
Method 1: Select the dedicated RC
oscillator as the ADC conversion
clock source, and perform all
conversions with the device in
Sleep.
Method 2: Provide a fixed delay in software
to stop the A-to-D conversion
manually, after all 10 bits are
converted, but before the
conversion would complete
automatically. The conversion is
stopped by clearing the GO/
DONE bit in software. The GO/
DONE bit must be cleared during
the last ½ TAD cycle, before the
conversion would have
comple ted automatical ly. Refer to
Figure 1 for details.
FIGURE 1: INSTRUCTION CYCLE DELAY CALCULATION EXAMPLE
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A8).
A6 A8
X
FOSC = 32 MHz
TCY = 4/32 MHz = 125 nsec
TAD = 1 µsec, ADCS = FOSC/32
88 TCY
84 TCY
8 TCY
4 TCY
1 TAD 11 TAD
Stop the A/D conversion
between 10.5 and 11 TAD
cycles.
See the Analog-to-Digital
Conversion Timing diagram
in the Analog-to-Digital
Converter section of the
DS41413B data sheet.
}
See the ADC Clock Period (TAD) vs. Device Operating Frequencies table, in the Analog-to-Digital Converter
section of the DS414 13B data shee t.
PIC12(L)F1822/PIC16(L)F1823
DS80502C-page 4 2011 Microchip Technology Inc.
In Figure 1, 88 instruction cycles (TCY) will be
required to complete the full c onvers ion. Each TAD
cycle consists of 8 TCY periods. A fixed delay is
provided to stop the A/D conversion after 86
instruction cycles and terminate the conversion at
the correct time as shown in the figure above.
EXAMPLE 1: CODE EXAMPLE OF
INSTRUCTION CYCLE
DELAY
For other combinations of FOSC, TAD values and
instruction cycle delay counts, refer to Table 3.
TABLE 3: INSTRUCTION CYCLE DELAY
COUNTS FOR OTHER FOSC
AND TAD COMBINATIONS
Affected Silicon Revisions
3. Module: APFCON
3.1 Timer1 Gate
The APFCON register is normally used to remap
the T1 Ga te to an alte rnate pin. Th e T1GSEL bit of
the APFCON register is found to be not writable
and therefore the T1Gate pin cannot be
remappe d. The default v alue for the T1GSEL bit is
0 and, t herefore, the T 1Gate will be found on RA 4.
This affects the PIC16(L)F1823 devices on ly.
Work around
None.
Affected Silicon Revisions
4. Module: Enhanced Capture Compare
PWM (ECCP)
4.1 Enhanced PWM
When the PW M is confi gured for Ful l-Bridge mode
and the duty cycle is set to 0%, writing the
PxM<1:0> bits to change the direction has no
effect on PxA and PxC outputs.
Work around
Increas e the duty cycl e to a va lue grea ter than 0 %
before changing directions.
Affected Silicon Revisions
4.2 Enhanced PWM
In PWM mode, when the duty cycle is set to 0%
and the STRxSYNC bit is set, writing the STRxA,
STRxB, STRxC and the STRxD bits to enable/
disable steering to port pins has no effect on the
outputs.
Work around
Increas e the duty cycl e to a va lue grea ter than 0 %
before enabling/disabling steering to port pins.
Affected Silicon Revisions
Note: The exact delay time will depend on the
choice of FOSC and the TAD divisor
(ADCS) selection. The TCY counts shown
in the timing diagram above apply to this
example only. Refer to Table 3 for the
required delay counts for other
configurations.
FOSC TAD Instruction Cycl e Delay
Counts
32 MHz FOSC/64 172
FOSC/32 86
16 MHz FOSC/64 172
FOSC/32 86
FOSC/16 43
8 MHz FOSC/32 86
FOSC/16 43
A6 A8
X
BSF ADCON0, GO/DONE; Start ADC conversion
; Provide 86
instruction cycle
delay here
BCF ADCON0, GO/DONE; Terminate the
conversion manually
MOVF ADRESH, W ; Read conversion
result
A6 A8
X
A6 A8
X
A6 A8
X
2011 Microchip Technology Inc. DS80502C-page 5
PIC12(L)F1822/PIC16(L)F1823
5. Module: Clock Switching
5.1 OSTS Status Bit
When the 4xPLL is enab led, the Osc illator S tart-u p
Time-out Status (OSTS) bit always remains clear.
Work around
None.
Affected Silicon Revisions
6. Module: Timer1 Gate
6.1 Timer1 Gate Toggle mode
When Timer1 Gate Toggle mode is enabled, it is
possible to measure the full-cycle length of a
Timer1 Gate signal. To perform this function, the
Timer1 Gate source is routed through a flip-flop
that changes state on every incrementing edge of
the gate signal. Timer1 Gate Toggle mode is
enabled by setting the T1GTM bit of the T1GCON
register. When working properly, clearing either
the T1G TM bit or the TM R1ON bit wou ld also clear
the output value of this flip-flop, and hold it clear.
This is done in order to control which edge is being
measured. The issue that exists is that cl earing the
TMR1ON bit does not cl ear the outpu t valu e of the
flip-flop and hold it clear.
Work around
Clear the T1GTM bit in the T1GCON register to
clear and hold clear the output value of the flip-
flop.
Affected Silicon Revisions
7. Module: In-Circuit Serial Programming™
(ICSP™)
7.1 Low-Voltage Programming
The B ulk Eras e featur e is not av ailable with Lo w-
Voltage Programming mode.
A Bulk Erase of the program Flash memory or data
memory cannot be executed in Low-Voltage
Programming mode.
Work around
Method 1: If ICSP Low-Voltage
Prog ramming mode is required,
use row erases to erase the
program memory , as described in
the Program /Verify mode s ectio n
of the Programming
S pecif ication. Dat a memory must
be overwritten with the desired
values.
Method 2: Use the ICSP High-Voltage
Programming mode if a Bulk
Erase is required.
Affected Silicon Revisions
A6 A8
X X
A6 A8
X X
Note: Only t he Bulk Erase featur e will erase the
program or data memory if the code or
dat a protecti on is ena bled. Meth od 2 must
be used if the code or data protection is
enabled.
A6 A8
X
PIC12(L)F1822/PIC16(L)F1823
DS80502C-page 6 2011 Microchip Technology Inc.
8. Module: BOR
8.1 BOR Re set
This issue affects only the PIC12(L)F1822/
PIC16(L) F1823 devi ces . The devic e ma y un derg o
a BOR Reset when waking-up from Sleep and
BOR is re -enab led. A B OR Rese t may a lso oc cur
the moment the software BOR is enabled.
Unde r certain voltage and te mper ature co nditi ons
and when either SBODEN or BOR_NSLEEP is
select ed, the devices may occasiona lly reset when
waking-up from Sleep or BOR is enabled.
Work around
Method 1: In appli catio ns w here BO R use is
not critical, turn off the BOR in the
Configuration Word.
Method 2: Set the FVREN bit of the
FVRCON register. Maintain this
bit on at al l times.
Method 3: When BOR module is needed
only during run-time, use the
softw are - en a ble d B OR by set ti ng
the SBODEN option on the
Conf igurat ion Word. BO R sho uld
be turned off by software before
Sleep, then follow the below
sequence for turning BOR on
after Wake-up:
a. Wake-up event occurs;
b. T urn on FVR (FVREN bit of the
FVRCON register);
c. Wait until FVRRDY bit is set;
d. Wait 15 µs after the FVR
Ready bit is set;
e. Manually turn on the BOR.
Method 4: Use the software-enabled BOR
as des cribed in Me thod 3, but us e
the following sequence:
a. Switch to internal 32 kHz
oscillator immediately before
Sleep;
b. Upon wake-up, turn on FVR
(FVREN bit of the FVRCON
register);
c. Manually turn on the BOR;
d. Switch the clock back to the
prefe rred clo ck sourc e.
Affected Silicon Revisions
Note: When using the software BOR follow the
steps in Methods 3 or 4 above when
enabling BOR for the first time during
program execution.
A6 A8
X X
2011 Microchip Technology Inc. DS80502C-page 7
PIC12(L)F1822/PIC16(L)F1823
Data Sheet Clarifications
The foll owing ty pographic corrections and clar ification s
are to be note d fo r the latest ve rsi on of the devi ce data
sheet (DS41413B):
None.
PIC12(L)F1822/PIC16(L)F1823
DS80502C-page 8 2011 Microchip Technology Inc.
APPENDIX A: DOCUMENT
REVISION HISTORY
Rev A Document (6/2010)
Initial release of this docum ent.
Rev B Document (11/2010)
Updated errata to the new format; Added Silicon
Revision A8; Added Modu le 5: Clock Switching.
Rev C Document (03/2011)
Added Modules 6, 7 and 8.
2011 Microchip Technology Inc. DS80502C-page 9
Information contained in this publication regarding device
applications a nd t he lik e is provid ed only for your convenience
and may be su perseded by updates. I t is y our respo ns i bil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
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OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PI C START,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Em bedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI- TIDE, In-Circu it Se rial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Cert ified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-948-8
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that it s family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Mill ennium Copyright Act. If such act s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS80502C-page 10 2011 Microchip Technology Inc.
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