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LM22673-ADJ

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SS SW

BOOT

GND

VIN

VOUT

IADJ

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LM22673

LM22673-Q1

SNVS586O –SEPTEMBER 2008–REVISED NOVEMBER 2014

LM22673/-Q1 42 V, 3 A SIMPLE SWITCHER

, Step-Down Voltage Regulator

with Features

1 Features 3 Description

The LM22673 switching regulator provides all of the

1• Wide Input Voltage Range: 4.5 V to 42 V functions necessary to implement an efficient high

• Internally Compensated Voltage Mode Control voltage step-down (buck) regulator using a minimum

• Stable with Low ESR Ceramic Capacitors of external components. This easy to use regulator

incorporates a 42 V N-channel MOSFET switch

• 120 mΩN-Channel MOSFET PFM Package capable of providing up to 3 A of load current.

• 100 mΩN-Channel MOSFET SO PowerPAD Excellent line and load regulation along with high

Package efficiency (> 90%) are featured. Voltage mode control

• Output Voltage Options: offers short minimum on-time, allowing the widest

-ADJ (Outputs as Low as 1.285 V) ratio between input and output voltages. Internal loop

-5.0 (Output Fixed to 5 V) compensation means that the user is free from the

tedious task of calculating the loop compensation

• ±1.5% Feedback Reference Accuracy components. Fixed 5 V output and adjustable output

• Switching Frequency of 500 kHz voltage options are available. A switching frequency

• –40°C to 125°C Operating Junction of 500 kHz allows for small external components and

Temperature Range good transient response. An adjustable soft-start

feature is provided through the selection of a single

• Adjustable Soft-Start external capacitor. In addition, the switch current limit

• Adjustable Current Limit can be programmed with a single external resistor,

• Integrated Boot-Strap Diode allowing solution optimization. The LM22673 device

also has built-in thermal shutdown, and current

• Fully Webench®Enabled limiting to protect against accidental overloads.

• LM22673-Q1 is an Automotive Grade Product

that is AEC-Q100 Grade 1 Qualified (–40°C to The LM22673 device is a member of Texas

Instruments' SIMPLE SWITCHER®family. The

+125°C Junction Temperature) SIMPLE SWITCHER®concept provides for an easy

• SO PowerPAD (Exposed Pad) to use complete design using a minimum number of

• PFM (Exposed Pad) external components and the TI WEBENCH®design

tool. TI's WEBENCH®tool includes features such as

2 Applications external component calculation, electrical simulation,

thermal simulation, and Build-It boards for easy

• Industrial Control design-in.

• Telecom and Datacom Systems

• Embedded Systems Device Information(1)

• Conversions from Standard 24 V, 12 V and 5 V PART NUMBER PACKAGE BODY SIZE (NOM)

Input Rails HSOP (8) 4.89 mm x 3.90 mm

LM22673,

LM22673-Q1 TO-263 10.16 mm x 9.85 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Application Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM22673

LM22673-Q1

SNVS586O –SEPTEMBER 2008–REVISED NOVEMBER 2014

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Table of Contents

7.4 Device Functional Modes........................................ 10

1 Features.................................................................. 18 Applications and Implementation ...................... 13

2 Applications ........................................................... 18.1 Application Information............................................ 13

3 Description............................................................. 18.2 Typical Application.................................................. 14

4 Revision History..................................................... 29 Power Supply Recommendations...................... 17

5 Pin Configuration and Functions......................... 310 Layout................................................................... 17

6 Specifications......................................................... 410.1 Layout Guidelines ................................................. 17

6.1 Absolute Maximum Ratings ...................................... 410.2 Layout Examples................................................... 18

6.2 Handling Ratings....................................................... 410.3 Thermal Considerations........................................ 19

6.3 Handling Ratings: LM22673-Q1................................ 411 Device and Documentation Support................. 20

6.4 Recommended Operating Conditions....................... 411.1 Documentation Support ........................................ 20

6.5 Thermal Information.................................................. 411.2 Related Links ........................................................ 20

6.6 Electrical Characteristics........................................... 511.3 Trademarks........................................................... 20

6.7 Typical Characteristics.............................................. 611.4 Electrostatic Discharge Caution............................ 20

7 Detailed Description.............................................. 711.5 Glossary................................................................ 20

7.1 Overview................................................................... 712 Mechanical, Packaging, and Orderable

7.2 Functional Block Diagram......................................... 8Information........................................................... 20

7.3 Feature Description................................................... 8

4 Revision History

Changes from Revision N (April 2013) to Revision O Page

• Added Pin Configuration and Functions section, Handling Rating table, Thermal Information table, Feature

Description section, Device Functional Modes,Application and Implementation section, Power Supply

Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,

Packaging, and Orderable Information section ..................................................................................................................... 1

• Deleted Inverting Regulator Application .............................................................................................................................. 13

Changes from Revision M (April 2013) to Revision N Page

• Changed from National format toTI format ............................................................................................................................ 1

Product Folder Links: LM22673 LM22673-Q1

Exposed Pad

Connect to GND

5 IADJ

6 FB

3 BOOT

1 SW

2 VIN

4 GND

7 SS

Exposed Pad

Connect to GND

IADJ 3

FB 4

BOOT 1

NC 2

8 SW

7 VIN

6 GND

5 SS

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SNVS586O –SEPTEMBER 2008–REVISED NOVEMBER 2014

5 Pin Configuration and Functions

8-Pin

HSOP

Top View

7-Pin

PFM

Top View

Pin Functions

PIN TYPE DESCRIPTION APPLICATION INFORMATION

NAME PFM

PowerPAD

BOOT 1 3 I Bootstrap input Provides the gate voltage for the high side NFET.

Pin is not electrically connected inside the chip.

NC 2 — — Not Connected Pin does function as thermal conductor.

A resistor attached between this pin and GND can

IADJ 3 5 I Current limit adjust input pin be used to set the current limit threshold. Pin can

be left floating and internal setting will be default.

FB 4 6 I Feedback input Feedback input to regulator.

Used to increase soft-start time. See Soft-Start

SS 5 7 Soft-Start pin section of data sheet.

Ground input to regulator;

GND 6 4 — System ground pin.

system common

VIN 7 2 I Input voltage Supply input to the regulator.

SW 8 1 O Switch output Switching output of regulator.

Connect to ground. Provides thermal connection

EP EP EP — Exposed Pad to PCB. See Thermal Considerations.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

VIN to GND 43 V

SS, IADJ Pin Voltage –0.5 7 V

SW to GND(1) –5 VIN V

Boot Pin Voltage VSW + 7 V

FB Pin Voltage –0.5 7 V

Power Dissipation Internally Limited

Junction Temperature 150 °C

For soldering specifications, refer to Application Report Absolute Maximum Ratings for Soldering (SNOA549).

(1) The absolute maximum specification of the ‘SW to GND’ applies to dc voltage. An extended negative voltage limit of –10 V applies to a

pulse of up to 50 ns.

6.2 Handling Ratings MIN MAX UNIT

Tstg Storage temperature range –65 150 °C

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

V(ESD) Electrostatic discharge –2 2 V

pins(1)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Handling Ratings: LM22673-Q1 MIN MAX UNIT

Tstg Storage temperature range –65 150 °C

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) –2 2 kV

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.4 Recommended Operating Conditions MIN MAX UNIT

VIN Supply Voltage 4.5 42 V

Junction Temperature –40 125 °C

6.5 Thermal Information LM22673

THERMAL METRIC(1) DDA NDR UNIT

8 PINS 7 PINS

RθJA Junction-to-ambient thermal resistance 60 22 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

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6.6 Electrical Characteristics

Typical values represent the most likely parametric norm at TA= TJ= 25°C, and are provided for reference purposes only.

Unless otherwise specified: VIN = 12 V.

PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT

LM22673-5.0

VIN = 8 V to 42 V 4.925 5.0 5.075

VFB Feedback Voltage V

VIN = 8 V to 42 V, –40°C ≤TJ≤125°C 4.9 5.1

LM22673-ADJ

VIN = 4.7 V to 42 V 1.266 1.285 1.304

VFB Feedback Voltage V

VIN = 4.7 V to 42 V, –40°C ≤TJ≤125°C 1.259 1.311

ALL OUTPUT VOLTAGE VERSIONS

VFB = 5 V 3.4

IQQuiescent Current mA

VFB = 5 V, –40°C ≤TJ≤125°C 6

0.8

VADJ Current Limit Adjust Voltage V

–40°C ≤TJ≤125°C 0.65 0.9

3.4 4.2 5.3

ICL Current Limit A

–40°C ≤TJ≤125°C 3.35 5.5

PFM Package 0.12 0.16

PFM Package, –40°C ≤TJ≤125°C 0.22

RDS(ON) Switch On-Resistance Ω

SO PowerPAD Package 0.10 0.16

SO PowerPAD Package, –40°C ≤TJ≤125°C 0.20

500

fOOscillator Frequency kHz

–40°C ≤TJ≤125°C 400 600

200

TOFFMIN Minimum Off-time ns

–40°C ≤TJ≤125°C 100 300

TONMIN Minimum On-time 100 ns

IBIAS Feedback Bias Current VFB = 1.3 V (ADJ Version Only) 230 nA

EN Input = 0 V 50

ISS Soft-start Current µA

EN Input = 0 V, –40°C ≤TJ≤125°C 30 70

Thermal Shutdown

TSD 150 °C

Threshold

(1) MIN and MAX limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation

using Statistical Quality Control (SQC) methods. Limits are used to calculate TI's Average Outgoing Quality Level (AOQL).

(2) Typical values represent most likely parametric norms at the conditions specified and are not ensured.

Product Folder Links: LM22673 LM22673-Q1

1.5

1.2

1.4

0.8

0.9

0.6

0.7

1.0

1.1

1.3

–50 –25 0 25 50 75 100 125

NORMALIZED RDS(ON)

TEMPERATURE (°C)

PFM Package

SO Package

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6.7 Typical Characteristics

Vin = 12 V, TJ= 25°C (unless otherwise specified)

Figure 1. Efficiency vs IOUT and VIN Figure 2. Current Limit vs Temperature

VOUT = 3.3 V

Figure 3. Normalized Switching Frequency vs Temperature Figure 4. Feedback Bias Current vs Temperature

Figure 5. Normalized Feedback Voltage vs Temperature Figure 6. Normalized RDS(ON) vs Temperature

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Typical Characteristics (continued)

Vin = 12 V, TJ= 25°C (unless otherwise specified)

Figure 8. Soft-Start Current vs Temperature

Figure 7. Normalized Feedback Voltage vs Input Voltage

Figure 9. Current Limit vs IADJ Resistor

7 Detailed Description

7.1 Overview

The LM22673 device incorporates a voltage mode constant frequency PWM architecture. In addition, input

voltage feedforward is used to stabilize the loop gain against variations in input voltage. This allows the loop

compensation to be optimized for transient performance. The power MOSFET, in conjunction with the diode,

produce a rectangular waveform at the switch pin, that swings from about zero volts to VIN. The inductor and

output capacitor average this waveform to become the regulator output voltage. By adjusting the duty cycle of

this waveform, the output voltage can be controlled. The error amplifier compares the output voltage with the

internal reference and adjusts the duty cycle to regulate the output at the desired value.

The internal loop compensation of the -ADJ option is optimized for outputs of 5V and below. If an output voltage

of 5V or greater is required, the -5.0 option can be used with an external voltage divider. The minimum output

voltage is equal to the reference voltage, that is, 1.285 V (typ).

Product Folder Links: LM22673 LM22673-Q1

SS SS

T 26 10 C» ´ ×

LOGIC

OSC

TYPE III

COMP

1.285V

Soft-Start

INT REG, EN,UVLO

GNDRT/SYNC

BOOT

VIN

VOUT

Error Amp.

PWM Cmp.

Vcc

ILimit

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7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 UVLO

The LM22673 also incorporates an input undervoltage lock-out (UVLO) feature. This prevents the regulator from

turning on when the input voltage is not great enough to properly bias the internal circuitry. The rising threshold is

4.3 V (typ) while the falling threshold is 3.9 V (typ).

7.3.2 Soft-Start

The soft-start feature allows the regulator to gradually reach steady-state operation, thus reducing start-up

stresses. The internal soft-start feature brings the output voltage up in about 500 µs. This time can be extended

by using an external capacitor connected to the SS pin. Values in the range of 100 nF to 1 µF are recommended.

The approximate soft-start time can be estimated from Equation 1.

(1)

Soft-start is reset any time the part is shut down or a thermal overload event occurs.

Product Folder Links: LM22673 LM22673-Q1

100 1k 10k 100k 1M 10M

COMPENSATOR GAIN (dB)

FREQUENCY (Hz)

-ADJ

-5.0

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Feature Description (continued)

7.3.3 Boot-Strap Supply

The LM22673 incorporates a floating high-side gate driver to control the power MOSFET. The supply for this

driver is the external boot-strap capacitor connected between the BOOT pin and SW. A good quality 10 nF

ceramic capacitor must be connected to these pins with short, wide PCB traces. One reason the regulator

imposes a minimum off-time is to ensure that this capacitor recharges every switching cycle. A minimum load of

about 5 mA is required to fully recharge the boot-strap capacitor in the minimum off-time. Some of this load can

be provided by the output voltage divider, if used.

7.3.4 Internal Compensation

The LM22673 has internal loop compensation designed to provide a stable regulator over a wide range of

external power stage components. The internal compensation of the -ADJ option is optimized for output voltages

below 5 V. If an output voltage of 5 V or greater is needed, the -5.0 option with an external resistor divider can be

used.

Ensuring stability of a design with a specific power stage (inductor and output capacitor) can be tricky. The

LM22673 stability can be verified using the WEBENCH Designer online circuit simulation tool. A quick start

spreadsheet can also be downloaded from the online product folder.

The complete transfer function for the regulator loop is found by combining the compensation and power stage

transfer functions. The LM22673 has internal type III loop compensation, as detailed in Figure 10. This is the

approximate "straight line" function from the FB pin to the input of the PWM modulator. The power stage transfer

function consists of a dc gain and a second order pole created by the inductor and output capacitor(s). Due to

the input voltage feedforward employed in the LM22673, the power stage dc gain is fixed at 20 dB. The second

order pole is characterized by its resonant frequency and its quality factor (Q). For a first pass design, the

product of inductance and output capacitance should conform to Equation 2.

(2)

Alternatively, this pole should be placed between 1.5 kHz and 15 kHz and is given by Equation 3.

(3)

The Q factor depends on the parasitic resistance of the power stage components and is not typically in the

control of the designer. Of course, loop compensation is only one consideration when selecting power stage

components (see the Applications and Implementation section for more details).

Figure 10. Compensator Gain

In general, hand calculations or simulations can only aid in selecting good power stage components. Good

design practice dictates that load and line transient testing should be done to verify the stability of the application.

Also, Bode plot measurements should be made to determine stability margins. AN-1889 How to Measure the

Loop Transfer Function of Power Supplies (SNVA364) shows how to perform a loop transfer function

measurement with only an oscilloscope and function generator.

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7.4 Device Functional Modes

7.4.1 Current Limit

The LM22673 has current limiting to prevent the switch current from exceeding safe values during an accidental

overload on the output. This peak current limit is found in the Electrical Characteristics table under the heading of

ICL. The maximum load current that can be provided, before current limit is reached, is determined from

Equation 4.

(4)

Where:

L is the value of the power inductor.

When the LM22673 enters current limit, the output voltage will drop and the peak inductor current will be fixed at

ICL at the end of each cycle. The switching frequency will remain constant while the duty cycle drops. The load

current will not remain constant, but will depend on the severity of the overload and the output voltage.

For very severe overloads ("short-circuit"), the regulator changes to a low frequency current foldback mode of

operation. The frequency foldback is about 1/5 of the nominal switching frequency. This will occur when the

current limit trips before the minimum on-time has elapsed. This mode of operation is used to prevent inductor

current "run-away", and is associated with very low output voltages when in overload. Equation 5 can be used to

determine what level of output voltage will cause the part to change to low frequency current foldback.

(5)

Where:

Fsw is the normal switching frequency.

Vin is the maximum for the application.

If the overload drives the output voltage to less than or equal to Vx, the part will enter current foldback mode. If a

given application can drive the output voltage to ≤Vx, during an overload, then a second criterion must be

checked. Equation 6 gives the maximum input voltage, when in this mode, before damage occurs.

(6)

Where:

Vsc is the value of output voltage during the overload.

fsw is the normal switching frequency.

NOTE

If the input voltage should exceed this value, while in foldback mode, the regulator and/or

the diode may be damaged.

It is important to note that the voltages in Equation 4 through Equation 6 are measured at the inductor. Normal

trace and wiring resistance will cause the voltage at the inductor to be higher than that at a remote load.

Therefore, even if the load is shorted with zero volts across its terminals, the inductor will still see a finite voltage.

It is this value that should be used for Vxand Vsc in the calculations. In order to return from foldback mode, the

load must be reduced to a value much lower than that required to initiate foldback. This load "hysteresis" is a

normal aspect of any type of current limit foldback associated with voltage regulators.

The safe operating area, when in short circuit mode, is shown in Figure 11. Operating points below and to the

right of the curve represent safe operation.

Product Folder Links: LM22673 LM22673-Q1

0.0 0.2 0.4 0.6 0.8 1.0 1.2

INPUT VOLTAGE (v)

SHORT CIRCUIT VOLTAGE (v)

SAFE OPERATING AREA

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Device Functional Modes (continued)

Figure 11. SOA

7.4.2 Current-Limit Adjustment

A key feature of the LM22673 is the ability to adjust the peak switch current limit. This can be useful when the full

current capability of the regulator is not required for a given application. A smaller current limit may allow the use

of power components with lower current ratings, thus saving space and reducing cost. A single resistor between

the IADJ pin and ground controls the current limit in accordance with Figure 12. The current limit mode is set

during start-up of the regulator. When VIN is applied, a weak pullup is connected to the IADJ pin and, after

approximately 100 µs, the voltage on the pin is checked against a threshold of about 0.8V. With the IADJ pin

open, the voltage floats above this threshold, and the current limit is set to the default value of 4.2A (typ). With a

resistor present, an internal reference holds the pin voltage at 0.8 V; the resulting current sets the current limit.

The accuracy of the adjusted current limit will be slightly worse than that of the default value, that is, +35% /

–25% is to be expected. Resistor values should not exceed the limits shown in Figure 12.

Figure 12. Current Limit vs IADJ Resistor

7.4.3 Thermal Protection

Internal thermal shutdown circuitry protects the LM22673 should the maximum junction temperature be

exceeded. This protection is activated at about 150°C, with the result that the regulator will shutdown until the

temperature drops below about 135°C.

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Device Functional Modes (continued)

7.4.4 Duty-Cycle Limits

Ideally the regulator would control the duty cycle over the full range of zero to one. However due to inherent

delays in the circuitry, there are limits on both the maximum and minimum duty cycles that can be reliably

controlled. This in turn places limits on the maximum and minimum input and output voltages that can be

converted by the LM22673. A minimum on-time is imposed by the regulator in order to correctly measure the

switch current during a current limit event. A minimum off-time is imposed in order the re-charge the bootstrap

capacitor. Equation 7 can be used to determine the approximate maximum input voltage for a given output

voltage.

(7)

Where:

Fsw is the switching frequency.

TON is the minimum on-time.

Both parameters are found in the Electrical Characteristics table.

Nominal values should be used. The worst case is lowest output voltage. If this input voltage is exceeded, the

regulator will skip cycles, effectively lowering the switching frequency. The consequences of this are higher

output voltage ripple and a degradation of the output voltage accuracy.

The second limitation is the maximum duty cycle before the output voltage will "dropout" of regulation. Equation 8

can be used to approximate the minimum input voltage before dropout occurs.

(8)

Where:

The values of TOFF and RDS(ON) are found in the Electrical Characteristics table.

The worst case here is largest load. In this equation, RLis the dc inductor resistance. Of course, the lowest input

voltage to the regulator must not be less than 4.5 V (typ).

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Vout

RFBT

RFBB

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8 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM22673 device is a step down dc-to-dc regulator. It is typically used to convert a higher dc voltage to a

lower dc voltage with a maximum output current of 3 A. Detailed Design Procedure can be used to select

components for the LM22673 device. Alternately, the WEBENCH® software may be used to generate complete

designs. When generating a design, the WEBENCH® software utilizes iterative design procedure and accesses

comprehensive databases of components. Go to WEBENCH Designer for more details. This section presents a

simplified discussion of the design process.

8.1.1 Output Voltage Divider Selection

For output voltages between about 1.285 V and 5 V, the -ADJ option should be used, with an appropriate voltage

divider as shown in Figure 13.Equation 9 can be used to calculate the resistor values of this divider.

(9)

A good value for RFBB is 1 kΩ. This will help to provide some of the minimum load current requirement and

reduce susceptibility to noise pick-up. The top of RFBT should be connected directly to the output capacitor or to

the load for remote sensing. If the divider is connected to the load, a local high-frequency bypass should be

provided at that location.

For output voltages of 5 V, the -5.0 option should be used. In this case no divider is needed and the FB pin is

connected to the output. The approximate values of the internal voltage divider are as follows: 7.38 kΩfrom the

FB pin to the input of the error amplifier and 2.55 kΩfrom there to ground.

Both the -ADJ and -5.0 options can be used for output voltages greater than 5 V, by using the correct output

divider. As mentioned in the Internal Compensation section, the -5.0 option is optimized for output voltages of 5

V. However, for output voltages greater than 5 V, this option may provide better loop bandwidth than the -ADJ

option, in some applications. If the -5.0 option is to be used at output voltages greater than 5 V, Equation 10

should be used to determine the resistor values in the output divider.

(10)

A value of RFBB of about 1 kΩis a good first choice.

Figure 13. Resistive Feedback Divider

A maximum value of 10 kΩis recommended for the sum of RFBB and RFBT to maintain good output voltage

accuracy for the -ADJ option. A maximum of 2 kΩis recommended for the -5.0 option. For the -5.0 option, the

total internal divider resistance is typically 9.93 kΩ.

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LM22673-ADJ

GND

VIN

BOOT

GND

IADJ

VIN 4.5V to 42V

22 PFC1

6.8 PF

10 nF L1

8.2 PH

120 PF

GND

RFBT

1.54 k:

RFBB

976:

60V, 5A

VOUT 3.3V

1 PF

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Application Information (continued)

In all cases the output voltage divider should be placed as close as possible to the FB pin of the LM22673,

because this is a high impedance input and is susceptible to noise pick-up.

8.1.2 Power Diode

A Schottky-type power diode is required for all LM22673 applications. Ultra-fast diodes are not recommended

and may result in damage to the IC due to reverse recovery current transients. The near ideal reverse recovery

characteristics and low forward voltage drop of Schottky diodes are particularly important for high input voltage

and low output voltage applications common to the LM22673. The reverse breakdown rating of the diode should

be selected for the maximum VIN, plus some safety margin. A good rule of thumb is to select a diode with a

reverse voltage rating of 1.3 times the maximum input voltage.

Select a diode with an average current rating at least equal to the maximum load current that will be seen in the

application.

8.2 Typical Application

8.2.1 Typical Buck Regulator Application

Figure 14 shows an example of converting an input voltage range of 5.5 V to 42 V, to an output of 3.3 V at 3 A.

Figure 14. Typical Buck Regulator Application

8.2.1.1 Design Requirements

DESIGN PARAMETERS EXAMPLE VALUE

Driver Supply Voltage (VIN) 5.5 to 42 V

Output Voltage (VOUT) 3.3 V

RFBT Calculated based on RFBB and VREF of 1.285 V.

RFBB 1 kΩto 10 kΩ

IOUT 3 A

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 External Components

The following guidelines should be used when designing a step-down (buck) converter with the LM22673.

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8.2.1.2.2 Inductor

The inductor value is determined based on the load current, ripple current, and the minimum and maximum input

voltages. To keep the application in continuous conduction mode (CCM), the maximum ripple current, IRIPPLE ,

should be less than twice the minimum load current.

The general rule of keeping the inductor current peak-to-peak ripple around 30% of the nominal output current is

a good compromise between excessive output voltage ripple and excessive component size and cost. Using this

value of ripple current, the value of inductor, L, is calculated using Equation 11.

(11)

Where:

Fsw is the switching frequency.

Vin should be taken at its maximum value, for the given application.

The formula in Equation 11 provides a guide to select the value of the inductor L; the nearest standard value will

then be used in the circuit.

Once the inductor is selected, the actual ripple current can be determined by Equation 12.

(12)

Increasing the inductance will generally slow down the transient response but reduce the output voltage ripple.

Reducing the inductance will generally improve the transient response but increase the output voltage ripple.

The inductor must be rated for the peak current, IPK, in a given application, to prevent saturation. During normal

loading conditions, the peak current is equal to the load current plus 1/2 of the inductor ripple current.

During an overload condition, as well as during certain load transients, the controller may trip current limit. In this

case the peak inductor current is given by ICL, found in the Electrical Characteristics table. Good design practice

requires that the inductor rating be adequate for this overload condition.

NOTE

If the inductor is not rated for the maximum expected current, it can saturate resulting in

damage to the LM22673 and/or the power diode.

This consideration highlights the value of the current limit adjust feature of the LM22673.

8.2.1.2.3 Input Capacitor

The input capacitor selection is based on both input voltage ripple and RMS current. Good quality input

capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the regulator current

during switch on-time. Low ESR ceramic capacitors are preferred. Larger values of input capacitance are

desirable to reduce voltage ripple and noise on the input supply. This noise may find its way into other circuitry,

sharing the same input supply, unless adequate bypassing is provided. A very approximate formula for

determining the input voltage ripple is shown in Equation 13.

(13)

Where:

Vri is the peak-to-peak ripple voltage at the switching frequency.

Another concern is the RMS current passing through this capacitor. Equation 14 gives an approximation to this

current.

(14)

The capacitor must be rated for at least this level of RMS current at the switching frequency.

Product Folder Links: LM22673 LM22673-Q1

LM22673

LM22673-Q1

SNVS586O –SEPTEMBER 2008–REVISED NOVEMBER 2014

www.ti.com

All ceramic capacitors have large voltage coefficients, in addition to normal tolerances and temperature

coefficients. To help mitigate these effects, multiple capacitors can be used in parallel to bring the minimum

capacitance up to the desired value. This may also help with RMS current constraints by sharing the current

among several capacitors. Many times it is desirable to use an electrolytic capacitor on the input, in parallel with

the ceramics. The moderate ESR of this capacitor can help to damp any ringing on the input supply caused by

long power leads. This method can also help to reduce voltage spikes that may exceed the maximum input

voltage rating of the LM22673.

It is good practice to include a high frequency bypass capacitor as close as possible to the LM22673. This small

case size, low ESR, ceramic capacitor should be connected directly to the VIN and GND pins with the shortest

possible PCB traces. Values in the range of 0.47 µF to 1 µF are appropriate. This capacitor helps to provide a

low impedance supply to sensitive internal circuitry. It also helps to suppress any fast noise spikes on the input

supply that may lead to increased EMI.

8.2.1.2.4 Output Capacitor

The output capacitor is responsible for filtering the output voltage and supplying load current during transients.

Capacitor selection depends on application conditions as well as ripple and transient requirements. Best

performance is achieved with a parallel combination of ceramic capacitors and a low ESR SP™ or POSCAP™

type. Very low ESR capacitors such as ceramics reduce the output ripple and noise spikes, while higher value

electrolytics or polymers provide large bulk capacitance to supply transients. Assuming very low ESR,

Equation 15 gives an approximation to the output voltage ripple.

(15)

Typically, a total value of 100 µF, or greater, is recommended for output capacitance.

In applications with Vout less than 3.3 V, it is critical that low ESR output capacitors are selected. This will limit

potential output voltage overshoots as the input voltage falls below the device normal operating range.

8.2.1.2.5 Boot-Strap Capacitor

The bootstrap capacitor between the BOOT pin and the SW pin supplies the gate current to turn on the N-

channel MOSFET. The recommended value of this capacitor is 10 nF and should be a good quality, low ESR

ceramic capacitor. In some cases it may be desirable to slow down the turn-on of the internal power MOSFET, in

order to reduce EMI. This can be done by placing a small resistor in series with the Cboot capacitor. Resistors in

the range of 10 Ωto 50 Ωcan be used. This technique should only be used when absolutely necessary, because

it will increase switching losses and thereby reduce efficiency.

8.2.1.3 Application Curve

Figure 15. Efficiency vs IOUT and VIN

VOUT = 3.3 V

Product Folder Links: LM22673 LM22673-Q1

LM22673

LM22673-Q1

www.ti.com

SNVS586O –SEPTEMBER 2008–REVISED NOVEMBER 2014

9 Power Supply Recommendations

The LM22673 device is designed to operate from an input voltage supply range between 4.5 V and 42 V. This

input supply should be well regulated and able to withstand maximum input current and maintain a stable

voltage. The resistance of the input supply rail should be low enough that an input current transient does not

cause a high enough drop at the LM22673 supply voltage that can cause a false UVLO fault triggering and

system reset. If the input supply is located more than a few inches from the LM22673, additional bulk

capacitance may be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not

critical, but a 47 μF or 100 μF electrolytic capacitor is a typical choice.

10 Layout

10.1 Layout Guidelines

Board layout is critical for the proper operation of switching power supplies. First, the ground plane area must be

sufficient for thermal dissipation purposes. Second, appropriate guidelines must be followed to reduce the effects

of switching noise. Switch mode converters are very fast switching devices. In such cases, the rapid increase of

input current combined with the parasitic trace inductance generates unwanted L di/dt noise spikes. The

magnitude of this noise tends to increase as the output current increases. This noise may turn into

electromagnetic interference (EMI) and can also cause problems in device performance. Therefore, care must be

taken in layout to minimize the effect of this switching noise.

The most important layout rule is to keep the ac current loops as small as possible. Figure 16 shows the current

flow in a buck converter. The top schematic shows a dotted line which represents the current flow during the FET

switch on-state. The middle schematic shows the current flow during the FET switch off-state.

The bottom schematic shows the currents referred to as ac currents. These ac currents are the most critical

because they are changing in a very short time period. The dotted lines of the bottom schematic are the traces to

keep as short and wide as possible. This will also yield a small loop area reducing the loop inductance. To avoid

functional problems due to layout, review the PCB layout example. Best results are achieved if the placement of

the LM22673, the bypass capacitor, RFFB, RFBT, the Schottky diode and the inductor are placed as shown in the

example. In the layout shown, R1 = RFBB and R2 = RFBT. It is also recommended to use 2 oz copper boards or

heavier to help thermal dissipation and to reduce the parasitic inductances of board traces. See AN-1229

SIMPLE SWITCHER ® PCB Layout Guidelines (SNVA054) for more information.

Figure 16. Current Flow in a Buck Application

Product Folder Links: LM22673 LM22673-Q1

LM22673

LM22673-Q1

SNVS586O –SEPTEMBER 2008–REVISED NOVEMBER 2014

www.ti.com

10.2 Layout Examples

Figure 17. PCB Layout Example for PFM Package

Figure 18. PCB Layout Example for SO PowerPAD Package

Product Folder Links: LM22673 LM22673-Q1

LM22673

LM22673-Q1

www.ti.com

SNVS586O –SEPTEMBER 2008–REVISED NOVEMBER 2014

10.3 Thermal Considerations

The components with the highest power dissipation are the power diode and the power MOSFET internal to the

LM22673 regulator. The easiest method to determine the power dissipation within the LM22673 is to measure

the total conversion losses then subtract the power losses in the diode and inductor. The total conversion loss is

the difference between the input power and the output power. An approximation for the power diode loss is

shown in Equation 16.

(16)

Where:

VDis the diode voltage drop.

An approximation for the inductor power is determined by Equation 17.

(17)

Where:

RLis the dc resistance of the inductor.

The 1.1 factor is an approximation for the ac losses.

The regulator has an exposed thermal pad to aid power dissipation. Adding multiple vias under the device to the

ground plane will greatly reduce the regulator junction temperature. Selecting a diode with an exposed pad will

also aid the power dissipation of the diode. The most significant variables that affect the power dissipation of the

regulator are output current, input voltage and operating frequency. The power dissipated while operating near

the maximum output current and maximum input voltage can be appreciable. The junction-to-ambient thermal

resistance of the LM22673 will vary with the application. The most significant variables are the area of copper in

the PC board, the number of vias under the IC exposed pad and the amount of forced air cooling provided. A

large continuos ground plane on the top or bottom PCB layer will provide the most effective heat dissipation. The

integrity of the solder connection from the IC exposed pad to the PC board is critical. Excessive voids will greatly

diminish the thermal dissipation capacity. The junction-to-ambient thermal resistance of the LM22673 SO

PowerPAD package, and the PFM package, are specified in the Electrical Characteristics table. See AN-2020

Thermal Design By Insight, Not Hindsight (SNVA419) for more information.

Product Folder Links: LM22673 LM22673-Q1

LM22673

LM22673-Q1

SNVS586O –SEPTEMBER 2008–REVISED NOVEMBER 2014

www.ti.com

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

•AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419)

•AN-1229 SIMPLE SWITCHER ® PCB Layout Guidelines (SNVA054)

•AN-1894 LM22673 Evaluation Board (SNVA367)

•AN-1889 How to Measure the Loop Transfer Function of Power Supplies (SNVA364)

•AN-1797 TO-263 THIN Package (SNVA328)

11.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 1. Related Links

TECHNICAL TOOLS & SUPPORT &

PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY

LM22673 Click here Click here Click here Click here Click here

LM22673-Q1 Click here Click here Click here Click here Click here

11.3 Trademarks

SIMPLE SWITCHER, WEBENCH are registered trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: LM22673 LM22673-Q1

PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM22673MR-5.0/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS

& no Sb/Br) SN Level-3-260C-168 HR -40 to 125 L22673

5.0

LM22673MR-ADJ/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS

& no Sb/Br) SN Level-3-260C-168 HR -40 to 125 L22673

ADJ

LM22673MRE-5.0/NOPB ACTIVE SO PowerPAD DDA 8 250 Green (RoHS

& no Sb/Br) SN Level-3-260C-168 HR -40 to 125 L22673

5.0

LM22673MRE-ADJ/NOPB ACTIVE SO PowerPAD DDA 8 250 Green (RoHS

& no Sb/Br) SN Level-3-260C-168 HR -40 to 125 L22673

ADJ

LM22673MRX-5.0/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS

& no Sb/Br) SN Level-3-260C-168 HR -40 to 125 L22673

5.0

LM22673MRX-ADJ/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS

& no Sb/Br) SN Level-3-260C-168 HR -40 to 125 L22673

ADJ

LM22673QMR-5.0/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS

& no Sb/Br) SN Level-3-260C-168 HR -40 to 125 L22673

Q-5.0

LM22673QMR-ADJ/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS

& no Sb/Br) SN Level-3-260C-168 HR -40 to 125 L22673

QADJ

LM22673QMRE-5.0/NOPB ACTIVE SO PowerPAD DDA 8 250 Green (RoHS

& no Sb/Br) SN Level-3-260C-168 HR -40 to 125 L22673

Q-5.0

LM22673QMRE-ADJ/NOPB ACTIVE SO PowerPAD DDA 8 250 Green (RoHS

& no Sb/Br) SN Level-3-260C-168 HR -40 to 125 L22673

QADJ

LM22673QMRX-5.0/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS

& no Sb/Br) SN Level-3-260C-168 HR -40 to 125 L22673

Q-5.0

LM22673QMRX-ADJ/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS

& no Sb/Br) SN Level-3-260C-168 HR -40 to 125 L22673

QADJ

LM22673QTJ-5.0/NOPB ACTIVE TO-263 NDR 7 1000 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LM22673

QTJ-5.0

LM22673QTJ-ADJ/NOPB ACTIVE TO-263 NDR 7 1000 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LM22673

QTJ-ADJ

LM22673QTJE-5.0/NOPB ACTIVE TO-263 NDR 7 250 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LM22673

QTJ-5.0

LM22673QTJE-ADJ/NOPB ACTIVE TO-263 NDR 7 250 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LM22673

QTJ-ADJ

LM22673TJ-5.0/NOPB ACTIVE TO-263 NDR 7 1000 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LM22673

TJ-5.0

PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM22673TJ-ADJ/NOPB ACTIVE TO-263 NDR 7 1000 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LM22673

TJ-ADJ

LM22673TJE-5.0/NOPB ACTIVE TO-263 NDR 7 250 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LM22673

TJ-5.0

LM22673TJE-ADJ/NOPB ACTIVE TO-263 NDR 7 250 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LM22673

TJ-ADJ

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Addendum-Page 3

OTHER QUALIFIED VERSIONS OF LM22673, LM22673-Q1 :

•Catalog: LM22673

•Automotive: LM22673-Q1

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM22673MRE-5.0/NOPB SO

Power

PAD

DDA 8 250 178.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LM22673MRE-ADJ/NOPB SO

Power

PAD

DDA 8 250 178.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LM22673MRX-5.0/NOPB SO

Power

PAD

DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LM22673MRX-ADJ/NOPB SO

Power

PAD

DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LM22673QMRE-5.0/NOP

BSO

Power

PAD

DDA 8 250 178.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LM22673QMRE-ADJ/NOP

BSO

Power

PAD

DDA 8 250 178.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LM22673QMRX-5.0/NOP

BSO

Power

PAD

DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LM22673QMRX-ADJ/NOP SO DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 12-Jul-2019

Pack Materials-Page 1

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

B Power

PAD

LM22673QTJ-5.0/NOPB TO-263 NDR 7 1000 330.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2

LM22673QTJ-ADJ/NOPB TO-263 NDR 7 1000 330.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2

LM22673QTJE-5.0/NOPB TO-263 NDR 7 250 178.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2

LM22673QTJE-ADJ/NOP

BTO-263 NDR 7 250 178.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2

LM22673TJ-5.0/NOPB TO-263 NDR 7 1000 330.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2

LM22673TJ-ADJ/NOPB TO-263 NDR 7 1000 330.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2

LM22673TJE-5.0/NOPB TO-263 NDR 7 250 178.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2

LM22673TJE-ADJ/NOPB TO-263 NDR 7 250 178.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM22673MRE-5.0/NOPB SO PowerPAD DDA 8 250 210.0 185.0 35.0

LM22673MRE-ADJ/NOPB SO PowerPAD DDA 8 250 210.0 185.0 35.0

LM22673MRX-5.0/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0

LM22673MRX-ADJ/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0

LM22673QMRE-5.0/NOPB SO PowerPAD DDA 8 250 210.0 185.0 35.0

LM22673QMRE-ADJ/NOP

BSO PowerPAD DDA 8 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 12-Jul-2019

Pack Materials-Page 2

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM22673QMRX-5.0/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0

LM22673QMRX-ADJ/NOP

BSO PowerPAD DDA 8 2500 367.0 367.0 35.0

LM22673QTJ-5.0/NOPB TO-263 NDR 7 1000 367.0 367.0 35.0

LM22673QTJ-ADJ/NOPB TO-263 NDR 7 1000 367.0 367.0 35.0

LM22673QTJE-5.0/NOPB TO-263 NDR 7 250 210.0 185.0 35.0

LM22673QTJE-ADJ/NOPB TO-263 NDR 7 250 210.0 185.0 35.0

LM22673TJ-5.0/NOPB TO-263 NDR 7 1000 367.0 367.0 35.0

LM22673TJ-ADJ/NOPB TO-263 NDR 7 1000 367.0 367.0 35.0

LM22673TJE-5.0/NOPB TO-263 NDR 7 250 210.0 185.0 35.0

LM22673TJE-ADJ/NOPB TO-263 NDR 7 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 12-Jul-2019

Pack Materials-Page 3

www.ti.com

PACKAGE OUTLINE

-60

10.1

9.6

10.41

9.91

2.1

1.9

1.05

0.95

10.76

10.26

12.45

11.95

14.36

13.66

0-0.15

STAND-OFF

NOTE 5

R0.7

MAX TYP

ALL AROUND

(2.66) 6.5

6.1

5.75

5.40

7.1

6.5

6.6

6.3

4.1

3.9

1.05

0.65

6.11

5.85

7X 0.735

0.635

6X 1.27

7.62

7X 0.508

0.381

4219872/A 04/2019

TO-263 - 2.25 mm max heightNDR0007A

TO-263

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Features may not exist and shape may vary per different assembly sites.

4. Reference JEDEC registration TO-279B.

5. Under all conditions, leads must not be above Datum C

SCALE 1.000

0.15

0.25 C A B 1

PIN 1 ID

EXPOSED PAD

(OUTLINE DOES NOT

INCLUDE MOLD FLASH)

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ALL AROUND 0.07 MIN

ALL AROUND

(6.35)

(5.59)

(0.91)(8.28)

6X (1.27)

(7.62)

7X (2.41)

7X (0.91)

4219872/A 04/2019

TO-263 - 2.25 mm max heightNDR0007A

TO-263

NOTES: (continued)

6. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers

SLMA002(www.ti.com/lit/slm002) and SLMA004 (www.ti.com/lit/slma004).

7. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented.

OPENING

SOLDER MASK METAL

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

SYMM

PKG

www.ti.com

EXAMPLE STENCIL DESIGN

20X (1)

20X (1.13)

R(0.05) TYP

(1.2) TYP

(1.33) TYP

(0.665)

(0.29)

0.91(8.28)

(7.62)

6X (1.27)

7X (2.41) 7X (0.91)

4219872/A 04/2019

TO-263 - 2.25 mm max heightNDR0007A

TO-263

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

64% PRINTED SOLDER COVERAGE BY AREA

SCALE:7X

8SYMM

PKG

EXPOSED METAL

TYP

www.ti.com

PACKAGE OUTLINE

6X 1.27

8X 0.51

0.31

3.81

TYP

0.25

0.10

0 - 8 0.15

0.00

2.71

2.11

3.4

2.8 0.25

GAGE PLANE

1.27

0.40

4214849/A 08/2016

PowerPAD SOIC - 1.7 mm max heightDDA0008B

PLASTIC SMALL OUTLINE

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MS-012.

PowerPAD is a trademark of Texas Instruments.

0.25 C A B

PIN 1 ID

AREA

NOTE 4

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.400

EXPOSED

THERMAL PAD

TYP

6.2

5.8

1.7 MAX

NOTE 3

5.0

4.8

B4.0

3.8

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EXAMPLE BOARD LAYOUT

(5.4)

(1.3) TYP

( ) TYP

VIA

0.2

(R ) TYP0.05

0.07 MAX

ALL AROUND 0.07 MIN

ALL AROUND

8X (1.55)

8X (0.6)

6X (1.27)

(2.95)

NOTE 9

(4.9)

NOTE 9

(2.71)

(3.4)

SOLDER MASK

OPENING

(1.3)

TYP

4214849/A 08/2016

PowerPAD SOIC - 1.7 mm max heightDDA0008B

PLASTIC SMALL OUTLINE

SYMM

SEE DETAILS

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

METAL COVERED

BY SOLDER MASK

SOLDER MASK

DEFINED PAD

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

PADS 1-8

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

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EXAMPLE STENCIL DESIGN

(R ) TYP0.05

8X (1.55)

8X (0.6)

6X (1.27)

(5.4)

(2.71)

(3.4)

BASED ON

0.125 THICK

STENCIL

4214849/A 08/2016

PowerPAD SOIC - 1.7 mm max heightDDA0008B

PLASTIC SMALL OUTLINE

2.29 X 2.870.175 2.47 X 3.100.150 2.71 X 3.40 (SHOWN)0.125 3.03 X 3.800.1

SOLDER STENCIL

OPENING

STENCIL

THICKNESS

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

SYMM

BASED ON

0.125 THICK

STENCIL

BY SOLDER MASK

METAL COVERED SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

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