ADS8344E/2K5G4 - Texas Instruments

16-Bit, 8-Channel Serial Output Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

●PIN FOR PIN WITH ADS7844

●SINGLE SUPPLY: 2.7V to 5V

●8-CHANNEL SINGLE-ENDED OR

4-CHANNEL DIFFERENTIAL INPUT

●UP TO 100kHz CONVERSION RATE

●84dB SINAD

●SERIAL INTERFACE

●QSOP-20 AND SSOP-20 PACKAGES

APPLICATIONS

●DATA ACQUISITION

●TEST AND MEASUREMENT EQUIPMENT

●INDUSTRIAL PROCESS CONTROL

●PERSONAL DIGITAL ASSISTANTS

●BATTERY-POWERED SYSTEMS

DESCRIPTION

The ADS8344 is an 8-channel, 16-bit, sampling

Analog-to-Digital (A/D) converter with a synchronous serial

interface. Typical power dissipation is 10mW at a 100kHz

throughput rate and a +5V supply. The reference voltage

(VREF) can be varied between 500mV and VCC, providing a

corresponding input voltage range of 0V to VREF. The

device includes a shutdown mode that reduces power dissi-

pation to under 15µW. The ADS8344 is tested down to 2.7V

operation.

Low power, high speed, and an on-board multiplexer make

the ADS8344 ideal for battery-operated systems such as

personal digital assistants, portable multi-channel data log-

gers, and measurement equipment. The serial interface also

provides low-cost isolation for remote data acquisition. The

ADS8344 is available in a QSOP-20 or SSOP-20 package

and is ensured over the –40°C to +85°C temperature range.

CDAC

SAR

Comparator

8-Channel

Multiplexer Serial

Interface

and

Control

CH4

CH5

CH6

CH7

COM

REF

SHDN

OUT

BUSY

DCLK

CH0

CH1

CH2

CH3

4-Channel

Multiplexer

CH0

CH1

CH2

CH3

COM

ADS8343

ADS8341 ADS8345

ADS8344

SBAS139E – SEPTEMBER 2000 – REVISED SEPTEMBER 2006

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

ADS8344

2SBAS139E

MINIMUM

RELATIVE MAXIMUM SPECIFIED PACKAGE

ACCURACY GAIN ERROR TEMPERATURE PACKAGE DRAWING ORDERING TRANSPORT

PRODUCT (LSB) (%) RANGE DESIGNATOR PACKAGE-LEAD NUMBER NUMBER MEDIA, QUANTITY

ADS8344E 8 ±0.05 –40°C to +85°C DBQ QSOP-20 DBQ ADS8344E Rails, 56

" " " " " " " ADS8344E/2K5 Tape and Reel, 2500

ADS8344N " " " DB SSOP-20 DB ADS8344N Rails, 68

" " " " " " " ADS8344N/1K Tape and Reel, 1000

ADS8344EB 6 ±0.024 –40°C to +85°C DBQ QSOP-20 DBQ ADS8344EB Rails, 56

" " " " " " " ADS8344EB/2K5 Tape and Reel, 2500

ADS8344NB " " " DB SSOP-20 DB ADS8344NB Rails, 68

" " " " " " " ADS8344NB/1K Tape and Reel, 1000

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web site at

www.ti.com.

PACKAGE/ORDERING INFORMATION(1)

ABSOLUTE MAXIMUM RATINGS(1)

+VCC to GND ........................................................................ –0.3V to +6V

Analog Inputs to GND ............................................ –0.3V to +VCC + 0.3V

Digital Inputs to GND ........................................................... –0.3V to +6V

Power Dissipation .......................................................................... 250mW

Maximum Junction Temperature................................................... +150°C

Operating Temperature Range ........................................–40°C to +85°C

Storage Temperature Range .........................................–65°C to +150°C

Lead Temperature (soldering, 10s)............................................... +300°C

NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may

cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

PIN CONFIGURATION

Top View SSOP

PIN DESCRIPTIONS

PIN NAME DESCRIPTION

1 CH0 Analog Input Channel 0

2 CH1 Analog Input Channel 1

3 CH2 Analog Input Channel 2

4 CH3 Analog Input Channel 3

5 CH4 Analog Input Channel 4

6 CH5 Analog Input Channel 5

7 CH6 Analog Input Channel 6

8 CH7 Analog Input Channel 7

9 COM

Ground reference for analog inputs. Sets zero code

voltage in single–ended mode. Connect this pin to ground

or ground reference point.

10 SHDN Shutdown. When LOW, the device enters a very

low-power shutdown mode.

11 VREF Voltage Reference Input. See Electrical Characteristics

Table for ranges.

12 +VCC Power Supply, 2.7V to 5V

13 GND Ground

14 GND Ground

15 DOUT Serial Data Output. Data is shifted on the falling edge of

DCLK. This output is high impedance when CS is HIGH.

16 BUSY Busy Output. Busy goes LOW when the DIN control bits

are being read and also when the device is converting.

The Output is high impedance when CS is HIGH.

17 DIN Serial Data Input. If CS is LOW, data is latched on rising

edge of DCLK.

18 CS Chip Select Input. Active LOW. Data will not be clocked

into DIN unless CS is LOW. When CS is HIGH, DOUT is

high impedance.

19 DCLK External Clock Input. The clock speed determines the

conversion rate by the equation fDCLK = 24 • fSAMPLE.

20 +VCC Power Supply

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

SHDN

+VCC

DCLK

DIN

BUSY

DOUT

GND

+VCC

VREF

ADS8344

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instruments

recommends that all integrated circuits be handled with appropriate

precautions. Failure to observe proper handling and installation proce-

dures can cause damage.

ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

ADS8344 3

SBAS139E

ELECTRICAL CHARACTERISTICS: +5V

At TA = –40°C to +85°C, +VCC = +5V, VREF = +5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.

ADS8344E, N ADS8344EB, NB

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

RESOLUTION 16 ✻BITS

ANALOG INPUT

Full-Scale Input Span Positive Input - Negative Input 0 VREF ✻✻V

Absolute Input Range Positive Input –0.2

+VCC + 0.2

✻✻V

Negative Input –0.2 +1.25 ✻✻V

Capacitance 25 ✻pF

Leakage Current ±1✻µA

SYSTEM PERFORMANCE

No Missing Codes 14 15 Bits

Integral Linearity Error 86LSB

Offset Error ±2±1mV

Offset Error Match 1.2 4 ✻✻LSB(1)

Gain Error ±0.05 ±0.024 %

Gain Error Match 1.0 4 ✻✻ LSB

Noise 20 ✻µVrms

Power-Supply Rejection +4.75V < VCC < 5.25V 3 ✻LSB(1)

SAMPLING DYNAMICS

Conversion Time 16 ✻CLK Cycles

Acquisition Time 4.5 ✻CLK Cycles

Throughput Rate 100 ✻kHz

Multiplexer Settling Time 500 ✻ns

Aperture Delay 30 ✻ns

Aperture Jitter 100 ✻ps

Internal Clock Frequency SHDN = VDD 2.4 ✻MHz

External Clock Frequency 0.024 2.4 ✻✻MHz

Data Transfer Only 0 2.4 ✻✻MHz

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion(2) VIN = 5Vp-p at 10kHz –90 ✻dB

Signal-to-(Noise + Distortion) VIN = 5Vp-p at 10kHz 86 ✻dB

Spurious–Free Dynamic Range VIN = 5Vp-p at 10kHz 92 ✻dB

Channel-to-Channel Isolation VIN = 5Vp-p at 10kHz 100 ✻dB

REFERENCE INPUT

Range 0.5 +VCC ✻✻V

Resistance DCLK Static 5 ✻GΩ

Input Current 40 100 ✻✻ µA

fSAMPLE = 12.5kHz 2.5 ✻µA

DCLK Static 0.001 3 ✻✻ µA

DIGITAL INPUT/OUTPUT

Logic Family CMOS ✻

Logic Levels

VIH | IIH | ≤ +5µA 3.0 5.5 ✻✻V

VIL | IIL | ≤ +5µA–0.3 +0.8 ✻✻V

VOH IOH = –250µA 3.5 ✻V

VOL IOL = 250µA 0.4 ✻V

Data Format Straight Binary ✻

POWER-SUPPLY REQUIREMENTS

+VCC Specified Performance 4.75 5.25 ✻✻V

Quiescent Current 1.5 2.0 ✻mA

fSAMPLE = 100kHz 300 ✻µA

Power-Down Mode(3), CS = +VCC 3✻µA

Power Dissipation 7.5 10 ✻mW

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻°C

✻ Same specifications as ADS8344E, N.

NOTES: (1) LSB means Least Significant Bit. With VREF equal to +5.0V, one LSB is 76µV. (2) First nine harmonics of the test frequency. (3) Auto power-down mode

(PD1 = PD0 = 0) active or SHDN = GND.

ADS8344

4SBAS139E

ELECTRICAL CHARACTERISTICS: +2.7V

At TA = –40°C to +85°C, +VCC = +2.7V, VREF = +2.7V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.

ADS8344E, N ADS8344EB, NB

✻ Same specifications as ADS8344E, N.

NOTES: (1) LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 38µV. (2) First nine harmonics of the test frequency. (3) Auto power-down mode

(PD1 = PD0 = 0) active or SHDN = GND.

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

RESOLUTION 16 ✻BITS

ANALOG INPUT

Full-Scale Input Span Positive Input - Negative Input 0 VREF ✻✻V

Absolute Input Range Positive Input –0.2

+VCC + 0.2

✻✻V

Negative Input –0.2 +0.2 ✻✻V

Capacitance 25 ✻pF

Leakage Current ±1✻µA

SYSTEM PERFORMANCE

No Missing Codes 14 15 Bits

Integral Linearity Error 12 8 LSB

Offset Error ±1 0.5 mV

Offset Error Match 1.2 4 ✻✻ LSB

Gain Error ±0.05 ±0.024 % of FSR

Gain Error Match 14 ✻✻ LSB

Noise 20 ✻µVrms

Power-Supply Rejection +2.7 < VCC < +3.3V 3 ✻LSB(1)

SAMPLING DYNAMICS

Conversion Time 16 ✻CLK Cycles

Acquisition Time 4.5 ✻CLK Cycles

Throughput Rate 100 ✻kHz

Multiplexer Settling Time 500 ✻ns

Aperture Delay 30 ✻ns

Aperture Jitter 100 ✻ps

Internal Clock Frequency SHDN = VDD 2.4 ✻MHz

External Clock Frequency 0.024 2.4 MHz

When used with Internal Clock 0.024 2.0 ✻✻MHz

Data Transfer Only 0 2.4 ✻✻MHz

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion(2) VIN = 2.5Vp-p at 1kHz –90 ✻dB

Signal-to-(Noise + Distortion) VIN = 2.5Vp-p at 1kHz 86 ✻dB

Spurious-Free Dynamic Range VIN = 2.5Vp-p at 1kHz 92 ✻dB

Channel-to-Channel Isolation VIN = 2.5Vp-p at 10kHz 100 ✻dB

REFERENCE INPUT

Range 0.5 +VCC ✻✻V

Resistance DCLK Static 5 ✻GΩ

Input Current 13 40 ✻✻ µA

fSAMPLE = 12.5kHz 2.5 ✻µA

DCLK Static 0.001 3 ✻✻ µA

DIGITAL INPUT/OUTPUT

Logic Family CMOS ✻

Logic Levels

VIH | IIH | ≤ +5µA+V

CC • 0.7 5.5 ✻✻V

VIL | IIL | ≤ +5µA–0.3 +0.8 ✻✻V

VOH IOH = –250µA+V

CC • 0.8 ✻V

VOL IOL = 250µA 0.4 ✻V

Data Format Straight Binary ✻

POWER-SUPPLY REQUIREMENTS

+VCC Specified Performance 2.7 3.6 ✻✻V

Quiescent Current 1.2 1.85 ✻✻ mA

fSAMPLE = 100kHz 220 ✻µA

Power-Down Mode(3), CS = +VCC 3✻µA

Power Dissipation 3.2 5 ✻mW

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻°C

ADS8344 5

SBAS139E

TYPICAL CHARACTERISTICS: +5V

At TA = +25°C, +VCC = +5V, VREF = +5V, fSAMPLE = 100kHz, and fDCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.

–20

–40

–60

–80

–100

–120

–140

–160

FREQUENCY SPECTRUM

(4096 Point FFT; fIN = 1.001kHz, –0.2dB)

0 1020304050

Frequency (kHz)

Amplitude (dB)

–20

–40

–60

–80

–100

–120

–140

–160

FREQUENCY SPECTRUM

(4096 Point FFT; f

= 9.985kHz, –0.2dB)

0 1020304050

Frequency (kHz)

Amplitude (dB)

SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-

(NOISE+DISTORTION) vs INPUT FREQUENCY

101 100

Frequency (kHz)

SNR and SINAD (dB)

100

SINAD

SNR

SPURIOUS-FREE DYNAMIC RANGE AND TOTAL

HARMONIC DISTORTION vs INPUT FREQUENCY

101 100

Frequency (kHz)

SFDR (dB)

THD (dB)

100

–100

–90

–80

–70

–60

THD

(1)

SFDR

NOTE: (1) First Nine Harmonics

of the Input Frequency

CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)

vs TEMPERATURE

–40 –25 0 20 50 75 100

Temperature (°C)

Delta from +25°C (dB)

0.2

0.0

–0.2

–0.4

–0.6

–0.8

0.4

= 9.985kHz, –0.2dB

EFFECTIVE NUMBER OF BITS

vs INPUT FREQUENCY

101 100

Frequency (kHz)

Effective Number of Bits

15.0

14.5

14.0

13.5

13.0

12.5

12.0

11.5

11.0

ADS8344

6SBAS139E

TYPICAL CHARACTERISTICS: +5V (Cont.)

At TA = +25°C, +VCC = +5V, VREF = +5V, fSAMPLE = 100kHz, and fDCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.

Output Code

–1

–2

–3

–4

INTEGRAL LINEARITY ERROR vs CODE

8000

C000

FFFF

0000

4000

ILE (LSB)

Output Code

–1

–2

–3

DIFFERENTIAL LINEARITY ERROR vs CODE

8000HC000HFFFFH

0000H4000H

DLE (LSB)

WORST CASE CHANNEL-TO-CHANNEL

OFFSET MATCH vs TEMPERATURE

3.0

2.5

2.0

1.5

1.0

Offset Match (LSB)

Temperature (°C)

–50 –25 0 25 50 75 100

WORST CASE CHANNEL-TO-CHANNEL

GAIN MATCH vs TEMPERATURE

2.0

1.5

1.0

0.5

0.0

Gain Match (LSB)

Temperature (°C)

–50 –25 0 25 50 75 100

–1

–2

–3–50 –25 0 25 50 75 100

CHANGE IN OFFSET vs TEMPERATURE

Temperature (°C)

Delta from 25°C (LSB)

1.0

0.5

0.0

–0.5–50 –25 0 25 50 75 100

CHANGE IN GAIN vs TEMPERATURE

Temperature (°C)

Delta from 25°C (LSB)

ADS8344 7

SBAS139E

1.8

1.7

1.6

1.5

1.4

1.3–50 –25 0 25 50 75 100

SUPPLY CURRENT vs TEMPERATURE

Temperature (°C)

Supply Current (mA)

TYPICAL CHARACTERISTICS: +5V (Cont.)

At TA = +25°C, +VCC = +5V, VREF = +5V, fSAMPLE = 100kHz, and fDCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.

POWER DOWN SUPPLY CURRENT

vs TEMPERATURE

3.0

2.5

2.0

1.5

1.0

Supply Current (µA)

Temperature (°C)

–50 –25 0 25 50 75 100

ADS8344

8SBAS139E

TYPICAL CHARACTERISTICS: +2.7V

At TA = +25°C, +VCC = +2.7V, VREF = +2.7V, fSAMPLE = 100kHz, and fDCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.

–20

–40

–60

–80

–100

–120

–140

–160

FREQUENCY SPECTRUM

(4096 Point FFT; f

= 1.001kHz, –0.2dB)

0 1020304050

Frequency (kHz)

Amplitude (dB)

–20

–40

–60

–80

–100

–120

–140

–160

FREQUENCY SPECTRUM

(4096 Point FFT; f

= 9.985kHz, –0.2dB)

0 1020304050

Frequency (kHz)

Amplitude (dB)

SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-

(NOISE+DISTORTION) vs INPUT FREQUENCY

101 100

Frequency (kHz)

SNR and SINAD (dB)

100

SINAD

SNR

SPURIOUS-FREE DYNAMIC RANGE AND TOTAL

HARMONIC DISTORTION vs INPUT FREQUENCY

101 100

Frequency (kHz)

SFDR (dB)

THD(1)

SFDR

100

THD (dB)

–100

–90

–80

–70

–60

–50

NOTE: (1) First Nine Harmonics

of the Input Frequency

EFFECTIVE NUMBER OF BITS

vs INPUT FREQUENCY

101 100

Frequency (kHz)

Effective Number of Bits

CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)

vs TEMPERATURE

–40 –25 0 20 50 75 100

Temperature (°C)

Delta from +25°C (dB)

2.0

1.5

1.0

0.5

0.0

–0.5

–1.0

–1.5

–2.0

= 9.985kHz, –0.2dB

ADS8344 9

SBAS139E

TYPICAL CHARACTERISTICS: +2.7V (Cont.)

At TA = +25°C, +VCC = +2.7V, VREF = +2.7V, fSAMPLE = 100kHz, and fDCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.

Output Code

–1

–2

–3

INTEGRAL LINEARITY ERROR vs CODE

8000

C000

FFFF

0000

4000

ILE (LSB)

Output Code

–1

–2

–3

DIFFERENTIAL LINEARITY ERROR vs CODE

8000

C000

FFFF

0000

4000

DLE (LSB)

1.2

1.0

0.8

0.6

0.4

0.2

0–50 –25 0 25 50 75 100

WORST CASE CHANNEL-TO-CHANNEL

OFFSET MATCH vs TEMPERATURE

Temperature (°C)

Offset Match (LSBS)

WORST CASE CHANNEL-TO-CHANNEL

GAIN MATCH vs TEMPERATURE

1.2

1.0

0.8

0.6

0.4

Gain Match (LSBS)

Temperature (°C)

–50 –25 0 25 50 75 100

CHANGE IN OFFSET vs TEMPERATURE

–1

Delta from 25°C (LSB)

Temperature (°C)

–50 –25 0 25 50 75 100

0.3

0.2

0.1

0.0

–0.1

–0.2–50 –25 0 25 50 75 100

CHANGE IN GAIN vs TEMPERATURE

Temperature (°C)

Delta from 25°C (LSB)

ADS8344

10 SBAS139E

TYPICAL CHARACTERISTICS: +2.7V (Cont.)

At TA = +25°C, +VCC = +2.7V, VREF = +2.7V, fSAMPLE = 100kHz, and fDCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.

1.25

1.20

1.15

1.10

1.05

1.00–50 –25 0 25 50 75 100

SUPPLY CURRENT vs TEMPERATURE

Temperature (°C)

Supply Current (mA)

SUPPLY CURRENT vs +VSS

2.5 3.0 3.5 4.0 4.5 5.0

+VSS (V)

Supply Current (mA)

1.6

1.5

1.4

1.3

1.2

1.1

1.0

fSAMPLE = 100kHz, VREF = +VSS

POWER DOWN SUPPLY CURRENT

vs TEMPERATURE

3.0

2.5

2.0

1.5

1.0

Supply Current (µA)

Temperature (°C)

–50 –25 0 25 50 75 100

ADS8344 11

SBAS139E

THEORY OF OPERATION

The ADS8344 is a classic Successive Approximation

capacitive redistribution that inherently includes a sample-

and-hold function. The converter is fabricated on a 0.6µs

CMOS process.

The basic operation of the ADS8344 is shown in Figure 1.

The device requires an external reference and an external

clock. It operates from a single supply of 2.7V to 5.25V. The

external reference can be any voltage between 500mV and

+VCC. The value of the reference voltage directly sets the

input range of the converter. The average reference input

current depends on the conversion rate of the ADS8344.

The analog input to the converter is differential and is

provided via an 8-channel multiplexer. The input can be

provided in reference to a voltage on the COM pin (which

is generally ground) or differentially by using four of the

eight input channels (CH0 - CH7). The particular configura-

tion is selectable via the digital interface.

A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

00 0+IN–IN

00 1 +IN–IN

01 0 +IN–IN

01 1 +IN–IN

10 0–IN +IN

10 1 –IN +IN

11 0 –IN +IN

11 1 –IN +IN

TABLE II. Differential Channel Control (SGL/DIF LOW).

TABLE I. Single-Ended Channel Selection (SGL/DIF HIGH).

FIGURE 1. Basic Operation of the ADS8344.

A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

000+IN –IN

100 +IN –IN

001 +IN –IN

101 +IN –IN

010 +IN –IN

110 +IN –IN

011 +IN –IN

111 +IN–IN

ANALOG INPUT

See Figure 2 for a block diagram of the input multiplexer on

the ADS8344. The differential input of the converter is

derived from one of the eight inputs in reference to the COM

pin, or four of the eight inputs. Table I and Table II show the

relationship between the A2, A1, A0, and SGL/DIF control

bits and the configuration of the analog multiplexer. The

control bits are provided serially via the DIN pin (see the

Digital Interface section of this data sheet for more details).

When the converter enters the hold mode, the voltage

difference between the +IN and –IN inputs is captured on

the internal capacitor array (see Figure 2). The voltage on

the –IN input is limited between –0.2V and 1.25V, allowing

the input to reject small signals that are common to both the

+IN and –IN input. The +IN input has a range of –0.2V to

+VCC + 0.2V.

The input current on the analog inputs depends on the conver-

sion rate of the device. During the sample period, the source

must charge the internal sampling capacitor (typically 25pF).

After the capacitor has been fully charged, there is no further

input current. The rate of charge transfer from the analog

source to the converter is a function of conversion rate.

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

SHDN

DCLK

BUSY

OUT

GND

REF

Serial/Conversion Clock

Chip Select

Serial Data In

Serial Data Out

+2.7V to +5V

1µF to 10µF

ADS8344

Single-ended

or differential

analog inputs

1µF to 10µF1µF

0.1µF

External

REF

ADS8344

12 SBAS139E

REFERENCE INPUT

The external reference sets the analog input range. The

ADS8344 will operate with a reference in the range of

100mV to +VCC. Keep in mind that the analog input is the

difference between the +IN input and the –IN input, as

shown in Figure 2. For example, in the single-ended mode,

a 1.25V reference with the COM pin grounded, the selected

input channel (CH0 - CH7) will properly digitize a signal in

the range of 0V to 1.25V. If the COM pin is connected to

0.5V, the input range on the selected channel is 0.5V to

1.75V.

There are several critical items concerning the reference

input and its wide-voltage range. As the reference voltage is

reduced, the analog voltage weight of each digital output

code is also reduced. This is often referred to as the LSB

FIGURE 2. Simplified Diagram of the Analog Input.

Converter

+IN

–IN

CH0

CH1

CH2

CH3

A2-A0

(shown 00o

)

(1)

SGL/DIF

(shown HIGH)

CH4

CH5

CH6

CH7

COM

NOTE: (1) See Truth Tables, Table I

and Table II for address coding.

(Least Significant Bit) size and is equal to the reference

voltage divided by 65536. Any offset or gain error inherent

in the A/D converter will appear to increase, in terms of LSB

size, as the reference voltage is reduced. For example, if the

offset of a given converter is 2LSBs with a 2.5V reference,

then it will typically be 10LSBs with a 0.5V reference. In

each case, the actual offset of the device is the same,

76.3µV.

Likewise, the noise or uncertainty of the digitized output

will increase with lower LSB size. With a reference voltage

of 500mV, the LSB size is 7.6µV. This level is below the

internal noise of the device. As a result, the digital output

code will not be stable and will vary around a mean value by

a number of LSBs. The distribution of output codes will be

gaussian and the noise can be reduced by simply averaging

consecutive conversion results or applying a digital filter.

With a lower reference voltage, care should be taken to

provide a clean layout including adequate bypassing, a clean

(low-noise, low-ripple) power supply, a low-noise reference,

and a low-noise input signal. Because the LSB size is lower,

the converter will also be more sensitive to nearby digital

signals and electromagnetic interference.

The voltage into the VREF input is not buffered and directly

drives the Capacitor Digital-to-Analog Converter (CDAC)

portion of the ADS8344. Typically, the input current is

13µA with a 2.5V reference. This value will vary by

microamps depending on the result of the conversion. The

reference current diminishes directly with both conversion

rate and reference voltage. As the current from the reference

is drawn on each bit decision, clocking the converter more

quickly during a given conversion period will not reduce

overall current drain from the reference.

DIGITAL INTERFACE

The ADS8344 has a four-wire serial interface compatible

with several microprocessor families (note that the digital

inputs are over-voltage tolerant up to +5.5V, regardless of

+VCC). Figure 3 shows the typical operation of the ADS8344

digital interface.

Most microprocessors communicate using 8-bit transfers;

the ADS8344 can complete a conversion with three such

transfers, for a total of 24 clock cycles on the DCLK input,

provided the timing is as shown in Figure 3.

FIGURE 3. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK Delay Required with Dedicated

Serial Port.

ACQ

AcquireIdle Conversion

DCLK

OUT

BUSY

(MSB)

(START)

(LSB)

A2S

A1 A0

SGL/

DIF

PD1 PD0

14131211109 8 7654321 0 Zero Filled...

81 8

AcquireIdle Conversion

181

(MSB)

(START)

A2SA1A0

SGL/

DIF

PD1 PD0

ADS8344 13

SBAS139E

The first eight clock cycles are used to provide the control

byte via the DIN pin. When the converter has enough

information about the following conversion to set the input

multiplexer appropriately, it enters the acquisition (sample)

mode. After four more clock cycles, the control byte is

complete and the converter enters the conversion mode. At

this point, the input sample-and-hold goes into the Hold

mode. The next sixteen clock cycles accomplish the actual

A/D conversion.

Control Byte

See Figure 3 for placement and order of the control bits

within the control byte. Tables III and IV give detailed

information about these bits. The first bit, the “S” bit, must

always be HIGH and indicates the start of the control byte.

The ADS8344 will ignore inputs on the DIN pin until the

START bit is detected. The next three bits (A2-A0) select

the active input channel or channels of the input multiplexer

(see Tables I and II and Figure 2).

BIT 7 BIT 0

(MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 (LSB)

SA2A1A0—SGL/DIF PD1 PD0

TABLE III. Order of the Control Bits in the Control Byte.

TABLE IV.Descriptions of the Control Bits within the

Control Byte.

BIT NAME DESCRIPTION

7 S Start Bit. Control byte starts with first HIGH bit on

DIN.

6 - 4 A2 - A0 Channel Select Bits. Along with the SGL/DIF bit,

these bits control the setting of the multiplexer input,

see Tables I and II.

2 SGL/DIF Single-Ended/Differential Select Bit. Along with bits

A2 - A0, this bit controls the setting of the multiplexer

input, see Tables I and II.

1 - 0 PD1 - PD0 Power-Down Mode Select Bits. See Table V for

details.

PD1 PD0 DESCRIPTION

0 0 Power-down between conversions. When each

conversion is finished, the converter enters a

low-power mode. At the start of the next conver-

sion, the device instantly powers up to full power.

There is no need for additional delays to assure full

operation and the very first conversion is valid.

1 0 Selects Internal Clock Mode.

0 1 Reserved for Future Use.

1 1 No power-down between conversions, device al-

ways powered. Selects external clock mode.

TABLE V. Power-Down Selection.

FIGURE 4. Detailed Timing Diagram.

PD0

BDV

CSS

BTR

CSH

DCLK

OUT

BUSY

HIGH, the device is always powered up. If both PD1 and

PD0 are LOW, the device enters a power-down mode

between conversions. When a new conversion is initiated,

the device will resume normal operation instantly—no delay

is needed to allow the device to power up and the very first

conversion will be valid.

Clock Modes

The ADS8344 can be used with an external serial clock or an

internal clock to perform the successive-approximation con-

version. In both clock modes, the external clock shifts data in

and out of the device. Internal clock mode is selected when

PD1 is HIGH and PD0 is LOW.

If the user decides to switch from one clock mode to the other,

an extra conversion cycle will be required before the

ADS8344 can switch to the new mode. The extra cycle is

required because the PD0 and PD1 control bits need to be

written to the ADS8344 prior to the change in clock modes.

When power is first applied to the ADS8344, the user must

set the desired clock mode. It can be set by writing PD1

= 1 and PD0 = 0 for internal clock mode or PD1 = 1 and PD0

= 1 for external clock mode. After enabling the required

clock mode, only then should the ADS8344 be set to power-

down between conversions (i.e., PD1 = PD0 = 0). The

ADS8344 maintains the clock mode it was in prior to

entering the power-down modes.

External Clock Mode

In external clock mode, the external clock not only shifts data

in and out of the ADS8344, it also controls the A/D conversion

steps. BUSY will go HIGH for one clock period after the last

bit of the control byte is shifted in. Successive-approximation

bit decisions are made and appear at DOUT on each of the next

16 DCLK falling edges (see Figure 3). Figure 4 shows the

BUSY timing in external clock mode.

The SGL/DIF-bit controls the multiplexer input mode: ei-

ther in single-ended mode, where the selected input channel

is referenced to the COM pin, or in differential mode, where

the two selected inputs provide a differential input.

See Tables I and II and Figure 2 for more information. The

last two bits (PD1 - PD0) select the power-down mode and

Clock mode, as shown in Table V. If both PD1 and PD0 are

ADS8344

14 SBAS139E

SYMBOL DESCRIPTION MIN TYP MAX UNITS

tACQ Acquisition Time 1.5 µs

tDS DIN Valid Prior to DCLK Rising 100 ns

tDH DIN Hold After DCLK HIGH 10 ns

tDO DCLK Falling to DOUT Valid 200 ns

tDV CS Falling to DOUT Enabled 200 ns

tTR CS Rising to DOUT Disabled 200 ns

tCSS CS Falling to First DCLK Rising 100 ns

tCSH CS Rising to DCLK Ignored 0 ns

tCH DCLK HIGH 200 ns

tCL DCLK LOW 200 ns

tBD DCLK Falling to BUSY Rising 200 ns

tBDV CS Falling to BUSY Enabled 200 ns

tBTR CS Rising to BUSY Disabled 200 ns

TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V,

TA = –40°C to +85°C, CLOAD = 50pF).

Since one clock cycle of the serial clock is consumed with

BUSY going HIGH (while the MSB decision is being

made), 16 additional clocks must be given to clock out all 16

bits of data; thus, one conversion takes a minimum of 25

clock cycles to fully read the data. Since most microproces-

sors communicate in 8-bit transfers, this means that an

additional transfer must be made to capture the LSB.

There are two ways of handling this requirement. One is

where the beginning of the next control byte appears at the

same time the LSB is being clocked out of the ADS8344

(see Figure 3). This method allows for maximum throughput

and 24 clock cycles per conversion.

The other method is shown in Figure 5, which uses 32 clock

cycles per conversion; the last seven clock cycles simply

shift out zeros on the DOUT line. BUSY and DOUT go into a

high-impedance state when CS goes HIGH; after the next

CS falling edge, BUSY will go LOW.

Internal Clock Mode

In internal clock mode, the ADS8344 generates its own

conversion clock internally. This relieves the microproces-

sor from having to generate the SAR conversion clock and

allows the conversion result to be read back at the processor’s

convenience, at any clock rate from 0MHz to 2.0MHz.

BUSY goes LOW at the start of a conversion and then

returns HIGH when the conversion is complete. During the

conversion, BUSY will remain LOW for a maximum of 8µs.

Also, during the conversion, DCLK should remain LOW to

achieve the best noise performance. The conversion result is

stored in an internal register; the data may be clocked out of

this register any time after the conversion is complete.

ACQ

AcquireIdle Conversion

CLK

OUT

BUSY

(MSB)

(START)

(LSB)

A2S

A1 A0

SGL/

DIF

PD1 PD0

14131211109 8 7654321 0

81 8

Idle

Zero Filled...

If CS is LOW when BUSY goes LOW following a conver-

sion, the next falling edge of the external serial clock will

write out the MSB on the DOUT line. The remaining bits

(D14-D0) will be clocked out on each successive clock cycle

following the MSB. If CS is HIGH when BUSY goes LOW

then the DOUT line will remain in tri-state until CS goes

LOW, as shown in Figure 6. CS does not need to remain

LOW once a conversion has started. Note that BUSY is not

tri-stated when CS goes HIGH in internal clock mode.

Data can be shifted in and out of the ADS8344 at clock rates

exceeding 2.4MHz, provided that the minimum acquisition

time tACQ, is kept above 1.7µs.

Digital Timing

Figure 4 and Tables VI and VII provide detailed timing for

the digital interface of the ADS8344.

ACQ

AcquireIdle Conversion

CLK

9 1011121314151617181920212223242526272829303132

OUT

BUSY

(MSB)

(START)

(LSB)

A2S

A1 A0

SGL/

DIF

PD1 PD0

14131211109 8 7654321 0 Zero Filled...

FIGURE 5. External Clock Mode, 32 Clocks Per Conversion.

FIGURE 6. Internal Clock Mode Timing.

ADS8344 15

SBAS139E

SYMBOL DESCRIPTION MIN TYP MAX UNITS

tACQ Acquisition Time 1.7 µs

tDS DIN Valid Prior to DCLK Rising 50 ns

tDH DIN Hold After DCLK HIGH 10 ns

tDO DCLK Falling to DOUT Valid 100 ns

tDV CS Falling to DOUT Enabled 70 ns

tTR CS Rising to DOUT Disabled 70 ns

tCSS CS Falling to First DCLK Rising 50 ns

tCSH CS Rising to DCLK Ignored 0 ns

tCH DCLK HIGH 150 ns

tCL DCLK LOW 150 ns

tBD DCLK Falling to BUSY Rising 100 ns

tBDV CS Falling to BUSY Enabled 70 ns

tBTR CS Rising to BUSY Disabled 70 ns

FIGURE 7. Ideal Input Voltages and Output Codes.

TABLE VII. Timing Specifications (+VCC = +4.75V to

+5.25V, TA = –40°C to +85°C, CLOAD = 50pF).

Output Code

FS = Full-Scale Voltage = V

REF

1LSB = V

REF

/65,536

FS – 1LSB

11...111

11...110

11...101

00...010

00...001

00...000

1LSB

NOTE: (1) Voltage at converter input, after multiplexer: +IN – (–IN). (See Figure 2.)

Input Voltage

(1)

(V)

Data Format

The ADS8344 output data is in straight binary format, as

shown in Figure 7. This figure shows the ideal output code

for the given input voltage and does not include the effects

of offset, gain, or noise.

POWER DISSIPATION

There are three power modes for the ADS8344: full-power

(PD1 - PD0 = 11B), auto power-down (PD1 - PD0 = 00B),

and shutdown (SHDN LOW). The effects of these modes

varies depending on how the ADS8344 is being operated.

For example, at full conversion rate and 24-clocks per

conversion, there is very little difference between

full-power mode and auto power-down; a shutdown will not

lower power dissipation.

When operating at full-speed and 24-clocks per conversion

(see Figure 3), the ADS8344 spends most of its time

acquiring or converting. There is little time for auto

power-down, assuming that this mode is active. Thus, the

difference between full-power mode and auto power-down

is negligible. If the conversion rate is decreased by simply

slowing the frequency of the DCLK input, the two modes

remain approximately equal. However, if the DCLK fre-

quency is kept at the maximum rate during a conversion, but

conversions are simply done less often, then the difference

between the two modes is dramatic. In the latter case, the

converter spends an increasing percentage of its time in

power-down mode (assuming the auto power-down mode is

active).

If DCLK is active and CS is LOW while the ADS8344 is in

auto power-down mode, the device will continue to dissipate

some power in the digital logic. The power can be reduced

to a minimum by keeping CS HIGH.

Operating the ADS8344 in auto power-down mode will

result in the lowest power dissipation, and there is no

conversion time “penalty” on power-up. The very first

conversion will be valid. SHDN can be used to force an

immediate power-down.

NOISE

The noise floor of the ADS8344 itself is extremely low, as

shown in Figures 8 thru 11, and is much lower than compet-

ing A/D converters. The ADS8344 was tested at both 5V

and 2.7V, and in both the internal and external clock modes.

A low-level DC input was applied to the analog-input pins

and the converter was put through 5,000 conversions. The

digital output of the A/D converter will vary in output code

due to the internal noise of the ADS8344. This is true for all

16-bit SAR-type A/D converters. Using a histogram to plot

the output codes, the distribution should appear bell-shaped

with the peak of the bell curve representing the nominal code

for the input value. The ±1σ, ±2σ, and ±3σ distributions will

represent the 68.3%, 95.5%, and 99.7%, respectively, of all

codes. The transition noise can be calculated by dividing the

number of codes measured by 6 and this will yield the ±3σ

distribution, or 99.7%, of all codes. Statistically, up to 3

codes could fall outside the distribution when executing

1,000 conversions. The ADS8344, with < 3 output codes for

the ±3σ distribution, will yield a < ±0.5LSB transition noise

at 5V operation. Remember, to achieve this low-noise per-

formance, the peak-to-peak noise of the input signal and

reference must be < 50µV.

FIGURE 8. Histogram of 5,000 Conversions of a DC Input at the

Code Transition, 5V operation external clock mode.

Code

4561

24200197

7FFE7FFD 800180007FFF

ADS8344

16 SBAS139E

FIGURE 9. Histogram of 5,000 Conversions of a DC Input at the

Code Center, 5V operation internal clock mode.

Code

4507

25100242

7FFE7FFD 800180007FFF

FIGURE 10. Histogram of 5,000 Conversions of a DC Input at the

Code Transition, 2.7V operation external clock mode.

FIGURE 11. Histogram of 5,000 Conversions of a DC Input at the

Code Center, 2.7V operation internal clock mode.

Code

3511

721666

50 52

7FFE7FFD 800180007FFF

Code

2868

1137

858

78 59

7FFE7FFD 800180007FFF

sion results will reduce the transition noise by 1/2 to

±0.25LSBs. Averaging should only be used for input signals

with frequencies near DC.

For AC signals, a digital filter can be used to low-pass filter

and decimate the output codes. This works in a similar

manner to averaging: for every decimation by 2, the

signal-to-noise ratio will improve 3dB.

LAYOUT

For optimum performance, care should be taken with the

physical layout of the ADS8344 circuitry. This is particu-

larly true if the reference voltage is LOW and/or the conver-

sion rate is HIGH.

The basic SAR architecture is sensitive to glitches or sudden

changes on the power supply, reference, ground connec-

tions, and digital inputs that occur just prior to latching the

output of the analog comparator. Thus, during any single

conversion for an n-bit SAR converter, there are n “win-

dows” in which large external transient voltages can easily

affect the conversion result. Such glitches might originate

from switching power supplies, nearby digital logic, and

high-power devices. The degree of error in the digital output

depends on the reference voltage, layout, and the exact

timing of the external event. The error can change if the

external event changes in time with respect to the DCLK

input.

With this in mind, power to the ADS8344 should be clean

and well bypassed. A 0.1µF ceramic bypass capacitor should

be placed as close to the device as possible. In addition, a

1µF to 10µF capacitor and a 5Ω or 10Ω series resistor may

be used to low-pass filter a noisy supply.

The reference should be similarly bypassed with a 0.1µF

capacitor. Again, a series resistor and large capacitor can be

used to low-pass filter the reference voltage. If the reference

voltage originates from an op amp, make sure that it can

drive the bypass capacitor without oscillation (the series

resistor can help in this case). The ADS8344 draws very

little current from the reference on average, but it does place

larger demands on the reference circuitry over short periods

of time (on each rising edge of DCLK during a conversion).

The ADS8344 architecture offers no inherent rejection of

noise or voltage variation in regards to the reference input.

This is of particular concern when the reference input is tied

to the power supply. Any noise and ripple from the supply

will appear directly in the digital results. While

high-frequency noise can be filtered out as discussed in the

previous paragraph, voltage variation due to line frequency

(50Hz or 60Hz) can be difficult to remove.

The GND pin should be connected to a clean ground point.

In many cases, this will be the “analog” ground. Avoid

connections that are too near the grounding point of a

microcontroller or digital signal processor. If needed, run a

ground trace directly from the converter to the power-supply

entry point. The ideal layout will include an analog ground

plane dedicated to the converter and associated analog

circuitry.

AVERAGING

The noise of the A/D converter can be compensated by

averaging the digital codes. By averaging conversion result s,

transition noise will be reduced by a factor of 1/√n, where n

is the number of averages. For example, averaging 4 conver-

ADS8344 17

SBAS139E

DATE REVISION PAGE SECTION DESCRIPTION

2 Package/Ordering Info Added quantity to last column.

4 Electrical Characteristics Fixed typo. Changed +2.7V Gain Error minimum value (for EB, NB grade)

from ±0.0024 to ±0.024.

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

9/06 E

PACKAGE OPTION ADDENDUM

www.ti.com 16-Aug-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

ADS8344E ACTIVE SSOP DBQ 20 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS8344E/2K5 ACTIVE SSOP DBQ 20 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS8344E/2K5G4 ACTIVE SSOP DBQ 20 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS8344EB ACTIVE SSOP DBQ 20 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS8344EB/2K5 ACTIVE SSOP DBQ 20 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS8344EB/2K5G4 ACTIVE SSOP DBQ 20 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS8344EBG4 ACTIVE SSOP DBQ 20 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS8344EG4 ACTIVE SSOP DBQ 20 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS8344N ACTIVE SSOP DB 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS8344N/1K ACTIVE SSOP DB 20 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS8344N/1KG4 ACTIVE SSOP DB 20 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS8344NB ACTIVE SSOP DB 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS8344NB/1K ACTIVE SSOP DB 20 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS8344NB/1KG4 ACTIVE SSOP DB 20 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS8344NBG4 ACTIVE SSOP DB 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS8344NG4 ACTIVE SSOP DB 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

PACKAGE OPTION ADDENDUM

www.ti.com 16-Aug-2012

Addendum-Page 2

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADS8344E/2K5 SSOP DBQ 20 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

ADS8344EB/2K5 SSOP DBQ 20 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

ADS8344N/1K SSOP DB 20 1000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1

ADS8344NB/1K SSOP DB 20 1000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Aug-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADS8344E/2K5 SSOP DBQ 20 2500 367.0 367.0 38.0

ADS8344EB/2K5 SSOP DBQ 20 2500 367.0 367.0 38.0

ADS8344N/1K SSOP DB 20 1000 367.0 367.0 38.0

ADS8344NB/1K SSOP DB 20 1000 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Aug-2012

Pack Materials-Page 2

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

4040065 /E 12/01

28 PINS SHOWN

Gage Plane

8,20

7,40

0,55

0,95

0,25

12,90

12,30

10,50

8,50

Seating Plane

9,907,90

10,50

9,90

0,38

5,60

5,00

0,22

2016

6,50

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65 M

0,15

0°–ā8°

0,10

0,09

0,25

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

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harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which

have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such

components to meet such requirements.

Products Applications

Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive

Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications

Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers

DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps

DSP dsp.ti.com Energy and Lighting www.ti.com/energy

Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial

Interface interface.ti.com Medical www.ti.com/medical

Logic logic.ti.com Security www.ti.com/security

Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com

Wireless Connectivity www.ti.com/wirelessconnectivity

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