PEF20320 - Infineon Technologies

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http://www.synopsys.com/products/lm/ds/h/SIE20320.ls.txt 10.07.2000

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{* Logic Model README file for Siemens PEB20320 *}

{* HDLC Multichannel Network Interface Controller *}

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{* Data from PEB 20320 Data Sheet, March 1993 *}

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{* shell_revision: G *}

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Model Verification:

===================

Before using your model within a simulation, you should use the "Play

Vectors" menu item within the "lm" utility to verify that the test vectors

provided play successfully. Refer to the Logic Model Installation

Instructions which accompanied this model and your modeler's manual for more

information.

Three test vector files exist for model verification: SIE20320.OVA,

SIE20320.OVB and SIE20320.VEC. These test vector files are incompatible

with one another. Devices which pass test vectors found in SIE20320.OVA have

been electronically labeled with a model_revision of A (LM-family adapters)

or C (ModelSource adapters). Devices which pass test vectors found in

SIE20320.OVB have been electronically labeled with a model_revision of B

(LM-family adapters) or D (ModelSource adapters). Devices which pass test

vectors found in SIE20320.VEC have been electronically labeled with a

model_revision of E (LM-family adapters) or F (ModelSource adapters).

Before playing test vectors, use the "lm" utility and select the "Show Logic

Models" option within the "Modeler Configuration" menu. The "Rev." field

will indicate which test vector file you should use while playing vectors,

as shown in the table below:

LM-family Rev. ModelSource Rev. Test Vector File

-------------- ---------------- ----------------

A C SIE20320.OVA

B D SIE20320.OVB

E F SIE20320.VEC

NOTE: The test vectors supplied are in the "VEC" file format (as opposed to

the older "TST" file format). The VEC file format requires that you have

version 2.0 or greater of both the Runtime Modeler Software (RMS) and the lm

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http://www.synopsys.com/products/lm/ds/h/SIE20320.ls.txt 10.07.2000

utility.

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Usage During Simulation:

========================

Store Pins with Data Attributes:

--------------------------------

The -BGACK/PM pin exhibits "store" characteristics (i.e., it can change the

internal state of the device) if it is changed after reset when the device

is in the Intel Bus Mode of operation. Changing this pin after reset in the

Intel Bus Mode violates the manufacturer's specifications. In order to save

pattern memory and decrease simulation time, this pin has been declared as a

"data" pin within the Shell Software. For this reason, the model might not

exhibit the actual device behavior if this signal is changed after reset,

in the Intel Bus Mode.

If you are using the device in the Intel Bus Mode, and you are interested

in using the device in such a way that the -BGACK/PM signal changes after

reset, you must change the pin attribute of the -BGACK/PM pin to "store"

in the SIE20320.DEV file.

Boundary Scan Unit and Test Mode:

---------------------------------

The Boundary Scan Unit and the Test Mode functions of the SIE20320 have not

been verified. Although conservative attributes have been assigned to the

relevant signals, functionality of the Boundary Scan Unit and the Test Mode

of the model is not guaranteed.

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Initialization Information:

===========================

Device State at Time Zero:

--------------------------

The device is in the reset state with the RESET signal asserted.

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Timing Considerations:

======================

Speed Grades versus Model File Name:

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Speed grade MDL file

----------- ------------

16.384 MHz SIE20320.MDL

Maximum Delays Unspecified:

---------------------------

The manufacturer has only specified minimum propagation delay values for the

following parameters:

47 Transmit data delay min 50

48 Transmit clock to high impedance min 50

In other words, no maximum delays have been provided in the data sheet.

Within the Shell Software, the maximum value for each delay has been set

equal to the minimum value provided. Although this assumption is not

realistic, it produces the most conservative simulation results. Of course,

you have the option of making a local copy of the timing file and

changing the maximum delay to one which suits your simulation requirements.

Unspecified Delays:

-------------------

Not all propagation delays have been specified by the device manufacturer.

Some of these delays have been estimated and have been labeled "UD_EST"

("Unspecified Delay, Estimated") within the Shell Software. Other

unspecified delays will be supplied by the timing file's "default_delay"

statement. You have the option of changing the UD_EST delay values as well as

the delay values in the default_delay statement to suit your simulation

needs. You may also add specific delay relationships to the timing file(s).

To determine the other delays not specified by the manufacturer, edit a local

copy of the options file (.OPT) and change the setting of the "report

missing_delays" statement from "off" to "on". Then run your simulation or

use lm to play test vectors.

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