BUELA 300 K BLUE - SKS Kontakttechnik

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 1

PIC16C5X

Devices Included in thi s Data Sheet:

•PIC16C54

• PIC16CR54

•PIC16C55

•PIC16C56

• PIC16CR56

•PIC16C57

• PIC16CR57

•PIC16C58

• PIC16CR58

High-Performance RISC CPU:

• Only 33 single word instructions to learn

• All instructions are single cy cle except for pro-

gram branches which are two-cycle

• Operating speed: DC - 40 MHz clock input

DC - 100 ns instruction cycle

• 12-bit wide instructions

• 8-bit wide data path

• Seven or e ight sp ecial functi on hard ware regis ters

• Two-level deep hard w are st a ck

• Direct, indirect and relative addressing modes for

data and instru cti on s

Peripheral Feat ures:

• 8-bit real time cl ock /c oun ter (TM R0 ) with 8-bit

progra mmable prescaler

• Power-on Reset (POR)

• Device Reset Timer (DRT)

• Watchdog Timer (WDT) with its own on-chip

RC oscillator for reliable operation

• Programmable Code Protection

• Power saving SLEEP mode

• Selectable oscillator opti ons :

- RC: Low cost RC oscillator

- XT: Standard crystal/resonator

- HS: High speed crystal/resonator

- LP: Power saving, low frequency crystal

CMOS Technology:

• Low power, high speed CMOS EPROM/ROM tech-

nology

• Fully static design

• Wide operating voltage and temperature range:

- EPROM Commercial/Industrial 2.0V to 6.25V

- ROM Commercia l/In du stri al 2.0 V to 6.25V

- EPROM Extended 2.5V to 6.0V

- ROM Extended 2.5V to 6.0V

• Low power consumption

- < 2 mA typical @ 5V, 4 MHz

-15 A typical @ 3V, 32 kHz

- < 0.6 A typic al st andby current

(with WDT disa bled) @ 3V, 0C to 70C

Note: PIC16C 5X refers to all rev isions of the part

(i.e., PIC16C54 refers to PIC16C54,

PIC16C54A, and PIC16C54C), unless

specifically called out otherwise.

Device Pins I/O EPROM/

ROM RAM

PIC16C54 18 12 512 25

PIC16C54A 18 12 512 25

PIC16C54C 18 12 512 25

PIC16CR54A 18 12 512 25

PIC16CR54C 18 12 512 25

PIC16C55 28 20 512 24

PIC16C55A 28 20 512 24

PIC16C56 18 12 1K 25

PIC16C56A 18 12 1K 25

PIC16CR56A 18 12 1K 25

PIC16C57 28 20 2K 72

PIC16C57C 28 20 2K 72

PIC16CR57C 28 20 2K 72

PIC16C58B 18 12 2K 73

PIC16CR58B 18 12 2K 73 Note: In this document, figure and table titles

refer to all vari eties of the part nu mber indi-

cated, (i.e., The title “Figure 15-1: Load

Conditions For Device Timing Specifica-

tions - PIC16C54A”, also refers to

PIC16LC54A and PIC16LV54A parts),

unless specifically called out otherwise.

EPROM/ROM-Based 8-bit CMOS Microcontroller Series

PIC16C5X

DS30453E-page 2 Preliminary  1997-2013 Microchip Technology Inc.

Pin Diagrams

Device Differences

Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.

Device Voltage

Range

Oscillator

Selection

(Program) Oscillator Process

Technology

(Microns)

ROM

Equivalent MCLR

Filter

PIC16C54 2.5-6.25 Factory See Note 1 1.2 PIC16CR54A No

PIC16C54A 2.0-6.25 User See Note 1 0.9 — No

PIC16C54C 2.5-5.5 User See Note 1 0.7 PIC16CR54C Yes

PIC16C55 2.5-6.25 Factory See Note 1 1.7 — No

PIC16C55A 2.5-5.5 User See Note 1 0.7 — Yes

PIC16C56 2.5-6.25 Factory See Note 1 1.7 — No

PIC16C56A 2.5-5.5 User See Note 1 0.7 PIC16CR56A Yes

PIC16C57 2.5-6.25 Factory See Note 1 1.2 — No

PIC16C57C 2.5-5.5 User See Note 1 0.7 PIC16CR57C Yes

PIC16C58B 2.5-5.5 User See Note 1 0.7 PIC16CR58B Yes

PIC16CR54A 2.5-6.25 Factory See Note 1 1.2 N/A Yes

PIC16CR54C 2.5-5.5 Factory See Note 1 0.7 N/A Yes

PIC16CR56A 2.5-5.5 Factory See Note 1 0.7 N/A Yes

PIC16CR57C 2.5-5.5 Factory See Note 1 0.7 N/A Yes

PIC16CR58B 2.5-5.5 Factory See Note 1 0.7 N/A Yes

PDIP, SOIC, Wi nd owed CE R D IP

PIC16CR54

PIC16C58

PIC16CR58

PIC16C54

RA1

RA0

OSC1/CLKIN

OSC2/CLKOUT

VDD

RB7

RB6

RB5

RB4

RA2

RA3

T0CKI

MCLR/VPP

VSS

RB0

RB1

RB2

RB3

1

SSOP

PIC16C56

PIC16CR56

PIC16CR54

PIC16C58

PIC16CR58

PIC16C54

PIC16C56

PIC16CR56

RA2

RA3

T0CKI

MCLR/VPP

VSS

RB0

RB1

RB2

RB3

1

910

RA1

RA0

OSC1/CLKIN

OSC2/CLKOUT

VDD

RB7

RB6

RB5

RB4

•1

PDIP, SOIC, Wind owe d CERDIP

PIC16C57

PIC16C55

MCLR/VPP

OSC1/CLKIN

OSC2/CLKOUT

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

RB7

RB6

RB5

T0CKI

VDD

VSS

RA0

RA1

RA2

RA3

RB0

RB1

RB2

RB3

RB4

1

SSOP

PIC16C55

VDD

VSS

PIC16CR57

T0CKI

VDD

N/C

VSS

N/C

RA0

RA1

RA2

RA3

RB0

RB1

RB2

RB3

RB4

MCLR/VPP

OSC1/CLKIN

OSC2/CLKOUT

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

RB7

RB6

RB5

PIC16C57

Note: The table shown above shows the generic names of the PIC16C5X devices. For device varieties, please

refer to Section 2.0.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 3

PIC16C5X

Table of Contents

1.0 General Description........... .... ....... .... .. .... .... ....... .... .... .. .... ....... .... .... .. .... ......... .. .... .... .. ...... ............................................................. 5

2.0 PIC1 6 C 5 X Device Var i e ties ............. .......... ........... ..................... .......... ........... ..................... ........................................................ 7

3.0 Architectural Overview ................................................................................................................................................................ 9

4.0 Oscillator Configurations............................................................................................................................................................ 15

5.0 Reset.......................................................................................................................................................................................... 19

6.0 Memory Organization................................................................................................................................................................. 25

7.0 I /O Po rts.............. .......... ........... .......... ........... .......... ........... .......... ........... ................................................................................... 35

8.0 Timer0 Module and TMR0 Register........................................................................................................................................... 37

9.0 Sp e cial Feat u res of the CPU......................... ..................... .......... ........... ..................... .............................................................. 43

10.0 Instruction Set Summary............................................................................................................................................................ 49

11.0 Development Support................................................................................................................................................................. 61

12.0 Electrical Characteristics - PIC16C54/55/56/57......................................................................................................................... 67

13.0 Electrical Characteristics - PIC16CR54A................................................................................................................................... 79

14.0 Device Characterization - PIC16C54/55/56/57/CR54A.............................................................................................................. 91

15.0 Electrical Characteristics - PIC16C54A.................................................................................................................................... 103

16.0 Device Characterization - PIC16C54A..................................................................................................................................... 117

17.0 Elect rical Charact eristics - PIC1 6C54C/CR54C /C55 A/C56 A/CR 56A/ C57C /CR5 7C/C 58B/ CR58 B .... .... ...... ...... ..... ...... .... ..... 131

18.0 Device Characterization - PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/ CR57C/C58B/ CR58B.......................................... 145

19.0 Electrical Characteristics - PIC16C54C/C55A/C56A/C57C/C58B 40MHz............................................................................... 155

20.0 Devi ce C h a r a cterization - PIC 1 6 C54C /C 5 5 A/C5 6 A / C 5 7 C /C58B 4 0 M H z ................................................................................ 165

21.0 Packagin g In fo rmation.................... ..................... .......... ........... ..................... .......... ................................................................. 171

Appendix A: Compatibility ................................................ .. ......... .. .... .... .. ......... .... .. .... .. ......... . ....................................................... 182

On-Line Support................................................. .. ........... .... .. .... ......... .... .... .... ......... .... .... ................................................................... 187

Reader Response.............................................................................................................................................................................. 188

Product Identification System ............................................................................................................................................................ 189

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our publications to bette r suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or c omm ents regarding t his publication, p lease c ontact the M arket ing Communications Department via

E-mail at docerrors@mail.microchip.com or fax the R eader Response Form in the back of th is data sheet to (480) 792-4150.

We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the dat a sheet and recommended workarounds, may exist f or current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web sit e; http://www.microchip.com

• Your local Microchip sales office (see last page)

• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277

When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter-

ature number) you are using.

Customer No tific atio n Syst em

PIC16C5X

DS30453E-page 4 Preliminary  1997-2013 Microchip Technology Inc.

NOTES:

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 5

PIC16C5X

1.0 GENERAL DESCRIP T ION

The PIC16C5X from Microchip Technology is a family

of low cost, high performance, 8-bit fully static,

EPROM/ROM-based CMOS microcontrollers. It

empl oy s a R ISC a rc hi t ec t ure w i th o nl y 33 si n gl e wor d/

single cycle instructions. All instructions are single

cycle except for program branches which take two

cycles. The PIC16C5X delivers performance in an

order of magnitude higher than its competitors in the

same price category. The 12-bit wide instructions are

highly symmetrical resulting in 2:1 code compression

ove r othe r 8-bit micr ocontr ollers in its clas s. The easy

to use and easy to remember instruction set reduces

development time significantly.

The PIC1 6C5X product s are equip ped with speci al fea-

tures tha t reduce syste m cost and po wer requirement s.

The Power-on Reset (POR) and Device Reset Timer

(DRT) eliminate the need for external RESET circuitry.

There are four oscill ator configu rati ons to choo se from ,

including the power saving LP (Low Power) oscillator

and cost saving RC oscillator. Power saving SLEEP

mode, Watchdog Timer and Code Protection features

improve system cost, power and reliability.

The UV eras able CERD IP package d version s are ideal

for code development, while the cost effective One

Time Programmable (OTP) versions are suitable for

production in any volume. The customer can take full

advantage of Microchip’s price leadership in OTP

microcontrollers, while benefiting from the OTP’s

flexibility.

The PIC16C5X products are supported by a full fea-

tured macr o assembler, a software simulator, an in-cir-

cuit e mulator, a l ow cos t devel opment p rogrammer and

a full featured programmer. All the tools are supported

on IBM PC and compatible machines.

1.1 Applications

The PIC16C5X series fits perfectly in applications rang-

ing from high speed automotive and appliance motor

control to low power remote transmitters/receivers,

pointing devi ces and telecom process ors. The EPROM

technology makes customizing application programs

(transmitter codes, motor speeds, receiver frequen-

cies, etc.) extremely fast and convenient. The small

footprint pack ages, for through hole or surface mount-

ing, ma ke this microcontroller series perfect for applica-

tions with space limitations. Low cost, low power, high

performance ease of use and I/O flexibility make the

PIC16C5X series ve ry versatile even in areas where no

microcontroller use has been considered before (e.g.,

timer functions, replacement of “glue” logic in larger

systems, co-processor applications).

8-Bit EPROM/ROM-Based CMOS Microcontrollers

PIC16C5X

DS30453E-page 6 Preliminary  1997-2013 Microchip Technology Inc.

TABLE 1-1: PIC16C5X FAMILY OF DEVICES

Features PIC16C54 PIC16CR54 PIC16C55 PIC16C56 PIC16CR56

Maximum Operation Frequency 40 MHz 20 MHz 40 MHz 40 MHz 20 MHz

EPROM Program Memory (x12 words) 512 — 512 1K —

ROM Program Memory (x12 words) — 512 — — 1K

RAM Data Memory (bytes) 25 25 24 25 25

Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0

I/O Pins 12 12 20 12 12

Number of Instructions 33 33 33 33 33

Packages 18-pin DIP,

SOIC;

20-pin SS OP

18-pin DIP,

SOIC;

20-pin SS OP

28-pin DIP,

SOIC;

28-pin SS OP

18-pin DIP,

SOIC;

20-pin SS OP

18-pin DIP,

SOIC;

20-pin SSOP

All PIC® Family devices have Power-on Reset, selectable Watchdog Timer, selectable Code Protect and high

I/O current capability.

Features PIC16C57 PIC16CR57 PIC16C58 PIC16CR58

Maximum Operation Frequency 40 MHz 20 MHz 40 MHz 20 MHz

EPROM Program Memory (x12 words) 2K — 2K —

ROM Program Memory (x12 words) — 2K — 2K

RAM Data Memory (bytes) 72 72 73 73

Timer Module(s) TMR0 TMR0 TMR0 TMR0

I/O Pins 20 20 12 12

Number of Instructions 33 33 33 33

Packages 28-pin DIP, SOIC;

28-pin SSOP 28-pin DIP, SOIC;

28-pin SSOP 18-pin DIP, SOIC;

20-pin SSOP 18-pin DIP, SOIC;

20-pin SSOP

All PIC® Family devices have Power-on Reset, selectable Watchdog Timer, selectable Code Protect and high

I/O current capability.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 7

PIC16C5X

2.0 PIC16C5X DEVICE VARIETIES

A variety of frequency ranges and packaging options

are avail able. Depending on application an d production

requirem ents, the p roper device o ption can be s elected

using the information in this section. When placing

orders, please use the PIC16C5X Product Identifica-

tion S ystem at the ba ck of this data s heet to spe cify the

correct part numbe r.

For the PIC16C5X family of devices, there are four

device types, as indicated in the device number:

1. C, as in PIC16C54C. These devices have

EPROM progra m m emo ry an d ope rate ove r the

standard voltage range.

2. LC, as in PIC16LC54A. These devices have

EPROM program memory and operate over an

extended voltage range.

3. CR, as in PIC16CR54A. These devices have

ROM program memory and operate over the

standard voltage range.

4. LCR, as in PIC16LCR54A. Thes e de vic es have

ROM program memory and operate over an

extended voltage range.

2.1 UV Erasable Devices (EPROM)

The UV erasable versions offered in CERDIP pack-

ages, are optimal for prototype development and pilot

programs.

UV eras able device s can be pro grammed for a ny of the

four oscillator configurations. Microchip's

PICSTART Plus(1) and PRO MATE programmers

both support programming of the PIC16C5X. Third

party programmers also are available. Refer to the

Third Party Guide (DS00104) for a list of sources.

2.2 One-Time-Programmable (OTP)

Devices

The availability of OTP devices is especially useful for

customers expecting frequent code changes and

updates, or small volume applications.

The OT P devices , packaged i n plasti c packages , per-

mit the user to program them once. In addition to the

program memory, the configuration bits must be pro-

grammed.

2.3 Quick-Turnaround-Production

(QT P ) D e vices

Microchip offers a QTP Programming Service for fac-

tory produc tion or ders. Th is servi ce is ma de availa ble

for users who choose not to program a medium to high

quantity of units and whose code patterns have stabi-

lized. The devices ar e identical to the OT P d evi ce s b u t

with all EPROM locations and configuration bit options

already programmed by the factory. Certain code and

prototype verification procedures apply before produc-

tion shipments are available. Please contact your

Microchip Technology sales office for more details.

2.4 Serialized Quick-Turnaround-

Production (SQTPSM) Devices

Microchip offers the unique programming service

where a few user defined locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or sequen-

tial. The devices are identical to the OTP devices but

with all EPROM locations and configuration bit options

already programmed by the factory.

Serial programming allows each device to have a

unique number which can serve as an entry code,

password or ID number.

2.5 Read Only Memory (ROM) Devices

Microchip offers masked ROM versions of several of

the highest volume parts, giving the customer a low

cost option for high volume, mature products.

Note 1: PIC16LC54C and PIC16C54A devices

require OSC2 not to be connected while

programming with PICS TA RT® Plus

programmer.

PIC16C5X

DS30453E-page 8 Preliminary  1997-2013 Microchip Technology Inc.

NOTES:

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 9

PIC16C5X

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC16C5X family can be

attributed to a number of architectural features com-

monly found in RISC microprocessors. To begin with,

the PIC16C5X uses a Harvard architecture in which

program and data are accessed on separate buses.

This i mproves ba ndwidth o ver tradition al von N eumann

architecture where program and data are fetched on

the same bus. Separating program and data memory

further allows instructions to be sized differently than

the 8-bit wide data word. Instruction opcodes are 12

bits wide making it possible to have all single word

instructions. A 12-bit wide program memory access

bus fetc hes a 12-bit i nstruc tion i n a sin gle cy cle. A two-

stage pipeline overlaps fetch and execution of instruc-

tions. Consequently, all instructions (33) execute in a

single cycle except for program branches.

The PIC1 6C54/CR54 and PIC16C 55 address 5 12 x 12

of program memory, the PIC16C56/CR56 address

1K x 12 of program memory, and the PIC16C57/CR57

and PIC16C58/CR58 address 2K x 12 of program

memor y. All program memory is internal.

The PIC16C5X can directly or indirectly address its

isters i nclud ing the program c ounter a re mapp ed in th e

data memory. The PIC16C5X has a highly orthogonal

(symmetrical) instruction set that makes it possible to

carry out any operation on any register using any

addressing mode. This sy mmetrical nature and lack of

‘speci al opti mal s ituat ions ’ make prog rammi ng wi th the

PIC16C5X si mple yet ef ficien t. In additi on, the learnin g

curve is reduced significantly.

The PIC16C5 X device cont ains an 8-bit ALU and work-

ing register. The ALU is a general purpose arithmetic

unit. It performs arithmetic and Boolean functions

between data in the working register and any register

file.

The ALU is 8 bits wide and capable of addition, subtrac-

tion, shift and logical operations. Unless otherwise

mentioned, arithmetic operations are two's comple-

ment in nature. In two-operand instructions, typically

one operand is the W (working) register. The other

operand is either a file register or an immediate con-

stant. In single operand instructions, the operand is

either the W register or a file register.

The W registe r is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affe ct the values of the Carry (C), Digit Carry (DC), and

Zero (Z) bit s in the ST ATUS register. The C and DC bits

operate as a borrow and digit borrow out bit, respec-

tively, in subtraction. See the SUBWF and ADDWF

instructions for examples.

A simplified block diagram is shown in Figure 3-1, with

the corresponding device pins described in Table 3-1

(for PIC16C54/56/58) and Table 3-2 (for PIC16C55/

57).

PIC16C5X

DS30453E-page 10 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 3-1: PI C16C5 X SERIES BLOCK DIAGRAM

WDT TIME

OUT

STACK 1

STACK 2

EPROM/ROM

512 X 12 TO

2048 X 12

INSTRUCTION

DECODER

WATCHDOG

TIMER

CONFIGURATION WORD

OSCILLATOR/

TIMING &

CONTROL

GENERAL

PURPOSE

FILE

(SRAM)

24, 25, 72 or

73 Bytes

WDT/TMR0

PRESCALER

OPTION REG. “OPTION”

“SLEEP”

“CODE

PROTECT”

“OSC

SELECT”

DIRECT ADDRESS

TMR0

FROM W

“TRIS 5” “TRIS 6” “TRIS 7”

FSR

TRISA PORTA TRISB PORTC

TRISC

PORTB

FROM W

T0CKI

9-11

DATA BUS

ALU

STATUS

FROM W

CLKOUT

5-7

OSC1 OSC2 MCLR

LITERALS

PC “DISABLE”

RA<3:0> RB<7:0> RC<7:0>

(28-Pin

Devices O nl y)

DIRECT RAM

ADDRESS

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 11

PIC16C5X

TABLE 3-1: PINOUT DESCRIPTION - PIC16C54, PIC16CR54, PIC16C56, PIC16CR56, PIC16C58,

PIC16CR58

Pin Name Pin Number Pin Buffer Description

DIP SOIC SSOP Type Type

RA0

RA1

RA2

RA3

I/O

TTL

Bi-directional I/O port

RB0

RB1

RB2

RB3

RB4

RB5

RB6

RB7

I/O

TTL

Bi-directional I/O port

T0CKI 3 3 3 I ST Clock inp ut to T imer0. Must be tied to VSS or VDD, if not in

use, to reduce current consumption.

MCLR/VPP 4 4 4 I ST Master clear (RESET) input/programming voltage input.

This p in is an acti ve lo w RESET to the d evice. Volt age on

the MCLR/VPP pin must not exceed VDD to avoid unin-

tended entering of Programming mode.

OSC1/CLKIN 16 16 18 I ST Oscillator crystal input/external clock source input.

OSC2/CLKO UT 15 15 17 O — Oscilla tor crystal output. Con nec t s to cry st a l or res ona tor

in crystal Oscillator mode. In RC mode, OSC2 pin outputs

CLKOUT, which has 1/4 the frequency of OSC1 and

denotes the instruction cycle rate.

VDD 14 14 15,16 P — Positive supply for logic and I/O pins.

VSS 5 5 5,6 P — Ground reference for logic and I/O pins.

Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger

input

PIC16C5X

DS30453E-page 12 Preliminary  1997-2013 Microchip Technology Inc.

TABLE 3-2: PINOUT DESCRIPTION - PIC16C55, PIC16C57, PIC16CR57

Pin Name Pin Number Pin

Type Buffer

Type Description

DIP SOIC SSOP

RA0

RA1

RA2

RA3

I/O

TTL

Bi-directional I/O port

RB0

RB1

RB2

RB3

RB4

RB5

RB6

RB7

I/O

TTL

Bi-directional I/O port

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

I/O

TTL

Bi-directional I/O port

T0CKI 1 1 2 I ST Clock inpu t to T imer0. M ust be tied to VSS or VDD, if not in

use, to reduce current consumption.

MCLR 28 28 28 I ST Master clear (RESET) input. This pin is an active low

RESET to the device.

OSC1/CLKIN 27 27 27 I ST Oscillator crystal input/external clock source input.

OSC2/CL K OUT 26 26 26 O — Oscill ato r crystal ou tput . C on nec t s to cry s t al or resonator

in cryst al Oscil lator mode. In RC mode, OSC 2 pin outpu ts

CLKOUT whic h has 1/4 the frequency of OSC1, and

denotes the instruction cycle rate.

VDD 2 2 3,4 P — Positive supply for logic and I/O pins.

VSS 4 4 1,14 P — Ground reference for logic and I/O pins.

N/C 3,5 3,5 — — — Unused, do not connect.

Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger

input

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 13

PIC16C5X

3.1 Clocking Scheme/Instruction

Cycle

The clock input (OSC1/CLKIN pin) is internally divided

by four to generate four non-overlapping quadrature

clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-

gram c oun ter is incremente d ev ery Q 1 and th e ins tru c-

tion is fetched from program memory and latched into

the instruction register in Q4. It is decoded and exe-

cuted during the following Q1 through Q4. The cl ocks

and i nstru c ti on ex ec ut i on f l ow ar e s ho wn i n Fi g ur e 3-2

and Example 3-1.

3.2 Instr uction Flow/Pipelining

An Instruction Cycle consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle,

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO),

then tw o cycles are req uired to com plete the ins truction

(Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the ex ecution cycle , the fetched instruction i s latched

into the Instruction Register in cycle Q1. This instruc-

tion is then decoded and executed during the Q2, Q3

and Q4 cycles. Data memory is read during Q2 (oper-

and read) and written during Q4 (destination write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

OSC2/CLKOUT

(RC mode)

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (PC+1)

Internal

phase

clock

All instru ctions are sing le cycle, except fo r any progra m branches. These ta ke two cycles si nce the fetch instruc tion

is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

1. MOVLW H'55' Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. CALL SUB_1 Fetch 3 Execute 3

4. BSF PORTA, BIT3 Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

PIC16C5X

DS30453E-page 14 Preliminary  1997-2013 Microchip Technology Inc.

NOTES:

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 15

PIC16C5X

4.0 OSCILLATOR

CONFIGURATIONS

4.1 Oscillator Types

PIC16C5Xs can be operated in four different oscillator

modes. The user can program two configuration bits

(FOSC1:FOSC0) to select one of these four modes:

1. LP : Low Power Crystal

2. XT: Crystal/Resonator

3. HS: High Speed Crystal/Resonator

4. RC: Resistor/Capacitor

4.2 Crystal Oscillator /Ceramic

Resonators

In XT, LP or HS modes, a crystal or ceramic resonator

is connected to the OSC1/CLKIN and OSC2/CLKOUT

pins to establish oscillation (Figure 4-1). The

PIC16C5X os cillator desi gn requires the use of a para l-

lel cut crystal. Use of a series cut crystal may give a fre-

quency out of the crystal manufacturers specifications.

When in XT, LP or HS modes, the device can have an

external clock source drive the OSC1/CLKIN pin

(Figure 4-2).

FIGURE 4-1: CRYSTAL/CERAMIC

RESONATOR OPERATION

(HS, XT OR LP OSC

CONFIGURATION)

FIGURE 4-2: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR

LP OSC

CONFIGURATION)

T ABLE 4-1: CAP ACITOR SELECTION FOR

CERAMIC RESONATORS -

PIC16C5X, PIC16CR5X

T ABLE 4-2: CAP ACITOR SELECTION FOR

CRYSTAL OSCILLATOR -

PIC16C5X, PIC16CR5X

Note: Not all os ci ll ator sele ct ion s av ail abl e for al l

parts. See Section 9.1.

Note 1: See Capacitor Selection tables for

recommended values of C1 and C2.

2: A series resistor (RS) may be required

for AT strip cut crystals.

3: RF varies with the Oscill ator mode cho-

sen (approx. value = 10 M).

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3) SLEEP

To internal

logic

RS(2)

PIC16C5X

Osc

Type Resonator

Freq Cap. Range

C1 Cap. Range

XT 455 kHz

2.0 MHz

4.0 MHz

68-100 pF

15-33 pF

10-22 pF

68-100 pF

15-33 pF

10-22 pF

HS 8. 0 MHz

16.0 MHz 10-22 pF

10 pF 10-22 pF

10 pF

These values are for design guidance only. Since

each reso nator has its own characteristics, the user

should co nsu lt the res ona tor man ufa ctu rer for

appropriate values of external components.

Osc

Type Crystal

Freq Cap.Range

C1 Cap. Range

LP 32 kHz(1) 15 pF 15 pF

XT 100 kHz

200 kHz

455 kHz

1 MHz

2 MHz

4 MHz

15-30 pF

15 pF

200-300 pF

100-200 pF

15-100 pF

15-30 pF

15 pF

HS 4 MHz

8 MHz

20 MHz

15 pF

Note 1: For VDD > 4.5V, C1 = C2  30 pF is

recommended.

These values are for design guidance only. Rs may

be require d in HS m ode as wel l as X T mode to avoid

overdr ivin g cryst als with low driv e leve l speci ficati on.

Since each crystal has its own characteristics, the

user should consult the crystal manufacturer for

appropriate values of external components.

Note: If you change from this device to another

device , ple ase ve rify os cilla tor c haract eris -

tics in your application.

Clock from

ext. system OSC1

OSC2PIC16C5X

Open

PIC16C5X

DS30453E-page 16 Preliminary  1997-2013 Microchip Technology Inc.

4.3 External Crystal Oscillator Circuit

Either a prepackaged oscillator or a simple oscillator

circuit with TTL gates can be used as an externa l c r ys-

tal os cillator circui t. Prepac kaged os cillat ors provi de a

wide operating range and better stability. A well-

designed crystal oscillator will provide good perfor-

mance with TTL gates. Two types of crystal oscillator

circuits can be used: one with parallel resonance, or

one with series resonance.

Figure 4-3 sho w s a n im ple me nt a tion example of a par-

allel resonant oscillator circuit. The circuit is designed

to use the fundamental frequency of the crystal. The

74AS04 inverter performs the 180-degree phase shift

that a parallel oscillator requires. The 4.7 k resistor

provides the negative feedback for stability. The 10 k

potentiometers bias the 74AS04 in the linear region.

This circuit could be used for external oscillator

designs.

FIGURE 4-3: EXAMPLE OF EXTERNAL

PARALLEL RESONANT

CRYSTAL OSCILLATOR

CIRCUIT (USING XT, HS

OR LP OSCILLATOR

MODE)

Figure 4-4 shows a series resonant oscillator circuit.

This circ uit is also designe d to use the fundame ntal fre-

quency of the crystal. The inverter performs a 180-

degree phase shift in a series resonant oscillator cir-

cuit. The 330 k resistors provide the negative feed-

back to bias the inverters in their linear region.

FIGURE 4-4: EXAMPLE OF EXTERNAL

SERIES RESO NANT

CRYSTAL OSCILLATOR

CIRCUIT (USING XT, HS

OR LP OSCILLATOR

MODE)

20 pF

+5V

20 pF

10K 4.7K

10K

74AS04

XTAL

10K

74AS04 PIC16C5X

CLKIN

To Other

Devices

OSC2

Open

330K

74AS04 74AS04 PIC16C5X

CLKIN

To Other

Devices

XTAL

330K

74AS04

0.1 FOSC2

Open

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 17

PIC16C5X

4.4 RC Oscillator

For timing insensitive applications, the RC device

option offers addition al co st sav in gs . The RC os cil la tor

frequ enc y i s a fu nct ion of the supply volt a ge , the re si s-

tor (REXT) a nd capac itor (CEXT) val ues, and the oper at-

ing temperature. In addition to this, the oscillator

freq ue n cy wi ll v ar y f rom u ni t to un i t du e to no r ma l pro -

cess parameter variation. Furthermore, the difference

in lead frame capacitance between package types will

also affect the oscillation frequency, especially for low

CEXT values. The user also needs to take in to account

variation due to tolerance of external R and C compo-

nents used.

Figure 4-5 shows how the R/C combination is con-

nected to the PIC16C5X. For REXT values below

2.2 k, the oscillator operation may become unstable,

or stop completely. For very high REXT values

(e.g., 1 M) the oscillator becomes sensitive to noise,

humidity and leakage. Thus, we recommend keeping

REXT between 3 k and 100 k.

Although the oscillator will operate with no external

capacitor (CEXT = 0 pF), we recomme nd using v alues

above 2 0 p F fo r noi se an d s t ability reasons. With no or

small external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or pack-

age lead frame capacitance.

The Electrical Specifications sections show RC fre-

quency variation from part to part due to normal pro-

cess vari ation. The variat ion is larger f or larger R (since

leakag e current vari ation will af fec t RC frequency mo re

for large R) and for smaller C (since variation of input

capacitance will affect RC frequency more).

Also, se e the Electrical Specifications secti ons fo r va ri-

ation of os cilla tor frequ ency due to VDD for given REXT/

CEXT values a s well as freq uency varia tion due to op er-

ating temperature for gi ven R, C, and VDD values.

The oscillator frequency, divided by 4, is available on

the OS C2/CLK OUT pin , and c an be use d for te st pur-

poses or to synchronize other logic.

FIGURE 4-5: RC OSCILLATOR MODE

Note: If you change from this device to another

device , ple ase ve rify os cilla tor c haract eris -

tics in your application.

VDD

REXT

CEXT

VSS

OSC1 Internal

clock

OSC2/CLKOUT

Fosc/4

PIC16C5X

DS30453E-page 18 Preliminary  1997-2013 Microchip Technology Inc.

NOTES:

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 19

PIC16C5X

5.0 RESET

PIC16C5X dev ices may be RESET in one of the foll ow-

ing ways:

• Power-On Reset (POR)

•MCLR

Reset (normal o peration)

•MCLR Wake-up Reset (from SLEEP)

• WDT Reset (normal operation)

• WDT Wake-up Reset (from SLEEP)

Table 5-1 shows these RESET conditions for the PCL

and STATUS registers.

Some registers are not affected in any RESET condi-

tion. Their status is unknown on POR and unchanged

in any othe r RESET. Most other registers are res et to a

“RESET state” on Power-On Reset (POR), MCLR or

WDT Reset. A MCLR or WDT wake-up from SLEEP

also results in a device RESET, and not a continuation

of operation before SLEEP.

The T O and PD b its (STATUS <4 :3>) are se t or cleare d

dependi ng on the dif ferent RESET co nditio ns (Table 5-

1). These bits may be used to determine the nature of

the RESET.

Table 5-3 lis ts a full description of RESET states of all

registers. Figure 5-1 shows a simplified block diagram

of the On-chip Reset circuit.

TABLE 5-1: STATUS BITS AND THEIR SIGNIFICANCE

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH RESET

Condition TO PD

Power-On Reset 11

MCLR Reset (normal operation) uu

MCLR Wake-up (from SLEEP) 10

WDT Reset (normal operation) 01

WDT Wake-up (from SLEEP) 00

Legend: u = unchanged, x = unknown, — = unimplemented read as '0'.

Add r e s s Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B it 2 Bit 1 B it 0 Value on

POR

Value on

MCLR a nd

WDT Reset

03h STATUS PA2 PA1 PA0 TO PD ZDC C0001 1xxx 000q quuu

Legend: u = unchanged, x = unknown, q = see Table 5-1 for possible values.

PIC16C5X

DS30453E-page 20 Preliminary  1997-2013 Microchip Technology Inc.

TABLE 5-3: RESET CON DITIONS FOR ALL REGISTERS

FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

WN/Axxxx xxxx uuuu uuuu

TRIS N/A 1111 1111 1111 1111

OPTION N/A --11 1111 --11 1111

INDF 00h xxxx xxxx uuuu uuuu

TMR0 01h xxxx xxxx uuuu uuuu

PCL 02h 1111 1111 1111 1111

STATUS 03h 0001 1xxx 000q quuu

FSR(1) 04h 1xxx xxxx 1uuu uuuu

PORTA 05h ---- xxxx ---- uuuu

PORTB 06h xxxx xxxx uuuu uuuu

PORTC(2) 07h xxxx xxxx uuuu uuuu

General Pu rpose Register Files 07-7Fh xxxx xxxx uuuu uuuu

Legend: x = unknown u = unchanged - = unimplemented, read as '0'

q = see tables in Table 5-1 for possible va lues.

Note 1: These valu es are val id for PIC16C5 7/CR57/C58/CR58. For the PIC16C5 4/CR 54 /C55 / C56/ C R56, the

value on RESET is 111x xxxx and for MCLR and WDT Reset, the value is 111u uuuu.

2: General purpose register file on PIC16C54/CR54/C56/CR56/C58/CR58.

8-bit Asynch

Ripple Counter

(Device Reset

VDD

MCLR/VPP pin

Power-Up

Detect

On-Chip

RC OSC

POR (Power-O n Reset)

WDT Time-out

RESET

CHIP RESET

WDT

Timer)

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 21

PIC16C5X

5.1 Power-On Reset (POR)

The PIC16C5X family incorporates on-chip Power-On

Reset (POR) circuitry which provides an internal chip

RESET for most power-up situations. To use this fea-

ture, the user merely ties the MCLR/VPP pin to VDD. A

simplified block diagram of the on-chip Power-On

Reset circuit is shown in Figure 5-1.

The Power-On Reset circuit and the Device Reset

Timer (Section 5.2) circuit are closely related. On

power-up, the RESET latch is set and the DRT is

RESET. The DRT timer be gins countin g once it detect s

MCLR to be high. After the time-out period, which is

typically 18 ms, it will RESET the reset latch and thus

end the on-chip RESET signal.

A power-up exam ple whe re MCLR is not tied to VDD is

shown in Figure 5-3. VDD is allowed to rise and stabilize

before bringing MCLR high. The ch ip will actually com e

out of reset TDRT msec after MCLR goes high.

In Figure 5-4, the on-chip Power-On Reset feature is

being used (MCLR and VDD are tied together). The VDD

is st able bef ore the st art-up timer times out and the re is

no problem in getting a proper RESET. However,

Figure 5-5 depic ts a pro blem situation w here VDD rises

too slowly. The time between when the DRT senses a

high on the MCLR/VPP pin, and when the MCLR/VPP

pin ( and VDD) ac tuall y reach th eir full valu e, is t oo lon g.

In this s itua tio n, whe n th e start-up timer time s o ut, V DD

has not reached the VDD (min) value and the chip is,

therefore, not guaranteed to function correctly. For

such situations, we recommend that external RC cir-

cuits be used to achieve longer POR delay times

(Figure 5-2).

For more information on PIC16C5X POR, see Power-

Up Considerations - AN522 in the Embedded Control

Handbook.

The POR circuit does not produce an internal RESET

when VDD declines.

FIGURE 5-2: EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

Note: When the device starts normal operation

(exits the RESET condition), device oper-

ating parameters (v ol t age , fre que nc y, tem-

perature, etc.) must be met to ensure

operation. If these conditions are not met,

the dev ice must be held in RESET unti l the

operating conditions are met.

MCLR

PIC16C5X

VDDVDD

• External Power-On Reset circuit is required

only if VDD power-up is too slow. The diode D

helps discharge the capacit or quickly when

VDD powers down.

•R < 40k is reco mm ended to make su re th at

voltage drop across R does not violate the

device electrical specification.

•R1 = 100 to 1 k will limit any current flow-

ing into M CLR from external capacitor C in the

even t of MC LR pin breakdown due to Electro-

static Discharge (ESD) or Electrical Over-

stress (EOS).

PIC16C5X

DS30453E-page 22 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)

FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE

TIME

FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE

TIME

VDD

MCLR

INTERNAL POR

DRT TI ME-OU T

INTERNAL RESET

TDRT

VDD

MCLR

INTERNAL POR

DRT TIM E- OU T

INTERNAL RESET

TDRT

VDD

MCLR

INTERNAL POR

DRT TIME-OU T

INTERNAL RESET

When VDD ri se s slowly, the TDRT time-out expires long before VDD has reached its final value. In

this example, the chip will RESET properly if, and only if, V1  VDD min

TDRT

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 23

PIC16C5X

5.2 Device Reset Timer (DRT)

The Device Reset Timer (DRT) provides an 18 ms

nominal time-out on RESET regardless of Oscillator

mode us ed. The DR T opera tes on an internal RC oscil-

lator. The processor is kept in RESET as long as the

DRT i s active. The DR T delay allows VDD to rise above

VDD min., and for the oscillator to stabilize.

Oscil lator c ircuit s ba sed on cryst als or cera mic res ona-

tors require a certain time after power-up to establish a

stab le oscill ation. The on-c hip DR T keep s the devi ce in

a RESET condition for approximately 18 ms after the

voltage on the MCLR/VPP pin has rea ch ed a logic high

(VIH) level. Thus, external RC networks connected to

the MCLR input are not required in most cases, allow-

ing for sav ings in co st-sensitiv e and/or sp ace restri cted

applications.

The Device Reset time delay will vary from chip to chip

due to VDD, temperature, and process variation. See

AC parameters for details.

The D RT w ill also be tri ggered upon a Watchdog Timer

time-out. This is particularly important for applications

using the WDT to wake the PIC16C5X from SLEEP

mode automatically.

5.3 Reset on Brown-Out

A brown-out is a condition where device power (VDD)

dips below it s minimum value, but no t to zero, an d then

recovers. The device should be RESET in the event of

a brown-out.

To RESET PIC16C5X devices when a brown-out

occurs, external brown-out protection circuits may be

built, as shown in Figure 5-6, Figure 5-7 and Figure 5-

FIGURE 5-6: EX T ERNAL BROWN-OUT

PROTECTION CIRCUIT 1

FIGURE 5-7: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 2

FIGURE 5-8: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 3

This circuit will activate RE SET when VDD goes below Vz

+ 0.7V (where Vz = Zener voltage).

33K

10K

40K

VDD

MCLR

PIC16C5X

VDD

This brown-out circuit is less expensive, although

less accurate. Transistor Q1 turns off when VDD

is below a certain level such that:

VDD • R1

R1 + R2 = 0.7V

R2 40K

VDD

MCLR

PIC16C5X

VDD

This brown-out protection circuit employs Micro-

chip Technology’s MCP809 microcontroller

supervisor. The MCP8XX and MCP1XX families

of supervi so r s pro vi de pu sh -pul l and open collec -

tor outputs with both "active high and active low"

RESET pins. Th ere are 7 dif ferent trip point se lec-

tions to accommodate 5V and 3V systems.

MCLR

PIC16C5X

VDD

Vss RST

MCP809

VDD

bypass

capacitor VDD

PIC16C5X

DS30453E-page 24 Preliminary  1997-2013 Microchip Technology Inc.

NOTES:

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 25

PIC16C5X

6.0 MEMORY ORGANIZATION

PIC16C5X m em ory is orga niz ed into pro gram me mo ry

and data memory. For devices with more than 512

bytes of program memory, a paging scheme is used.

Program memory pages are accessed using one or two

STA TUS Regist er bits. For device s with a d ata me mory

scheme is used. Data memory banks are accessed

using the File Selection Register (FSR).

6.1 Program Memory Organization

The PIC16C54, PIC16CR54 and PIC16C55 have a 9-

bit Progra m Coun ter (PC) capabl e o f a ddre ssin g a 51 2

x 12 program memory space (Figure 6-1). The

PIC16C56 and PIC16CR56 have a 10-bit Program

Counter (PC) capable of addressing a 1K x 12 program

memory space (Figure 6-2). The PIC16CR57,

PIC16C58 and PIC16CR58 have an 11-bit Program

Counter capable of addressing a 2K x 12 program

memory space (Figure 6-3). Accessing a location

above th e physic ally impl emented a ddress will cause a

wraparound.

A NOP at the RESET vector loca tion will caus e a restart

at locat ion 000 h. The RESET vector for the PIC16C5 4,

PIC16CR54 and PIC16C55 is at 1FFh. The RESET

vector for the PIC16C56 and PIC16CR56 is at 3FFh.

The RESET vector for the PIC16C57, PIC16CR57,

PIC16C58, and PIC16CR58 is at 7FFh. See

Section 6.5 for additional information using CALL and

GOTO instructi ons .

FIGURE 6-1: PI C16C5 4/CR5 4/C5 5

PROGRAM MEMORY MAP

AND STACK

FIGURE 6-2: PIC16C56/CR56

PROGRAM ME MORY MAP

AND STACK

FIGURE 6-3: PIC16C57/CR57/C58/

CR58 PROGRAM

MEMORY MAP AND

STACK

PC<8:0>

Stack Level 1

Stack Level 2

User Memory

Space

CALL, RETLW 9

000h

1FFh

RESET Vector

0FFh

100h

On-chip

Program

Memory

PC<9:0>

Stack Level 1

Stack Level 2

User Memory

Space

000h

1FFh

RESET Vector

0FFh

100h

On-chip Program

Memory (Page 0)

On-chip Program

Memory (Page 1)

200h

2FFh

300h

3FFh

CALL, RETLW

PC<10:0>

Stack Level 1

Stack Level 2

User Memory

Space

000h

1FFh

RESET Vector

0FFh

100h

On-chip Program

Memory (Page 0)

On-chip Program

Memory (Page 1)

On-chip Program

Memory (Page 2)

On-chip Program

Memory (Page 3)

200h

3FFh

2FFh

300h

400h

5FFh

4FFh

500h

600h

7FFh

6FFh

700h

CALL, RETLW

PIC16C5X

DS30453E-page 26 Preliminary  1997-2013 Microchip Technology Inc.

6.2 Data Memory Organization

Data memory is composed of registers, or bytes of

RAM. T herefore, data me mory for a devic e is specified

by its register file. The register file is divided into two

functional groups: Special Fu nction Registers and Gen-

eral Purpo se Regi st ers .

The Special Function Registers include the TMR0 reg-

ister, the Program Counter (PC), the Status Register,

the I/O registers (ports) and the File Select Register

(FSR). In a ddition, Specia l Purpose R egisters are used

to control the I/O port configuration and prescaler

options.

The General Purpose Registers are used for data and

control inf ormati on under com mand of the instru ctions .

For the PIC16C54, PIC16CR54, PIC16C56 and

PIC16CR56, the register file is composed of 7 Special

Funct i on Regi s te rs an d 25 Gen er al Pu r p os e Reg i st ers

(Figure 6-4).

For the PIC16C55, the register file is composed of 8

Special Function Registers and 24 General Purpose

Registers.

For the PIC16C57 and PIC16CR57, the register file is

compos ed of 8 Specia l Fun ction Re gister s, 24 Ge nera l

Purpose Registers and up to 48 additional General

Purpose Registers that may be addressed using a

banking scheme (Figure 6-5).

For the PIC16C58 and PIC16CR58, the register file is

compos ed of 7 Specia l Fun ction Re gister s, 25 Ge nera l

Purpose Registers and up to 48 additional General

Purpose Registers that may be addressed using a

banking scheme (Figure 6-6).

6.2.1 GENERAL PURPOSE REGISTER

FILE

The register file is accessed either directly or indirectly

through the File Select Register (FSR). The FSR Reg-

ister is described in Section 6.7.

FIGURE 6-4: PIC16C54, PIC16CR54,

PIC16C55, P IC1 6C56 ,

PIC16CR56 REGISTER

FILE MAP

File Address

00h

01h

02h

03h

04h

05h

06h

07h

1Fh

INDF(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

General

Purpose

Registers

Note 1: Not a physical register. See

Section 6.7.

2: PIC16C55 o nly, in all other devices thi s

is impl emente d as a a gen eral pu rpose

PORTC(2)

08h

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 27

PIC16C5X

FIGURE 6-5: PIC16C57/CR57 REGISTER FILE MAP

FIGURE 6-6: PIC16C58/CR58 REGISTER FILE MAP

File Address

00h

01h

02h

03h

04h

05h

06h

07h

1Fh

INDF(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

0Fh

10h

Bank 0 Bank 1 Bank 2 Bank 3

3Fh

30h

20h

2Fh

5Fh

50h

40h

4Fh

7Fh

70h

60h

6Fh

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

PORTC

08h

Addresses map back to

addresses in Bank 0.

Note 1: Not a physical register. See Section 6.7.

FSR<6:5> 00 01 10 11

File Address

00h

01h

02h

03h

04h

05h

06h

07h

1Fh

INDF(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

0Fh

10h

Bank 0 Bank 1 Bank 2 Bank 3

3Fh

30h

20h

2Fh

5Fh

50h

40h

4Fh

7Fh

70h

60h

6Fh

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

Addresses map back to

addresses in Bank 0.

Note 1: Not a physical register. See Section 6.7.

FSR<6:5> 00 01 10 11

PIC16C5X

DS30453E-page 28 Preliminary  1997-2013 Microchip Technology Inc.

6.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions to control the opera-

tion of the device (Table 6-1).

The Special Registers can be classified into two sets.

The Special Function Registers associated with the

“core” functions are described in this section. Those

related to the operation of the peripheral features are

des c ribed in the section for each peripheral feature.

TABLE 6-1: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

Power-on

Reset

Details

on Page

N/A TRI S I/O Control Registers (TRISA, TRISB, TRISC) 1111 1111 35

N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler --11 1111 30

00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx 32

01h TMR0 Timer0 Module Register xxxx xxxx 38

02h(1) PCL Low order 8 bits of PC 1111 1111 31

03h STATUS PA2 PA1 PA0 TO PD ZDCC 0001 1xxx 29

04h FSR Indirect data memory address pointer 1xxx xxxx(3) 32

05h PORTA — — — — RA3 RA2 RA1 RA0 ---- xxxx 35

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 35

07h(2) PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 35

Legend: x = unknown, u = unchanged, – = unimplemented, read as '0' (if applicable). Shaded cells = unimplemented or unused

Note 1: The upper byte of the Program Counter is not directly accessible. See Section 6.5 for an explanation of how to access

these bits.

2: File address 07h is a General Purpose Register on the PIC16C54, PIC16CR54, PIC16C56, PIC16CR56, PIC16C58 and

PIC16CR58.

3: These values are valid for PIC16C57/CR57/C58/CR58. For the PIC16C54/CR54/C55/C56/CR56, the value on RESET is

111x xxxx and for MCLR and WDT Reset, the value is 111u uuuu.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 29

PIC16C5X

6.3 STATUS Register

This register contains the arithmetic status of the ALU,

the RESET status and the page preselect bits for pro-

gram memories larger than 512 words.

The STATUS Register can be the destination for any

instruction, as with any other register. If the STATUS

Regis ter is the destin ation for an in struct ion that af fect s

the Z, DC or C bits, then the write to these three bits is

disabl ed. These bit s are set or clea red according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS R egis t er as d es tin at i o n m ay b e diffe r en t t h an

intended.

For example, CLRF STATUS will clear the upper three

bits and se t the Z bit . This leav es t he STATUS Regist er

as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF and

MOVWF instructions be us ed to alter the STATUS Reg-

ister b ecaus e the se i nstruct ions do n ot af fec t the Z, D C

or C bits from the STATUS Register. For other instruc-

tions which do affect STATUS Bits, see Section 10.0,

Instruction Set Summary.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

PA2 PA1 PA0 TO PD ZDCC

bit 7 bit 0

bit 7: PA2: This bit unused at this time.

Use of the PA2 bit as a ge neral purpose read/w ri te bi t is no t re com m end ed, si nc e thi s m ay affect upward

compatibility with future products.

bit 6-5: PA<1:0>: Program page preselect bits (PIC16C56/CR56)(PIC16C57/CR57)(PIC16C58/CR58)

00 = Page 0 (000h - 1FFh) - PIC16C56/CR56, PIC16C57/CR57, PIC16C58/CR58

01 = Page 1 (200h - 3FFh) - PIC16C56/CR56, PIC16C57/CR57, PIC16C58/CR58

10 = Page 2 (400h - 5FFh) - PIC16C57/CR57, PIC16C58/CR58

11 = Page 3 (600h - 7FFh) - PIC16C57/CR57, PIC16C58/CR58

Each page is 512 words.

Using the PA<1:0> bits as general purpose read/write bits in devices which do not use them for program

page preselect is not recommended since this may affect upward compatibility with future products.

bit 4: TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred

bit 3: PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions)

ADDWF

1 = A carry from the 4th low order bit of the result occurred

0 = A carry from the 4th low order bit of the result did not occur

SUBWF

1 = A borrow from the 4th low order bit of the result did not occur

0 = A borrow from the 4th low order bit of the result occurred

bit 0: C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)

ADDWF SUBWF RRF or RLF

1 = A carry occurred 1 = A borrow did not occur Loaded with LSb or MSb, respectively

0 = A carry did not occur 0 = A borrow occurred

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown

PIC16C5X

DS30453E-page 30 Preliminary  1997-2013 Microchip Technology Inc.

6.4 OPTION Register

The OPTION Register is a 6-bit wide, write-only regis-

ter which contains various control bits to configure the

Timer0/WDT prescaler and Timer0.

By executing the OPTION instruction, the contents of

the W Register will be transferred to the OPTION Reg-

ister. A RESET sets the OPTION<5:0> bits.

U-0 U-0 W-1 W-1 W-1 W-1 W-1 W-1

—— T0CS TOSE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7-6: Unimplemented: Read as ‘0’

bit 5: T0CS: Timer0 clock source select bit

1 = Tr ans iti on on T0CK I pin

0 = Internal instruction cycle cloc k (CLKOUT)

bit 4: T0SE: Timer0 source edge select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

bit 3: PSA: Prescaler assignmen t bit

1 = Prescaler assigned to the WDT

0 = Prescaler assigned to Timer0

bit 2-0: PS<2:0>: Prescaler rate sel ec t bit s

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value Timer0 Rate WDT Rate

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 31

PIC16C5X

6.5 Program Counter

As a program instruction is executed, the Program

Counter (PC) will contain the address of the next pro-

gram instruction to be executed. The PC value is

increased by one, every instruction cycle, unless an

instruction changes the PC.

For a GOTO instruction, bits 8:0 of the PC are provided

by the GOTO instruction word. The PC Latch (PCL) is

mapped to PC<7:0> (Figure 6-7, Figure 6-8 and

Figure 6-9).

For the PIC16C56, PIC16CR56, PIC16C57,

PIC16CR 57, PIC16C58 and PIC 16CR58, a pa ge num-

ber must be supplied as well. Bit5 and bit6 of the STA-

TUS Register provide page information to bit9 and

bit10 of the PC (Figure 6-8 and Figure 6-9).

For a CALL instruction, or any instruction where the

PCL is t he destina tion, bit s 7:0 of th e PC again are p ro-

vided by the instruction word. However, PC<8> does

not come from the instruction word, but is always

cleared (Figure 6-7 and Figure 6-8).

Instr uctions where the PCL is th e destinatio n, or modif y

PCL instructions, include MOVWF PCL, ADDWF PCL,

and BSF PCL,5.

For the PIC16C56, PIC16CR56, PIC16C57,

PIC16CR 57, PIC16C58 and PIC 16CR58, a pa ge num-

ber again must be supplied. Bit5 and bit6 of the STA-

TUS Register provide page information to bit9 and

bit10 of the PC (Figure 6-8 and Figure 6-9).

FIGURE 6-7: LOADING OF PC

BRANCH INSTRUCTIONS

- PIC16C54, PIC16CR54,

PIC16C55

FIGURE 6-8: LOADING OF PC

BRANCH INSTRUCTIONS

- PIC16C56/PIC16CR56

FIGURE 6-9: LOADING OF PC

BRANCH INSTRUCTIONS

- PIC16C57/PIC16CR57,

AND PIC16C58/

PIC16CR58

Note: Because PC<8> is cleared in the CALL

instruction, or any modify PCL instruction,

all subroutine calls or computed jumps are

limited to the first 256 lo ca tion s o f an y pro-

gram memory page (512 words long).

87 0

PCL

87 0

PCL

Reset to '0'

Instruction Word

GOTO Instruction

CALL or Modify PCL Instruction

PA<1:0>

STATUS

PC 87 0

PCL

910

PA<1:0>

STATUS

PC 87 0

PCL

910

Instruction Word

Reset to ‘0’

Instruction Word

GOTO Instruction

CALL or Modify PCL Instruction

PA<1:0>

STATUS

PC 87 0

PCL

910

PA<1:0>

STATUS

PC 87 0

PCL

910

Instruction Word

Reset to ‘0’

Instruction Word

GOTO Instruction

CALL or Modify PCL Instruction

PIC16C5X

DS30453E-page 32 Preliminary  1997-2013 Microchip Technology Inc.

6.5.1 PAGING CONSIDERATIONS –

PIC16C56/CR56, PIC16C57/CR57

AND PIC16C58/CR58

If the Prog ram Counter is pointi ng to the last addre ss of

a selected memory page, when it increments it will

cause th e program to continue in the nex t highe r pag e.

However, the page preselec t bits in the STATUS Reg-

ister will not be updated. Therefore, the next GOTO,

CALL or modify PCL instruction will send the program

to the p age s pecified by the p age pr eselect bits (PA0 or

PA<1:0>).

For example, a NOP at location 1FFh (page 0) incre-

ments the PC to 200h (page 1). A GOTO xxx at 200h

will return the program to address xxh on page 0

(assuming that PA<1:0> are clear).

To prevent this, the page preselect bits must be

updated under program control.

6.5.2 EFFECTS OF RESET

The Program Counter is set upon a RESET, which

means that the PC addresses the last location in the

last page (i.e., the RESET vector).

The STATUS Register page preselect bits are cleared

upon a RESET, which means that page 0 is pre-

selected.

Therefore, upon a RESET, a GOTO instruction at the

RESET vector locatio n will automatical ly cause the p ro-

gram to jump to page 0.

6.6 Stack

PIC16C5X devices have a 10-bit or 11-bit wide, two-

level hardware pu sh/pop stack.

A CALL instruction will push the current value of stack

1 into st ack 2 and then pus h the current program cou n-

ter value, incremented by one, into stack level 1. If

more than two sequential CALL’s are executed, only

the most recent two return addresses are stored.

A RETLW in struction will po p the contents of stack l eve l

1 into the program counter and then copy stack level 2

contents into level 1. If more than two sequential

RETLW’s are executed, the stack will be filled with the

address previously stored in level 2. Note that the

W Register will be lo aded with the literal value specifie d

in the instruction. This is particularly useful for the

implementation of data look-up tables within the pro-

gram memory.

For the RETLW instruction, the PC is loaded with the

Top of St ack (T OS) content s. All of the devices cov ered

in this d ata sheet hav e a two-l evel st ack. The sta ck has

the same bit width as the device PC, therefore, paging

is not an issue when returning from a subroutine.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 33

PIC16C5X

6.7 Indirect Data Addressing; INDF

and FSR Registers

The INDF Register is not a physical register.

Addressing INDF actually addresses the register

whose address is contained in the FSR Register (FSR

is a pointer). This is indirect addressing.

EXAMPLE 6-1: INDIRECT ADDRESSI NG

• Register file 08 contains the value 10h

• Register file 09 contains the value 0Ah

• Load the value 08 into the FSR Register

• A read of the INDF Register will return the value

of 10h

• Increment the value of the FSR Register by one

(FSR = 09h)

• A read of the INDF register now will return the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce

00h. Writing to the INDF Register indirectly results in a

no-operati on (although STATUS bits may be affected).

A simple program to clear RAM locations 10h-1Fh

using indirect addressing is shown in Example 6-2.

EXAMPLE 6-2: HOW TO CLEAR RAM

USING INDIRECT

ADDRESSING

MOVLW H'10' ;initialize pointer

MOVWF FSR ; to RAM

NEXT CLRF INDF ;clear INDF Register

INCF FSR,F ;inc pointer

BTFSC FSR,4 ;all done?

GOTO NEXT ;NO, clear next

CONTINUE

: ;YES, continue

The FSR is either a 5-bit (PIC16C54, PIC16CR54,

PIC16C55, PIC16C56, PIC16CR56) or 7-bit

(PIC16C57, PIC16CR57, PIC16C58, PIC16CR58)

wide register. It is used in conjunction with the INDF

The FSR<4:0> bits are used to select data memory

addresses 00h to 1Fh.

PIC16C54, PIC16CR54, PIC16C55, PIC16C56,

PIC16CR56: These do not us e banking. FSR<6 :5> bit s

are unimplemented and read as '1's.

PIC16C57, PIC16CR57, PIC16C58, PIC16CR58:

FSR<6:5> are the bank select bits and are used to

select the bank to be addressed (00 = bank 0,

01 =bank 1, 10 = bank 2, 11 = bank 3).

FIGURE 6-10: DIRECT/INDIRECT ADDRESSING

Note 1: For register map detail see Section 6.2.

bank location select

location select

bank select

Indirect Addressing

Direct Addressing

Data

Memory(1) 0Fh

10h

Bank 0 Bank 1 Bank 2 Bank 3

(FSR)

1000 01 11

00h

1Fh 3Fh 5Fh 7Fh

(opcode) 04

(FSR)

Addresses map back to

addresses in Bank 0.

321

PIC16C5X

DS30453E-page 34 Preliminary  1997-2013 Microchip Technology Inc.

NOTES:

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 35

PIC16C5X

7.0 I/O PORTS

As with any other register, the I/O Registers can be

written and read und er program contro l. Howeve r , rea d

instructions (e.g., MOVF PORTB,W) always read t he I/O

pins independent of the pin’s input/output modes. On

RESET, all I/O ports are defined as input (inputs are at

hi-impedance) since the I/O control registers (TRISA,

TRISB, TRISC) are al l set.

7.1 PORTA

PORTA is a 4-bit I/O Regis ter. Only the low order 4 bit s

are used (RA<3:0>). Bits 7-4 are unimplemented and

read as '0's.

7.2 PORTB

PORTB is an 8-bit I/O Register (PORTB<7:0>).

7.3 PORTC

PORTC is an 8-bit I/O Register for PIC16C55,

PIC16C57 and PIC16CR57.

PORTC is a General Purpose Register for PIC16C54,

PIC16CR54, PIC16C56, PIC16CR56, PIC16C58 and

PIC16CR58.

7.4 TRIS Registers

The Output Driver Control Registers are loaded with

the contents of the W Register by executing the

TRIS f instruction. A '1' from a TRIS Register bit puts

the corresponding output driver in a hi-impedance

(input) mode. A '0' puts the contents of the output data

latch o n the s ele cted pins, enabl ing the output buffer.

The TRIS Regi sters are “write-only ” and are set (output

drivers disabled) upon RESET.

7.5 I/O Int erfacing

The equivalent circuit for an I/O port pin is shown in

Figure 7-1. All ports may be used for both input and

output operation. For input operations these ports are

non-latching. Any input must be present until read by

an input instruction (e.g., MOVF PORTB, W). The out-

put s are latched an d remain unc hanged until t he output

latch is rewritten. To use a port pin as output, th e corre-

sponding direction control bit (in TRISA, TRISB,

TRISC) must be cl eare d (= 0 ) . Fo r us e as an i nput, the

correspo nding TRIS bit must be set. Any I/O p in can b e

programmed individually as input or output.

FIGURE 7-1: EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

TABLE 7-1: SUMMARY OF PORT REGISTERS

Note: A read of the por ts re ads the pin s, n ot the

output data latches. That is, if an output

driver on a pin is enabled and driven high,

but the external system is holding it low, a

read of the port will indicate that the pin is

low.

Note 1: I/O pins have protection diodes to VDD and VSS.

Data

Bus

CK P

Port

TRIS ‘f’

Data

TRIS

RD Port

VSS

VDD

I/O

pin(1)

Reg

Latch

RESET

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 V a lue on

Power-On

Reset

Value on

MCLR and

WDT Reset

N/A TRIS I/O Control Registers (TRISA, T RISB, TRISC) 1111 1111 1111 1111

05h PORTA ———— RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu

07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu

Legend: x = unknown, u = unchanged, — = unimplemented, read as '0', Shaded cells = unimplemented, read as ‘0’

PIC16C5X

DS30453E-page 36 Preliminary  1997-2013 Microchip Technology Inc.

7.6 I/O Progra mming Consi derations

7.6.1 BI-DIRECTIONAL I/O PORTS

Some instructions operate internally as read followed

by write operations. The BCF and BSF instructions, for

exampl e, read the entire port into the CPU, execute the

bit operation and re-write the result. Caution must be

used when these instructions are applied to a port

where one or more pin s are us ed as in put/ outputs. For

exampl e, a BSF ope rati on o n bi t5 o f PO RTB will cause

all eight bi t s of POR TB to be read into the CPU, bi t5 to

be set and the POR TB val ue to be w ritten to the outp ut

latches. If another bit of PORTB is used as a bi-direc-

tional I/O pin (say bit0) and it is defined as an input at

this tim e, the input signa l present on the pin it self would

be read into the CPU and rewritten to the data latch of

this particular pin, overwriting the previous content. As

long as the pin stays in the Input mode, no problem

occurs. However, if bit0 is switched into Output mode

later on, the content of the data latch may now be

unknown.

Example 7-1 shows the effect of two sequential read-

modify-write instructions (e.g., BCF, BSF, etc.) on an

I/O port.

A pin actively outputting a high or a low should not be

driven from external devices at the same time in order

to chang e the level o n this pin (“wired -or”, “wired-an d”).

The resulting high output currents may damage the

chip.

EXAMPLE 7-1: READ-MODIFY-WRITE

INSTRUCTIONS ON AN I/O

PORT

;Initial PORT Settings

; PORTB<7:4> Inputs

; PORTB<3:0> Outputs

;PORTB<7:6> have external pull-ups and are

;not connected to other circuitry

;

; PORT latch PORT pins

; ---------- ----------

BCF PORTB, 7 ;01pp pppp 11pp pppp

BCF PORTB, 6 ;10pp pppp 11pp pppp

MOVLW H'3F' ;

TRIS PORTB ;10pp pppp 10pp pppp

;

;Note that the user may have expected the pin

;values to be 00pp pppp. The 2nd BCF caused

;RB7 to be latched as the pin value (High).

7.6.2 SUCCESSIVE OPERATIONS ON I/O

PORTS

The actu al write to an I/O port happe ns at th e end of a n

instruction cycle, whereas for reading, the data must be

valid a t the beg innin g of the ins tructio n cycle (Figure 7-

2). Therefore, care must be exercised if a write followed

by a read o peratio n is ca rried ou t on the s ame I/O po rt.

The sequence of instructions should allow the pin volt-

age to stabilize (load dependent) before the next

instruction, which causes that file to be read into the

CPU, is executed. Otherw ise, the prev ious st ate of that

pin may be read into th e CPU rather than the new stat e.

When in doubt, it is better to separate these instruc-

tions with a NOP or another instruction not accessing

this I/O port.

FIGURE 7-2: SUCCESSIVE I/O OPERATION

PC PC + 1 PC + 2 PC + 3

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Instruction

fetched

RB<7:0>

MOVWF PORTB NOP

Port pin

sampled here

NOPMOVF PORTB,W

Instruction

executed

MOVWF PORTB

(Write to

PORTB)

NOP

MOVF PORTB, W

This example shows a write

to PORTB followed by a read

from PORTB.

(Read

PORTB)

Port pin

written here

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 37

PIC16C5X

8.0 TIMER0 MODULE AND TMR0

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

- Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

- Edge select for external clock

Figure 8-1 is a simplified block diagram of the Timer0

module , while Fig ure 8-2 shows the elect rical stru ctur e

of the Timer0 input.

Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In Timer mode, the Timer0 module will

increm ent ev ery ins tru cti on cycle (witho ut p res ca ler). If

TMR0 register is written, the increment is inhibited for

the following two cycles (Figure 8-3 and Figure 8-4).

The user can work around this by writing an adjusted

value to the TMR0 register.

Counter mode is selected by setting the T0CS bit

(OPTION<5>). In this mode, Timer0 will increment

either on every rising or falling edge of pin T0CKI. The

incrementing edge is determined by the source edge

select bit T0SE (OPTION<4>). Clearing the T0SE bit

selects the rising edge. Restrictions on the external

clock input are di scussed in detail in Section 8.1 .

The prescaler assignment is controlled in software by

the cont rol bit PSA (OPTION<3>). Clearing th e PSA bit

will assign the prescale r to T imer0 . The pres caler is not

readable or writable. Whe n the prescaler is assi gned to

the Timer0 module, prescale values of 1:2, 1:4,...,

1:256 are selectable. Section 8.2 details the operation

of the pres caler.

A summary of registers associated with the Timer0

module is found in Table 8-1.

FIGURE 8-1: TIMER0 BLOCK DIAGRAM

FIGURE 8-2: ELECTRICAL STRUCTURE OF T0CKI PIN

Note: The prescaler may be used by either the

T imer 0 module or the W atchdog Timer, but

not both.

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION regis ter

(Section 6.4).

2: The prescaler is shared with the Watchdog Timer (Figure 8-6).

T0CKI

T0SE

(1)

T0CS

(1)

OSC

Programmable

Prescaler

(2)

Sync with

Internal

Clocks TMR0 reg

PSout

(2 cycle delay)

PSout

Data Bus

PSA

(1)

PS2, PS1, PS0

(1)

Sync

VSS

RIN

Schmitt Trigger

NInput Buffer

T0CKI

Note 1: ESD protection circuits.

(1) (1)

PIC16C5X

DS30453E-page 38 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 8-3: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER

FIGURE 8-4: TIMER0 TIMING: INTERNAL CLOCK/PRESCALER 1:2

TABLE 8-1: REGISTERS ASSOCIATED WITH TIMER0

Add r e s s Name Bit 7 Bit 6 B it 5 Bit 4 B it 3 Bit 2 Bit 1 B it 0 Value on

Power-on

Reset

Value on

MCLR a nd

WDT Reset

01h TMR0 Timer0 - 8-bit real-time clock/counter xxxx xxxx uuuu uuuu

N/A OPTION —— T0CS T0SE PSA PS2 PS1 PS0 --11 1111 --11 1111

Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells not used by Timer0.

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

Timer0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0

executed Read TMR0

reads NT0 Read TMR0

reads NT0 + 1 Read TMR0

reads NT0 + 2

Instruction

Executed

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

Timer0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 NT0+1

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0

executed Read TMR0

reads NT0 Read TMR0

reads NT0 + 1

T0+1 NT0

Instruction

Execute

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 39

PIC16C5X

8.1 Using Timer0 with an External

Clock

When an external cl ock input i s used for T ime r0, it must

meet ce r tain r equ ir e me nts. The ex t er na l cl oc k req u ire -

ment is due to internal phase clock (TOSC) synchron iza-

tion. Also , there is a dela y in the ac tual incr emen ting of

Timer0 after synchronization.

8.1.1 EXT ERN AL CLOC K

SYNCHRONIZATION

When no pr escal er is used, t he ex ternal clo ck inp ut is

the same as the pre sc al er outp ut. Th e sy nch ron iz atio n

of T0CKI with the internal phase clocks is accom-

plishe d by sampling the prescale r output on the Q2 and

Q4 cycles of the internal phase clocks (Figure 8-5).

Therefore, it is necessary for T0CKI to be high for at

least 2TOSC (and a small R C delay of 2 0 ns) a nd low for

at le ast 2 TOSC (and a small RC de lay of 20 ns). Refer

to the electrical specification of the desired device.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple counter-type pres-

caler so that the prescaler output is symmetrical. For

the external clock to meet the sampling requirement,

the ripple counter must be taken into account. There-

fore, it is necessary for T0CKI to have a period of at

least 4TOSC (and a sm all RC de lay of 40 ns) div ided b y

the prescaler value. The only requirement on T0CKI

high and low time is that they do not violate the mini-

mum pulse width requirement of 10 ns. Refer to param-

eters 40, 4 1 an d 42 in the electrica l spec ifi ca tion of the

desired device.

8.1.2 TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock ed ge occurs to th e time the T im er0 mod-

ule is actuall y increm ented. F igure 8-5 show s the de lay

from the e xte rnal cl oc k edge to the time r inc rem en tin g.

FIGURE 8-5: TIMER0 TIMING WITH EXTERNAL CLOCK

Increment Timer0 (Q4)

External Clock Input or Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Timer0 T0 T0 + 1 T0 + 2

Small pulse

misses sampling

External Clock/Prescaler

Output After Sampling (2)

Prescaler Output (1)

(3)

Note 1: External clock if no prescaler selected, prescaler output otherwise.

2: The arrows indicate the points in time where sampling occurs.

3: Delay from clock input c hange to T ime r0 in crement is 3Tosc to 7Tosc (duration of Q = Tosc). Therefo re,

the error in measuring the interval between two edges on Timer0 input =  4Tosc max.

PIC16C5X

DS30453E-page 40 Preliminary  1997-2013 Microchip Technology Inc.

8.2 Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer (WDT), respectively (Section 9.2.1). For simplic-

ity, this counter is being referred to as “prescaler”

througho ut this data she et. Note that the prescal er may

be used by either the Timer0 module or the WDT, but

not both. Thus, a prescaler assignment for the Timer0

module means that there is no prescaler for the WDT,

and vice-versa.

The PSA and PS<2:0> bits (OPTION<3:0>) determine

prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF 1,

MOVWF 1, BSF 1,x, etc.) will clear the prescaler.

When ass igned to WDT, a CLRWDT in struction will c lear

the pr esca ler alo ng with the WD T. The presca ler is ne i-

ther readable nor writable. On a RESET, the prescaler

contains all '0's.

8.2.1 SWITCHIN G PRESCA LER

ASSIGNMENT

The prescaler assignment is fully under software con-

trol (i.e., it can be changed “on the fly” during program

execut ion ). To avoid a n un in tend ed device RESET, the

following instruction sequence (Example 8-1) must be

executed when changing the prescaler assignment

from Timer0 to the WDT.

EXAMPLE 8-1: CHANGING PRESCALER

(TIMER0WDT)

CLRWDT ;Clear WDT

CLRF TMR0 ;Clear TMR0 & Prescaler

MOVLW B'00xx1111’ ;Last 3 instructions in

this example

OPTION ;are required only if

;desired

CLRWDT ;PS<2:0> are 000 or

;001

MOVLW B'00xx1xxx’ ;Set Prescaler to

OPTION ;desired WDT rate

To change prescaler from the WDT to the Timer0 mod-

ule, use the sequence shown in Example 8-2. This

sequenc e mus t be us ed ev en if th e WDT is disab led. A

CLRWDT instruction should be executed before switch-

ing the prescaler.

EXAMPLE 8-2: CHANGING PRESCALER

(WDTTIMER0)

CLRWDT ;Clear WDT and

;prescaler

MOVLW B'xxxx0xxx' ;Select TMR0, new

;prescale value and

;clock source

OPTION

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 41

PIC16C5X

FIGURE 8-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

T0CKI

T0SE

TCY ( = FOSC/4)

Sync

Cycles TMR0 reg

8-bit Prescaler

8 - to - 1MUX

MUX

Watchdog

Timer

PSA

WDT

Time-Out

PS<2:0>

Note: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.

PSA

WDT Enable bit

Data Bus

PSA

T0CS

PIC16C5X

DS30453E-page 42 Preliminary  1997-2013 Microchip Technology Inc.

NOTES:

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 43

PIC16C5X

9.0 SPECIAL FEATURES OF THE

CPU

What sets a microcontroller apart from other proces-

sors a re special circuits that deal with the nee ds of real-

time applications. The PIC16C5X family of microcon-

trollers have a host of such features intended to maxi-

mize system reliability, minimize cost through

elimination of external components, provide power sav-

ing operating modes and offer code protec tion. These

features are:

• Oscillator Selection (Section 4.0)

• RESET (Section 5.0)

• Power-On Reset (Section 5.1)

• Device Re se t Timer (Section 5.2)

• Watchdog Timer (WDT) (Section 9.2)

• SLEEP (Section 9.3)

• Code protection (Section 9.4)

• ID locations (Section 9.5)

The PIC16C5X Family has a Watchdog Timer which

can be shut off only through configuration bit WDTE. It

runs off of its own RC oscillator for added reliability.

There is an 18 ms delay provided by the Device Reset

Timer (DRT), intended to keep the chip in RESET until

the crystal oscillator is stable. With this timer on-chip,

most applications need no external RESET circuitry.

The SLEEP mode is designed to offer a very low cur-

rent Power-down mode. The user can wake up from

SLEEP through external RESET or through a Watch-

dog Timer time-out. Several oscillator options are also

made available to allow the part to fit the application.

The RC oscillator option saves system cost while the

LP crystal option saves power. A set of configuration

bits are used to select various options.

PIC16C5X

DS30453E-page 44 Preliminary  1997-2013 Microchip Technology Inc.

9.1 Configuration Bits

Configuration bits can be programmed to select various

device configurations. Two bits are for the selection of

the oscillator type and one bit is the Watchdog Timer

enable bit. Nine bits are code protection bits for the

PIC16C54A, PIC16CR54A, PIC16C54C,

PIC16CR54C, PIC16C55A, PIC16C56A,

PIC16CR56A, PIC16C57C, PIC16CR57C,

PIC16C58B , and PIC 16CR58B dev ices (Registe r 9-1).

One bit is for code protection for the PIC16C54,

PIC16C55, PIC16C56 and PIC16C57 devices

(Register 9-2).

QTP or R OM de vic es ha ve the osci lla tor c onfig ur ation

programmed at the factory and these parts are tested

accordingly (see "Product Identification System" dia-

grams in the back of this data sheet).

CR56A/C57C/CR57C/C58B/CR58B

CP CP CP CP CP CP CP CP CP WDTE FOSC1 FOSC0

bit 11 bit 0

bit 11-3: CP: Code Protection Bit

1 = Code protection off

0 = Code protection on

bit 2: WDTE: Watchdog timer enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator Selection Bit

00 = LP oscil la tor

01 = XT oscillator

10 = HS oscillator

11 = RC oscillator

Note 1: Refer to the PIC16C5X Programming Specification (Literature Number DS30190) to determine how to

access the co nfiguration word.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 45

PIC16C5X

———————— CP WDTE FOSC1 FOSC0

bit 11 bit 0

bit 11-4: Unimplemented: Read as ‘0’

bit 3: CP: Code protection bit.

1 = Code protection off

0 = Code protection on

bit 2: WDTE: Watchdog timer enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator selection b its(2)

00 = LP oscillator

01 = XT oscillator

10 = HS oscillator

11 = RC oscil lator

Note 1: Refer to the PIC16C5X Programming Specifications (Literature Number DS30190) to determine how to

access the configur ation word.

2: PIC16LV54A supports XT, RC and LP oscillator only.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown

PIC16C5X

DS30453E-page 46 Preliminary  1997-2013 Microchip Technology Inc.

9.2 Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip

RC osc illato r whi ch doe s not req uire an y exte rnal co m-

ponents. This RC oscillator is separate from the RC

oscillator of the OSC1/CLKIN pin. That means that the

WDT wi ll run e ven i f the cloc k on the O SC1/CL KIN a nd

OSC2/CLKOUT pins have been stopped, for example,

by execution of a SLEEP instruction. During normal

operation or SLEEP, a WDT Reset or Wake-up Reset

generates a device RESET.

The TO bit (ST A TUS<4>) will be cleared upon a W atch-

dog Timer R eset (Section 6.3).

The WDT can be permanently disabled by program-

ming the configuration bit WDTE as a '0' (Section 9.1).

Refer to the PIC16C5X Programming Specifications

(Literature Number DS30190) to determine how to

acces s the co nfig ura tion word.

9.2.1 WDT PERIOD

An 8-bit counter is available as a prescaler for the

Timer0 module (Sec tion 8.2), or as a po stscaler for the

Watchdog Timer (WDT), respectively. For simplicity,

this c ou nte r i s bei ng referred to as “pre sc ale r” t hrou gh-

out this data sheet. Note that the prescaler may be

used by either the Timer0 module or the WDT, but not

both. Thus, a prescaler assignment for the Timer0

module means that there is no prescaler for the WDT,

and vice-versa.

The PSA and PS<2:0> bits (OPTION<3:0>) determine

prescaler assignment and prescale ratio (Section 6.4).

The WDT has a nominal ti me -out peri od of 18 ms (with

no prescaler). If a longer time-out period is desired, a

prescaler with a division ratio of up to 1:128 can be

assigned to the WDT (under software control) by writ-

ing to the OPTION register. Thus, time-out a period of

a nominal 2.3 seconds can be realized. Thes e periods

vary with temperature, VDD and part-to-part process

variations (see Device Characterization).

Under wo rst cas e cond itions (VDD = M in., Temperature

= Max., WDT prescaler = 1:128), it may take several

seconds before a WDT time-out occurs.

9.2.2 WDT PROGRAMMING

CONSIDERATIONS

The CLRWDT instruction clears the WDT and the pres-

caler, if assigned to the WDT, and prevents it from tim-

ing out and generating a device RESET.

The SLEEP instruction RESETS the WDT and the pres-

caler, if assigned to the WDT. This gives the maximum

SLEEP time before a WDT Wake-up Reset.

FIGURE 9-1: W ATCHDOG TIMER BLOCK DIAGRAM

TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

Power-On

Reset

Value on

MCLR and

WDT Reset

N/A OPTION — — Tosc Tose PSA PS2 PS1 PS0 --11 1111 --11 1111

Legend: u = unchanged, - = unimplemented, read as '0'. Shaded cells not used by Watchdog Timer.

From TMR0 Clock Source

To TMR0

WDT Enable

EPROM Bi t

PSA

WDT

Time-out

PS2:PS0

PSA

MUX

8 - to - 1 MUX

Watchdog

Timer

Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the

OPTION r e gister.

Prescaler

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 47

PIC16C5X

9.3 Power-Down Mode (SLEEP)

A device may be powered down (SLEEP) and later

powered up (Wake-up from SLEEP).

9.3.1 SLEEP

The Power-down mode is entered by executing a

SLEEP instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the TO bit (STATUS<4>) is set, the PD

bit (STATUS<3>) is cleared and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, driving low, or hi-impedance).

It should be noted that a RESET generated by a WDT

time-out does not drive the MCLR/VPP pin low.

For lowest current consumption while powered down,

the T0CKI input should be at VDD or VSS and the

MCLR/VPP pin must be at a logic high level

(MCLR = VIH).

9.3.2 WAKE-UP FROM SLEEP

The device can wake up from SLEEP through one of

the following events:

1. An external RESET input on MCLR/VPP pin.

2. A Watchdog Timer Time-out Reset (if WDT was

enabled).

Both of these events cause a device RESET. The TO

and PD bits can be used to determine the cause of

device RESET. The TO bit is cleared if a WDT time-

out occ urred (an d ca us ed wake-up). The PD bit, whic h

is set on power-up, is cleared when SLEEP is invoked.

The WDT is cleared when the device wakes from

SLEEP, regardless of the wake-up source.

9.4 Program Verification/Code

Protection

If the code protection bit(s) have not been pro-

grammed, the on-chip program memory can be read

out for verification purposes.

9.5 ID Locations

Four memory locations are designated as ID locations

where the user can store checksum or other code-iden-

tification numbers. These locations are not accessible

during normal execution but are readable and writable

during program/verify.

Use on ly the lower 4 bits of the ID locati ons and al ways

program the upper 8 bits as '1's.

Note: Microchip does not recommend code pro-

tecting w ind ow ed devic es .

Note: Microchip will assign a unique pattern

number for QTP and SQTP requests and

for ROM devices. This pattern number will

be unique and traceable to the submitted

code.

PIC16C5X

DS30453E-page 48 Preliminary  1997-2013 Microchip Technology Inc.

NOTES:

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 49

PIC16C5X

10.0 INSTRUCTION SET SUMMARY

Each PIC16C5X instr uction is a 12-bit word divided into

an O PCODE, wh ich spec ifies th e instru ction ty pe and

one or more operands which further sp ec ify the ope ra-

tion of the instruction. The PIC16C5X instruction set

summary in Table 10-2 groups the instructions into

byte-ori ente d, bit-oriented, and literal and control op er-

ations. Table 10-1 shows the opco de fi eld descri ptions .

For byte-oriented i nst ruc tio ns, 'f' rep r es ents a file reg-

ister designator and 'd' represents a destination desig-

nator. The file register designator is used to specify

which one of the 32 file registers in that bank is to be

used by the instruction.

The desti nation designator specifies where the resul t of

the operation is to be placed. If 'd' is '0', the result is

placed in the W register. If 'd' is '1', the result is placed

in the file register specified in the instruction.

For bit-oriented instructions, 'b' represents a bit field

designator which sel ec t s the number of th e bi t a ffected

by the operation, while 'f' represents the number of the

file in which the bit is located.

For literal and control operations, 'k' represents an

8 or 9-bit constant or literal value.

TABLE 10-1: OPCODE FIELD

DESCRIPTIONS

All instructions are executed within one single instruc-

tion cycle, unless a conditional test is true or the pro-

gram counter is changed as a result of an instruction.

In this c ase, the execu tion t a kes two i nstruc tion c ycles.

One in struction cycle consist s of f our oscil lator p eriods.

Thus, for an oscillator frequency of 4 MHz, the normal

instruction execution time would be 1 s. If a condi-

tional test is true o r th e program counte r is changed as

a resu lt o f an ins tru cti on, the instructio n exec uti on time

would be 2 s.

Figure 10-1 shows the three general formats that the

instructions can have. All examples in the figure use

the following format to represent a hexadecimal num-

ber: 0xhhh

where 'h' signifies a hexadecimal digit.

FIGURE 10-1: GENERAL FORMAT FOR

INSTRUCTIONS

Field Description

fRegister file address (0x00 to 0x1F)

WWorking regist er (a ccumulato r)

bBit addres s w ith in an 8- bi t file re gi st er

kLiteral fiel d, con stan t da ta or lab el

xDon't care location (= 0 or 1)

The assembler will generate code with x = 0.

It is the reco m mended form of use f or com -

patibility with all Microchip software tools.

dDestination select;

d = 0 (store result in W)

d = 1 (store result in file register 'f')

Default is d = 1

label Label name

TOS Top of Stack

PC Program Counter

WDT Watchdog Timer Counter

TO Time-out bit

PD Power-do w n bit

dest Destination, either the W register or the

specifi ed r egi st er file locatio n

[ ] Options

( ) Contents

Assigne d to

< > Register bit field

In the set o f

italics U se r de fined term (font i s cou rier )

Byte-oriented file register operations

11 6 5 4 0

d = 0 for destination W

OP C O D E d f (FILE #)

d = 1 for destination f

f = 5-bit file register address

Bit-oriented file register operations

11 8 7 5 4 0

OP C O D E b (BIT # ) f (FILE #)

b = 3-bit bit address

f = 5-bit file register address

Literal and control operations (except GOTO)

11 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

Literal and control operations - GOTO instruction

11 9 8 0

OPCODE k (l i te ra l )

k = 9-bit immediate value

PIC16C5X

DS30453E-page 50 Preliminary  1997-2013 Microchip Technology Inc.

TABLE 10-2: INSTRUCTION SET SUMMARY

Mnemonic,

Operands Description Cycles 12-Bit Opcode Status

Affected Notes

MSb LSb

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f,d

–

f, d

–

f, d

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Incr eme nt f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate left f through Carry

Rotate right f through Carry

Subtract W from f

Swap f

Exclusive OR W with f

1(2)

0001

0000

0010

0000

0010

0011

0001

0010

0000

0011

0000

0011

0001

11df

01df

011f

0100

01df

11df

10df

11df

00df

001f

0000

01df

00df

10df

ffff

0000

ffff

0000

ffff

C,DC,Z

None

C,DC,Z

None

1,2,4

2,4

1,4

2,4

1,2,4

2,4

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

0100

0101

0110

0111

bbbf

ffff

None

2,4

LITERAL AND CONTROL OPERATIONS

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

OPTION

RETLW

SLEEP

TRIS

XORLW

–

AND literal with W

Call subroutine

Clear Watchdog Timer

Unconditional branch

Inclusive OR Literal with W

Move Literal to W

Load OPTION register

Return, place Literal in W

Go into standby mode

Load TRIS register

Exclusive OR Literal to W

1110

1001

0000

101k

1101

1100

0000

1000

0000

1111

kkkk

0000

kkkk

0000

kkkk

0000

kkkk

0100

kkkk

0010

kkkk

0011

0fff

kkkk

None

TO, PD

None

TO, PD

None

Note 1: The 9th bi t of the program counter will be forced to a '0' by any instruction that writes to the PC exce pt for

GOTO (see Section 6.5 for more on program counter).

2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used w ill be that

value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and

is driven low by an external device, the data will be written back with a '0'.

3: The instruc tion TRIS f, where f = 5, 6 or 7 c auses t he conten ts of the W reg ister to be writte n to t he tris tat e

latches of PORTA, B or C respectively. A '1' forces the pin to a hi-impedance state and disables the output

buffers.

4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be

cleared (if assigned to TMR0).

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 51

PIC16C5X

ADDWF Add W and f

Syntax: [ label ] ADDWF f,d

Operands: 0  f  31

d 

Operation: (W) + (f)  (des t)

Status Affected: C, DC, Z

Encoding: 0001 11df ffff

Description: Add the contents of the W register

and register 'f'. If 'd' is 0 the result

is stored in the W register. If 'd' is

'1' the result is stored back in

Words: 1

Cycles: 1

Example: ADDWF TEMP_REG, 0

Before Instruction

W =0x17

TEMP_REG = 0xC2

After Instruction

W=0xD9

TEMP_REG = 0xC2

ANDLW AND literal with W

Syntax: [ label ] ANDLW k

Operands: 0  k  255

Operation: (W).AND. (k)  (W)

Status Affected: Z

Encoding: 1110 kkkk kkkk

Description: The contents of the W register are

AND’ed with the eig ht-b it li tera l 'k'.

The result is pla ce d in th e W regi s-

ter.

Words: 1

Cycles: 1

Example: ANDLW H'5F'

Before Instruction

W=0xA3

After Instruction

W=0x03

ANDWF AND W with f

Syntax: [ label ] ANDWF f,d

Operands: 0  f  31

d 

Operation: (W) .AND. (f)  (dest)

Status Af fe cted: Z

Encoding: 0001 01df ffff

Description: The contents of the W register are

AND’ed with register 'f'. If 'd' is 0

the result is stored in the W regis-

ter. If 'd' is '1' the result is stored

back in register 'f'.

Words: 1

Cycles: 1

Example: ANDWF TEMP_REG, 1

Before Instruc tio n

W=0x17

TEMP_REG = 0xC2

After Instruction

W =0x17

TEMP_REG = 0x02

BCF Bit Clear f

Syntax: [ label ] BCF f,b

Operands: 0  f  31

0  b  7

Operation: 0  (f<b>)

Status Af fe cted: None

Encoding: 0100 bbbf ffff

Description: Bit 'b' in register 'f' is cleared.

Words: 1

Cycles: 1

Example: BCF FLAG_REG, 7

Before Instruction

FLAG_REG = 0xC7

After Instruction

FLAG_REG = 0x47

PIC16C5X

DS30453E-page 52 Preliminary  1997-2013 Microchip Technology Inc.

BSF Bit Set f

Syntax: [ label ] BSF f,b

Operands: 0  f  31

0  b  7

Operation: 1  (f<b>)

Status Affected: None

Encoding: 0101 bbbf ffff

Description: Bit 'b' in register 'f' is set.

Words: 1

Cycles: 1

Example: BSF FLAG_REG, 7

Before Instruction

FLAG_REG = 0x0A

After Instruction

FLAG_REG = 0x8A

BTFSC Bit Test f, Skip if Clear

Syntax: [ label ] BTFSC f,b

Operands: 0  f  31

0  b  7

Operation: skip if (f<b>) = 0

Status Affected: None

Encoding: 0110 bbbf ffff

Description: If bit 'b' in register 'f' is 0 then the

next instruction is skipped.

If bit 'b' is 0 then the next instruc-

tion fetched during the current

instruction execution is discarded,

and a NOP is executed in stead,

making this a 2-cycle instruction.

Words: 1

Cycles: 1(2)

Example: HERE

FALSE

TRUE

BTFSC

GOTO

•

FLAG,1

PROCESS_CODE

Before Instruction

PC = address (HERE)

After Instruction

if FLAG<1> = 0,

PC = address (TRUE);

if FLAG<1> = 1,

PC = address(FALSE)

BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BTFSS f,b

Operands: 0  f  31

0  b < 7

Operation: skip if (f<b>) = 1

Status Af fe cted: None

Encoding: 0111 bbbf ffff

Description: If bit 'b' in register 'f' is '1' then the

next instruction is skipped.

If bit 'b' is '1', then the next instruc-

tion fetched during the current

instruction execution, is discarded

and a NOP is executed instead,

making this a 2-cycle instruction.

Words: 1

Cycles: 1(2)

Example: HERE BTFSS FLAG,1

FALSE GOTO PROCESS_CODE

TRUE 





Before Instruction

PC = address (HERE)

After Instruc tio n

If FLAG<1> = 0,

PC = address (FALSE);

if FLAG<1> = 1,

PC = address (TRUE)

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 53

PIC16C5X

CALL Subroutine Call

Syntax: [ label ] CALL k

Operands: 0  k  255

Operation: (PC) + 1 TOS;

k  PC<7:0>;

(STATUS<6:5>)  PC<10:9>;

0  PC<8>

Status Affected: None

Encoding: 1001 kkkk kkkk

Description: Subroutine call. Firs t, return

address (PC+1) is pushed onto th e

stack. The eight bit immediate

address is loaded into PC bits

<7:0>. The upper bits PC<10:9>

are loaded from STATUS<6:5>,

PC<8> is cleared. CALL is a two-

cycle instr uction.

Words: 1

Cycles: 2

Example: HERE CALL THERE

Before In struction

PC = address (HERE)

After Instruction

PC = address (THERE)

TOS = address (HERE + 1)

CLRF Clear f

Syntax: [ label ] CLRF f

Operands: 0  f  31

Operation: 00h  (f);

1  Z

Status Affected: Z

Encoding: 0000 011f ffff

Description: The contents of register 'f' are

cleared and the Z bit is set.

Words: 1

Cycles: 1

Example: CLRF FLAG_REG

Before Instruction

FLAG_REG = 0x5A

After Instruc tio n

FLAG_REG = 0x00

Z=1

CLRW Clear W

Syntax: [ label ] CLRW

Operands: None

Operation: 00h  (W);

1  Z

Status Af fe cted: Z

Encoding: 0000 0100 0000

Description: The W register is cleared. Zero bit

(Z) is set.

Words: 1

Cycles: 1

Example: CLRW

Before Instruction

W=0x5A

After Instruc tio n

W=0x00

Z=1

CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT

Operands: None

Operation: 00h  WDT;

0  WDT prescaler (if assigned);

1  TO;

1  PD

Status Af fe cted: TO, PD

Encoding: 0000 0000 0100

Description: The CLRWDT instruction resets the

WDT. It also reset s the prescaler, if

the prescaler is assigned to the

WDT and not Timer0. Status bits

TO and PD are set.

Words: 1

Cycles: 1

Example: CLRWDT

Before Instruction

WDT counter = ?

After Instruction

WDT counter = 0x00

WDT presca ler = 0

TO =1

PD =1

PIC16C5X

DS30453E-page 54 Preliminary  1997-2013 Microchip Technology Inc.

COMF Complement f

Syntax: [ label ] COMF f,d

Operands: 0  f  31

d  [0,1]

Operation: (f)  (dest)

Status Affected: Z

Encoding: 0010 01df ffff

Description: The contents of register 'f' are

comple me nte d. If 'd ' is 0 the res ult

is store d in the W regi ster . If ' d' is 1

the result is stored back in

Words: 1

Cycles: 1

Example: COMF REG1,0

Before Instruction

REG1 = 0x13

After Instruction

REG1 = 0x13

W=0xEC

DECF Decrement f

Syntax: [ label ] DECF f,d

Operands: 0  f  31

d  [0,1]

Operation: (f) – 1  (dest)

Status Affected: Z

Encoding: 0000 11df ffff

Desc ription : Decrem ent reg ister 'f' . If 'd' is 0 the

result is stored in the W register. If

'd' is 1 the result is stored back in

Words: 1

Cycles: 1

Example: DECF CNT, 1

Before Instruction

CNT = 0x01

Z=0

After Instruction

CNT = 0x00

Z=1

DECFSZ Decrement f, Skip if 0

Syntax: [ label ] DECFSZ f,d

Operands: 0  f  31

d  [0,1]

Operati on: (f) – 1  d; skip if result = 0

Status Af fe cted: None

Encoding: 0010 11df ffff

Descripti on: The con ten ts of register 'f' are dec-

remented. If 'd' is 0 the result is

placed in the W register. If 'd' is 1

the result is placed back in

If the resu lt is 0, the next instruc-

tion, which is already fetched, is

discard ed and a NOP is executed

instead making it a two-cycle

instruction.

Words: 1

Cycles: 1(2)

Example: HERE DECFSZ CNT, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address(HERE)

After Instruction

CNT = CNT - 1;

if CNT = 0,

PC = address (CONTINUE);

if CNT 0,

PC = address (HERE+1)

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 55

PIC16C5X

GOTO Unconditional Branch

Syntax: [ label ] GOTO k

Operands: 0  k  511

Operation: k  PC<8:0>;

STATUS<6:5>  PC<10:9>

Status Affected: None

Encoding: 101k kkkk kkkk

Description: GOTO is an unconditi onal bran ch .

The 9-bit immediate value is

loaded into PC bits <8:0>. The

upper bits of PC are loaded from

STATUS<6:5>. GOTO is a two-

cycle instr uction.

Words: 1

Cycles: 2

Example: GOTO THERE

After Instruc tio n

PC = address (THERE)

INCF Increment f

Syntax: [ label ] INCF f,d

Operands: 0  f  31

d  [0,1]

Operati on: (f) + 1  (dest)

Status Affected: Z

Encoding: 0010 10df ffff

Description: The contents of register 'f' are

incremented. If 'd' is 0 the result is

placed in the W register. If 'd' is 1

the result is placed back in

Words: 1

Cycles: 1

Example: INCF CNT, 1

Before Instruction

CNT = 0xFF

Z=0

After Instruction

CNT = 0x00

Z=1

INCFSZ Increment f, Skip if 0

Syntax: [ label ] INCFSZ f,d

Operands: 0  f  31

d  [0,1]

Operati on: (f) + 1  (dest), skip if result = 0

Status Af fe cted: None

Encoding: 0011 11df ffff

Description: The contents of register 'f' ar e

incremen ted. If 'd' is 0 the result is

placed in the W register. If 'd' is 1

the result is placed back in

If the result is 0, then the next

instruction, which is already

fetched, is discarded and a NOP is

executed instead making it a two-

cycle instruction.

Words: 1

Cycles: 1(2)

Example: HERE INCFSZ CNT, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address (HERE)

After Instruction

CNT = CNT + 1;

if CNT = 0,

PC = address (CONTINUE);

if CNT 0,

PC = address (HERE +1)

PIC16C5X

DS30453E-page 56 Preliminary  1997-2013 Microchip Technology Inc.

IORLW Inclusive OR literal with W

Syntax: [ label ] IORLW k

Operands: 0  k  255

Operation: (W) .OR. (k)  (W)

Status Affected: Z

Encoding: 1101 kkkk kkkk

Description: The contents of the W register are

OR’ed with the eight bit literal 'k'.

The result is pla ce d in th e W regi s-

ter.

Words: 1

Cycles: 1

Example: IORLW 0x35

Before Instruction

W= 0x9A

After Instruction

W= 0xBF

Z=0

IORWF Inclusive OR W with f

Syntax: [ label ] IORWF f,d

Operands: 0  f  31

d  [0,1]

Operation: (W).OR. (f)  (dest)

Status Affected: Z

Encoding: 0001 00df ffff

Description: I nclusive OR the W register with

placed in the W register. If 'd' is 1

the result is placed back in

Words: 1

Cycles: 1

Example: IORWF RESULT, 0

Before In struction

RESULT = 0x13

W = 0x91

After Instruction

RESULT = 0x13

W = 0x93

Z=0

MOVF Move f

Syntax: [ label ] MOVF f,d

Operands: 0  f  31

d  [0,1]

Operation: (f)  (dest)

Status Af fe cted: Z

Encoding: 0010 00df ffff

Description: The contents of registe r 'f' is

moved to destination 'd'. If 'd' is 0,

destination is the W register. If 'd'

is 1, the destination is file

file register since status flag Z is

affected.

Words: 1

Cycles: 1

Example: MOVF FSR, 0

After Instruction

W = value in FSR register

MOVLW Move Literal to W

Syntax: [ label ] MOVLW k

Operands: 0  k  255

Operation: k  (W)

Status Af fe cted: None

Encoding: 1100 kkkk kkkk

Descr iption: The eigh t bit literal 'k' is loaded int o

the W register.

Words: 1

Cycles: 1

Example: MOVLW 0x5A

After Instruction

W = 0x5A

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 57

PIC16C5X

MOVWF Move W to f

Syntax: [ label ] MOVWF f

Operands: 0  f  31

Operation: (W)  (f)

Status Affected: None

Encoding: 0000 001f ffff

Description: Move data from the W register to

Words: 1

Cycles: 1

Example: MOVWF TEMP_REG

Before Instruction

TEMP_REG = 0xFF

W = 0x4F

After Instruc tio n

TEMP_REG = 0x4F

W = 0x4F

NOP No Operation

Syntax: [ label ] NOP

Operands: None

Operati on: No operation

Status Affected: None

Encoding: 0000 0000 0000

Desc ript ion : No operation.

Words: 1

Cycles: 1

Example: NOP

OPTION Load OPTION Register

Syntax: [ label ] OPTION

Operands: None

Operation: (W)  OPTION

Status Af fe cted: None

Encoding: 0000 0000 0010

Description: The content of the W register is

loaded into the OPTION regi ster.

Words: 1

Cycles: 1

Example OPTION

Before Instruction

W = 0x07

After Ins truction

OPTION = 0x07

RETLW Return with Literal in W

Syntax: [ label ] RETLW k

Operands: 0  k  255

Operation: k  (W);

TOS  PC

Status Af fe cted: None

Encoding: 1000 kkkk kkkk

Description: The W register is loaded with the

eight bit literal 'k'. The program

counter is loaded from the top of

the stack (the return address). This

is a two-cy cle instruction.

Words: 1

Cycles: 2

Example:

TABLE

CALL TABLE ;W contains

;table offset

;value.

• ;W now has table

• ;value.

•

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

•

RETLW kn ; End of table

Before Instruc tio n

W=0x07

After Instruction

W = value of k8

PIC16C5X

DS30453E-page 58 Preliminary  1997-2013 Microchip Technology Inc.

RLF Rotate Left f through Carry

Syntax: [ label ] RLF f,d

Operands: 0  f  31

d  [0,1]

Operation: See description below

Status Affected: C

Encoding: 0011 01df ffff

Description: The contents of register 'f' are

rotated one bit to the left through

the Carry Fla g (STATUS<0>). If 'd'

is 0 the result is placed in the W

stored back in

Words: 1

Cycles: 1

Example: RLF REG1,0

Before Instruction

REG1 = 1110 0110

C=0

After Instruction

REG1 = 1110 0110

W=1100 1100

C=1

Cregister 'f'

RRF Rotate Right f through Carry

Syntax: [ label ] RRF f,d

Operands: 0  f  31

d  [0,1]

Operation: See description below

Status Af fe cted: C

Encoding: 0011 00df ffff

Description: The contents of register 'f' ar e

rotated one bit to the right through

the Carry Fla g (STATUS<0>). If 'd'

is 0 the result is placed in the W

placed bac k in

Words: 1

Cycles: 1

Example: RRF REG1,0

Before Instruction

REG1 = 1110 0110

C=0

After Instruction

REG1 = 1110 0110

W=0111 0011

C=0

SLEEP Enter SLEEP Mode

Syntax: [label] SLEEP

Operands: None

Operation: 00h  WDT;

0  WDT prescaler; if assigned

1  TO;

0  PD

Status Af fe cted: TO, PD

Encoding: 0000 0000 0011

Descr iption: T ime-out st atus bit (TO) is set. The

power-down status bit (PD) is

cleared. The WDT and its pres-

caler are cleared.

The processor is put into SLEEP

mode with the oscillator stopped.

See section on SLEEP for more

details.

Words: 1

Cycles: 1

Example: SLEEP

Cregister 'f'

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 59

PIC16C5X

SUBWF Subtract W from f

Syntax: [label] SUBWF f,d

Operands: 0 f 31

d  [0,1]

Operation: (f) – (W) dest)

Status Affected: C, DC, Z

Encoding: 0000 10df ffff

Descript ion: Subtract (2’ s complement m ethod)

the W regi ster from reg ister 'f'. If 'd'

is 0 the result is stored in the W

stored back in register 'f'.

Words: 1

Cycles: 1

Example 1:SUBWF REG1, 1

Before Instruction

REG1 = 3

W=2

C=?

After Instruction

REG1 = 1

W=2

C = 1 ; result is positive

Example 2:

Before Instruction

REG1 = 2

W=2

C=?

After Instruction

REG1 = 0

W=2

C = 1 ; result is zero

Example 3:

Before Instruction

REG1 = 1

W=2

C=?

After Instruction

REG1 = 0xFF

W=2

C = 0 ; result is negativ e

SWAPF Swap Nibbles in f

Syntax: [ label ] SWAPF f,d

Operands: 0  f  31

d  [0,1]

Operation: (f<3:0>)  (dest<7:4>);

(f<7:4>)  (dest<3:0>)

Status Af fe cted: None

Encoding: 0011 10df ffff

Description: The upper and lower nibbles of

the resul t is p laced in W reg ister. If

'd' is 1 the result is placed in

Words: 1

Cycles: 1

Example SWAPF REG1, 0

Before Instruc tio n

REG1 = 0xA5

After Instruction

REG1 = 0xA5

W=0x5A

TRIS Load TRIS Register

Syntax: [ label ] TRIS f

Operands: f = 5, 6 or 7

Operation: (W)  TRIS register f

Status Af fe cted: None

Encoding: 0000 0000 0fff

Description: TRIS register 'f' (f = 5, 6, or 7) is

loaded with the contents of the W

Words: 1

Cycles: 1

Example TRIS PORTB

Before Instruction

W=0xA5

After Instruc tio n

TRISB = 0xA5

PIC16C5X

DS30453E-page 60 Preliminary  1997-2013 Microchip Technology Inc.

XORLW Exclusive OR literal with W

Syntax: [label]XORLW k

Operands: 0 k 255

Operation: (W) .XOR. k W)

Status Affected: Z

Encoding: 1111 kkkk kkkk

Description: The contents of the W register are

XOR’ed with the eigh t bit litera l 'k '.

The result is pla ce d in th e W regi s-

ter.

Words: 1

Cycles: 1

Example: XORLW 0xAF

Before Instruction

W=0xB5

After Instruction

W=0x1A

XORWF Exclusive OR W with f

Syntax: [ label ] XORWF f,d

Operands: 0  f  31

d  [0,1]

Operation: (W) .XOR. (f) dest)

Status Affected: Z

Encoding: 0001 10df ffff

Description: Exclusive OR the contents of the

W regist er wi th regis ter 'f '. If 'd' i s 0

the result is stored in the W regis-

ter. If 'd' is 1 the result is stored

back in register ' f'.

Words: 1

Cycles: 1

Example XORWF REG,1

Before Instruction

REG = 0xAF

W=0xB5

After Instruction

REG = 0x1A

W=0xB5

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 61

PIC16C5X

11.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers are supported with a full

range of hardware and software development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Assemblers/Compilers/Linkers

- MPASMTM Assembler

- MPLAB C17 and MPLAB C18 C Compilers

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

• Simulators

- MPLAB SIM Software Simulator

•Emulators

- MPLAB ICE 2000 In-Circuit Emulator

- ICEPIC™ In-Circuit Emulator

• In-Circuit Debugger

- MPLAB ICD

• Device Progra mmers

-PRO MATE

® II Universal D evi ce Programm er

- PICSTART® Plus Entry-Level Development

Programmer

• Low Cost Demonstration Boards

- PICDEMTM 1 Demonstration Board

- PICDEM 2 Demonstration Board

- PICDEM 3 Demons trati on Boar d

- PICDEM 17 Demonstration Board

-K

EELOQ® Demonstration Board

11.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8-bit microcon-

troller market. The MPLAB IDE is a Windows®-based

application that contains:

• An interface to debugging tools

- simulator

- programmer (sold sep arately )

- emulator (sold separately)

- in-circuit debugger (sold separately)

• A full-featured editor

• A project manager

• Customizable toolbar and key mapping

• A status bar

• On-line help

The MPLAB IDE allows you to:

• Edit your source files (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools (auto-

matically updates all project information)

• Debug us ing :

- source files

- abs olute listing file

- machine code

The ability to use MPLAB IDE with multiple debugging

tools allows users to easily switch from the cost-

effective simulator to a full-featured emulator with

minimal retraining.

11.2 MPASM Assembler

The MPASM assembler is a full-featured universal

macro assembl er for all PIC MCUs.

The MPASM assembler has a command line interface

and a Windows shell. It can be used as a stand-alone

application on a Windows 3.x or greater system, or it

can be us ed through MPLAB ID E. The MP ASM assem-

bler generates relocatable object files for the MPLINK

object linker, Intel® standard HEX files, MAP files to

detail memory usage and symbol reference, an abso-

lute LST file that contains source lines and generated

machine code, and a COD file for debugging.

The MPASM assembler features include:

• Integration into MPLAB IDE projects .

• User-defined macros to streamline assembly

code.

• Condit ion al as sem bl y for mult i-p urpo se sourc e

files.

• Directives that allow complete control over the

assembly process.

11.3 MPLAB C17 and MPLAB C18

C Compilers

The MPLAB C1 7 and MP LAB C18 Code De vel op me nt

Systems are complete ANSI ‘C’ compilers for

Microchip’s PIC17CXXX and PIC18CXXX family of

microc ontrollers, re spectively. These compilers provide

powerful integration capabilities and ease of use not

found with other compilers.

For easier source level debugging, the compilers pro-

vide symbol information that is compatible with the

MPLAB IDE memory display.

PIC16C5X

DS30453E-page 62 Preliminary  1997-2013 Microchip Technology Inc.

11.4 MPLINK Object Linker/

MPLIB Object Librari an

The MPLINK object linker combines relocatable

objects created by the MPASM assembler and the

MPLAB C17 and MPLAB C18 C comp ilers. It can also

link relocatable objects from pre-compiled libraries,

using directives from a linker script.

The MPLIB object librarian is a librarian for pre-

compiled code to be used with the MPLINK object

linker. When a routine from a library is called from

another source file, only the modules that contain that

routine w ill be linked in with the ap plicatio n. This allo ws

large libraries to be used efficiently in many different

applications. The MPLIB object librarian manages the

creation and modification of library files.

The MPLIN K object linker features include:

• Integration with MPASM assembler and MPLAB

C17 and MPLAB C18 C compilers.

• Allows all m emory areas to be defin ed as sections

to provide l ink -time flex ibi lity.

The MPLIB object librarian features include:

• Easier linking because single libraries can be

included instead of many smaller files.

• Helps keep code maintainable by grouping

related modules together.

• Allows libraries to be created and modules to be

added, listed, replaced, deleted or extracted.

11.5 MPLAB SIM Software Simulator

The MPL AB SIM sof tware sim ulator allow s code de vel-

opment in a PC-hosted environment by simulating the

PIC s eri es m icroc ont roll ers on a n in stru cti on level . On

any given instruction, the data areas can be examined

or modified and stimuli can be applied from a file, or

user-defined key press, to any of the pins. The execu-

tion can be performed in single step, execute until

break, or trace mode.

The MPLAB SIM simulator fully supports symbolic debug-

ging using the MPLAB C17 and the MPLAB C18 C com-

pilers and the MP ASM assembler. The software simulator

offers the flexibility to develop and debug code outside of

the laborat ory envir onment, making it an excellent mu lti-

project software development tool.

11.6 MPLAB ICE High Performance

Universal In-Circuit Emulator with

MPLAB IDE

The MPLAB ICE universal in-circuit emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PIC micro-

controllers (MCUs). Sof tware control of the MPLAB ICE

in-circu it emulator is provided by the MPLAB Integrated

Developm en t Environment (IDE), which al low s edi tin g,

building, downloading and source debugging from a

single environment.

The MPLAB ICE 2000 is a full-featured emulator sys-

tem with enhanced trace, trigger and data monitoring

featur es. Interchangea ble processo r modules al low the

system to be easily reconfigured for emulation of differ-

ent processors. The universal architecture of the

MPLAB ICE in-circuit emulator allows expansion to

support new PIC micro co ntrol le rs.

The MPLAB ICE in-circuit emulator system has been

designed as a real-time emulation system, with

advanced features that are generally found on more

expensive development tools. The PC platform and

Microsoft® Windows environment were chosen to best

make these features available to you, the end user.

11.7 ICEPIC In-Circ ui t Em u l a to r

The ICEPIC low cost, in-circuit emulator is a solution

for the Microchip Technology PIC16C5X, PIC16C6X,

PIC16C7X and PIC16CXXX families of 8-bit One-

Time-Programmable (OTP) microcontrollers. The mod-

ular sy stem can su pport d ifferen t subset s of PIC16 C5X

or PIC16CXXX products through the use of inter-

changeable personality modules, or daughter boards.

The emulator is capable of emulating without target

applic atio n circ ui try bei ng pres en t.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 63

PIC16C5X

11.8 MPLAB ICD In-Circuit Debugger

Microc hip's In-Circu it Debugger , M PLAB ICD, is a pow-

erful, low cost, run-time development tool. This tool is

based on the FLASH PIC MCUs and can be used to

develop for this and other PIC microcontrollers. The

MPLAB ICD utilizes the in-circuit debugging capability

built into the FLASH devices. This feature, along with

Microchip's In-Circuit Serial ProgrammingTM protocol,

offers cost-effective in-circuit FLASH debugging from

the graphical user interface of the MPLAB Integrated

Devel opm en t Env iron ment. Th is enables a designer to

deve lop and debug s ource c ode b y watchin g variab les,

single-stepping and setting break points. Running at

full speed enables testing hardware in real-time.

11.9 PRO MATE II Universal Device

Programmer

The PRO MATE II universal device programmer is a

full-featured programmer, capable of operating in

Stand-alone mode, as well as PC-hosted mode. The

PRO MATE II device programmer is CE compliant.

The PRO MATE II device programmer has program-

mable VDD and VPP supplies, which allow it to verify

programmed memory at VDD min and VDD max for max-

imum reliability. It has an LCD display for instructions

and error messages, keys to enter commands and a

modular detachable socket assembly to support various

package types. In S tand-alone mode, the PRO MATE II

device programmer can read, verify, or program PIC

devices. It can also set code protection in this mode.

11.10 PICSTART Plus Entry Level

Development Programmer

The PICSTART Plus development programmer is an

easy-to-use, low cost, prototype programmer. It con-

nects to the PC via a COM (RS-232) port. MPLAB

Inte grated D evelopm ent Envir onment software m akes

using the programmer simple and efficient.

The PICSTART Plus development programmer sup-

ports all PIC devices with up to 40 pins. Larger pin

count devices, such as the PIC16C92X and

PIC17C76 X, may be suppor ted with an a dapter socket.

The PICSTART Plus development programmer is CE

compliant.

11.11 PICDEM 1 Low Cost PIC MCU

Demonstration Board

The PICDEM 1 demonstration board is a simple board

which demonstrates the capabilities of several of

Microc hip’ s m icroc ontrol lers. T he mi croco ntrolle rs su p-

ported are: PIC16C5X (PIC16C54 to PIC16C58A),

PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,

PIC17C42, PIC17C43 and PIC17C44. All necessary

hardware and software is included to run basic demo

programs. The user can program the sample microcon-

trollers provided with the PICDEM 1 demonstration

board on a PRO MATE II device programmer, or a

PICSTART Plus development programmer, and easily

test firmware. The user can also connect the

PICDEM 1 demonstration board to the MPLAB ICE in-

circuit emul ator and download th e firmware to the emu-

lator for testing. A prototype area is available for the

user to build some additional hardware and connect it

to the microcontroller socket(s). Some of the features

include an RS-232 interface, a potentiometer for simu-

lated analog input, push button switches and eight

LEDs connected to PORTB.

11.12 PICDEM 2 Low Cost PIC16CXX

Demonstration Board

The PICDEM 2 demonstration board is a simple dem-

onstration board that supports the PIC16C62,

PIC16C64, PIC16C65, PIC16C73 and PIC16C74

microcontrollers. All the necessary hardware and soft-

ware is included to run the basic demonstration pro-

grams. The user can program the sample

microcontrollers provided with the PICDEM 2 demon-

stration board on a PRO MATE II device programmer,

or a PICSTART Plus development programmer, and

easily test firmware . The MPLAB ICE in-circu it emula-

tor may a lso be used with t he PICDEM 2 demonstration

board to test firmware. A prototype area has been pro-

vided to the user for adding additional hardware and

connecting it to the microcontroller socket(s). Some of

the features include a RS-232 interface, push button

switches , a poten tiomet er for simula ted anal og inpu t, a

serial EEPROM to d emonstra te usage o f the I2CTM bus

and separate headers for connection to an LCD

module and a keypad.

PIC16C5X

DS30453E-page 64 Preliminary  1997-2013 Microchip Technology Inc.

11.13 PICDEM 3 Low Cost PIC16CXXX

Demonstration Board

The PICDEM 3 demonstration board is a simple dem-

onstration board that supports the PIC16C923 and

PIC16C924 in the PLCC package. It will also support

future 44-p in PLCC micro controlle rs with an LCD Mo d-

ule. All the necessary hardware and software is

includ ed to r un the basic dem onstrat ion pro grams . The

user can program the sample microcontrollers pro-

vided with the PICDEM 3 demonstration board on a

PRO MATE II device programmer , or a PICST AR T Plus

development programmer with an adapter socket, and

easily test firmware. The MPLAB ICE in-circuit emula-

tor may a lso be used with the PICDEM 3 demonstration

board to test firmware. A prototype area has been pro-

vided t o the use r for ad ding hardwa re and con necting it

to the microcontroller socket(s). Some of the features

include a RS-232 interface, push button switches, a

potentiometer for simulated analog input, a thermistor

and separate headers for connection to an external

LCD module and a keypad. Also provided on the

PICDEM 3 demonstration board is a LCD panel, with 4

commo ns and 1 2 segments, tha t is capable of display-

ing time, temperature and day of the week. The

PICDEM 3 d emons tration board pr ovi des an add itiona l

RS-232 interface and Windows software for showing

the demul tiplexed LC D signals on a PC. A si mple serial

interface allows the user to construct a hardware

demultiplexer for the L CD signals.

11.14 PICDEM 17 Demonstration Board

The P ICDEM 17 de mo ns t r at i on bo a r d is an ev al u ati on

board that demonstrates the capabilities of several

Microchip microcontrollers, including PIC17C752,

PIC17C756A, PIC17C762 and PIC17C766. All neces-

sary hard ware is inc luded to ru n basic d emo progra ms,

which are supplied on a 3.5-inch disk. A programmed

sample is included and the user may erase it and

program it with the other sample programs using the

PRO MATE II device programmer, or the PICSTART

Plus development programmer, and easily debug and

test the sample code. In addition, the PICDEM 17 dem-

onstratio n board supports download ing of programs to

and executing out of external FLASH memory on board.

The PICDEM 17 demonstration board is also usable

with the MPLAB ICE in-circuit emulator, or the

PICMAST ER emulat or and al l of the sample progr ams

can be run and modified using either emulator . Addition-

ally, a generous prototype area is available for user

hardware.

11.15 KEELOQ Evaluation and

Programming Tools

KEELOQ evaluation and programming tools support

Microchip’s HCS Secure Data Products. The HCS eval-

uation kit includes a LCD display to show changing

codes, a decoder to decode transmissions and a pro-

gramming interface to program test transmitters.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 65

PIC16C5X

TABLE 11-1: DEVELOPMENT TOOLS FROM MICROCHIP

PIC12CXXX

PIC14000

PIC16C5X

PIC16C6X

PIC16CXXX

PIC16F62X

PIC16C7X

PIC16C7XX

PIC16C8X

PIC16F8XX

PIC16C9XX

PIC17C4X

PIC17C7XX

PIC18CXX2

PIC18FXXX

24CXX/

25CXX/

93CXX

HCSXXX

MCRFXXX

MCP2510

Soft war e Tools

MPLAB® Integrated

Development E nvironment 

MPLAB® C17 C Comp ile r 

MPLAB® C18 C Comp ile r 

MPASMTM Assembler/

MPLINKTM Obje ct Linke r   

Emulators

MPLAB® ICE In-Circuit Emulator   

** 

ICEPICTM In-Circuit Emulator    

Debugger

MPLAB® ICD In-Circuit

Debugger **

Programmers

PICSTART® Plus Entry Level

Devel opment Programmer   

** 

PRO MATE® II

Universal Device Programmer   

**   

Demo Boards and Eval Kits

PICDEMTM 1 Demonstration

Board 

†

PICDEMTM 2 Demonstration

Board ††

PICDEMTM 3 Demonstration

Board 

PICDEMTM 14A Demonstration

Board 

PICDEMTM 17 Demo nstration

Board 

KEELOQ® Evaluation Kit 

KEELOQ® Transp on d er Kit 

microIDTM Programmer’s Kit 

125 kHz microIDTM

Developer’s Kit 

125 kHz Anticollision microIDTM

Developer’s Kit 

13.56 MHz Antic olli sion

microIDTM Developer’s Kit 

MCP2510 CAN Developer’s Kit 

* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB® ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.

** Contact Microchip Technology Inc. for availability date.

†Development tool is available on select devices.

PIC16C5X

DS30453E-page 66 Preliminary  1997-2013 Microchip Technology Inc.

NOTES:

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 67

PIC16C5X

12.0 ELECTRICAL CHARACTERISTICS - PIC16C54A

Abso lute Maximum Ratings(†)

Ambient Temperature under bias.....................................................................................................–55°C to +125°C

Storage Temperature .......................................................................................................................–65°C to +150°C

Volta ge on VDD with respect to VSS ..........................................................................................................0V to +7.5V

Volta ge on MC LR with respect to VSS(1)....................................................................................................0V to +14V

Voltage on all other pi ns with respect to VSS ............................................................................–0.6V to (VDD + 0.6V)

Total power dissipa tion(2) ...............................................................................................................................800 mW

Max. current out of VSS pin..................... ...... ..... ............................. ..... ...... ..... ...... ............................ ...... ..... ...150 mA

Max. current into VDD pin................................................................................................................................100 mA

Max. current into an inp ut pin (T0CKI only)... ............................ ...... ..... ...... ............................ ..... ...................±500 A

Input clamp current, IIK (VI < 0 or VI > VDD)....................................................................................................±20 mA

Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................±20 mA

Max. output current sunk by any I/O pin ...........................................................................................................25 mA

Max. output current sourced by any I/O pin......................................................................................................20 mA

Max. output current sourced by a sing le I/O port (PORTA, B or C) ..................................................................40 mA

Max. output current sunk by a single I/O port (PORTA, B or C)........................................................................50 mA

Note 1: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.

Thus, a series resistor of 50 to 100  shoul d be us ed when apply ing a “ low” level to the M CLR pin rather

than pulling this pin directly to VSS.

2: Power Di ssipa tion is calcula ted as fo llows: Pdi s = VDD x {IDD –  IOH} +  {(VDD – V OH) x IOH} + (VOL x IOL)

† NOTICE: Stress es abo ve thos e l is ted u nder “Maximum Ratings” may cause perm an ent dam ag e to th e device. This

is a stres s rat ing only and func ti ona l ope rati on of the d evi ce at tho se or any other conditions abov e tho se indi cated in

the operation listings of this specificatio n is not implied. Exposure to maximum rating conditions for extended periods

may affect device reliabilit y.

PIC16C5X

DS30453E-page 68 Preliminary  1997-2013 Microchip Technology Inc.

12.1 DC Characteristi cs:PIC16C54/55/56/57- RC, XT, 10, HS, LP (Commercial)

PIC16C54/55/56/57-RC, XT, 10, HS, LP

(Commercial) Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C  TA  +70 °C for commercial

Param

No. Symbol Characteristic/Device Min Typ† Max Units Conditions

D001 VDD Supply Voltage

PIC16C5X-RC

PIC16C5X-XT

PIC16C5X-10

PIC16C5X-HS

PIC16C5X-LP

3.0

4.5

2.5

—

6.25

5.5

6.25

D002 VDR RAM Data Retention Voltage(1) 1.5* — V Device in SLEEP Mode

D003 VPOR VDD Start Voltage to ensure

Power-on Reset VSS — V See Section 5.1 for details on

Power-on Reset

D004 SVDD VDD Rise Rate to ensure

Power-on Reset 0.05* — — V/ms See Section 5.1 for details on

Power-on Reset

D010 IDD Sup ply Current(2)

PIC16C5X-RC(3)

PIC16C5X-XT

PIC16C5X-10

PIC16C5X-HS

PIC16C5X-LP

—

1.8

4.8

9.0

3.3

A

FOSC = 4 MHz, VDD = 5.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 20 MHz, VDD = 5.5V

FOSC = 32 kHz, VDD = 3.0V,

WDT disabled

D020 IPD Power-down Current(2) —

—4.0

0.6 12

9A

AVDD = 3.0V, WDT enabled

VDD = 3.0V, WDT disabled

* These parameters are characterized but not tested.

† Data in “Typ” col umn is based o n characteri za tion res ult s at 25C.This data is for design g uidance only and is

not tested.

Note 1: This is the limit to w hich VDD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, os cillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current cons ump tio n.

a) The test conditions for all IDD measurements in ac tive Operation mode are: OSC1 = external square

wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT

enabled /d is abl ed as sp eci fied.

b) For standby current measurements , the conditions are the same, except that the device is in SLEEP

mode. The power-down current in SLEEP mode does not depend on the osc illator type.

3: Does not include current through REXT. The current through the resistor can be estimated by the formula:

IR=VDD/2REXT (mA) with REXT in k.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 69

PIC16C5X

12.2 DC Characteristics: PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI (Industrial)

PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI

(Industrial) Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C  TA  +85°C for industrial

Param

No. Symbol Characteristic/Device Min Typ† Max Units Conditions

D001 VDD Supply Voltage

PIC16C5X-RCI

PIC16C5X-XTI

PIC16C5X-10I

PIC16C5X-HSI

PIC16C5X-LPI

3.0

4.5

2.5

—

6.25

5.5

6.25

D002 VDR RAM Data Retention Voltage(1) — 1.5* — V Device in SLEEP mode

D003 VPOR VDD Start Voltage to ensure

Power-on Reset —VSS — V See Section 5.1 for de tails on

Power-on Reset

D004 SVDD VDD Rise Rate to ensure

Power-on Reset 0.05* — — V/ms See Section 5.1 for de tai ls o n

Power-on Reset

D010 IDD Supply Current(2)

PIC16C5X-RCI(3)

PIC16C5X-XTI

PIC16C5X-10I

PIC16C5X-HSI

PIC16C5X-LPI

—

1.8

4.8

9.0

3.3

A

FOSC = 4 MHz, VDD = 5.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 20 MHz, VDD = 5.5V

FOSC = 32 kHz, VDD = 3.0V,

WDT disabled

D020 IPD Power-down Current(2) —

—4.0

0.6 14

12 A

AVDD = 3.0V, WDT enabled

VDD = 3.0V, WDT disabled

* These parameters are characterized but not tested.

† Data in “Typ” colu mn is based on characteri za tion res ult s at 25C.This data is for design g uidance only and is

not tested.

Note 1: This is the limit to w hich VDD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current cons ump tio n.

a) The test conditions for all IDD measurements in ac tive Operation mode are: OSC1 = external square

wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT

enabled /d is abl ed as sp eci fied.

b) For standby current measurements , the conditions are the same, except that the device is in SLEEP

mode. The power-down current in SLEEP mode does not depend on the osc illator type.

3: Does not include current through REXT. The current through the resistor can be estimated by the formula:

IR=VDD/2REXT (mA) with REXT in k.

PIC16C5X

DS30453E-page 70 Preliminary  1997-2013 Microchip Technology Inc.

12.3 DC Characteristi cs:PIC16C54/55/56/57- RCE, XTE, 10E, HSE, LPE (Extended)

PIC16C54/55/56/57-RCE, XTE, 10E, HSE, LPE

(Extended) Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C  TA  +125°C for extended

Param

No. Symbol Characteristic/Device Min Typ† Max Units Conditions

D001 VDD Supply Voltage

PIC16C5X-RCE

PIC16C5X-XTE

PIC16C5X-10E

PIC16C5X-HSE

PIC16C5X-LPE

3.25

4.5

2.5

—

6.0

5.5

6.0

D002 VDR RAM Data Retention Voltage(1) — 1.5* — V Device in SLEEP mode

D003 VPOR VDD Start Voltage to ensure

Power-on Reset —VSS — V See Section 5.1 for details on

Power-on Rese t

D004 SVDD VDD Rise Rate to ensure

Power-on Reset 0.05* — — V/ms See Section 5.1 for detai ls on

Power-on Rese t

D010 IDD Supply Current(2)

PIC16C5X-RCE(3)

PIC16C5X-XTE

PIC16C5X-10E

PIC16C5X-HSE

PIC16C5X-LPE

—

1.8

4.8

9.0

3.3

A

FOSC = 4 MHz, VDD = 5.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 16 MHz, VDD = 5.5V

FOSC = 32 kHz, VDD = 3.25V,

WDT disabled

D020 IPD Power-down Current(2) —

—5.0

0.8 22

18 A

AVDD = 3.25V, WDT enabled

VDD = 3.25V, WDT disabled

* These parameters are characterized but not tested.

† Data in “Typ” co lumn i s base d on charac teriza tion res ult s at 25C.This data is for design guidance only and is

not tested.

Note 1: This is the limit to w hich VDD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, os cillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current cons ump tio n.

a) The t est condi tio ns fo r all IDD measurements in active Operation mode are: OSC1 = external square

wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT

enabled /d is abl ed as sp eci fied.

b) For standby current measurements, the conditions are the same, except that the device is in SLEEP

mode. The power-down current in SLEEP mode does not depend on the osc illator type.

3: Does not include current through REXT. The current through the resistor can be estimated by the formula:

IR=VDD/2REXT (mA) with REXT in k.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 71

PIC16C5X

12.4 DC Characteristics: PIC16C54/55/56/57-RC, XT, 10, HS, LP (Commercial)

PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI (Industrial)

DC CHARACTERISTICS S tandard Operating Conditions (unless othe rwis e speci fied)

Operati ng Temperature 0°C  TA  +70°C for commercial

–40°C  TA  +85°C fo r industrial

Param

No. Symbol Characteristic/Device Min Typ† Max Units Conditions

D030 VIL Input Low Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

VSS

—

0.2 VDD

0.15 VDD

0.3 VDD

Pin at hi-impedance

PIC16C5X-RC only(3)

PIC 16C5X -XT, 10, HS, LP

D040 VIH Input High Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

0.45 VDD

2.0

0.36 VDD

0.85 VDD

0.7 VDD

—

VDD

For all VDD(4)

4.0V < VDD  5.5V(4)

VDD > 5.5V

PIC16C5X-RC only(3)

PIC 16C5X -XT, 10, HS, LP

D050 VHYS Hysteresis of Schmitt

Trigger inputs 0.15 VDD*— — V

D060 IIL Input Leakage Current(1,2)

I/O ports

MCLR

T0CKI

OSC1

–1

–5

—

–3

0.5

—

0.5

—

A

For VDD  5.5V:

VSS  VPIN  VDD,

pin at hi-impedance

VPIN = VSS + 0.25V

VPIN = VDD

VSS  VPIN  VDD

VSS  VPIN  VDD,

PIC 16C5X -XT, 10, HS, LP

D080 VOL Output Low Voltage

I/O ports

OSC2/CLKOUT —

——

—0.6

0.6 V

VIOL = 8.7 mA, VDD = 4.5V

IOL = 1.6 mA, VDD = 4.5V,

PIC16C5X-RC

D090 VOH Output High Voltage(2)

I/O ports

OSC2/CLKOUT VDD – 0.7

VDD – 0.7 —

——

—V

VIOH = –5.4 mA, VDD = 4.5V

IOH = –1.0 mA, VDD = 4.5V,

PIC16C5X-RC

* These parameters are characterized but not tested.

† Data in the Typical (“Typ”) column is based on characterization result s at 25°C. This dat a is for design guidan ce

only and is not tested.

Note 1: The leakag e cu rrent on the MC LR/VPP pin is strong ly dep end ent on the app lie d vo ltage level. Th e sp ec ifie d

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltage.

2: Negative current is defined as coming out of the pin.

3: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the

PIC16C5X be driven with external clock in RC mode.

4: The user may use the better of the two specifications.

PIC16C5X

DS30453E-page 72 Preliminary  1997-2013 Microchip Technology Inc.

12.5 DC Characteristi cs:PIC16C54/55/56/57-RCE, XTE, 10E, HSE, LPE (Extende d)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C  TA  +125°C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

D030 VIL Input Low Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

Vss

—

0.15 VDD

0.3 VDD

Pin at hi-impedance

PIC16C5X-RC only(3)

PIC16C5X-XT, 10, HS, LP

D040 VIH Input High Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

0.45 VDD

2.0

0.36 VDD

0.85 VDD

0.7 VDD

—

VDD

For all VDD(4)

4.0V < VDD  5.5V(4)

VDD > 5.5 V

PIC16C5X-RC only(3)

PIC16C5X-XT, 10, HS, LP

D050 VHYS Hysteresis of Schmitt

Trigger inputs 0.15 VDD*— — V

D060 IIL Input Lea kag e Current (1,2)

I/O ports

MCLR

T0CKI

OSC1

–1

–5

—

–3

0.5

—

0.5

—

A

For VDD  5.5 V:

VSS  VPIN  VDD,

pin at hi-impedance

VPIN = VSS + 0.25V

VPIN = VDD

VSS  VPIN  VDD

VSS  VPIN  VDD,

PIC16C5X-XT, 10, HS, LP

D080 VOL Output Low Voltage

I/O ports

OSC2/CLKOUT —

——

—0.6

0.6 V

VIOL = 8.7 mA, VDD = 4.5V

IOL = 1.6 mA, VDD = 4.5V,

PIC16C5X-RC

D090 VOH Output High Voltage(2)

I/O ports

OSC2/CLKOUT VDD – 0.7

VDD – 0.7 —

——

—V

VIOH = –5.4 mA, VDD = 4.5V

IOH = –1.0 mA, VDD = 4.5V,

PIC16C5X-RC

* These parameters are characterized but not tested.

† Data in the T ypical (“Typ”) column is bas ed on characterization result s at 25°C. This data i s for design guidance

only and is not tested.

Note 1: The leakage current on the MC LR/VPP pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltage.

2: Negative current is defined as coming out of the pin.

3: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the

PIC16C5X be driven with external clock in RC mode.

4: The user may use the better of the two specifications.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 73

PIC16C5X

12.6 Timing Parameter Symbology and Load Conditions

The timing parameter symbols have been created with one of the following formats:

FIGURE 12-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS - PIC16C54/55/56/57

1. TppS2ppS

2. TppS

TF Frequency T Time

Lowercase letters (pp) and their meanings:

2to mcMCLR

ck CLKOUT osc oscillator

cy cycle time os OSC1

drt device reset timer t0 T0CKI

io I/O port wdt watchdog timer

Uppe rcase letters and their meanings:

SFFall PPeriod

HHigh RRise

I Invalid (Hi-impedance) V Valid

L Low Z Hi-impedance

VSS

Pin CL = 50 pF for all pins and OSC2 for RC mode

0 - 15 pF for OSC2 in XT, HS or LP modes when

external clock is used to drive OSC1

PIC16C5X

DS30453E-page 74 Preliminary  1997-2013 Microchip Technology Inc.

12.7 Timing Diagrams and Specifications

FIGURE 12-2: EXTERNAL CLOCK TIMING - PIC16C54/55/56/57

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

133

TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57

AC Charac teristics

S tandard Operating Conditions (unle ss othe rwis e speci fied )

Operati ng Temperature 0°C  TA  +70°C for commerci al

–40°C  TA  +85°C for industrial

–40°C  TA  +125°C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

1A FOSC External CLKIN Frequency(1) DC — 4.0 MHz XT OSC mode

DC — 10 MHz 10 MHz mode

DC — 20 MHz HS OSC mode (Comm/Ind)

DC — 16 MHz HS OSC mode (Ext)

DC — 40 kHz LP OSC mode

Oscillator Frequency(1) DC — 4.0 MHz RC OSC mode

0.1 — 4.0 MHz XT OSC mode

4.0 — 10 MHz 10 MHz mode

4.0 — 20 MHz HS OSC mode (Comm/Ind)

4.0 — 16 MHz HS OSC mode (Ext)

DC — 40 kHz LP OSC mode

* These parameters are characterized but not tested.

† Dat a in the T yp ical (“T y p”) column is at 5.0V, 25°C unless otherwis e stated . These para meters are for des ign

guidance only and are not tested.

Note 1: All specified values are based on characterization data for that particular oscillator type under standard

operating conditions with the device executing code. Exceeding these specified limits may result in an

unstable oscillator operation and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

2: Instruction cycle period (TCY) equals four times the input oscillator time base period.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 75

PIC16C5X

1TOSC External CLKIN Period(1) 250 — — ns XT OSC mode

100 — — ns 10 MHz mode

50 — — ns HS OSC mode (Comm/Ind)

62.5 — — ns HS OSC mode (Ext)

25 — — sLP

OSC mode

Osci llator Period(1) 250 — — ns RC OSC mode

250 — 10,000 ns XT OSC mode

100 — 250 ns 10 MHz mode

50 — 250 ns HS OSC mode (Comm/Ind)

62.5 — 250 ns HS OSC mode (Ext)

25 — — sLP

OSC mode

2 Tcy Instruction Cycle Time(2) —4/FOSC ——

3 TosL,

TosH Clock in (O SC1) Low o r Hig h

Time 85* — — n s XT oscillator

20* — — ns HS oscillator

2.0* — — s LP oscillat or

4TosR,

TosF Clock in (OSC1) Rise or Fall

Time — — 25* ns XT oscillator

— — 25* ns HS oscillator

— — 50* ns LP oscil lat or

TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57

AC Charac teristics

S tandard Operating Conditions (unle ss othe rwis e speci fied)

Operati ng Temperature 0°C  TA  +70°C for commerci al

–40°C  TA  +85°C for industrial

–40°C  TA  +125°C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

* These parameters are characterized but not tested.

† Dat a in the T yp ical (“T y p”) column is at 5.0V, 25°C unless otherwis e stated . These para meters are for des ign

guidance only and are not tested.

Note 1: All specified values are based on characterization data for that particular oscillator type under standard

operating conditions with the device executing code. Exceeding these specified limits may result in an

unstable oscillator operation and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

2: Instruction cycle period (TCY) equals four times the input oscillator time base period.

PIC16C5X

DS30453E-page 76 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 12-3: CLKOUT AND I/O TIMING - PIC16C54/55/56/57

TABLE 12-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54/55/56/57

AC Charac teristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C  TA  +70°C for commercial

–40°C  TA  +85°C for industrial

–40°C  TA  +125°C for extended

Param

No. Symbol Characteristic Min Typ† Max Units

10 TosH2ckL OSC1 to CLKOUT(1) —1530** ns

11 TosH2ckH OSC1 to CLKOUT(1) —1530** ns

12 TckR CLKOUT rise time(1) —5.015** ns

13 TckF CLKOUT fall time(1) —5.015** ns

14 TckL2ioV CLKOUT to Port out valid(1) ——40** ns

15 TioV2ckH Port in valid before CLKOUT(1) 0.25 TCY+30* — — ns

16 TckH2ioI Port in hold after CLKOUT(1) 0* — — ns

17 TosH2ioV OSC1 (Q1 cycle) to Port out valid(2) — — 100* ns

18 TosH2ioI OSC1 (Q2 cycle) to Port input invalid

(I/O in hold time) TBD — — ns

19 TioV2osH Port input valid to OSC1

(I/O in setup time) TBD — — ns

20 TioR Port output rise time(2) —1025** ns

21 TioF Port output fall time(2) —1025** ns

* These parameters are characterized but not tested.

** These parameters are design targets and are not tested. No characterization data available at this time.

† Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x Tosc.

2: Please refer to Figure 12-1 for load conditions.

OSC1

CLKOUT

I/O Pin

(input)

I/O Pin

(output)

Q4 Q1 Q2 Q3

13 14

20, 21

12 16

Old Value New Value

Note: Please refer to Figure 12-1 for load conditions.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 77

PIC16C5X

FIGURE 12-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING -

PIC16C54/55/56/57

TABLE 12-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54/55/56/57

AC Charac teristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C  TA  +70°C for commercial

–40°C  TA  +85°C for industrial

–40°C  TA  +125°C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

30 TmcL MCLR Pulse Width (low) 100* — — ns VDD = 5.0V

31 Twdt Watchdog Timer Time-out Period

(No Prescaler) 9.0* 18* 30* ms VDD = 5.0V (Comm)

32 TDRT Device Reset Timer Period 9.0* 18* 30* ms VDD = 5.0V (Comm)

34 TioZ I/O Hi-impedance from MCLR Low — — 100* ns

* These parameters are characterized but not tested.

† Data in th e Typical (“Typ”) c olu mn is at 5.0V, 25°C unles s o therwise state d. These parameters are for design

guidance only and are not tested.

VDD

MCLR

Internal

POR

DRT

Time-out

Internal

RESET

Watchdog

Timer

Reset

I/O pin

32 32

(Note 1)

Note 1: Please refer to Figure 12-1 for load conditions.

PIC16C5X

DS30453E-page 78 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 12-5: TIMER0 CLOCK TIMINGS - PIC16C54/55/56/57

TABLE 12-4: TIMER0 CLOCK REQUIREMENTS - PIC16C54/55/56/57

AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C  TA  +70°C for commercial

–40°C  TA  +85°C for industrial

–40°C  TA  +125°C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

40 Tt0H T0CKI High Pulse Width

- No Prescaler 0.5 TCY + 20* — — ns

- With Prescaler 10* — — ns

41 Tt0L T0CK I Low P ulse W idth

- No Prescaler 0.5 TCY + 20* — — ns

- With Prescaler 10* — — ns

42 Tt0P T0CKI Period 20 or TCY + 40*

N — — ns Whichever is greater.

N = Prescale Value

(1, 2, 4,..., 256)

* These parameters are characterized but not tested.

† Data in the Typical (“Typ”) colum n is at 5.0V, 25°C unles s otherwis e st ated. Thes e pa ramete rs are fo r design

guidance only and are not tested.

T0CKI

40 41

Note: Please refer to Figure 12-1 for load conditions.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 79

PIC16C5X

13.0 ELECTRICAL CHARACTERISTICS - PIC16CR54A

Absolute Maximum Ratings(†)

Ambient Temperature under bias.....................................................................................................–55°C to +125°C

Storage Temperature .......................................................................................................................–65°C to +150°C

Volta ge on VDD with respect to VSS ............................................................................................................0 to +7.5V

Volta ge on MC LR with respect to VSS(1)......................................................................................................0 to +14V

Voltage on all other pi ns with respect to VSS ............................................................................–0.6V to (VDD + 0.6V)

Total power dissipa tion(2) ...............................................................................................................................800 mW

Max. current out of VSS pin..................... ...... ..... ............................. ..... ...... ..... ...... ............................ ...... ..... ...150 mA

Max. current into VDD pin..................................................................................................................................50 mA

Max. current into an inp ut pin (T0CKI onl y) 500 A

Input clamp current, IIK (VI < 0 or VI > VDD)20 mA

Output clamp current, IOK (V0 < 0 or V0 > VDD)20 mA

Max. output current sunk by any I/O pin ...........................................................................................................25 mA

Max. output current sourced by any I/O pin......................................................................................................20 mA

Max. output current sourced by a sing le I/O port (PORTA or B).......................................................................40 mA

Max. output current sunk by a single I/O port (PORTA or B) ............................................................................50 mA

Note 1: V oltage spikes below Vss at the MCLR pin, ind ucing current s grea ter than 80 mA m ay cause latc h-up. Thus,

a seri es resi stor of 50 to 100  sh ould be used w hen applying a low level to th e MCLR pin rather than pulling

this pin directly to Vss.

2: Power Di ss ip ation is ca lcu la ted as fo llo w s: PDIS = VDD x { I DD -  IOH} +  {(VDD-VOH) x IOH} + (VOL x IOL)

† NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.

This is a s tress rating only and funct ion al op eration of th e dev ice at tho se or an y oth er co nditio ns ab ove t hose indi-

cated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

PIC16C5X

DS30453E-page 80 Preliminary  1997-2013 Microchip Technology Inc.

13.1 DC Characteristics:PIC16CR54A-04, 10, 20, PIC16LCR54A-04 (Commercial)

PIC16CR54A-04I, 10I, 20I, PIC16LCR54A-04I (Industrial)

PIC16LCR54A-04

PIC16LCR54A-04I

(Commercial, Industrial)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C  TA  +70°C for commercial

–40°C  TA  +85°C for industrial

PIC16CR54A-04, 10, 20

PIC16CR54A-04I, 10I, 20I

(Commercial, Industrial)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C  TA  +70°C for commercial

–40°C  TA  +85°C for industrial

Param

No. Symbol Characteristic/Device Min Typ† Max Units Conditions

VDD Supply Voltage

D001 PIC16LCR54A 2.0 — 6.25 V

D001

D001A PIC16CR54A 2.5

4.5 —

—6.25

5.5 V

VRC and XT modes

HS mode

D002 VDR RAM Data Retent i on

Voltage(1) — 1.5* — V Device in SLEEP mode

D003 VPOR VDD St art Volt age to ensure

Power-on Reset —VSS — V See Section 5.1 for details on

Power-on Reset

D004 SVDD VDD Rise Rate to ensure

Power-on Reset 0.05* — — V/ms See Section 5.1 for details on

Power-on Reset

IDD Supply Current(2)

D005 PICLCR54A —

—10

—20

70 A

AFosc = 32 kHz, VDD = 2.0V

Fosc = 32 kHz, VDD = 6.0V

D005A PIC16CR54A —

—

2.0

0.8

4.8

9.0

3.6

1.8

350

A

RC(3) and XT modes:

FOSC = 4.0 MHz, VDD = 6.0V

FOSC = 4.0 MHz, VDD = 3.0V

FOSC = 200 kHz, VDD = 2.5V

HS mode:

FOSC = 10 MHz, VDD = 5.5V

FOSC = 20 MHz, VDD = 5.5V

Legend: Rows with standard voltage device data only are shaded for improved readability.

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C, unl ess otherwise s tated. These p arameters are for desig n guidance only,

and are not tested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

2: The supp ly current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square

wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/

disabled as specified.

b) For standby current measurements, the conditions are the same, except that the device is in SLEEP

mode. The power-down current in SLEEP mode does not depend on the oscillator ty pe.

3: Does not inclu de current through REXT. The current through the resistor can be estimated by the formula:

IR= VDD/2REXT (mA) with REXT in k.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 81

PIC16C5X

IPD Power-down Current(2)

D006 PIC16LCR54A-Commercial —

—

1.0

2.0

3.0

5.0

6.0

8.0*

A

VDD = 2.5V, WDT disabled

VDD = 4.0V, WDT disabled

VDD = 6.0V, WDT disabled

VDD = 6.0V, WDT enabled

D006A PIC16CR54A-Commercial —

—

1.0

2.0

3.0

5.0

6.0

8.0*

A

VDD = 2.5V, WDT disabled

VDD = 4.0V, WDT disabled

VDD = 6.0V, WDT disabled

VDD = 6.0V, WDT enabled

D007 PIC16LCR54A-Industrial —

—

1.0

2.0

3.0

5.0

8.0

10*

20*

A

VDD = 2.5V, WDT disabled

VDD = 4.0V, WDT disabled

VDD = 4.0V, WDT enabled

VDD = 6.0V, WDT disabled

VDD = 6.0V, WDT enabled

D007A PIC16CR54A-Industrial —

—

1.0

2.0

3.0

5.0

8.0

10*

20*

A

VDD = 2.5V, WDT disabled

VDD = 4.0V, WDT disabled

VDD = 4.0V, WDT enabled

VDD = 6.0V, WDT disabled

VDD = 6.0V, WDT enabled

13.1 DC Characteristics:PIC16CR54A-04, 10, 20, PIC16LCR54A-04 (Commercial)

PIC16CR54A-04I, 10I, 20I, PIC16LCR54A-04I (Industrial)

PIC16LCR54A-04

PIC16LCR54A-04I

(Commercial, Industrial)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C  TA  +70°C for commercial

–40°C  TA  +85°C for industrial

PIC16CR54A-04, 10, 20

PIC16CR54A-04I, 10I, 20I

(Commercial, Industrial)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C  TA  +70°C for commercial

–40°C  TA  +85°C for industrial

Param

No. Symbol Characteristic/Device Min Typ† Max Units Conditions

Legend: Rows with standard voltage device data only are shaded for improved readability.

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C, unl ess otherwise s tated. These p arameters are for desig n guidance only,

and are not tested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

2: The supp ly current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square

wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/

disabled as specified.

b) For standby current measurements, the conditions are the same, except that the device is in SLEEP

mode. The power-down current in SLEEP mode does not depend on the oscillator ty pe.

3: Does not inclu de current through REXT. The current through the resistor can be estimated by the formula:

IR= VDD/2REXT (mA) with REXT in k.

PIC16C5X

DS30453E-page 82 Preliminary  1997-2013 Microchip Technology Inc.

13.2 DC Characteristi cs:PIC16CR54A-04E, 10E, 20E (Extended)

PIC16CR54A-04E, 10E, 20E

(Extended) Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C  TA  +125°C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

D001 VDD Supply Voltage

RC, XT and LP modes

HS mode 3.25

4.5 —

—6.0

5.5 V

D002 VDR RAM Data Retention Voltage(1) — 1.5* — V Device in SLEEP mode

D003 VPOR VDD Start Voltage to ens ure

Power-on Reset —VSS — V See Section 5.1 for details on

Power-on Reset

D004 SVDD VDD Rise Rate to ensure Power-

on Reset 0.05* — — V/ms See Sectio n 5.1 for details on

Power-on Reset

D010 IDD Supply Current(2)

RC(3) and XT modes

HS mode

—

1.8

4.8

9.0

3.3

FOSC = 4.0 MHz, VDD = 5.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 16 MHz, VDD = 5.5V

D020 IPD Power-down Current(2) —

—5.0

0.8 22

18 A

AVDD = 3.25V, WDT enabled

VDD = 3.25V, WDT disabled

* These parameters are characterized but not tested.

† Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design

guidance only and is not tested.

Note 1: This is the limit to w hich VDD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, os cillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current cons ump tio n.

a) The tes t con dit ion s for al l IDD measu rem en ts in active Operatio n mod e are: OSC 1 = ext erna l squ are

wave, from rai l-to-rai l; all I/O pins trist a ted, pull ed to VSS, T0CKI = VDD, MCLR = V DD; WDT enabled/

disabl ed as spec ifie d.

b) For standby current m ea sur eme nts, the conditions are the same, ex cept that the device is i n SLEE P

mode.The power-down current in SLEEP mode does not depend on the oscillator type.

3: Does not include current through REXT. The current through the resistor can be estimated by the

formula: IR = VDD/2REXT (mA) with REXT in k.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 83

PIC16C5X

13.3 DC Characteristics:PIC16CR54A-04, 10, 20, PIC16LCR54A-04 (Commercial)

PIC16CR54A-04I, 10I, 20I, PIC16LCR54A-04I (Industrial)

DC CHARACTERISTICS Standard Opera ting Conditi ons (unle ss othe rwis e speci fied )

Operati ng Temperature 0°C  TA  +70°C for commercial

–40°C  TA  +85°C for industrial

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

D030 VIL Input Low Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt T rig ge r)

OSC1

VSS

—

0.2 VDD

0.15 VDD

Pin at hi-impedance

RC mode only(3)

XT, HS and LP modes

D040 VIH Input High Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt T rig ge r)

OSC1

2.0

0.6 VDD

0.85 VDD

—

VDD

VDD = 3.0V to 5.5V(4)

Full VDD range(4)

RC mode only(3)

XT, HS and LP modes

D050 VHYS Hystere sis of Schmitt

Trigger inputs 0.15 VDD*— — V

D060 IIL Input Leakage Current(1,2)

I/O ports

MCLR

T0CKI

OSC1

–1.0

–5.0

—

–3.0

—

0.5

+1.0

—

+5.0

+3.0

A

For VDD  5.5V:

VSS  VPIN  VDD,

pin at hi-impedance

VPIN = VSS + 0.25V

VPIN = VDD

VSS  VPIN  VDD

VSS  VPIN  VDD,

XT, HS and LP modes

D080 VOL Output Low Voltage

I/O ports

OSC2/CLKOUT —

——

—0.5

0.5 V

VIOL = 10 mA, VDD = 6.0V

IOL = 1.9 mA, VDD = 6.0V,

RC mode only

D090 VOH Output High Voltage(2)

I/O ports

OSC2/CLKOUT VDD – 0.5

VDD – 0.5 —

——

—V

VIOH = –4.0 mA, VDD = 6.0V

IOH = –0.8 mA, VDD = 6.0V,

RC mode only

* These parameters are characterized but not tested.

† Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guid-

ance only and is not tested.

Note 1: The leakag e cu rren t on th e M C LR/VPP pin is stro ngl y dependent on the app lie d vo ltage level. T he s pec ifi ed

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltage.

2: Negative current is defined as coming out of the pin.

3: For the RC mo de, the OSC1/CLKIN pi n is a Schmitt T rig ger input. It is no t recommen ded that the PIC 16C5X

be driven with external clock in RC mode.

4: The user may use the better of the two specifications.

PIC16C5X

DS30453E-page 84 Preliminary  1997-2013 Microchip Technology Inc.

13.4 DC Characteristi cs:PIC16CR54A-04E, 10E, 20E (Extended)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C  TA  +125°C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

D030 VIL Input Low Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

Vss

—

0.15 VDD

0.3 VDD

Pin at hi-impedance

RC mode only(3)

XT, HS and LP modes

D040 VIH Input High Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

0.45 VDD

2.0

0.36 VDD

0.85 VDD

0.7 VDD

—

VDD

For all VDD(4)

4.0V < VDD  5.5V(4)

VDD > 5.5V

RC mode only(3)

XT, HS and LP modes

D050 VHYS Hysteresis of Schmitt

Trigger inputs 0.15 VDD*— — V

D060 IIL Input Leakage Current(1,2)

I/O ports

MCLR

T0CKI

OSC1

–1.0

–5.0

—

–3.0

0.5

—

0.5

+1.0

—

+5.0

+3.0

A

For VDD  5.5V:

VSS  VPIN  VDD,

pin at hi-impedance

VPIN = VSS + 0.25V

VPIN = VDD

VSS  VPIN  VDD

VSS  VPIN  VDD,

XT, HS and LP modes

D080 VOL Output Low Voltage

I/O ports

OSC2/CLKOUT —

——

—0.6

0.6 V

VIOL = 8.7 mA, VDD = 4.5V

IOL = 1.6 mA, VDD = 4.5V,

RC mode only

D090 VOH Output High Voltage(2)

I/O ports

OSC2/CLKOUT VDD – 0.7

VDD – 0.7 —

——

—V

VIOH = –5.4 mA, VDD = 4.5V

IOH = –1.0 mA, VDD = 4.5V,

RC mode only

* These parameters are characterized but not tested.

† Data in th e Typic al (“ Typ”) co lum n i s ba se d on c ha r ac teriz at ion results at 25C. This data is for design guid-

ance only and is not tested.

Note 1: The leaka ge cu rrent on the MCLR/VPP pin is strongly depen den t o n t he applied vol t ag e l ev el. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltage.

2: Negative current is defined as coming out of the pin.

3: For the RC mode, th e OSC1/CLK IN pin is a Sc hmitt T rigg er input. It is not reco mmended that the PIC16 C5X

be driven with external cloc k in RC mode.

4: The user may use the better of the two specifications.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 85

PIC16C5X

13.5 Timing Parameter Symbology and Load Conditions

The timing parameter symbols have been created with one of the following formats:

1. TppS2ppS

2. TppS

TF Frequency T Time

Lowercase letters (pp) and their meanings:

2to mcMCLR

ck CLKOUT osc oscillator

cy cycle time os OSC1

drt device reset timer t0 T0CKI

io I/O port wdt watchdog timer

Uppe rcase letters and their meanings:

SF Fall P Period

HHigh RRise

I Invalid (Hi-impedance) V Valid

L Low Z Hi-impedance

FIGURE 13-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS - PIC16CR54A

CL = 50 pF for all pins and OSC2 for RC modes

0 -15 pF for OSC2 in XT, HS or LP modes when

external clock is used to drive OSC1

VSS

PIC16C5X

DS30453E-page 86 Preliminary  1997-2013 Microchip Technology Inc.

13.6 Timing Diagrams and Specifications

FIGURE 13-2: EXTERN AL CLOCK TIMING - PIC16CR54A

TABLE 13-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54A

AC Charac teristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C  TA  +70°C for commercial

–40°C  TA  +85°C for industrial

–40°C  TA  +125°C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

FOSC External CLKIN Frequency(1) DC — 4.0 MHz XT OSC mode

DC — 4.0 MHz HS OSC mode (04)

DC — 10 MHz HS OSC mode (10)

DC — 20 MHz HS OSC mode (20)

DC — 200 kHz LP OSC mode

Oscill ator Frequency(1) DC — 4.0 MHz RC OSC mode

0.1 — 4.0 MHz XT OSC mode

4.0 — 4.0 MHz HS OSC mode (04)

4.0 — 10 MHz HS OSC mode (10)

4.0 — 20 MHz HS OSC mode (20)

5.0 — 200 kHz LP OSC mode

* These parameters are characterized but not tested.

† Data in the Typic al (“Typ”) c olumn is ba sed on charac teriza tio n resu lts at 25C. This dat a is f or desi gn gui d-

ance only and is not tested.

Note 1: All specified values are based on characterization data for that particular os cillator type under standard

operating conditions with the device executing code. Exceeding these specified limits may result in an

unstable oscillator operation and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

2: Instruction cycl e period (TCY) equals four times the input oscillator time base period.

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

133

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 87

PIC16C5X

1TOSC External CLKIN Period(1) 250 — — ns XT OSC mode

250 — — ns HS OSC mode (04)

100 — — ns HS OSC mode (10)

50 — — ns HS OSC mode (20)

5.0 — — sLP

OSC mo de

Oscill ator Period(1) 250 — — ns RC OSC mode

250 — 10,000 ns XT OSC mode

250 — 250 ns HS OSC mode (04)

100 — 250 ns HS OSC mode (10)

50 — 250 ns HS OSC mode (20)

5.0 — 200 sLP

OSC mo de

2 Tcy Instru ction Cycle Time(2) —4/FOSC ——

3 TosL, TosH Clock in (OSC1) Low or High

Time 50* — — ns XT oscillator

20* — — ns HS oscillator

2.0* — — s LP oscillator

4 TosR, TosF Clock in (OSC1) Rise or Fall

Time — — 25* ns XT oscillator

— — 25* ns HS oscillator

— — 50* ns LP oscillator

TABLE 13-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54A

AC Charac teristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C  TA  +70°C for commercial

–40°C  TA  +85°C for industrial

–40°C  TA  +125°C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

* These parameters are characterized but not tested.

† Data in the Typic al (“Typ”) c olumn is ba sed on charac teriza tion re sult s at 2 5C. This data is for design guid-

ance only and is not tested.

Note 1: All specified values are based on characterization data for that particular oscillator type under standard

operating conditions with the device executing code. Exceeding these specified limits may result in an

unstable oscillator operation and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

2: Instruction cycl e period (TCY) equals four times the input oscillator time base period.

PIC16C5X

DS30453E-page 88 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 13-3: CLKOUT AND I/O TIMING - PIC16CR54A

TABLE 13-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16CR54A

AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C  TA  +70C for commercial

–40C  TA  +85C for industrial

–40C  TA  +125C for extended

Param

No. Symbol Characteristic Min Typ† Max Units

10 TosH2ckL OSC1 to CLKOUT(1) —1530**ns

11 TosH2ckH OSC1 to CLKOUT(1) —1530**ns

12 Tck R CLKOUT rise time(1) —5.015**ns

13 Tck F CLKOUT fall time(1) —5.015**ns

14 TckL2ioV CLKOUT to Port out valid(1) ——40**ns

15 TioV2ckH Port in valid before CLKOUT(1) 0.25 TCY+30* — — ns

16 TckH2ioI Port in hold after CLKOUT(1) 0* — — ns

17 TosH2ioV OSC1 (Q1 cycle) to Port out valid(2) — — 100* ns

18 TosH2ioI OSC1 (Q2 cycle) to Port input invalid

(I/O in hold time) TBD — — ns

19 TioV2osH Port input valid to OSC1

(I/O in setup time) TBD — — ns

20 TioR Port output rise time(2) —1025**ns

21 TioF Port output fall time(2) —1025**ns

* These parameters are characterize d but not tested.

** These parameters are design targets and are not tested. No characterization data available at this time.

† Dat a in the Typical (“Typ”) co lum n is ba se d o n characterizatio n results a t 2 5C. This data is for design guid-

ance only and is not tested.

Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

2: Please refer to Figure 13.1 for load conditions .

OSC1

CLKOUT

I/O Pin

(input)

I/O Pin

(output)

Q4 Q1 Q2 Q3

20, 21

Old Value New Value

19 12

Note: Please refer to Figure 13.1 for load conditions.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 89

PIC16C5X

FIGURE 13-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16CR54A

TABLE 13-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16CR54A

AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0C  TA  +70°C for commercial

–40C  TA  +85C for industrial

–40C  TA  +125C for extend ed

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

30 TmcL MCLR Pulse Width (low) 1.0* — — sVDD = 5.0V

31 T wdt W atc hd og Timer T im e- out Perio d

(No Prescaler) 7.0* 18* 40* ms VDD = 5.0V (Comm)

32 TDRT Device Reset Timer Period 7.0* 18* 30* ms VDD = 5.0V (Comm)

34 TioZ I/O Hi-impedance from MCLR Low — — 1.0* s

* These parameters are characterized but not tested.

† Data in the T ypi cal (“T yp”) column is at 5.0V, 25°C unless otherw ise state d. These paramet ers are for design

guidance only and are not tested.

VDD

MCLR

Internal

POR

DRT

Time-out

Internal

RESET

Watchdog

Timer

RESET

I/O pin

32 32

(Note 1)

Note 1: Please refer to Figure 13.1 for load conditions.

PIC16C5X

DS30453E-page 90 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 13-5: TIMER0 CLOCK TIMINGS - PIC16CR54A

TABLE 13-4: TIMER0 CLOCK REQUIREMENTS - PIC16CR54A

AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0C  TA  +70C for commercial

–40C  TA  +85C for industrial

–40C  TA  +125C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

40 Tt0H T0CKI High Pulse Width

- No Prescaler 0.5 TCY + 20* — — ns

- With Prescaler 10* — — ns

41 Tt0L T0CKI Low Pulse Width

- No Prescaler 0.5 TCY + 20* — — ns

- With Prescaler 10* — — ns

42 Tt0P T0CKI Period 20 or TCY + 40*

N — — ns Whichev er is greater.

N = Prescale Value

(1, 2, 4,..., 256)

* These parameters are characterized but not tested.

† Data in the T ypical (“T yp”) colum n is at 5.0V, 25° C unl ess otherwis e stated . These p arameters are for design

guidance only and are not tested.

T0CKI

40 41

Note: Please refer to Figure 13.1 for load conditions.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 91

PIC16C5X

14.0 DEVICE CHARACTERIZATION - PIC16 C 54A

The graphs and t ables prov ided followi ng this note are a st atistica l summary bas ed on a limit ed numb er of samples an d

are provided for informational purposes only. The performance characteristics listed herein are not tested or guaran-

teed. In some grap hs or tables, the data presented may be outsid e the sp ecified operati ng range (e.g., out side specifie d

power supply range) and therefore outside the warranted range.

“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3) or (mean

– 3) respectively, where  is a standard deviation, over the whole temperature range.

FIGURE 14-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE

TABLE 14-1: RC OSCILLATOR FREQUENCIES

CEXT REXT Average

FOSC @ 5 V, 25C

20 pF 3.3K 5 MHz  27%

5K 3.8 MHz  21%

10K 2.2 MHz  21%

100K 262 kHz  31%

100 pF 3.3K 1.6 MHz  13%

5K 1.2 MHz  13%

10K 684 kHz  18%

100K 71 kHz  25%

300 pF 3.3K 660 kHz  10%

5.0K 484 kHz  14%

10K 267 kHz  15%

100K 29 kHz  19%

The frequencies are measured on DIP packages.

The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation

indicated is 3 standard deviations from the average value for VDD = 5V.

FOSC

FOSC (25C)

1.10

1.08

1.06

1.04

1.02

1.00

0.98

0.96

0.94

0.92

0.90

010 20253040506070

T(C)

Frequency normalized to +25C

VDD = 5.5V

VDD = 3.5V

REXT 10k

CEXT = 100 pF

0.88

PIC16C5X

DS30453E-page 92 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 14-2: TYPICAL RC OSC

FREQUENCY vs. VDD,

CEXT = 20 PF

FIGURE 14-3: TYPICAL RC OSC

FREQUENCY vs. VDD,

CEXT = 100 PF

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

3.0 3.5 4.0 4.5 5.0 5.5 6.0

(Volts)

Fos c ( M Hz)

R = 3.3K

R = 5K

R = 10K

R = 100K

Measured on DIP Packages, T = 25C

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

3.0 3.5 4.0 4.5 5.0 5.5 6.0

(Volts)

Fosc (MHz)

R = 3.3K

R = 5K

R = 10K

R = 100K

Measured on DIP Packages, T = 25C

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 93

PIC16C5X

FIGURE 14-4: TYPICAL RC OSC

FREQUENCY vs. VDD,

CEXT = 300 PF

FIGURE 14-5: TYPICAL IPD vs. VDD,

WA TCHDOG DISA BLED

800

700

600

500

400

300

200

100

3.0 3.5 4.0 4.5 5.0 5.5 6.0

(Volts)

Fosc (kHz)

R = 3.3K

R = 5K

R = 10K

R = 100K

Measured on DIP Packages, T = 25C

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

2.5

2.0

1.5

1.0

0.5

0.02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

IPD (A)

VDD (Volts)

T = 25C

Typical: statistical mean @ 25°C

Maximu m: mean + 3s (-40°C to 125 °C )

Minimum: mean – 3s (-40°C to 125°C)

PIC16C5X

DS30453E-page 94 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 14-6: MAXIMUM IPD vs. VDD,

WATC HDOG DISABLED

FIGURE 14-7: TYPICAL IPD vs. VDD,

WATC HDOG ENABLED

FIGURE 14-8: MAXIMUM IPD vs. VDD,

WA TCHDOG ENABLED

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Ipd (



(Volts)

6.5 7.0

100

+85°C

0°C

–40°C

–55°C

+125°C

+70°C

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

IPD (



VDD (Volts)

T = 25C

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

+70



2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

(



(Volts) 6.5 7.0

+85



–40



–55



+125



IPD, with WDT enabled, has two components:

The leakage current, which increases with higher temper-

ature, and the operating curr ent of the WDT logic, which

increases with lower temperature. At –40C, the latter

dominates explaining the apparently anomalous behav-

ior.

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 95

PIC16C5X

FIGURE 14-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD

FIGURE 14-10 : VIH, VIL OF MCLR, T0CKI AND OSC1 (RC MODE) vs. VDD

2.00

1.80

1.60

1.40

1.20

1.00

2.5 3.0 3.5 4.0 4.5 5.0

VDD (Volts)

Min (–40C to +85C)

0.80

0.60 5.5 6.0

Max (–40C to +85C)

Typ (+25C)

VTH (Volts)

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

3.5

3.0

2.5

2.0

1.5

1.0

2.5 3.0 3.5 4.0 4.5 5.0

VDD (Volts)

0.5

0.0 5.5 6.0

VIH, VIL (Volts)

4.0

4.5

min (–40C to +85C)

max (–40C to +85C)

typ +25C

min (–40C to +85C)

max (–40C to +85C)

typ +25C

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

Note: These input pins have Schmitt Trigger input buffers.

PIC16C5X

DS30453E-page 96 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 14-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT

(XT, HS, AND LP MODES) vs. VDD

FIGURE 14-12: TYPICAL IDD VS. FREQUENCY (EXTERNAL CLOCK, 25C)

2.4

2.2

2.0

1.8

1.6

1.4

2.5 3.0 3.5 4.0 4.5 5.0

VDD (V olts)

1.2

1.0 5.5 6.0

Typ (+25C)

VTH (V olts)

2.6

2.8

3.0

3.2

3.4

Max (–40C to +85C)

Min (–40C to +85C)

1.4

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

10K 100K 1M 10M 100M

0.01

0.1

1.0

IDD (mA)

External Clock Frequency (Hz)

5.0

4.5

4.0

2.5

3.0

3.5

5.5

6.0

6.5

7.0

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 97

PIC16C5X

FIGURE 14-13: MAXIMUM IDD VS. FREQUENCY (EXTERNAL CLOCK, –40C TO +85C)

FIGURE 14-14 : MAXIMUM IDD vs. FR EQUENCY (E XTERNAL CLOCK –55C TO +125C)

10K 100K 1M 10M 100M

0.01

0.1

1.0

IDD (mA)

External Clock Frequency (Hz)

5.0

4.5

4.0

3.5

5.5

6.0

6.5

7.0

2.5

3.0

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

10K 100K 1M 10M 100M

0.01

0.1

1.0

IDD (mA)

External Clock Frequency (Hz)

5.0

4.5

4.0

2.5

3.0

3.5

5.5

6.0

6.5

7.0

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s ( -40°C to 125°C)

PIC16C5X

DS30453E-page 98 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 14-15 : WDT TIMER TIME-OUT

PERIOD vs. VDD(1) FIGURE 14-16: TRANSCONDUCTANCE

(gm) OF HS OSCILLATOR

vs. VDD

52.03.04.05.06.07.0

(Volts)

WDT period (ms)

Max +85



Max +70



Typ +25



MIn 0



MIn –40



Note 1: Prescaler set to 1:1.

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

9000

8000

7000

6000

5000

4000

3000

2000

100

2.0 3.0 4.0 5.0 6.0 7.0

VDD (Volts)

gm (A/V)

Min +85C

Max –40C

Typ +25C

Ty pical : statistica l mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 99

PIC16C5X

FIGURE 14-17: TRANSCONDUCTANCE

(gm) OF LP OSCILLATOR

vs. VDD

FIGURE 14-18: TRANSCONDUCTANCE

(gm) OF XT OSCILLATOR

vs. VDD

VDD (Volts)

gm (A/V)

Min +85C

Max –40C

Typ +25C

2.0 3.0 4.0 5.0 6.0 7.0

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s ( -40°C to 125°C)

2500

2000

1500

1000

500

VDD (Volts)

gm (A/V)

Min +85C

Max –40C

Typ +25C

2.0 3.0 4.0 5.0 6.0 7.0

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

PIC16C5X

DS30453E-page 100 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 14-19: PORTA, B AND C IOH vs.

VOH, VDD = 3 V FIGURE 14-20: PORTA, B AND C IOH vs.

VOH, VDD = 5 V

–5

–10

–15

–20

–25 0 0.5 1.0 1.5 2.0 2.5

VOH (Vo lts)

IOH (mA)

Min +85C

3.0

Typ +25C

Max –40C

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

–10

–20

–30

–401.5 2.0 2.5 3.0 3.5 4.0

VOH (Volts)

IOH (mA)

Min +85C

Max –40C

4.5 5.0

Typ +25C

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 101

PIC16C5X

FIGURE 14-21: PORTA, B AND C IOL vs.

VOL, VDD = 3 V FIGURE 14-22: PORTA, B AND C IOL vs.

VOL, VDD = 5 V

00.0 0.5 1.0 1.5 2.0 2.5

VOL (Volts)

IOL (mA)

Min +85C

Max –40C

Typ +25C

3.0

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125 °C)

Mini mum: mean – 3 s (-40°C to 125°C)

00.0 0.5 1.0 1.5 2.0 2.5

VOL (Vo lts)

IOL (mA)

Min +85C

Max –40C

Typ +25C

3.0

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

PIC16C5X

DS30453E-page 102 Preliminary  1997-2013 Microchip Technology Inc.

TABLE 14-2: INPUT CAPACITANCE FOR

PIC16C54/56

TABLE 14-3: INPUT CAPACITANCE FOR

PIC16C55/57

Pin Typical Capacitance (pF)

18L PDIP 18L SOIC

RA port 5.0 4.3

RB port 5.0 4.3

MCLR 17.0 17.0

OSC1 4.0 3.5

OSC2/CLKOUT 4.3 3.5

T0CKI 3.2 2.8

All capacitance values are typical at 25C. A part-to-part

variation of ±25% (three standard deviations) should be

taken into account.

Typical Capacitance (pF)

28L PDIP

(600 mil) 28L SOIC

RA port 5.2 4.8

RB port 5.6 4.7

RC port 5.0 4.1

MCLR 17.0 17.0

OSC1 6.6 3.5

OSC2/CLKOUT 4.6 3.5

T0CKI 4.5 3.5

All capacitance values are typical at 25C. A part-to-part

variation of ±25% (three standard deviations) should be

taken into account.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 103

PIC16C5X

15.0 ELECTRIC AL CHARACTERISTICS - PI C16C54A

Absolute Maximum Ratings(†)

Ambient temperature under bias...................................................................................................... –55°C to +125°C

Storage temperature....................................................................................................................... –65°C to +150°C

Volta ge on VDD with respect to VSS ............................................................................................................0 to +7.5V

Volta ge on MC LR with respect to VSS..........................................................................................................0 to +14V

Voltage on all other pi ns with respect to VSS ............................................................................–0.6V to (VDD + 0.6V)

Total power dissipa tion(1) ...............................................................................................................................800 mW

Max. current out of VSS pin..................... ...... ..... ............................. ..... ...... ..... ...... ............................ ...... ..... ...150 mA

Max. current into VDD pin................................................................................................................................100 mA

Input clamp current, IIK (VI < 0 or VI > VDD)20 mA

Output clamp current, IOK (VO < 0 or VO > VDD)20 mA

Max. output current sunk by any I/O pin ...........................................................................................................25 mA

Max. output current sourced by any I/O pin......................................................................................................20 mA

Max. output current sourced by a sing le I/O port (PORTA or B).......................................................................50 mA

Max. output current sunk by a single I/O port (PORTA or B) ............................................................................50 mA

Note 1: Pow er dissipation is calcu la ted as follows : Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOL x IOL)

† NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.

This is a s tres s ra ting onl y an d functional opera tio n of th e de vice at those or any oth er co nd itio ns above those indi -

cated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

PIC16C5X

DS30453E-page 104 Preliminary  1997-2013 Microchip Technology Inc.

15.1 DC Characteristics: PIC16C54A-04, 10, 20 (Comme rcial)

PIC16C54A-04I, 10I, 20I (Industrial)

PIC16LC54A-04 (Commercial)

PIC16LC54A-04I (I ndustrial)

PIC16LC54A-04

PIC16LC54A-04I

(Commercial, Industrial)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C  TA  +70°C for comm erc ial

–40°C  TA  +85°C for industrial

PIC16C54A-04, 10, 20

PIC16C54A-04I, 10I, 20I

(Commercial, Industrial)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C  TA  +70°C for commercial

–40°C  TA  +85°C for industrial

Param

No. Symbol Characteristic/Device Min Typ† Max Units Conditions

VDD Supply Voltage

D001 PIC16LC54A 3.0

2.5 —

—6.25

6.25 V

VXT and RC modes

LP mode

D001A PIC16C54A 3.0

4.5 —

—6.25

5.5 V

VRC, XT and LP modes

HS mode

D002 VDR RAM Data Retention

Voltage(1) — 1.5* — V Device in SLEEP mode

D003 VPOR VDD Start Voltage to

ensure Power-on Reset — Vss — V See Sect ion 5.1 for details on

Power-on Rese t

D004 SVDD VDD Rise Rate to ensure

Power-on Reset 0.05* — — V/ms See Section 5.1 for details on

Power-on Rese t

IDD Supply Current(2)

D005 PIC16LC5X —

—

0.5

2.5

A

FOSC = 4.0 MH z, VDD = 5.5V,

RC(3) and XT modes

FOSC = 32 kHz, VDD = 2.5V,

WDT disabled, LP mode, Commercial

FOSC = 32 kHz, VDD = 2.5V,

WDT disabled, LP mode, Industrial

D005A PIC16C5X —

—

1.8

2.4

4.5

2.4

8.0

A

FOSC = 4.0 MH z, VDD = 5.5V,

RC(3) and XT modes

FOSC = 10 MHz, VDD = 5.5V, HS mode

FOSC = 20 MHz, VDD = 5.5V, HS mode

FOSC = 32 kHz, VDD = 3.0V,

WDT disabled, LP mode, Commercial

FOSC = 32 kHz, VDD = 3.0V,

WDT disabled, LP mode, Industrial

Legend: Rows with standard voltage device data only are shaded for improved readability.

* These parameters are characterized but not tested.

† Data in “T yp ” column is based on characteriza tio n res ul ts at 2 5°C . Th is da ta i s fo r de sign guidance onl y a nd

is not tested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

2: The supp ly current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square

wave, from ra il-t o-rai l; al l I/O pi ns tri stated, pulled to V SS, T0 CKI = VDD, MCLR = VDD; WDT en abl ed/

dis abled as spec ified.

b) For standby current measurements, the conditions are the same, except that the device is in SLEEP

mode. The power-down current in SLEEP mode does not depend on the oscillator type.

3: Does not inclu de current through REXT. The current through the resistor can be estimated by the formula:

IR=VDD/2REXT (mA) with REXT in k.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 105

PIC16C5X

IPD Power-down Current(2)

D006 PIC16LC5X —

—

2.5

0.25

2.5

0.25

4.0

5.0

A

VDD = 2.5V, WDT enabled, Commercial

VDD = 2.5V, WDT disabled, Commercial

VDD = 2.5V, WDT enabled, Industrial

VDD = 2.5V, WDT disabled, Industrial

D006A PIC16C5X —

—

4.0

0.25

5.0

0.3

4.0

5.0

A

VDD = 3.0V, WDT enabled, Commercial

VDD = 3.0V, WDT disabled, Commercial

VDD = 3.0V, WDT enabled, Industrial

VDD = 3.0V, WDT disabled , Industrial

15.1 DC Characteristics: PIC16C54A-04, 10, 20 (Comme rcial)

PIC16C54A-04I, 10I, 20I (Industrial)

PIC16LC54A-04 (Commercial)

PIC16LC54A-04I (I ndustrial)

PIC16LC54A-04

PIC16LC54A-04I

(Commercial, Industrial)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C  TA  +70°C for commerc ial

–40°C  TA  +85°C for industrial

PIC16C54A-04, 10, 20

PIC16C54A-04I, 10I, 20I

(Commercial, Industrial)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C  TA  +70°C for commercial

–40°C  TA  +85°C for industrial

Param

No. Symbol Characteristic/Device Min Typ† Max Units Conditions

Legend: Rows with standard voltage device data only are shaded for improved readability.

* These parameters are characterized but not tested.

† Data in “T yp” column is bas ed on characteriza tio n res ul ts at 2 5°C . Th is da ta i s fo r design guidan ce onl y a nd

is not tested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

2: The supp ly current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square

wave, from ra il-t o-rai l; al l I/O pi ns tri stated, pulled to V SS, T0 CKI = VDD, MCLR = VDD; WDT en abl ed/

dis abled as spec ified.

b) For standby current measurements, the conditions are the same, except that the device is in SLEEP

mode. The power-down current in SLEEP mode does not depend on the oscillator type.

3: Does not inclu de current through REXT. The current through the resistor can be estimated by the formula:

IR=VDD/2REXT (mA) with REXT in k.

PIC16C5X

DS30453E-page 106 Preliminary  1997-2013 Microchip Technology Inc.

15.2 DC Characteristi cs: PIC16C54A-04E, 10 E, 20E (Extended)

PIC16LC54A-04E (Extended)

PIC16LC54A-04E

(Extended) Standard Operatin g Cond itions (unless otherwise speci fied)

Operating Temperature –40°C  TA  +125C for extended

PIC16C54A-04E, 10E, 20E

(Extended) Standard Operatin g Cond itions (unless otherwise speci fied)

Operating Temperature –40°C  TA  +125C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

VDD Supply Voltage

D001 PIC16LC54A 3.0

2.5 —

—6.25

6.25 V

VXT and RC modes

LP mode

D001A PIC16C54A 3.5

4.5 —

—5.5

5.5 V

VRC and XT modes

HS mode

D002 VDR RAM Data Retention Voltage(1) — 1.5* — V Device in SLEEP mode

D003 VPOR VDD Start Voltage to ensure

Power-on Reset — Vss — V See Section 5.1 for details on

Power-on Reset

D004 SVDD VDD Rise Rate to ensure

Power-on Reset 0.05* — — V/ms See Section 5.1 for details on

Power-on Reset

IDD Supply Current(2)

D010 PIC16LC54A —

—

0.5

A

FOSC = 4.0 MHz, VDD = 5.5V,

RC(3) and XT modes

FOSC = 32 kHz, VDD = 2.5V,

LP mode, Comm ercial

FOSC = 32 kHz, VDD = 2.5V,

LP mode, Industrial

FOSC = 32 kHz, VDD = 2.5V,

LP mode, Extended

D010A PIC16C54A —

—

1.8

4.8

9.0

3.3

FOSC = 4.0 MHz, VDD = 5.5V,

RC(3) and XT modes

FOSC = 10 MHz, VDD = 5.5V,

HS mode

FOSC = 20 MHz, VDD = 5.5V,

HS mode

Legend: Rows with standard voltage device data only are shaded for improved readability.

* These parameters are characterized but not tested.

† Data in the Typic al (“Typ”) c olu mn is bas ed on characteriza tio n res ul t s at 25C. This dat a is fo r des ig n gu id-

ance only and is not tested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

2: The supp ly current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square

wave, from rail-t o-rail; all I/O pin s tristate d, pulle d to VSS, T0CKI = VDD, MCLR = VDD; WDT enabl ed/

dis abled as spec ified.

b) For standby current measurements, the conditions are the same, except that the device is in SLEEP

mode. The power-down current in SLEEP mode does not depend on the oscillator type.

3: Does not inclu de current through REXT. The current through the resistor can be estimated by the formula:

IR= VDD/2REXT (mA) with REXT in k.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 107

PIC16C5X

IPD Power-down Current(2)

D020 PIC16LC54A —

—

2.5

0.25

7.0

A

VDD = 2.5V, WDT enabled,

Extended

VDD = 2.5V, WDT disabled,

Extended

D020A PIC16C54A —

—5.0

0.8 22

18* A

AVDD = 3.5V, WDT enabled

VDD = 3.5V, WDT disabled

15.2 DC Characteristi cs: PIC16C54A-04E, 10 E, 20E (Extended)

PIC16LC54A-04E (Extended)

PIC16LC54A-04E

(Extended) Standard Operatin g Conditions (unless otherwis e s pecified)

Operating Temperature –40°C  TA  +125C for extended

PIC16C54A-04E, 10E, 20E

(Extended) S tandard Oper atin g Cond itions (unl ess othe rwis e s pecified)

Operating Temperature –40°C  TA  +125C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

Legend: Rows with standard voltage device data only are shaded for improved readability.

* These parameters are characterized but not tested.

† Data in the Typic al (“T y p”) c olu mn is bas ed on characteriza tio n res ul t s at 25C. This data is for desig n gu id -

ance only and is not tested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

2: The supp ly current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square

wave, from rail-t o-rail; all I/O pin s tristate d, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabl ed/

dis abled as spec ified.

b) For standby current measurements, the conditions are the same, except that the device is in SLEEP

mode. The power-down current in SLEEP mode does not depend on the oscillator type.

3: Does not inclu de current through REXT. The current through the resistor can be estimated by the formula:

IR= VDD/2REXT (mA) with REXT in k.

PIC16C5X

DS30453E-page 108 Preliminary  1997-2013 Microchip Technology Inc.

15.3 DC Characteristi cs:PIC16LV54A-02 (Commercial)

PIC16LV54A-02I (Industrial)

PIC16LV54A-02

PIC16LV54A-02I

(Commercial, Industrial)

Standard Operating Cond itions (unless otherwise specified)

Operating Temperature 0C  TA  +70C for commercial

–20C  TA  +85C for industrial

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

D001 VDD Supply Voltage

RC and XT modes 2.0 — 3.8 V

D002 VDR RAM Data Retention

Voltage(1) — 1.5* — V Device in SLEEP mode

D003 VPOR VDD St ar t Volt age to ensur e

Power-on Rese t — Vss — V See Section 5.1 for details on

Power-on Reset

D004 SVDD VDD Rise Rate to ensure

Power-on Rese t 0.05* — — V/ms See Section 5.1 for details on

Power-on Reset

D010 IDD Supply Current(2)

RC(3) and XT modes

LP mode, Commercial

LP mode, Industrial

—

0.5

—

A

FOSC = 2.0 MHz, VDD = 3.0V

FOSC = 32 kHz, VDD = 2.5V WDT disabled

D020 IPD Power-down Current(2,4)

Commercial

Industrial

—

2.5

0.25

3.5

0.3

4.0

5.0

A

VDD = 2.5V, WDT enabled

VDD = 2.5V, WDT disabled

VDD = 2.5V, WDT enabled

VDD = 2.5V, WDT disabled

* These parameters are characterized but not tested.

† Data in the Ty pical (“Typ”) column is based on characterization results at 25C. This data is for design guid-

ance only and is not tested.

Note 1: This is the limit to w hich VDD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, os cillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current cons ump tio n.

a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square

wave, from rail- to-ra il; all I/O pi ns trist ated, pulled to VSS, T0CKI = VDD, MCLR =VDD; WDT enabled/

dis abled as spec ified.

b) For standby current meas urements, the conditions are the same, except that the device is in SLEEP

mode. The power-down current in SLEEP mode does not depend on the oscillator type.

3: Does not include current through REXT. The current through the resistor can be estimated by the formula:

IR=VDD/2REXT (mA) with REXT in k.

4: The oscil lator s tart -up t ime c an be a s muc h as 8 seco nds for XT and L P oscil lat or select ion on wake -up from

SLEEP mode or during initial power-up.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 109

PIC16C5X

15.4 DC Characteristics: PIC16C54A-04, 10, 20, PIC16LC54A-04, PIC16LV54A-02 (Commercial)

PIC16C54A-04I, 10I, 20I, PIC16LC54A-04I, PIC16LV54A-02I (Industrial)

PIC16C54A-04E, 10E, 20E, PIC16LC54A-04E (Extended)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0C  TA  +70C for commercial

–40C  TA  +85C for industrial

–20C  TA  +85C for industrial-PIC16LV54A-02I

–40°C  TA  +125C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

D030 VIL Input Low Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

VSS

—

0.2 VDD

0.15 VDD

0.3 VDD

Pin at hi-impedance

RC mod e only (3)

XT, HS and LP modes

D040 VIH Input High Voltage

I/O ports

MCLR (Schmi tt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

0.2 VDD + 1

2.0

0.85 VDD

0.7 VDD

—

VDD

For all VDD(4)

4.0V < VDD 5.5V(4)

RC mode only(3)

XT, HS and LP modes

D050 VHYS Hysteresis of Schmitt

Trigger inputs 0.15 VDD*— — V

D060 IIL Input Leakage Current(1,2)

I/O ports

MCLR

T0CKI

OSC1

-1.0

-5.0

—

-3.0

0.5

—

0.5

+1.0

+5.0

+3.0

—

A

For VDD  5.5V:

VSS  VPIN  VDD,

pin at hi-impeda nce

VPIN = VSS +0.25V

VPIN = VDD

VSS  VPIN VDD

VSS  VPIN  VDD,

XT, HS and LP modes

D080 VOL Output Low Voltage

I/O ports

OSC2/CLKOUT —

——

—0.6

0.6 V

VIOL = 8.7 mA, VDD = 4.5V

IOL = 1.6 mA, VDD = 4.5V,

RC mode only

VOH Output High Volt age(2)

I/O ports

OSC2/CLKOUT VDD - 0.7

VDD - 0.7 —

——

—V

VIOH = -5 .4 mA, V DD = 4. 5V

IOH = -1 .0 mA, V DD = 4. 5V,

RC mode only

* These parameters are characterized but not tested.

† Data in the T ypical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only

and is not tested.

Note 1: The l eakage current on the MCLR/VPP pin is st ro ngl y dependent on t he applied voltage lev el . The specified level s

repre sent normal operating con di tio ns. H i ghe r leakage curr ent m ay be measured at d ifferent input vol tag e.

2: Nega tive current is def i ne d as co m i ng out of the pin.

3: For the R C mode , the OSC1/CLKIN pi n is a Schmitt Trigger input. It is not rec om m en ded that the PIC16C5X be

driven with external clock in RC mode.

PIC16C5X

DS30453E-page 110 Preliminary  1997-2013 Microchip Technology Inc.

15.5 Timing Parameter Symbology and Load Conditions

The timing parameter symbols have been created with one of the following formats:

FIGURE 15-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS - PIC16C54A

1. TppS2ppS

2. TppS

TF Frequency T Time

Lowercase letters (pp) and their meanings:

2to mcMCLR

ck CLKOUT osc oscillator

cy cycle time os OSC1

drt device reset timer t0 T0CKI

io I/O port wdt watchdog timer

Uppercase letters and thei r meanings:

SFFall PPeriod

HHigh RRise

I Invalid (Hi-impe dan ce ) V Valid

L Low Z Hi-impedance

CL = 50 pF for all pins and OSC2 for RC modes

0 -15 pF for OSC2 in XT, HS or LP mo des when

external clock is used to drive OSC1

VSS

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 111

PIC16C5X

15.6 Timing Diagrams and Specifications

FIGURE 15-2: EXTERNAL CLOCK TIMING - PIC16C54A

TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54A

AC Characteristics

Standard Operating Conditi ons (unle ss otherwis e specified)

Operating Temperature 0C  TA  +70C for commercial

–40C  TA  +85C for industrial

–20C  TA  +85C for industrial - PIC16LV54A-02I

–40C  TA  +125C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

FOSC External CLKIN Fre-

quency(1) DC — 4.0 MHz XT OSC mode

DC — 2.0 MHz XT OSC mode (PIC16LV54A)

DC — 4.0 MHz HS OSC mode (04)

DC — 10 MHz HS OSC mode (10)

DC — 20 MHz HS OSC mode (20)

DC — 200 kHz LP OSC mode

Oscillator Frequency(1) DC — 4.0 MHz RC OSC mode

DC — 2.0 MHz RC OSC mode (PIC16LV54A)

0.1 — 4.0 MHz XT OSC mode

0.1 — 2.0 MHz XT OSC mode (PIC16LV54A)

4.0 — 4.0 MHz HS OSC mode (04)

4.0 — 10 MHz HS OSC mode (10)

4.0 — 20 MHz HS OSC mode (20)

5.0 — 200 kHz LP OSC mode

* These parameters are characterized but not tested.

† Dat a i n the Typical (“Typ”) col um n i s bas ed on characteriz at ion results at 25 C. This data is for design guid-

ance only and is not tested.

Note 1: All specified values are based on characterization data for that particular oscillator type under standard

operating conditions with the device executing code. Exceeding these specified limits may result in an

unstable oscillator operation and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

2: Instruction cycl e period (TCY) equals four times the input oscillator time base period.

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

133

PIC16C5X

DS30453E-page 112 Preliminary  1997-2013 Microchip Technology Inc.

1TOSC External CLKIN Period(1) 250 — — ns XT OSC mode

500 — — ns XT OSC mode (PIC16LV54A)

250 — — ns HS OSC mode (04)

100 — — ns HS OSC mode (10)

50 — — ns HS OSC mode (20)

5.0 — — sLP

OSC mode

Oscillator Period(1) 250 — — ns RC OSC mode

500 — — ns RC OSC mode (PIC16LV54A)

250 — 10,000 ns XT OSC mode

500 — — ns XT OSC mode (PIC16LV54A)

250 — 250 ns HS OSC mode (04)

100 — 250 ns HS OSC mode (10)

50 — 250 ns HS OSC mode (20)

5.0 — 200 sLP

OSC mode

2 Tcy Instruction Cycle Time(2) —4/FOSC ——

3 TosL, TosH Clock in (OSC1) Low or

High Time 85* — — ns XT oscillator

20* — — ns HS oscillator

2.0* — — s LP oscillator

4 TosR, TosF Clock in (OSC1) Rise or

Fall Time — — 25* ns XT oscillator

— — 25* ns HS oscillator

— — 50* ns LP oscil lat or

TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54A

AC Characteristics

Standard Operating Conditi ons (unle ss otherwis e specified)

Operating Temperature 0C  TA  +70C for commercial

–40C  TA  +85C for industrial

–20C  TA  +85C for industrial - PIC16LV54A-02I

–40C  TA  +125C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

* These parameters are characterized but not tested.

† Dat a i n the Typical (“Typ”) col umn i s bas ed o n c ha r ac teri zat ion re sul t s at 25C. This data is for design guid-

ance only and is not tested.

Note 1: All specified values are based on characterization data for that particular os cillator type under standard

operating conditions with the device executing code. Exceeding these specified limits may result in an

unstable oscillator operation and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

2: Instruction cycl e period (TCY) equals four times the input oscillator time base period.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 113

PIC16C5X

FIGURE 15-3: CLKOUT AND I/O TIMING - PIC16C54A

TABLE 15-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54A

AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0C  TA  +70C for commercial

–40C  TA  +85C for industrial

–20C  TA  +85C for industrial - PIC16LV54A-02I

–40C  TA  +125C for extended

Param

No. Symbol Characteristic Min Typ† Max Units

10 TosH2ckL OSC1 to CLKOUT(1) —1530**ns

11 TosH2ckH OSC1 to CLKOUT(1) —1530**ns

12 TckR CLKOUT rise time(1) —5.015**ns

13 TckF CLKOUT fall time(1) —5.015**ns

14 TckL2ioV CLKOUT to Port out valid(1) ——40**ns

15 TioV2ckH Port in valid before CLKOUT(1) 0.25 TCY+30* — — ns

16 TckH2ioI Port in hold after CLKOUT(1) 0* — — ns

17 TosH2ioV OSC1 (Q1 cycle) to Port out valid(2) — — 100* ns

18 TosH2ioI OSC1 (Q2 cycle) to Port input invalid

(I/O in hold time) TBD — — ns

19 TioV2osH Port input valid to OSC1

(I/O in setup time) TBD — — ns

20 TioR Port output rise time(2) —1025**ns

21 TioF Port output fall time(2) —1025**ns

* These parameters are chara cte riz ed but not tested .

** These parameters are design targets and are not tested. No characterization data available at this time.

† Dat a in th e Typic al ( “Typ”) colu mn is base d on c harac terizat ion res ult s at 25C. This dat a is for des ign g uid-

ance only and is not tested.

Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

2: Please refer to Figure 15-1 for load conditions.

OSC1

CLKOUT

I/O Pin

(input)

I/O Pin

(output)

Q4 Q1 Q2 Q3

13 14

20, 21

12 16

Old Value New Value

Note: Please refer to Figure 15-1 for load conditions.

PIC16C5X

DS30453E-page 114 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 15-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C54A

TABLE 15-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54A

AC Charac teristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0C  TA  +70C for commercial

–40C  TA  +85C for industrial

–20C  TA  +85C for industrial - PIC16LV54A-02I

–40C  TA  +125C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

30 TmcL MCLR Pulse Width (low) 100*

1—

——

—ns

sVDD = 5.0V

VDD = 5.0V (PIC16LV54A only)

31 Twdt Watchdog Timer Time-out

Period (No Prescaler) 9.0* 18* 30* ms VDD = 5.0V (Comm)

32 TDRT Device Reset Timer Period 9.0* 18* 30* ms VDD = 5.0V (Comm)

34 TioZ I/O Hi-impedance from MCLR

Low —

——

—100*

1sns

— (PIC16LV54A only)

* These parameters are characterized but not tested.

† D ata i n th e Ty pica l ( “Typ”) colu mn i s at 5V, 25 C unless otherwise stated. These parameters are for design

guidanc e onl y and are not tes ted .

VDD

MCLR

Internal

POR

DRT

Time-out

Internal

RESET

Watchdog

Timer

RESET

I/O pin

32 32

(Note 1)

Note 1: Pleas e refer to Figure 15-1 for load conditions.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 115

PIC16C5X

FIGURE 15-5: TIMER0 CLOCK TIMINGS - PIC16C54A

TABLE 15-4: TIMER0 CLOCK REQUIREMENTS - PIC16C54A

AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0C  TA  +70C for commercial

–40C  TA  +85C for industrial

–20C  TA  +85C for industrial - PIC16LV54A-02I

–40C  TA  +125C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

40 Tt0H T0CK I High Pulse Width

- No Prescal er 0.5 TCY + 20* — — ns

- With Prescaler 10* — — ns

41 Tt0L T0CKI Low Pulse Width

- No Presc aler 0.5 TCY + 20* — — ns

- With Prescale r 10* — — ns

42 Tt0P T0CKI Period 20 or TCY + 40*

N — — ns Whichever is greater.

N = Pre s c a l e Value

(1, 2, 4,..., 256)

* These parameters are characterized but not tested.

† Data in the Ty pical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

T0CKI

40 41

Note: Please refer to Figure 15-1 for load conditions.

PIC16C5X

DS30453E-page 116 Preliminary  1997-2013 Microchip Technology Inc.

NOTES:

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 117

PIC16C5X

16.0 DEVICE CHARACTERIZATION - PIC16 C 54A

The graphs and t ables prov ided followi ng this note are a st atistica l summary bas ed on a limit ed numb er of samples an d

are provided for informational purposes only. The performance characteristics listed herein are not tested or guaran-

teed. In some grap hs or tables, the data presented may be outsid e the sp ecified operati ng range (e.g., out side specifie d

power supply range) and therefore outside the warranted range.

“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3) or (mean

– 3) respectively, where  is a standard deviation, over the whole temperature range.

FIGURE 16-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE

TABLE 16-1: RC OSCILLATOR FREQUENCIES

CEXT REXT Average

Fosc @ 5 V, 25C

20 pF 3.3K 5 MHz  27%

5K 3.8 MHz  21%

10K 2.2 MHz  21%

100K 262 kHz  31%

100 pF 3.3K 1.6 MHz  13%

5K 1.2 MHz  13%

10K 684 kHz  18%

100K 71 kHz  25%

300 pF 3.3K 660 kHz  10%

5.0K 484 kHz  14%

10K 267 kHz  15%

100K 29 kHz  19%

The frequencies are measured on DIP packages.

The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation

indicated is 3 standard deviation from average value for VDD = 5V.

Fosc

Fosc (25C)

1.10

1.06

1.04

1.02

1.00

0.98

0.96

0.94

0.92

0.90

0202530405070

T(C)

Frequency normalized to +25C

VDD = 5.5V

VDD = 3.5V

REXT  10 k W

CEXT = 100 pF

0.88

1.08

PIC16C5X

DS30453E-page 118 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 16-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF, 25C

FIGURE 16-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF, 25C

3.5 4.5 5.5

2.5

FOSC (MHz)

R=3.3K

R=5K

R=10K

R=100K

4.0 5.0 6.0

VDD (Volts)

03.0

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

R=3.3K

R=5K

R=10K

R=100K

3.5 4.5

2.5

FOSC (MHz)

4.0 5.0 6.0

VDD (Volts)

03.0 5.5

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125 °C)

Minimum: mean – 3s (-40°C to 125°C)

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 119

PIC16C5X

FIGURE 16-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF, 25C

FOSC (kHz)

700

600

500

400

300

200

100

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

R=3.3K

R=5K

R=10K

R=100K

VDD (Volts)

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125 °C)

Minimum: mean – 3s (-40°C to 125°C)

PIC16C5X

DS30453E-page 120 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 16-5: TYPICAL IPD vs. VDD, WATCHDOG DISABLED (25C)

FIGURE 16-6: TYPICAL IPD VS. VDD, WATCHDOG ENABLED (25C)

2.5

2.0

1.5

1.0

2.5 3.0 3.5 4.0 4.5 5.0

VDD (Volts)

0.5

05.5 6.0

IPD (A)

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

25.00

20.00

15.00

10.00

5.00

0.00

2.5 3 3.5 4.5 5.5456

VDD (Volts)

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 121

PIC16C5X

FIGURE 16-7: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS - VDD

FIGURE 16-8: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP

MODES) vs. VDD

2.0

1.8

1.6

1.4

1.2

1.0

2.5 3.0 3.5 4.0 4.5 5.0

VDD (Volts)

Min (–40C to +85C)

0.8

0.6 5.5 6.0

Max (–40C to +85C)

Typ (+25C)

VTH (Volts)

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

2.4

2.2

2.0

1.8

1.6

1.4

2.5 3.0 3.5 4.0 4.5 5.0

VDD (V olts)

1.2

1.0 5.5 6.0

Typ (+25C)

VTH (Volts)

2.6

2.8

3.0

3.2

3.4

Max (–40C to +85C)

Min (–40C to +85C)

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

PIC16C5X

DS30453E-page 122 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 16-9: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD

3.5

3.0

2.5

2.0

1.5

1.0

2.5 3.0 3.5 4.0 4.5 5.0

VDD (Volts)

0.5

0.0 5.5 6.0

VIH, VIL (Volts)

4.0

4.5

min (–40C to +85C)

max (–40C to +85C)

typ +25C

min (–40C to +85C)

max (–40C to +85C)

Vil typ +25C

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

Note: These input pins have Schmitt Trigger input buffers.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 123

PIC16C5X

FIGURE 16-10: TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 20 PF, 25C)

FIGURE 16-11: MAXIMUM IDD vs. FREQUENCY

(WDT DISABLED, RC MODE @ 20 PF, –40C to +85C)

10000

1000

100

100.1 1 10

IDD (A)

6.0V

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

Freq (MHz)

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

10000

1000

100

10 110

IDD (A)

6.0V

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

0.1 Freq (MHz)

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

PIC16C5X

DS30453E-page 124 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 16-12: TYP ICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 100 PF, 25C)

FIGURE 16-13 : MAXIMUM IDD vs. FREQUENCY

(WDT DISABLED, RC MODE @ 100 PF, –40C to +85C)

10000

1000

100

0.01 110

IDD (A)

6.0V

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

Freq (MHz)

0.1

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125 °C)

Mini mum: mean – 3 s (-40°C to 125 °C)

10000

1000

100

100.01 110

IDD (A)

Freq (MHz)

0.1

6.0V

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 125

PIC16C5X

FIGURE 16-14: TYP ICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 300 PF, 25C)

FIGURE 16-15 : MAXIMUM IDD vs. FREQUENCY

(WDT DISABLED, RC MODE @ 300 PF, –40C to +85C)

10000

1000

100

0.01 0.1 1

IDD (A)

Freq (MHz)

6.0V

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

1000

100

0.01 0.1

IDD (A)

6.0V

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

Freq (MHz) 1

10000

Typ ical: statistical mean @ 25°C

Maximu m: mean + 3s (-40°C to 125 °C )

Minimum: mean – 3s (-40°C to 125°C)

PIC16C5X

DS30453E-page 126 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 16-16 : WDT TIMER TIME-OUT

PERIOD vs. VDD(1) FIGURE 16-17: TRANSCONDUCTANCE

(gm) OF HS OSCILLATOR

vs. VDD

52.0 3.0 4.0 5.0 6.0 7.0

VDD (Volts)

WDT period (ms)

Max +85C

Max +70C

Typ +25C

MIn 0C

MIn –40C

Note 1: Prescaler set to 1:1.

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

9000

8000

7000

5000

4000

100

VDD (Volts)

gm (A/W)

Min +85C

Max –40C

Typ +25C

2.0 3.0 4.0 5.0 6.0 7.0

6000

3000

2000

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 127

PIC16C5X

FIGURE 16-18: TRANSCONDUCTANCE

(gm) OF LP OSCILLATOR

vs. VDD

FIGURE 16-19: TRANSCONDUCTANCE

(gm) OF XT OSCILLATOR

vs. VDD

VDD (Volts)

gm (A/V)

Min +85C

Max –40C

Ty p +2 5 C

2.0 3.0 4.0 5.0 6.0 7.0

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

2500

2000

1500

1000

500

VDD (Volts)

gm (A/V)

Min +85C

Max –40C

Ty p +2 5C

2.0 3.0 4.0 5.0 6.0 7.0

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125 °C)

Mini mum: mean – 3 s (-40°C to 125 °C)

PIC16C5X

DS30453E-page 128 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 16-20: PORTA, B AND C IOH vs.

VOH, VDD = 3V FIGURE 16-21: PORTA, B AND C IOH vs. VOH,

VDD = 5V

–5

–10

–15

–20

–25 0 0.5 1.0 1.5 2.0 2.5

VOH (Vo lts)

IOH (mA)

Min +85C

3.0

Typ +25C

Max –40C

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

–10

–20

–30

–401.52.02.53.03.54.0

VOH (Volts)

IOH (mA)

Min +85C

Max –40C

4.5 5.0

Typ +25C

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 129

PIC16C5X

FIGURE 16-22: PORTA, B AND C IOL vs.

VOL, VDD = 3V

TABLE 16-2: INPUT CAPACITANCE FOR

PIC16C54A/C58A

FIGURE 16-23: PORTA, B AND C IOL vs.

VOL, VDD = 5V

Pin Typical Capacitance (pF)

18L PDIP 18L SOIC

RA port 5.0 4.3

RB port 5.0 4.3

MCLR 17.0 17.0

OSC1 4.0 3.5

OSC2/CLKOUT 4.3 3.5

T0CKI 3.2 2.8

All capacitance values are typical at 25C. A part-to-part

variation of 25% (three standard deviations) should be

taken into account.

00.0 0.5 1.0 1.5 2.0 2.5

VOL (Volts)

IOL (mA)

Min + 85C

Max –40C

Typ +25C

3.0

Typ ical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

00.0 0.5 1.0 1.5 2.0 2.5

VOL (Volts)

IOL (mA)

Min +85C

Max –40C

Ty p +2 5C

3.0

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s ( -40°C to 125°C)

PIC16C5X

DS30453E-page 130 Preliminary  1997-2013 Microchip Technology Inc.

NOTES:

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 131

PIC16C5X

17.0 ELECTRICAL CHARACTERISTICS - PIC16LC54A

Abso lute Maximum Ratings(†)

Ambient temperature under bias............................................................................................................–55°C to +125°C

Storage temperature............................................................................................................................. –65°C to +150°C

Volta ge on VDD with respect to VSS ..................................................................................................................0 to +7.5V

Volta ge on MC LR with respect to VSS................................................................................................................0 to +14V

Voltage on all other pi ns with respect to VSS ................................................................................. –0.6V to (VDD + 0.6V)

Total power dissipa tion(1) .....................................................................................................................................800 mW

Max. current out of VSS pin..................... ...... ..... ............................. ..... ...... ..... ...... ............................ ...... ..... .........150 mA

Max. current into VDD pin......................................................................................................................................100 mA

Max. current into an inp ut pin (T0CKI onl y)500 A

Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA

Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA

Max. output current sunk by any I/O pin .................................................................................................................25 mA

Max. output current sourced by any I/O pin............................................................................................................20 mA

Max. output current sourced by a single I/O (Port A, B or C) .................................................................................50 mA

Max. output current sunk by a single I/O (Port A, B or C).......................................................................................50 mA

Note 1: Pow er dissipation is calcu la ted as follows : Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOL x IOL)

† NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.

This is a s tres s ra ting onl y an d functional opera tio n of th e de vice at those or any oth er co nd itio ns above those indi -

cated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

PIC16C5X

DS30453E-page 132 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 17-1: PIC16C5 4C/5 5A/5 6A/57 C/58B-04, 20 VOLTAGE-FREQUENCY GRAPH,

0C  TA  +70C (COMMERCIAL TEMPS )

FIGURE 17-2: PIC16C5 4C/5 5A/5 6A/57 C/58B-04, 20 VOLTAGE-FREQUENCY GRAPH,

-40C  TA  0C, +70C  TA  +125C (OUTSIDE OF COMMERCIAL TEMPS)

6.0

2.5

4.0

3.0

3.5

4.5

5.0

5.5

410

Frequency (MHz)

VDD

(Volts)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.

Please reference the Product Identification System section for the maximum rated speed of the parts.

6.0

2.5

4.0

3.0

3.5

4.5

5.0

5.5

410

Frequency (MHz)

VDD

(Volts)

2.0

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.

Please reference the Product Identification System section for the maximum rated speed of the parts.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 133

PIC16C5X

FIGURE 17-3: PIC16LC5 4C/5 5A/56 A/57 C /58B VOLTAGE-FREQUENCY GRAPH,

0C  TA  +85C

FIGURE 17-4: PIC16LC5 4C/5 5A/56 A/57 C/58B VOLTAGE-FREQUENCY GRAPH,

-40C  TA  0C

6.0

2.5

4.0

3.0

3.5

4.5

5.0

5.5

410

Frequency (MHz)

VDD

(Volts)

2.0

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.

Please reference the Product Identification System section for the maximum rated speed of the parts.

6.0

2.5

4.0

3.0

3.5

4.5

5.0

5.5

410

Frequency (MHz)

VDD

(Volts)

2.0

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.

Please reference the Product Identification System section for the maximum rated speed of the parts.

2.7

PIC16C5X

DS30453E-page 134 Preliminary  1997-2013 Microchip Technology Inc.

17.1 DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial)

PIC16LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial)

PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Indus trial)

PIC16LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial)

PIC16LC5X

PIC16LCR5X

(Comm ercial, Indu st rial )

Sta nda rd Oper at in g Cond itio ns (unless otherwise specif ied)

Operating Temperature 0C  TA  +70C for commercial

–40C  TA  +85C for ind ustrial

PIC16C5X

PIC16CR5X

(Comm ercial, Indu st rial )

Sta nda rd Oper at in g Cond itio ns (unless otherwise specif ied)

Operating Temperature 0C  TA  +70C for commercial

–40C  TA  +85C for ind ustrial

Param

No. Symbol Characteristic/Device Min Typ† Max Units Conditions

VDD Supply Voltage

D001 PIC16LC5X 2.5

2.7

2.5

—

5.5

–40C TA + 85C, 16LCR5X

–40C TA  0C, 16LC5X

0C TA + 85C 16LC5X

D001A PIC16C5X 3.0

4.5 —

—5.5

5.5 V

RC, XT, LP and HS mode

from 0 - 10 MHz

from 10 - 20 MHz

D002 VDR RAM Data Retention Volt-

age(1) — 1 .5* — V Device in SLEEP m od e

D003 VPOR VDD Start Voltage to ensure

Power-on Reset —VSS — V S e e Section 5.1 for de ta ils on

Power-on Res et

D004 SVDD VDD Rise Rate to ensure

Power-on Reset 0.05* — — V/m s See Section 5.1 for details on

Power-on Res et

Legend: Rows with standard voltage device data only are shaded for improved readability.

*Thes e pa rameters ar e ch ar act erized but no t test ed.

†Data in “ Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and

are no t t ested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode with out l osing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading,

osc i llator t ype, bus r ate, int ernal code executi on patt ern and tem peratur e also hav e an i m pact on t he current con-

sumption.

a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave,

from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WD T enabled/d isabled

as specified.

b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.

The power-down current in SLEEP mode does not depend on the oscillator type.

3: Does no t incl ude current through REXT. The cur re nt th ro ugh the resistor can be estimated by the form ula:

IR = VDD/2REXT (mA) with REXT in k.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 135

PIC16C5X

IDD Supply Current (2,3)

D010 PIC16LC5X —

—

0.5

2.4

A

FOSC = 4.0 MHz, V DD = 5. 5V, XT and

RC modes

FOSC = 32 kHz, V DD = 2.5V, LP mode,

Commercial

FOSC = 32 kHz, V DD = 2.5V, LP mode,

Industrial

D010A PIC16C5X —

—

1.8

2.6

4.5

2.4

3.6*

A

FOSC = 4 MHz, VDD = 5.5V, XT and RC

modes

FOSC = 10 MHz, VDD = 3.0V, HS mo de

FOSC = 20 MHz, VDD = 5.5V, HS mo de

FOSC = 32 kHz, V DD = 3.0V, LP mode,

Commercial

FOSC = 32 kHz, V DD = 3.0V, LP mode,

Industrial

17.1 DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial)

PIC16LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial)

PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Indus trial)

PIC16LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial)

PIC16LC5X

PIC16LCR5X

(Comm ercial, Indu st rial)

Sta nda rd Oper at in g Conditions (unless other wise sp ecified)

Operating Temperature 0C  TA  +70C for commercial

–40C  TA  +85C for ind ustrial

PIC16C5X

PIC16CR5X

(Comm ercial, Indu st rial)

Sta nda rd Oper at in g Conditions (unless other wise sp ecified)

Operating Temperature 0C  TA  +70C for commercial

–40C  TA  +85C for ind ustrial

Param

No. Symbol Characteristic/Device Min Typ† Max Units Conditions

Legend: Rows with standard voltage device data only are shaded for improved readability.

*Thes e pa rameters are characteri zed but not tested.

†Data in “ Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and

are no t t ested.

Note 1: This is the limit to which VDD can be lower ed in SLEEP mode wi th out losi ng RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading,

osc i llator t ype, bus r ate, int ernal code executi on patt ern and tem peratur e also hav e an i m pact on t he current con-

sumption.

a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave,

from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WD T enabled/d isabled

as specified.

b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.

The power-down current in SLEEP mode does not depend on the oscillator type.

3: Does no t incl ude current through REXT. The current through the resistor can be estimated by the formula:

IR = VDD/2REXT (mA) with REXT in k.

PIC16C5X

DS30453E-page 136 Preliminary  1997-2013 Microchip Technology Inc.

IPD Power-down Current(2)

D020 PIC16LC5X —

—

0.25

1.25

A

VDD = 2.5V, WDT disable d, Com m er ci al

VDD = 2.5V, WDT disable d, Ind us tri al

VDD = 2.5V, WDT enable d, Com m er ci a l

VDD = 2.5V, WDT enable d, Industrial

D020A PIC16C5X —

—

0.25

1.8

2.0

9.8

4.0

5.0

7.0*

8.0*

12*

14*

27*

30*

A

VDD = 3.0V, WDT disable d, Com m er ci al

VDD = 3.0V, WDT disable d, Ind us tri al

VDD = 5.5V, WDT disable d, Com m er ci al

VDD = 5.5V, WDT disable d, Ind us tri al

VDD = 3.0V, WDT enable d, Com m er ci a l

VDD = 3.0V, WDT enable d, Industrial

VDD = 5.5V, WDT enabled, Comm er cial

VDD = 5.5V, WDT enabled, Indus trial

17.1 DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial)

PIC16LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial)

PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Indus trial)

PIC16LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial)

PIC16LC5X

PIC16LCR5X

(Comm ercial, Indu st rial )

Sta nda rd Oper at in g Cond itio ns (unless otherwise specif ied)

Operating Temperature 0C  TA  +70C for commercial

–40C  TA  +85C for ind ustrial

PIC16C5X

PIC16CR5X

(Comm ercial, Indu st rial )

Sta nda rd Oper at in g Cond itio ns (unless otherwise specif ied)

Operating Temperature 0C  TA  +70C for commercial

–40C  TA  +85C for ind ustrial

Param

No. Symbol Characteristic/Device Min Typ† Max Units Conditions

Legend: Rows with standard voltage device data only are shaded for improved readability.

*Thes e pa rameters ar e ch ar act erized but no t test ed.

†Data in “ Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and

are no t t ested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode with out l osing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading,

osc i llator t ype, bus r ate, int ernal code executi on patt ern and tem peratur e also hav e an i m pact on t he current con-

sumption.

a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave,

from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WD T enabled/d isabled

as specified.

b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.

The power-down current in SLEEP mode does not depend on the oscillator type.

3: Does no t incl ude current through REXT. The cur re nt th ro ugh the resistor can be estimated by the form ula:

IR = VDD/2REXT (mA) with REXT in k.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 137

PIC16C5X

17.2 DC Characteristi cs:PIC16C54C/C55A/C56A/C 57C/C58B-04E, 20E (Extended)

PIC16CR54C/CR56A/CR57C/CR58B-04E, 20E (Extended)

PIC16C54C/C55A/C56A/C57C/C58B-04E, 20E

PIC16CR54C/CR56A/CR57C/CR58B-04E, 20E

(Extended)

St an dard Operating Conditi ons (un less otherwise specified)

Operating Temperature –40C  TA  +125C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

D001 VDD Supply Voltage 3.0

4.5 —

—5.5

5.5 V

RC, XT, LP, and HS mode

from 0 - 10 MHz

from 10 - 20 MHz

D002 VDR RAM Data Retention Voltage(1) — 1.5* — V Device in SLEEP mode

D003 VPOR VDD start voltage to ensure

Power-on Reset — Vss — V See Section 5.1 for details on

Power-on Reset

D004 SVDD VDD rise rate to ensure

Power-on Reset 0.05* — — V/ms See Section 5.1 for de tails on

Power-on Reset

D010 IDD Supply Current(2)

XT and RC(3) modes

HS mode —

—1.8

9.0 3.3

20 mA

mA FOSC = 4.0 MHz, VDD = 5.5V

FOSC = 20 MHz, VDD = 5.5V

D020 IPD Power-down Current(2) —

—

0.3

4.8

50*

60*

31*

68*

90*

A

VDD = 3.0V, WDT disabled

VDD = 4.5V, WDT disabled

VDD = 5.5V, WDT disabled

VDD = 3.0V, WDT enabled

VDD = 4.5V, WDT enabled

VDD = 5.5V, WDT enabled

* These parameters are characterized but not tested.

† Data in “ Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only,

and are not tested.

Note 1: This is the limit to w hich VDD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, os cillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current cons ump tio n.

a) The test conditions for all IDD meas urements in active Op eration mode are: OSC1 = ex ternal square

wave , from rail-to-rail; all I/ O pins trist ated, pulled to V SS, T0CKI = VDD, MCLR = VDD; WDT en abled/

disabled as specified.

b) For st andby current measuremen ts, the conditio ns are the s ame, except that the device is in SLEEP

mode. The power-down current in SLEEP mode does not depend on the oscillator type.

3: Does not include current through REXT. The current through the resistor can be estimated by the formula:

IR = VDD/2REXT (mA) with REXT in k.

PIC16C5X

DS30453E-page 138 Preliminary  1997-2013 Microchip Technology Inc.

17.3 DC Characteristi cs:PIC16C54C/C 55A/C56A/C57C/ C 58 B- 04 , 2 0 (Com me r ci al, In dus tr ia l, Ext end ed)

PIC16LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial)

PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, I ndustrial, Extended)

PIC16LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercia l, Industrial)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)

Operati ng Temperatur e 0°C  TA  +70C for commercial

–40C  TA  +85C for industrial

–40C  TA  +125C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

D030 VIL Input Low Voltage

I/O Ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

VSS

—

0.8 V

0.15 VDD

0.3 VDD

4.5V <VDD  5.5V

Otherwise

RC mode only(3)

XT, HS and LP modes

D040 VIH Input High Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

2.0

0.25 VDD+0.8

0.85 VDD

0.7 VDD

—

VDD

4.5V < VDD 5.5V

Otherwise

RC mode only(3)

XT, HS and LP modes

D050 VHYS Hysteres is of Schmitt

Trigger inputs 0.15 VDD*—— V

D060 IIL Input Leakage Current(1,2)

I/O ports

MCLR

T0CKI

OSC1

-1.0

-5.0

-3.0

0.5

—

0.5

+1.0

+5.0

+3.0

—

A

For VDD 5.5V:

VSS  VPIN  VDD,

pin at hi-impedance

VPIN = VSS +0.25V

VPIN = VDD

VSS  VPIN VDD

VSS  VPIN  VDD,

XT, HS and LP modes

D080 VOL Output Low Voltage

I/O ports

OSC2/CLKOUT —

——

—0.6

0.6 V

VIOL = 8.7 mA, VDD = 4.5V

IOL = 1.6 mA, VDD = 4.5V,

RC mode only

D090 VOH Output High Voltage(2)

I/O ports

OSC2/CLKOUT VDD - 0.7

VDD - 0.7 —

——

—V

VIOH = -5.4 mA, VDD = 4.5V

IOH = -1.0 mA, V DD = 4.5V,

RC mode only

* These parameters are characterized but not tested.

† Data in the Typical (“Typ”) column is based on charac terization results at 25C. This data is for design guid-

ance only and is not te sted.

Note 1: The leakage current on the MC LR/VPP pin is strongly dep end ent on the ap pli ed voltage level. The spe ci fie d

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltage.

2: Negative current is defined as coming out of the pin.

3: For the R C m ode, th e OSC1/ CLKIN p in is a Sch mitt Trigger i nput. I t is n ot rec ommende d that the PIC 16C5X

be driven with external cloc k in RC mode.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 139

PIC16C5X

17.4 Timing Parameter Symbology and Load Conditions

The timing parameter symbols have been created with one of the following formats:

1. TppS2ppS

2. TppS

TF Frequency T Time

Lowercase letters (pp) and their meanings:

2to mcMCLR

ck CLKOUT osc oscillator

cy cycle time os OSC1

drt device reset timer t0 T0CKI

io I/O port wdt watchdog timer

Uppe rcase letters and their meanings:

SFFall PPeriod

HHigh RRise

I Invalid (Hi-impedance) V Valid

L Low Z Hi-impedance

FIGURE 17-5: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS -

PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B-04, 20

CL = 50 pF for all pins and OSC2 for RC mode

0 -15 pF for OSC2 in XT, HS or LP mo des w hen

external clock is used to drive OSC1

VSS

PIC16C5X

DS30453E-page 140 Preliminary  1997-2013 Microchip Technology Inc.

17.5 Timing Diagrams and Specifications

FIGURE 17-6: EXTERN AL CLOCK TIMING - PIC16C5X, PIC16CR5X

TABLE 17-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C5X, PIC16CR5X

AC Charac teristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0C  TA  +70C for commercial

–40C  TA  +85C for industrial

–40C  TA  +125C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

FOSC External CLKIN Frequency(1) DC — 4.0 MHz XT OSC mode

DC — 4.0 MHz HS OSC mode (04)

DC — 20 MHz HS OSC mode (20)

DC — 200 kHz LP OSC mode

Oscill ator Frequency(1) DC — 4.0 MHz RC OSC mode

0.45 — 4.0 MHz XT OSC mode

4.0 — 4.0 MHz HS OSC mode (04)

4.0 — 20 MHz HS OSC mode (20)

5.0 — 200 kHz LP OSC mod e

OSC External CLKIN Period(1) 250 — — ns XT OSC mode

250 — — ns HS OSC mode (04)

50 — — ns HS OSC mode (20)

5.0 — — sLP

OSC mod e

Oscill ator Period(1) 250 — — ns RC OSC mode

250 — 2,200 ns XT OSC mode

250 — 250 ns HS OSC mode (04)

50 — 250 ns HS OSC mode (20)

5.0 — 200 sLP

OSC mod e

* These parameters are characterized but not tested.

† Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

Note 1: All specified values are based on characterization data for that particular oscil lat or ty pe und er s tandard oper-

ating conditions with the device executing code. Exceeding these specified limits may result in an unstable

oscillator operation and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

2: Instruction cycl e period (TCY) equals four times the input oscillator time base period.

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

133

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 141

PIC16C5X

2 Tcy Instru ction Cycle Time(2) —4/FOSC ——

3 TosL, TosH Clock in (OSC1) Low or High

Time 50* — — ns XT oscillator

20* — — ns HS oscillator

2.0* — — s LP oscillator

4 TosR, TosF Clock in (OSC1) Rise or Fall

Time — — 25* ns XT oscillator

— — 25* ns HS oscillator

— — 50* ns LP osci llator

TABLE 17-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C5X, PIC16CR5X

AC Charac teristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0C  TA  +70C for commercial

–40C  TA  +85C for industrial

–40C  TA  +125C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

* These parameters are characterized but not tested.

† Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

Note 1: All specified va lues are based on c hara cte riz ati on d at a for that particu lar osc il lat or ty pe und er s tandard oper-

ating conditions with the device executing code. Exceeding these specified limits may result in an unstable

oscillator operation and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

2: Instruction cycl e period (TCY) equals four times the input oscillator time base period.

PIC16C5X

DS30453E-page 142 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 17-7: CLKOUT AND I/O TIMING - PIC16C5X, PIC16CR5X

TABLE 17-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C5X, PIC16CR5X

AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C  TA  +7 0C for commerc ia l

–40C  TA  +85C for industrial

–40C  TA  +125C for extend ed

Param

No. Symbol Characteristic Min Typ† Max Units

10 TosH2ckL OSC1 to CLKOUT(1) — 15 30** ns

11 TosH2ckH OSC1 to CLKOUT(1) — 15 30** ns

12 TckR CLKOUT rise time(1) — 5.0 15** ns

13 TckF CLKOUT fall time(1) — 5.0 15** ns

14 TckL2ioV CLKOUT to Port out valid(1) — — 40** ns

15 TioV2ckH Port in valid be fore CLKOUT(1) 0.25 TCY+30* — — ns

16 TckH2ioI Port in hold after CLKOUT(1) 0* — — ns

17 TosH2ioV OSC1 (Q1 cycle) to Port out valid (2) — — 100* ns

18 TosH2ioI OSC1 (Q2 cycle) to Port input invalid

(I/O in hold time) TBD — — ns

19 Ti oV2osH Port input valid to OSC1

(I/O in setup time) TBD — — ns

20 TioR Port output rise time(2) — 10 25** ns

21 TioF Port output fall time(2) — 10 25** ns

* These parameters are characterized but not tested.

** These parameters are design targets and are not tested. No characterization data available at this time.

† Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

2: Refer to Figure 17-5 for load conditions.

OSC1

CLKOUT

I/O Pin

(input)

I/O Pin

(output)

Q4 Q1 Q2 Q3

13 14

20, 21

12 16

Old Value New Value

Note: Refer to Figure 17-5 for load conditions.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 143

PIC16C5X

FIGURE 17-8: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C5X,

PIC16CR5X

TABLE 17-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C5X, PIC16CR5X

AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C  TA  +70°C for commercial

–40°C  TA  +85°C for industrial

–40°C  TA  +125°C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

30 TmcL MCLR Pulse Width (low) 1000* — — ns VDD = 5.0V

31 Twdt Watchdog Timer Time-out Period

(No Prescaler) 9.0* 18* 30* ms VDD = 5.0V (Comm)

32 TDRT Device Reset Timer Period 9.0* 18* 30* ms VDD = 5.0V (Comm)

34 TioZ I/O Hi-impedance from MCLR Low 100* 300* 1000* ns

* These parameters are characterized but not tested.

† Data in t he Typ ical ( “Typ ”) col umn is at 5V, 25° C unle ss oth erwis e state d. Th ese param eter s are fo r des ign

guidance only and are not tested.

VDD

MCLR

Internal

POR

DRT

Time-out

Internal

RESET

Watchdog

Timer

RESET

I/O pin

32 32

(Note 1)

Note 1: Please refer to Figure 17-5 for load conditions.

PIC16C5X

DS30453E-page 144 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 17-9: TIMER0 CLOCK TIMINGS - PIC16C5X, PIC16CR5X

TABLE 17-4: TIMER0 CLOCK REQUIREMENTS - PIC16C5X, PIC16CR5X

AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C  TA  +70°C for commercial

–40°C  TA  +85°C for industrial

–40°C  TA  +125°C for extended

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

40 Tt0H T0CKI High Pulse Width

- No Prescaler 0.5 TCY + 20* — — ns

- With Prescaler 10* — — ns

41 Tt0L T0CKI Low Pu lse Widt h

- No Prescaler 0.5 TCY + 20* — — ns

- With Prescaler 10* — — ns

42 Tt0P T0CKI Period 20 or TCY + 40*

N — — ns Whichever is greater.

N = Pre scale Value

(1, 2, 4,..., 256)

* These para meters are chara cte riz ed but not tested .

† Data in the T ypical (“T yp”) column is at 5V , 25°C unless otherwise stated. These parameters are for design guid-

ance only and are not tested.

T0CKI

40 41

Note: Please refer to Figure 17-5 for load conditions.

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 145

PIC16C5X

18.0 DEVICE CHARACTERIZATION - PIC16LC54A

The graphs and t ables prov ided followi ng this note are a st atistica l summary bas ed on a limit ed numb er of samples an d

are provided for informational purposes only. The performance characteristics listed herein are not tested or guaran-

teed. In some grap hs or tables, the data presented may be outsid e the sp ecified operati ng range (e.g., out side specifie d

power supply range) and therefore outside the warranted range.

“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3) or (mean

– 3) respectively, where  is a standard deviation, over the whole temperature range.

FIGURE 18-1: TYPICAL RC OSCILLATOR FREQUENCY VS. TEMPERATURE

TABLE 18-1: RC OSCILLATOR FREQUENCIES

CEXT REXT Average

Fosc @ 5V, 25C

20 pF 3.3K 5 MHz ± 27%

5K 3.8 MHz ± 21%

10K 2.2 MHz ± 21%

100K 262 kHz ± 31%

100 pF 3.3K 1. 63 MHz ± 13%

5K 1.2 MHz ± 13%

10K 684 kHz ± 18%

100K 71 kHz ± 25%

300 pF 3.3K 660 kHz ± 10%

5.0K 484 kHz ± 14%

10K 267 kHz ± 15%

100K 29 kHz ± 19%

The frequencies are measured on DIP packages.

The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation

indicated is ±3 standard deviation from average value for VDD = 5V.

FOSC

FOSC (25C)

1.10

1.08

1.06

1.04

1.02

1.00

0.98

0.96

0.94

0.92

0.90

010 20253040506070

T(C)

Frequency normalized to +25C

VDD = 5.5V

VDD = 3.5V

REXT  10 kW

CEXT = 100 pF

0.88

PIC16C5X

DS30453E-page 146 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 18-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF, 25C

FIGURE 18-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF, 25C

(Volts)

R=100K

R=10K

R=3.3K

2.5 3.0 3.5 4.5 5.54.0 5.0 6.0

R=5K

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

(Volts)

1.8

1.6

0.6

1.0

0.2

R=100K

R=10K

R=5K

R=3.3K

OSC

(MHz)

1.4

2.5 3.0 3.5 4.5 5.5

4.0 5.0 6.0

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125 °C)

Minimum: mean – 3s (-40°C to 125°C)

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 147

PIC16C5X

FIGURE 18-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF, 25C

FIGURE 18-5: TYPICAL IPD vs. VDD, WATCHDOG DISABLED (25C)

VDD (Volts)

FOSC (kHz)

2.5 3.0 3.5 4.5 5.5

4.0 5.0 6.0

R=100K

R=10K

R=5K

R=3.3K

600

500

400

200

300

100

700

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s ( -40°C to 125°C)

(Volts)

(uA)

2.5 3.0 3.5 4.5 5.5

4.0 5.0 6.0

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

PIC16C5X

DS30453E-page 148 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 18-6: TYPICAL IPD vs. VDD, WATCHDOG ENABLED (25C)

FIGURE 18-7: TYPICAL IPD vs. VDD, WATCHDOG ENABLED (–40°C, 85°C)

VDD (Volts)

IPD (uA)

02.5 3.0 4.5 5.5

4.0 5.0 6.0

5.0

3.5

Ty pical : statistica l mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

VDD (Volts)

IPD (uA)

5.0

(-40C)

(+85C)

2.5 3.0 4.5 5.5

4.0 5.0 6.0

3.5

Ty pical : statistica l mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 149

PIC16C5X

FIGURE 18-8: VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF I/O PINS vs. VDD

FIGURE 18-9: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD

2.0

1.8

1.6

1.4

1.2

1.0

2.5 3.0 3.5 4.0 4.5 5.0

VDD (Volts)

0.8

0.6 5.5 6.0

Typ (+25C)

VTH (Volts)

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

3.5

3.0

2.5

2.0

1.5

1.0

2.5 3.0 3.5 4.0 4.5 5.0

VDD (Volts)

0.5

0.0 5.5 6.0

VIH, VIL (Volts)

4.0

4.5

min (–40C to +85C)

max (–40C to +85C)

typ +25C

min (–40C to +85C)

max (–40C to +85C)

typ +25C

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125 °C)

Mini mum: mean – 3 s (-40°C to 125 °C)

Note: These input pins have Schmitt Tr igger input buffers.

PIC16C5X

DS30453E-page 150 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 18-10 : VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF OSC1 INPUT (IN XT, HS

AND LP MODES) vs. VDD

FIGURE 18-11: TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 20 PF, 25C)

2.4

2.2

2.0

1.8

1.6

1.4

2.5 3.0 3.5 4.0 4.5 5.0

VDD (V olts)

1.2

1.0 5.5 6.0

Typ (+25C)

VTH (Volts)

2.6

2.8

3.0

3.2

3.4

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

TYPICAL IDD v s FREQ (RC MO DE @ 20pF/25C)

100

1000

10000

0.1 1 10

FREQ(MHz)

IDD(A)

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

5.5V

4.5V

3.5V

2.5V

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 151

PIC16C5X

FIGURE 18-12: TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 100 PF, 25C)

FIGURE 18-13: TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 300 PF, 25C)

TYPIC AL I DD vs FREQ(R C MODE @ 100 pF/25C)

100

1000

10000

0.1 1 10

FREQ(MHz)

IDD(A)

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

5.5V

4.5V

3.5V

2.5V

TYPIC AL I DD vs FREQ (RC MODE @ 300 pF/25C)

1000

10000

0.01 0.1 1

FREQ(MHz)

IDD(A)

100

Typ ical: statistical mean @ 25°C

Maximu m: mean + 3s (-40°C to 125 °C )

Minimum: mean – 3s (-40°C to 125°C)

5.5V

4.5V

3.5V

2.5V

PIC16C5X

DS30453E-page 152 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 18-14 : WDT TIMER TIME-OUT

PERIOD vs. VDD(1) FIGURE 18-15: PORTA, B AND C IOH vs.

VOH, VDD = 3 V

5.02.0

3.0

4.0 5.0 6.0 7.0

VDD (Volts)

WDT period (ms)

Typ +125C

Typ +85C

Typ +25C

Typ –40C

Note 1: Prescaler set to 1:1.

Typ ical: statistical mean @ 25°C

Maximu m: mean + 3s (-40°C to 125 °C )

Minimum: mean – 3s (-40°C to 125°C)

–5

–10

–20

–25 0 0.5 1.0 2.0 2.5

VOH (Volts)

IOH (mA)

Min +85C

3.0

Typ +25C

Max –40C

–15

1.5

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 153

PIC16C5X

FIGURE 18-16: PORTA, B AND C IOH vs.

VOH, VDD = 5 V FIGURE 18-17: PORTA, B AND C IOL vs.

VOL, VDD = 3 V

–20

–30

–401.5 2.0 2.5 3.0 3.5 4.0

VOH (Volts)

IOH (mA)

Typ –40C

4.5 5.0

Typ +85C

Typ +125C

Typ +25C

–10

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

00.0 0.5 1.0 1.5 2.0 2.5

VOL (Volts)

IOL (mA)

Min +85C

Max –40C

Typ +25C

3.0

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125°C)

Minimum: mean – 3s (-40°C to 125°C)

PIC16C5X

DS30453E-page 154 Preliminary  1997-2013 Microchip Technology Inc.

FIGURE 18-18: PORTA, B AND C IOL vs.

VOL, VDD = 5 V

TABLE 18-2: INPUT CAPACIT ANCE

Pin Typical Capacitance (pF)

18L PDIP 18L SOIC

RA port 5.0 4.3

RB port 5.0 4.3

MCLR 17.0 17.0

OSC1 4.0 3.5

OSC2/CLKOUT 4.3 3.5

T0CKI 3.2 2.8

All capacitance values are typical at 25C. A part-to-part

variation of ±25% (three standard deviations) should be

taken into account.

00.0 0.5 1.0 1.5 2.0 2.5

VOL (Vo lts)

IOL (mA)

Min +85C

Max –40C

Typ +25C

3.0

Typical: statistical mean @ 25°C

Maximum: mean + 3s (-40°C to 125 °C)

Minimum: mean – 3s (-40°C to 125°C)

 1997-2013 Microchip Technology Inc. Preliminary DS30453E-page 155

PIC16C5X

19.0 ELECTRICAL CHARACTERISTICS - PIC16LC54C 40MHz