! !
SLOS245E − MARCH 2000 − REVISED JANUAR Y 2005
1
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DSupply Voltage Range . . . 1.8 V to 3.6 V
DRail-to-Rail Input/Output
DHigh Bandwidth ...8 MHz
DHigh Slew Rate . . . 4.8 V/µs
DVICR Exceeds Rails ...−0.2 V to V
DD+ 0.2
DSupply Current . . . 650 µA/Channel
DInput Noise Voltage ...9 nV/√Hz at 10 kHz
DSpecified Temperature Range:
0°C to 70°C... Commercial Grade
−40°C to 125°C... Industrial Grade
DUltrasmall Packaging
DUniversal Operational Amplifier EVM
description
The TLV278x single supply operational amplifiers
provide rail-to-rail input and output capability. The
TLV278x takes the minimum operating supply
voltage down to 1.8 V over the extended industrial
temperature range (−40°C to 125°C) while adding
the rail-to-rail output swing feature. The TLV278x also provides 8 MHz bandwidth from only 650 µA of supply
current. The maximum recommended supply voltage is 3.6 V, which allows the devices to be operated from
(±1.8 V supplies down to ±0.9 V) two rechargeable cells.
The combination of wide bandwidth, low noise, and low distortion makes it ideal for high speed and high
resolution data converter applications.
All members are available in PDIP, SOIC, and the newer, smaller SOT -23 (singles), MSOP (duals), and TSSOP
(quads).
FAMILY PACKAGE TABLE
DEVICE VDD
[V] VIO
[µV] IDD/ch
[µA] IIB
[pA] GBW
[MHz] SLEW RATE
[V/µs] Vn, 1 kHz
[nV/√Hz]IO
[mA] SHUTDOWN RAIL-TO-
RAIL
TLV278x(A) 1.8−3.6 250 650 2.5 8 5 18 10 Y I/O
TLV276x(A) 1.8−3.6 550 20 3 0.5 0.23 95 5 Y I/O
TLV246x(A) 2.7−6 150 550 1300 6.4 1.6 11 25 Y I/O
TLV247x(A) 2.7−6 250 600 2.5 2.8 1.5 15 20 Y I/O
TLV244x(A) 2.7−10 300 750 1 1.81 1.4 16 2 — O
TLV277x(A) 2.5−5.5 360 1000 2 5.1 10.5 17 6 Y O
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
" #$%&'()*#&$ #+ ,-''.$* )+ &% /-01#,)*#&$ 2)*.
'&2-,*+ ,&$%&'( *& +/.,#%#,)*#&$+ /.' *3. *.'(+ &% .)+ $+*'-(.$*+
+*)$2)'2 4)'')$*5 '&2-,*#&$ /'&,.++#$6 2&.+ $&* $.,.++)'#15 #$,1-2.
*.+*#$6 &% )11 /)')(.*.'+
Copyright 2000−2005, Texas Instruments Incorporated
240
210
180
150
120
90
60
30
0
−30
−60
−90
−120
Phase Margin − °
0
20
40
70
80
1 k 10 k 100 k
DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE
vs
FREQUENCY
f − Frequency − Hz
− Differential Voltage Amplification − dBAVD
60
50
30
10
−10
−20
−30
−40 1 M 10 M
VDD = 1.8 V & 2.7 V
RL= 2 kΩ
CL = 10 pF
TA = 25° C
Gain
Phase
Operational Amplifier
+
−
! !
SLOS245E − MARCH 2000 − REVISED JANUAR Y 2005
2WWW.TI.COM
TLV2780 and TLV2781 AVAILABLE OPTIONS(1)
V max
PACKAGED DEVICES
T
A
VIOmax
AT 25
°
C
SMALL OUTLINE
†
SOT-23
PLASTIC DIP
TA
IO
AT 25
°
C
SMALL OUTLINE
(D)†(DBV)‡ SYMBOL
PLASTIC DIP
(P)
0°C to 70°C3000 µVTLV2780CD
TLV2781CD TLV2780CDBV
TLV2781CDBV VASC
VATC —
—
-40°C to 125°C
3000 µVTLV2780ID
TLV2781ID TLV2780IDBV
TLV2781IDBV VASI
VATI TLV2780IP
TLV2781IP
-40
°
C to 125
°
C
2000 µVTLV2780AID
TLV2781AID —
——
——
—
†This package is available taped and reeled. To order this packaging option, add an R suf fix to the part number (e.g., TLV2780CDR).
‡This package is only available taped and reeled. For standard quantities (3,000 pieces per reel), add an R suffix (i.e., TLV2780CDBVR). For
smaller quantities (250 pieces per mini-reel), add a T suf fix to the part number (e.g. TLV2780CDBVT).
TLV2782 and TLV2783 AVAILABLE OPTIONS(1)
PACKAGED DEVICES
T
A
VIOmax
AT 25
°
C
SMALL
OUTLINE†
MSOP PLASTIC
DIP
PLASTIC
DIP
TA
IO
AT 25
°
C
OUTLINE†
(D) (DGK)†SYMBOL (DGS)†SYMBOL
DIP
(N)
DIP
(P)
0°C to 70°C3000 µVTLV2782CD
TLV2783CD TLV2782CDGK
—xxTIADL
——
TLV2783CDGS —
xxTIADN —
——
—
−40°C to 125°C
3000 µVTLV2782ID
TLV2783ID TLV2782IDGK
—xxTIADM
——
TLV2783IDGS —
xxTIADO —
TLV2783IN TLV2782IP
—
−40
°
C to 125
°
C
2000 µVTLV2782AID
TLV2783AID —
——
——
——
——
——
—
†This package is available taped and reeled. To order this packaging option, add an R suf fix to the part number (e.g., TLV2782CDR).
TLV2784 and TLV2785 AVAILABLE OPTIONS(1)
VIOmax
PACKAGED DEVICES
TAVIOmax
AT 25°CSMALL OUTLINE
(D) PLASTIC DIP
(N) TSSOP†
(PW)
0°C to 70°C3000 µVTLV2784CD
TLV2785CD —
—TLV2784CPW
TLV2785CPW
−40°C to 125°C
3000 µVTLV2784ID
TLV2785ID TLV2784IN
TLV2785IN TLV2784IPW
TLV2785IPW
−40
°
C to 125
°
C
2000 µVTLV2784AID
TLV2785AID —
—TLV2784AIPW
TLV2785AIPW
†This package is available taped and reeled. To order this packaging option, add an R suffix to the part number
(e.g., TLV2784CDR).
1. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website
at www.ti.com.
! !
SLOS245E − MARCH 2000 − REVISED JANUAR Y 2005
3
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TLV278x PACKAGE PINOUTS
1
2
3
4
5
10
9
8
7
6
1OUT
1IN−
1IN+
GND
1SHDN
VDD
2OUT
2IN−
2IN+
2SHDN
3
2
4
5
(TOP VIEW)
1
OUT
GND
IN+
VDD
IN−
TLV2781
DBV PACKAGE
3
2
4
6
(TOP VIEW)
1
OUT
GND
IN+
VDD
IN−
TLV2780
DBV PACKAGE
5SHDN
TLV2783
DGS PACKAGE
(TOP VIEW)
NC − No internal connection
1
2
3
4
8
7
6
5
NC
IN−
IN+
GND
SHDN
VDD
OUT
NC
TLV2780
D OR P PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
NC
IN−
IN+
GND
NC
VDD
OUT
NC
TLV2781
D OR P PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
GND
NC
1SHDN
NC
VDD
2OUT
2IN−
2IN+
NC
2SHDN
NC
(TOP VIEW)
TLV2783
D OR N PACKAGE
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
VDD
2IN+
2IN−
2OUT
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
(TOP VIEW)
TLV2784
D, N, OR PW PACKAGE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1OUT
1IN−
1IN+
VDD
2IN+
2IN−
2OUT
1/2SHDN
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
3/4SHDN
(TOP VIEW)
TLV2785
D, N, OR PW PACKAGE
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
GND
VDD
2OUT
2IN−
2IN+
TLV2782
D, DGK, OR P PACKAGE
(TOP VIEW)
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SLOS245E − MARCH 2000 − REVISED JANUAR Y 2005
4WWW.TI.COM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID ±VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II (any input) ± 10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO ± 10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: C-suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I-suffix −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE
Θ
JC
Θ
JA
TA
≤
25
°
C
TA = 125
°
C
PACKAGE
ΘJC
(°C/W)
ΘJA
(°C/W)
TA ≤ 25 C
POWER RATING
TA = 125 C
POWER RATING
D (8) 38.3 176 710 mW 142 mW
D (14) 26.9 122.3 1022 mW 204.4 mW
D (16) 25.7 114.7 1090 mW 218 mW
DBV (5) 55 324.1 385 mW 77.1 mW
DBV (6) 55 294.3 425 mW 85 mW
DGK (8) 54.2 259.9 481 mW 96.2 mW
DGS (10) 54.1 257.7 485 mW 97 mW
N (14, 16) 32 78 1600 mW 320.5 mW
P (8) 41 104 1200 mW 240.4 mW
PW (14) 29.3 173.6 720 mW 144 mW
PW (16) 28.7 161.4 774 mW 154.9 mW
recommended operating conditions
MIN MAX UNIT
Supply voltage, VDD
Single supply 1.8 3.6
V
Supply voltage, VDD Split supply ±0.9 ±1.8 V
Common-mode input voltage range, VICR −0.2 VDD+0.2 V
Operating free-air temperature, TA
C-suffix 0 70
°C
Operating free-air temperature, T
AI-suffix −40 125 °
C
VIH
VDD < 2.7 V 0.75VDD
Shutdown on/off voltage level‡VIH VDD = 2.7 to 3.6 V 2V
Shutdown on/off voltage level‡
VIL 0.6
V
‡Relative to GND.
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SLOS245E − MARCH 2000 − REVISED JANUAR Y 2005
5
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electrical characteristics at specified free-air temperature, VDD = 1.8 V, 2.7 V (unless otherwise
noted)
dc performance
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
TLV278x
25°C 250 3000
VIO
Input offset voltage
VO = VDD/2,
TLV278x Full range 4500
V
VIO Input offset voltage VO = VDD/2,
RL = 2 kΩ,
TLV278xA
25°C 250 2000 µV
R
L
= 2 k
Ω
,
RS = 50 Ω
TLV278xA Full range 3000
VIO
Temperature coef ficient of input offset
RS = 50 Ω
8
V/°C
αVIO
Temperature coef ficient of input offset
voltage 8µV/°C
VDD = 1.8 V
25°C 50 76
V
IC
= 0 to V
DD
,
R = 50
V
DD
= 1.8 V
Full range 50
CMRR
Common-mode rejection ratio
VIC = 0 to VDD,
RS = 50 Ω
VDD = 2.7 V/ 3.6 V
25°C 55 80
dB
CMRR
Common-mode rejection ratio
S
V
DD
= 2.7 V/ 3.6 V
Full range 50
dB
VIC = 1.2 V to VDD,
VDD = 2.7 V/ 3.6 V
25°C 70 100
VIC = 1.2 V to VDD,
RS = 50 Ω
V
DD
= 2.7 V/ 3.6 V
Full range 70
VDD = 1.8 V
25°C 200 600
AVD
Large-signal differential voltage
RL = 2 k
Ω
,
VDD = 1.8 V Full range 50
V/mV
AVD
Large-signal differential voltage
amplification
RL = 2 kΩ,
VO(PP) = 1 V
VDD = 2.7 V/ 3.6 V
25°C 200 1000 V/mV
amplification
VO(PP) = 1 V
VDD = 2.7 V/ 3.6 V Full range 70
†Full range is 0°C to 70°C for the C-suffix and −40°C to 125°C for the I-suffix. If not specified, full range is −40°C to 125°C.
input characteristics
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
25°C 2.5 15
I
IO
Input offset current
V = V /2,
TLV278xC Full range 100 pA
IIO
Input offset current
VO = VDD/2,
RL = 2 kΩ,
TLV278xI Full range 300
pA
R
L
= 2 k
Ω
,
RS = 50 Ω
25°C 2.5 15
I
IB
Input bias current
RS = 50 Ω
TLV278xC Full range 100 pA
IIB
Input bias current
TLV278xI Full range 300
pA
ri(d) Differential input resistance 25°C 1000 GΩ
Ci(c) Common-mode input capacitance f = 1 kHz 25°C 19 pF
†Full range is 0°C to 70°C for the C-suffix and −40°C to 125°C for the I-suffix. If not specified, full range is −40°C to 125°C.
! !
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6WWW.TI.COM
electrical characteristics at specified free-air temperature, VDD = 1.8 V, 2.7 V (unless otherwise
noted) (continued)
output characteristics
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
VDD = 1.8 V
25°C 1.7 1.77
VDD = 1.8 V Full range 1.63
I
OH
= −1 mA
VDD = 2.7 V
25°C 2.6 2.68
IOH = −1 mA
VDD = 2.7 V Full range 2.6
VOH
High-level output voltage
VDD = 3.6 V 25°C 3.58
V
VOH High-level output voltage
VDD = 1.8 V
25°C 1.5 1.55 V
VDD = 1.8 V Full range 1.46
I
OH
= −5 mA
VDD = 2.7 V
25°C 2.5 2.55
IOH = −5 mA
VDD = 2.7 V Full range 2.45
VDD = 3.6 V 25°C 3.55
IOL = 1 mA
25°C 70
IOL = 1 mA Full range 80
VOL
Low-level output voltage
VDD = 1.8 V
25°C 180 240
mV
VOL Low-level output voltage
IOL = 5 mA
VDD = 1.8 V Full range 290 mV
IOL = 5 mA
VDD = 2.7 V
25°C 120 170
VDD = 2.7 V Full range 200
VDD = 1.8 V,
Positive rail 10
IO
Output current
VDD = 1.8 V,
VO = 0.5 V from Negative rail
25°C
15
mA
IOOutput current
VDD = 2.7 V,
Positive rail 25°C17 mA
VDD = 2.7 V,
VO = 0.5 V from Negative rail 23
Sourcing
VDD = 1.8 V 13
IOS
Short-circuit output current
Sourcing VDD = 2.7 V
25°C
35
mA
IOS Short-circuit output current
Sinking
VDD = 1.8 V 25°C21 mA
Sinking VDD = 2.7 V 45
†Full range is 0°C to 70°C for the C-suffix and −40°C to 125°C for the I-suffix. If not specified, full range is −40°C to 125°C.
power supply
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
IDD
Supply current (per channel)
VO = VDD/2,
SHDN = VDD
25°C 650 770
A
IDD Supply current (per channel) VO = VDD/2,
SHDN = V
DD Full range 820 µA
VDD = 1.8 V to 2.7 V,
No load,
25°C 60 75
VDD = 1.8 V to 2.7 V,
VIC = VDD/2
No load,
Full range 58
kSVR
Supply voltage rejection ratio
VDD = 2.7 V to 3.6 V,
No load,
25°C 75 90
dB
kSVR
Supply voltage rejection ratio
(∆VDD /∆VIO)
VDD = 2.7 V to 3.6 V,
VIC = VDD/2
No load,
Full range 70 dB
( VDD / VIO)
VDD = 1.8 V to 3.6 V,
No load,
25°C 65 80
VDD = 1.8 V to 3.6 V,
VIC = VDD/2
No load,
Full range 60
†Full range is 0°C to 70°C for the C-suffix and −40°C to 125°C for the I-suffix. If not specified, full range is −40°C to 125°C.
! !
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7
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electrical characteristics at specified free-air temperature, VDD = 1.8 V, 2.7 V (unless otherwise
noted) (continued)
dynamic performance
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
UGBW Unity gain bandwidth RL = 2 kΩ,C
L = 25 pF 25°C 8 MHz
VDD = 1.8 V
25°C3.3 4.3
V = 1 V,
VDD = 1.8 V Full range 3.1
SR+
Positive slew rate at unity gain
VO(PP) = 1 V,
RL = 2 kΩ
VDD = 2.7 V
25°C3.8 4.8
SR+ Positive slew rate at unity gain
O(PP)
R
L
= 2 k
Ω,
CL = 50 pF
VDD = 2.7 V Full range 3.5
CL = 50 pF
VDD = 3.6 V
25°C4 5
VDD = 3.6 V Full range 3.6
V/ s
VDD = 1.8 V
25°C2.1 2.8 V/µs
V = 1 V,
VDD = 1.8 V Full range 1.89
SR−
Negative slew rate at unity gain
VO(PP) = 1 V,
RL = 2 kΩ
VDD = 2.7 V
25°C2.2 2.8
SR− Negative slew rate at unity gain
O(PP)
R
L
= 2 k
Ω,
CL = 50 pF
VDD = 2.7 V Full range 1.97
CL = 50 pF
VDD = 3.6 V
25°C3.5 4.2
VDD = 3.6 V Full range 3.4
φmPhase margin
RL = 2 kΩ,
CL = 25 pF
25°C
58°
Gain margin
R
L
= 2 k
Ω
,
C
L
= 25 pF
25
°
C
8 dB
VDD = 1.8 V,
V(STEP)PP = 1 V,
0.1% 1.7
ts
Settling time
V(STEP)PP = 1 V,
AV = −1,
C
L
= 10 pF, R
L
= 2 kΩ0.01%
25°C
2.8
s
tsSettling time VDD = 2.7 V,
V(STEP)PP = 1 V,
0.1% 25°C1.7 µs
V(STEP)PP = 1 V,
AV = −1,
C
L
= 10 pF, R
L
= 2 kΩ0.01% 2.4
†Full range is 0°C to 70°C for the C-suffix and −40°C to 125°C for the I-suffix. If not specified, full range is −40°C to 125°C.
noise/distortion performance
PARAMETER TEST CONDITIONS TAMIN TYP MAX UNIT
VO(PP) = VDD/2,
AV = 1 0.055%
THD + N Total harmonic distortion plus noise
VO(PP) = VDD/2,
R
L
= 2 kΩ,
f = 10 kHz
AV = 10 0.08%
THD + N
Total harmonic distortion plus noise
RL = 2 kΩ,
f = 10 kHz AV = 100
25°C
0.45%
Vn
Equivalent input noise voltage
f = 1 kHz 25°C18
nV/√Hz
VnEquivalent input noise voltage f = 10 kHz 9
nV/√Hz
InEquivalent input noise current f = 1 kHz 0.9 fA/√Hz
shutdown characteristics
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
IDD(SHDN)
Supply current, per channel in shutdown mode
SHDN = 0 V
25°C 900 1400
nA
IDD(SHDN
)
Supply current, per channel in shutdown mode
(TLV2780, TLV2783, TLV2785)
SHDN = 0 V
Full range 1700 nA
t(on) Amplifier turnon time‡RL = 2 kΩ
25°C
800
ns
t(off) Amplifier turnoff time‡RL = 2 kΩ25°C200 ns
†Full range is 0°C to 70°C for the C-suffix and −40°C to 125°C for the I-suffix. If not specified, full range is −40°C to 125°C.
‡Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current
has reached half its final value.
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input offset voltage vs Common-mode input voltage 1, 2
CMRR Common-mode rejection ratio vs Frequency 3
VOH High-level output voltage vs High-level output current 4, 6
VOL Low-level output voltage vs Low-level output current 5, 7
VO(PP) Maximum peak-to-peak output voltage vs Frequency 8
ZoOutput impedance vs Frequency 9
IDD Supply current vs Supply voltage 10
IDD Supply current vs Free-air temperature 11
PSRR Power supply rejection ratio vs Frequency 12
AVD Differential voltage amplification & phase vs Frequency 13
Gain-bandwidth product vs Free-air temperature 14
SR
Slew rate
vs Supply voltage 15
SR Slew rate vs Free-air temperature 16, 17
φmPhase margin vs Load capacitance 18
VnEquivalent input noise voltage vs Frequency 19
Voltage-follower large-signal pulse response vs Time 20
Voltage-follower small-signal pulse response vs Time 21
Inverting large-signal pulse response vs Time 22
Inverting small-signal pulse response vs Time 23
Crosstalk vs Frequency 24
Shutdown forward & reverse isolation vs Frequency 25
IDD(SHDN) Shutdown supply current vs Free-air temperature 26
IDD(SHDN) Shutdown supply current vs Supply voltage 27
IDD(SHDN) Shutdown supply current/output voltage vs Time 28
! !
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9
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TYPICAL CHARACTERISTICS
Figure 1
−1000
−800
−600
−400
−200
0
200
400
−0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
IO
VInput Offset Voltage −−Vµ
VDD=1.8 V
TA=25° C
VICR − Common-Mode Input Voltage − V
Figure 2
−400
−350
−300
−250
−200
−150
−100
−50
0
50
100
−0.2 0.2 0.6 1 1.4 1.8 2.2 2.6 3
IO
VInput Offset Voltage −−Vµ
VDD=2.7 V
TA=25 °C
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
VICR − Common-Mode Input Voltage − V
Figure 3
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
f − Frequency − Hz
0 10 100 10k 1M 10M
CMRR − Common-Mode Rejection Ratio − dB
VDD = 3.6 V
VDD = 1.8 V
VDD = 2.7 V
1k 100k
Figure 4
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0246810121416
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
IOH − High-Level Output Current − mA
VDD=1.8 V
VOH − High-Level Output Voltage − V
TA = 125°C
TA = 70°C
TA = 25°C
TA = 0°C
TA = −40°C
Figure 5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0 2 4 6 8 10 12 14 16 1820 22 24 28
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
IOL − Low-Level Output Current − mA
VDD=1.8 V
OL
V − Low-Level Output Voltage − V
TA=125°C
TA=70°C
TA=25°C
TA=0°C
TA=−40°C
26
Figure 6
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
0 5 10 15 20 25 30 35 40
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
IOH − High-Level Output Current − mA
VDD = 2.7 V
VOH − High-Level Output Voltage − V
TA=125°C
TA=70°C
TA=25°C
TA=0°C
TA=−40°C
Figure 7
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
0 5 10 15 20 25 30 35 40 45 50 55
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
IOL − Low-Level Output Current − mA
VDD= 2.7 V
OL
V − Low-Level Output Voltage − V
TA=125°C
TA= 70°C
TA=25°C
TA=0°C
TA=−40°C
Figure 8
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
100 1 k 10 k 100 k 1 M 10 M
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE
vs
FREQUENCY
f − Frequency − Hz
VO(PP) − Maximum Peak-To-Peak Output Voltage − V
VO(PP)= 2.7 V
AV = −10
RL=2 kΩ
CL = 10 pF
TA = 25° C
VO(PP)= 1.8 V
Figure 9
OUTPUT IMPEDANCE
vs
FREQUENCY
f − Frequency − Hz
100 1k 10k 100k 1M 10M
− Output Impedance −ZoΩ
0.1
10
1
100
AV = 10
AV = 1
VDD = 2.7 V
TA = 25° C
! !
SLOS245E − MARCH 2000 − REVISED JANUAR Y 2005
10 WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 10
0
100
200
300
400
500
600
700
0 0.6 1.2 1.8 2.4 3 3.6
AV= 1
VIC = VDD/2 V
VDD − Supply Voltage − V
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
TA = −40°C
TA = 25°C
TA = 125°C
DD
I Supply Current − −Aµ
Figure 11
1
1.05
1.1
1.15
1.2
1.25
1.3
1.35
1.4
−40−25−10 5 20 35 50 65 80 95 110 125
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
AV = 1
VIC = VDD/2
IDD − Supply Current − mA
VDD = 3.6 V
VDD = 2.7 V
VDD = 1.8 V
Figure 12
0
20
40
60
80
100
120
10 100 1 k 10 k 100 k 1 M 10 M
VDD=2.7 V
TA=25°C
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
f − Frequency − Hz
− Power Supply Rejection Ratio − dBPSRR
Figure 13
240
210
180
150
120
90
60
30
0
−30
−60
−90
−120
Phase Margin − °
0
20
40
70
80
1 k 10 k 100 k
DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE
vs
FREQUENCY
f − Frequency − Hz
− Differential Voltage Amplification − dBAVD
60
50
30
10
−10
−20
−30
−40 1 M 10 M
VDD = 1.8 V & 2.7 V
RL= 2 kΩ
CL = 10 pF
TA = 25° C
Gain
Phase
Figure 14
0
1
2
3
4
5
6
7
8
9
−40−25−10 5 20 35 50 65 80 95 110 125
RL = 2 kΩ
CL = 10 pF
f = 10 kHz
VDD = 1.8 V
VDD = 2.7 V
TA − Free-Air Temperature − °C
GAIN-BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
Gain-Bandwidth Product − MHz
Figure 15
0
1
2
3
4
5
6
7
8
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
SR−
SR+
SLEW RATE
vs
SUPPLY VOLTAGE
VDD − Supply Voltage − V
SR − Slew Rate − V/µs
AV = 1
RL = 2 kΩ
CL =10 pF
VO = 1 VPP
VIC = VDD/2
TA = 25° C
Figure 16
0
1
2
3
4
5
6
−40−25 −10 5 20 35 50 65 80 95 110 125
VDD = 1.8 V
AV = 1
RL=2 kΩ
CL=10 pF
VIC = VDD/2
SR−
SR+
SLEW RATE
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
SR − Slew Rate − V/µs
Figure 17
0
1
2
3
4
5
6
−40−25−10 5 20 35 50 65 80 95 110 125
VDD = 2.7 V
AV = 1
RL= 2 kΩ
CL = 10 pF
VO = 1 VPP
VIC = VDD/2
SR+
SLEW RATE
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
SR − Slew Rate − V/µs
SR−
! !
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11
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TYPICAL CHARACTERISTICS
Figure 18
0
10
20
30
40
50
60
70
80
90
100
10 100 1 k 10 k
PHASE MARGIN
vs
LOAD CAPACITANCE
CL − Load Capacitance − pF
VDD = 2.7 V
RL = 2 kΩ
AV = 1
TA = 25°C
Rnull=50 Ω
Rnull=20 Ω
Rnull=0 Ω
φm− Phase Margin − °
Figure 19
0
20
40
60
80
100
120
140
10 100 1 k 10 k 100 k
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
f − Frequency − Hz
nV/ Hz− Equivalent Input Noise Voltage −Vn
VDD = 2.7 V
VDD = 1.8 V
TA = 25°C
Figure 20
0
0.5
1
1.5
2
2.5
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
0.5
1
1.5
2
2.5
t − Time − µs
VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE
vs
TIME
VDD = 2.7 V
RL = 2 kΩ
CL = 10 pF
AV = 1
TA = 25°C
VI
VO
− Input Voltage − VVI
− Output Voltage − VVO
Figure 21
t − Time − µs
VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE
vs
TIME
VDD = 2.7 V
RL = 2 kΩ
CL = 10 pF
AV = 1
TA = 25°C
− Output Voltage − VVO
− Input Voltage − VVI
1.25
1.30
1.35
1.40
0 0.2 0.4 0.6 0.8 1 1.2 1.4
1.25
1.30
1.35
1.40
1.45
VI
VO
Figure 22
t − Time − µs
− Output Voltage − VVO
INVERTING LARGE-SIGNAL PULSE RESPONSE
vs
TIME
0
0.5
1
1.5
2
2.5
0 0.3 0.6 0.9 1.21.5 1.8 2.1 2.4 2.7 3 3.3
−1
−0.5
0
0.5
1
− Input Voltage − VVI
VDD = 2.7 V
RL = 2 kΩ
CL = 10 pF
AV = −1
TA = 25°C
VI
VO
Figure 23
t − Time − µs
INVERTING SMALL-SIGNAL PULSE RESPONSE
vs
TIME
− Output Voltage − VVO
1.25
1.30
1.35
1.40
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3
−0.05
0
0.05
0.10
VDD = 2.7 V
RL = 2 kΩ
CL = 10 pF
AV = −1
TA = 25°C
− Input Voltage − VVI
VO
VI
! !
SLOS245E − MARCH 2000 − REVISED JANUAR Y 2005
12 WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 24
−140
−120
−100
−80
−60
−40
−20
0
10 100 1 k 10 k 100 k
Crosstalk in Shutdown
VDD = 1.8 V & 2.7 V
VIC = 60% of VDD
AV = 1
RL= 2 kΩ
TA = 25°C
All Channels
CROSSTALK
vs
FREQUENCY
f − Frequency − Hz
Crosstalk − dB
Crosstalk/No Shutdown
Figure 25
0
20
40
60
80
100
120
140
10 100 1 k 10 k 100 k 1 M 10 M
Forward and Reverse Isolation
VDD = 1.8 & 2.7 V
VIC = VDD /2
RL = 2 kΩ
CL= 10 pF
AV = 1
TA = 25°C
SHUTDOWN FORWARD
AND REVERSE ISOLATION
vs
FREQUENCY
f − Frequency − Hz
Shutdown Forward Isolation - dB
Figure 26
0
0.5
1
1.5
2.0
2.5
3
−40−25 −10 5 20 35 50 65 80 95 110 125
SHUTDOWN SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
Shutdown = 0V
VIC = VDD/2
AV = 1
DD
I Shutdown Supply Current −−Aµ
VDD = 2.7 V
VDD= 3.6 V
VDD = 1.8 V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6
− Supply Current −
SHUTDOWN SUPPLY CURRENT
vs
SUPPLY VOLTAGE
IDD Aµ
Shutdown = 0 V
VIC = VDD/2
AV = 1
VDD − Supply Voltage − V
TA = 125°C
TA = 25°C
TA = −40°C
Figure 27
−1 0 1 2 3 4 5
SHUTDOWN SUPPLY CURRENT / OUTPUT VOLTAGE
vs
TIME
67 8 10
− Shutdown Current −
IDD(SD) SD − Shutdown Pulse − V
9
t − Time − µsec
SD
VDD = 2.7 V
AV = 1
RL = 10 kΩ
CL = 10 pF
VIC = VDD/2
TA = 25°C
IDD(SD)
VO
1.5
0.0
0.3
0.5
0.8
1.0
1.3
1.5
0.0
0.3
0.5
0.8
1.0
1.3
1.8
Figure 28
3.0
0.0
0.5
1.0
1.5
2.0
2.5
− Output Voltage − mVVO
Aµ
! !
SLOS245E − MARCH 2000 − REVISED JANUAR Y 2005
13
WWW.TI.COM
PARAMETER MEASUREMENT INFORMATION
_
+
RNULL
RLCL
Figure 29
APPLICATION INFORMATION
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as
shown in Figure 30.
CL
R
F
Input Output
RGRNULL
+
−
RLCL
R
F
Input Outpu
t
RGRNULL
+
−
RL
Snubber
C
(a) (b)
Figure 30. Driving a Capacitive Load
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
VOO +VIOǒ1)ǒRF
RGǓǓ"IIB)RSǒ1)ǒRF
RGǓǓ"IIB– RF
+
−
VI+
RG
RS
RF
IIB−
VO
IIB+
Figure 31. Output Offset Voltage Model
! !
SLOS245E − MARCH 2000 − REVISED JANUAR Y 2005
14 WWW.TI.COM
APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 32).
VIVO
C1
+
−
RGRF
R1
f–3dB +1
2pR1C1
VO
VI+ǒ1)RF
RGǓǒ1
1)2pfR1C1Ǔ
Figure 32. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
VI
C2
R2R1
C1
RF
RG
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
(
=1
Q
2 − )
RGRF
_
+f–3dB +1
2pRC
Figure 33. 2-Pole Low-Pass Sallen-Key Filter
! !
SLOS245E − MARCH 2000 − REVISED JANUAR Y 2005
15
WWW.TI.COM
APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high performance o f the TLV278x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
DGround planes − It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
DProper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
DSockets − Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
DShort trace runs/compact part placements − Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at
the input of the amplifier.
DSurface-mount passive components − Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
shutdown function
Three members of the TLV278x family (TLV2780/3/5) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied l o w, the supply current is reduced to 900 nA/channel,
the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the
shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care
should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place
the operational amplifier into shutdown.
! !
SLOS245E − MARCH 2000 − REVISED JANUAR Y 2005
16 WWW.TI.COM
APPLICATION INFORMATION
general power dissipation considerations
For a given θJA, the maximum power dissipation is shown in Figure 34 and is calculated by the following formula:
PD+ǒTMAX–TA
qJA Ǔ
Where: PD= Maximum power dissipation of TLV278x IC (watts)
TMAX= Absolute maximum junction temperature (150°C)
TA= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
1
0.75
0.5
0
−55−40 −25 −10 5
Maximum Power Dissipation − W
1.25
1.5
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
1.75
20 35 50
0.25
TA − Free-Air Temperature − °C
2
65 80 95 110 125
MSOP Package
Low-K Test PCB
θJA = 260°C/W
TJ = 150°C
PDIP Package
Low-K Test PCB
θJA = 104°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 34. Maximum Power Dissipation vs Free-Air Temperature
! !
SLOS245E − MARCH 2000 − REVISED JANUAR Y 2005
17
WWW.TI.COM
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim PartsRelease 9.1, the model generation
software used with Microsim PSpice. The Boyle macromodel (see Note 2) and subcircuit in Figure 35 are
generated using TLV278x typical electrical and operating characteristics at TA = 25°C. Using this information,
output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
DMaximum positive output voltage swing
DMaximum negative output voltage swing
DSlew rate
DQuiescent power dissipation
DInput bias current
DOpen-loop voltage amplification
DUnity-gain frequency
DCommon-mode rejection ratio
DPhase margin
DDC output resistance
DAC output resistance
DShort-circuit output current limit
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
* TLV2782_HVDD operational amplifier ”macromodel” subcircuit
* created using Model Editor release 9.1 on 03/3/00 at 9:47
* Model Editor is an OrCAD product.
*
* connections: non−inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
.subckt TLV2782_HVDD 1 2 3 4 5
*c1 11 12 49.58E−15
c2 6 7 10.200E−12
css 10 99 1.0000E−30
dc 5 53 dy
de 54 5 dy
dlp 90 91 dx
dln 92 90 dx
dp 4 3 dx
egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
fb 7 99 poly(5) vb vc ve vlp vln 0
41.096E6 −1E3 1E3 41E6
−41E6
ga 6 0 11 12 544.75E−6
gcm 0 6 10 99 1.1538E−9
iss 10 4 dc 56.957E−6
hlim 90 0 vlim 1K
j1 11 2 10 jx1
J2 12 1 10 jx2
r2 6 9 100.00E3
rd1 3 11 1.8357E3
rd2 3 12 1.8357E3
ro1 8 5 10
ro2 7 99 10
rp 3 4 2.1845E3
rss 10 99 3.5114E6
vb 9 0 dc 0
vc 3 53 dc .81911
ve 54 4 dc .81911
vlim 7 8 dc 0
vlp 91 0 dc 45.400
vln 0 92 dc 45.400
.model dx D(Is=800.00E−18)
.model dy D(Is=800.00E−18 Rs=1m Cjo=10p)
.model jx1 NJF(Is=500.00E−15 Beta=5.2102E−3 Vto=−1)
.model jx2 NJF(Is=500.00E−15 Beta=5.2102E−3 Vto=−1)
.ends
IN− G
D
S
D
S
G
rp
IN+
rd1 rd2 rss egnd fb ro2
ro1
vlim
OUT
ga
ioffgcm
vb
c1
dc
iss
dp
GND
VDD
css
c2
ve de
dlp dln
vlnhlimvlp
10
4
1
11 12
3
53
54
96
8
5
7
91 90 92
vc
99
+
+
+
+
+
+
+
−
−
−
−
−−
−
−+
r2
2
Figure 35. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV2780CDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2780CDBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2780CDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2780CDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2780IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2780IDBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2780IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2780IDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2780IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2780IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2781CDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2781CDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2781CDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2781CDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2781ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2781IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2781IDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV2781IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2781IDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2781IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2781IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2781IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2782AID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2782AIDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2782AIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2782AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2782CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2782CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2782CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2782CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2782CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2782CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2782CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2782CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2782ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV2782IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2782IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2782IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2782IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2782IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2782IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2782IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2782IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2782IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2783CDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2783CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2783ID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2783IDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2783IDGS ACTIVE MSOP DGS 10 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2783IDGSG4 ACTIVE MSOP DGS 10 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2783IDGSR ACTIVE MSOP DGS 10 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2783IDGSRG4 ACTIVE MSOP DGS 10 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2783IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2783INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 4
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV2784AID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2784AIDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2784AIDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2784AIDRG4 ACTIVE SOIC D 14 TBD Call TI Call TI
TLV2784CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2784CPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2784ID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2784IDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2784IDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2784IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2784IPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2784IPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2784IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2784IPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2785AID ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2785AIDG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2785CPW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2785CPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 5
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV2785CPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2785CPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2785IDR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2785IDRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2785IN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2785INE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2785IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2785IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 6
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV2780CDBVR SOT-23 DBV 6 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TLV2780CDBVT SOT-23 DBV 6 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TLV2780IDBVR SOT-23 DBV 6 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TLV2780IDBVT SOT-23 DBV 6 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TLV2780IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV2781CDBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TLV2781CDBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TLV2781IDBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TLV2781IDBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TLV2781IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV2782AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV2782CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV2782CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV2782CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV2782IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV2782IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV2782IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV2783CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV2783IDGSR MSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV2784AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLV2784CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLV2784IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLV2784IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLV2785CPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLV2785IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TLV2785IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV2780CDBVR SOT-23 DBV 6 3000 182.0 182.0 20.0
TLV2780CDBVT SOT-23 DBV 6 250 182.0 182.0 20.0
TLV2780IDBVR SOT-23 DBV 6 3000 182.0 182.0 20.0
TLV2780IDBVT SOT-23 DBV 6 250 182.0 182.0 20.0
TLV2780IDR SOIC D 8 2500 367.0 367.0 35.0
TLV2781CDBVR SOT-23 DBV 5 3000 182.0 182.0 20.0
TLV2781CDBVT SOT-23 DBV 5 250 182.0 182.0 20.0
TLV2781IDBVR SOT-23 DBV 5 3000 182.0 182.0 20.0
TLV2781IDBVT SOT-23 DBV 5 250 182.0 182.0 20.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV2781IDR SOIC D 8 2500 340.5 338.1 20.6
TLV2782AIDR SOIC D 8 2500 340.5 338.1 20.6
TLV2782CDGKR VSSOP DGK 8 2500 364.0 364.0 27.0
TLV2782CDGKR VSSOP DGK 8 2500 358.0 335.0 35.0
TLV2782CDR SOIC D 8 2500 340.5 338.1 20.6
TLV2782IDGKR VSSOP DGK 8 2500 364.0 364.0 27.0
TLV2782IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0
TLV2782IDR SOIC D 8 2500 340.5 338.1 20.6
TLV2783CDR SOIC D 14 2500 367.0 367.0 38.0
TLV2783IDGSR MSOP DGS 10 2500 358.0 335.0 35.0
TLV2784AIDR SOIC D 14 2500 367.0 367.0 38.0
TLV2784CPWR TSSOP PW 14 2000 367.0 367.0 35.0
TLV2784IDR SOIC D 14 2500 367.0 367.0 38.0
TLV2784IPWR TSSOP PW 14 2000 367.0 367.0 35.0
TLV2785CPWR TSSOP PW 16 2000 367.0 367.0 35.0
TLV2785IDR SOIC D 16 2500 367.0 367.0 38.0
TLV2785IPWR TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 3
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