HX6228KBFT - Honeywell - Microelectronics & Precision Sensors

HX6228

128K x 8 STATIC RAM - SOI

The 128K x 8 Radiation Harden ed Static RAM is a high performance 131,072 word

x 8-bit static random access memory with industry-standard functionality. It is

fabricated with Honeywell’s radiation hardened SOI-CMOS technology, and is

designed f or use in s ystems operating in r adiat ion environm ents . T he RAM operat es

over the full militar y tem perature range and requires only a single 5 V ± 10% power

supply. The RAM is wire bond programmable for either TTL or CMOS compatible

I/O. Power consumption is typically less than 25 mW/MHz in operation, and less

than 5 mW in the low power disabled mode. The RAM read operation is fully

asynchro nous , with an associated typical access time of 16 ns at 5V.

Honeywell’s enhanced SOI-IV CMOS technology is radiation hardened through the use of advanced and proprietary

design, la yout and process harden ing techniques . The SOI-IV pr ocess is an adv anced 5-volt, SO I CMOS tec hnolog y with

a 150 Å gate oxide and a minimum feature size of 0.7 µm (0.55 µm effective gate length—Leff). Additional features

include Honeywell’s proprietary SHARP planarization process, and a lightly doped drain (LDD) structure for improved

short channel reliability. A 7 transistor (7T) memory cell is used for superior single event upset hardening, while three

layer metal power bussing and the low collection volume SOI substrate provide improved dose rate hardening.

FEATURES

RADIATION

• Fabricate d with SOI-IV CMOS 0.7 µm

(Leff = 0.55 µm)

• Total Dose Hardness through 1x106 rad(Si)

• Neutron Hardness through 1x1014 N/cm2

• Dynamic and Static Transient Upset Hardness

through 1x1011 rad(SiO2)/s

• Dose Rate Survivability through 1x1012 rad(SiO2)/s

• Soft Error Rate of <1x10-10 upsets/bit-day in

Geosy nchronous Orbit

• No Latchup

OTHER

• Read/Write Cycle Times

o ≤ 16 ns (Typical)

o ≤ 25 ns (-55 to 125°C)

• Asynchronous Operation

• Typical Operating Power <25 mW/MHz

• CMOS or TTL Compatible I/O

• Single 5 V ± 10% Power Supply

• Packaging Options

o 32-Lead Flat Pack (0.820 in. x 0.600 in.)

o 40-Lead Flat Pack (0.775 in. x 0.710 in.)

HX6228

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FUNCTIONAL DIAGRAM

SIGNAL DEFINITIONS

A: 0-16 Address input pins which select a particular eight-bit word within the memory array.

DQ: 0-7 Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write

operation.

NCS Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS

forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables

all input buffers except CE. If this signal is not used it must be connected to VSS.

NWE Negative write enable, when at a low level activates a write operation and holds the data output drivers in a high

impedance state. When at a high level NWE allows normal read operation.

NOE Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a

low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must be

connected to VSS.

CE Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a

precharge co nd ition, ho lds the data out put dri vers in a high impedanc e state and disab les all the input buf fers

except the NCS input buffer. If this signal is not used it must be connected to VDD.

TRUTH TABLE

CE NCS NWE NOE MODE DQ

H L H L Read Data Out

H L L X Write Data In

X H XX XX Deselected High Z

L X XX XX Disabled High Z

Notes:

X: VI=VIH or VIL

XX: VSS≤VI≤VDD

NOE=H: High Z output state

maintained for NCS=X,

CE=X, NWE=X

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RADIATION CHARACTERISTI CS

Total Ionizing Radiation Dos e

The SRAM will meet all stated functional and electrical

specifications over the entire operating temperature

range af ter the spec ified total io nizing radiati on dose. All

electrica l and t im ing performance par ameters will rem ain

within spec ificatio ns after rebou nd at VDD = 5. 5 V and T

=125°C extrapolated to ten years of operation. Total

dose hardness is assured by wafer level testing of

process monitor transistors and RAM product using 10

keV X-ray and Co60 radiation sources. Transistor gate

threshold s hift correlat ions have been made betwee n 10

keV X -rays applie d at a do se rate of 1x 105 rad(SiO2)/min

at T = 25°C and gamma rays (Cobalt 60 source) to

ensure that wafer level X-ray testing is consistent with

standard military radiation test environments.

Transient Pulse Ionizing Radi ation

The SRAM is capable of writing, reading, and retaining

stored data during and after exposure to a transient

ionizing radiation pulse up to the transient dose rate

upset specification, when applied under recommended

operating conditions. To ensure validity of all specified

performance parameters before, during, and after

radiation (timing degradation during transient pulse

radiation is ≤20%), it is suggested that stiffening

capacita nce be placed on or near the pack age VDD and

VSS, with a maximum inductance between the package

(chip) and stiffening capacitance of 0.7 nH per part. If

there are no operate-through or valid stored data

requirements, typical circuit board mounted de-coupling

capacitors are recommended.

The SRAM will meet any functional or electrical

specification after exposure to a radiation pulse of up to

the transient dose rate survivability specification, when

applied under recommended operating conditions. Note

that the current conducted during the pulse by the RAM

inputs, outputs and power supply may significantly

exceed the normal operating levels. The application

design must accommodate these effects.

Neutron Radiation

The SRAM will meet any functional or timing

specification after exposure to the specified neutron

fluence under recommended operating or storage

conditio ns. T his ass um es equiva lent n eutro n energ y of 1

MeV.

Soft Error Rate

The SRAM is immune to single event upsets (SEU’s) to

the specified soft error rate (SER), under recommended

operating conditions. This hardness level is defined by

the Adams 10% worst case cosmic ray environment for

geosynchronous orbits.

Latchup

The SRAM will not latch up due to any of the above

radiation exposure conditions when applied under

recommended operating conditions. Fabrication with the

SOI-IV substrate material provides oxide isolation

between adjacent PMOS and NMOS transistors and

eliminates any potential SCR latchup structures.

Suffic ient trans istor bod y tie conn ectio ns to the p- and n-

channel substrates are made to ensure no source/drain

snapback occurs.

RADIATION HARDNESS RATINGS

Parameter Limits (2) Units Test Conditions

Total Dose ≥1x106 rad(Si) TA=25°C

Transient Dose Rate Upset (3) ≥1x1011 rad(SiO2)/s Pulse width ≤1 μs

Transient Dose Rate Survivability (3) ≥1x1012 rad(Si O2)/s Pulse width ≤50 ns, X-ray, VDD=6.0V, TA=25°C

Soft Error Rate (SER) <1x10-10 upsets/bit-day TA=25°C, Ad ams 90% worst case environment

Neutron Fluence ≥1x1014 N/cm2 1 MeV equivalent energy, Unbiased, TA=25°C

(1) Device will not latch up due to any of the specified radiation exposure conditions.

(2) Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, TA=-55°C to 125°C.

(3) Applies to 40-lead flat pack only. Assume ≥1x109 rad(SiO2)/s for 32-lead flat pac k. St iffe ning cap ac itan ce is sug ges ted for optimum

expected dose rate upset performance as stated above.

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ABSOLUTE MAXIMUM RATINGS (1)

Symbol

Parameter

Rating

Units

Min

Max

VDD Pos it ive Sup ply Voltage (2) -0.5 6.5 V

VPIN Voltage on Any Pin (2) -0.5 VDD +0.5 V

TSTORE Storage Temperature (Zero Bias) -65 150 °C

TSOLDER Soldering Temperature (5 seconds) 270 °C

PD Maximum Package Power Dissipation (3) 2.5 W

IOUT DC or Average Output Current 25 mA

VPROT ESD Input Protection Voltage (4) 2000 V

ΘJC Thermal Resistance (Jct-to-Case) 2 °C/W

TJ Junction Temperature 175 °C

(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these

levels is not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.

(2) Voltage referenced to VSS.

(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this

specification.

(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.

RECOMMENDED O PERATING CONDITIONS

Symbol

Parameter

Description

Units

Min

Typical

Max

VDD Supply Voltage (referenced to VSS) 4.5 5.0 5.5 V

TA Ambient Temperature -55 25 125 °C

VDDRAMP VDD Turn On Ramp Time 50 ms

VPIN Voltage On Any Pin (referenced to VSS) -0.3 VDD+0.3 V

VDD Ramp

Time

Supply Voltage Ramp Rate 50 ms

CAPACITANCE (1)

Symbol

Parameter

Worst Case

Units

Test Conditions

Min Max

CI Input Capacitance 7 pF VI=VDD or VSS, f=1 MHz

CO Output Cap acita nc e 9 pF VIO=VDD or VSS, f=1 MHz

(1) This parameter is tested during initial design characterization only.

DATA RETENTIO N CHARACTERIS T ICS (1)

Symbol

Parameter

Worst Case (2)

Units

Test Conditions

Min Max

VDR Data Retention Voltage(3) 2.5 V NCS=VDR, VI=VDR or VSS

IDR Data Retention Current 700 μA NCS=VDD=VDR, VI=VDD or VSS

(1) Typical operating conditions: TA= 25°C, pre-radiation.

(2) Worst case operating conditions: TA= -55°C to +125°C, post total dose at 25°C.

(3) To maintain valid data storage during transient radiation, VDD must be held within the recommended operating range.

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DC ELECTRICAL CH ARACTERISTICS

Symbol

Parameter

Typical

(1)

Worst Case (2)

Units

Test Conditions

Min Max

IDDSB Static Supply Current 0.4 2.0 mA VIH=VDD, IO=0

VIL=VSS, f=0MHz

IDDSBMF Standby Supply Current –

Deselected 0.4 2.0 mA NCS=VDD, IO=0,

f=40 MHz

IDDOPW Dynamic Supply Current, Selected

(Write) 1 MHz

2 MHz

10 MHz

25 MHz

40 MHz

6

12

60

150

240

mA

VDD=max, Iout=0mA,

NSL=VIH, NCS=VIL (1) (3)

IDDOPR Dynamic Supply Current, Selected

(Read) 1 MH z

2 MHz

10 MHz

25 MHz

40 MHz

4.5

9

45

112

180

mA

VDD=max, Iout=0mA,

NSL=VIH, NCS=VIL (1) (3)

II Input Leakage Current -5 +5 μA VSS ≤ VI ≤ VDD

IOZ Output Leakage Current -10 +10 μA VSS ≤ VI ≤ VDD

Output = high Z

VIL Low-Level Input Voltage CMOS

TTL

0.3xVDD

0.8 V March Pattern

VDD = 4.5V

VIH High-Level Input Voltage CMOS

TTL 0.7xVDD

2.2 V March Pattern

VDD = 5.5V

VOL Low-Level Output Voltage 0.4

0.1 V VDD=4.5V, IOL = 10 mA

VDD=4.5V, IOL = 200 μA

VOH High-Level Output Voltage VDD - 0.3

VDD - 0.1 V VDD=4.5V, IOL = -5 mA

VDD=4.5V, IOL = -200 μA

(1) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.

(2) Worst case operating conditions: VDD=4.5 V to 5.5 V, TA=-55°C to +125°C, post total dose at 25°C.

(3) All inputs switchi ng. DC av er age curre nt.

Tester Equi valent Loa d Ci r cuit

DUT

Output

Valid Low

Output

Valid High

Output

2.9V

249

Vref1

Vref2

CL ≥ 50 pf *

* CL = 5 pf for TWLQZ, TSHQZ, TELQZ, and TGHQZ

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READ CYCLE AC TIMING CHARACTERISTICS (1)

Symbol

Parameter

Typical (2)

Worst Case (3)

Units

-55 to 125° C

Min Max

TAVAVR Address Read Cycle Time 25 ns

TAVQV Address Access Time 25 ns

TAXQX Address Change to Output Invalid Time 3 ns

TSLQV Chip Select Access Time 25 ns

TSLQX Chip Select Output Enable Time 5 ns

TSHQZ Chip Select Output Disable Time 10 ns

TEHQV Chip Select Access Time 25 ns

TEHQX Chip Select Output Enable Time 5 ns

TELQZ Chip Select Output Disable Time 10 ns

TGLQV Output Enable Acces s Time 9 ns

TGLQX Output Enable Output Enable Time 0 ns

TGHQZ Output Enable Output Disable Time 9 ns

(1) Test conditions: input switching levels,VIL/VIH=0V/3V, input rise and fall times <1 ns/V, input and output timing reference levels

shown in the Tester AC Timing Characteristics table, capacitive output loading CL>50 pF, or equivalent capacitive output loading

CL=5 pF for TSHQZ, TELQZ TGHQZ. For CL >50 pF, derate access times by 0.02 ns/pF (typical).

(2) Typical operating conditions: VDD=3.3 V, TA=25°C, pre-radiation.

(3) Worst case operating conditions: VDD=3.0 V to 3.6 V, post total dose at 25°C.

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WRITE CYCLE AC TIMI NG CHARACTERISTI CS (1)

Symbol

Parameter

Typical

(2)

Worst Case (3)

Units

-55 to 125° C

Min Max

TAVAVW Write Cycle Time (4) 25 ns

TWLWH Write Enable Write Pulse Width 20 ns

TSLWH Chip Select to End of Write Time 20 ns

TDVWH Data Valid to End of Write Time 15 ns

TAVWH Addres s Val id to End of W rite Tim e 20 ns

TWHDX Data Hold Time after End of Write Time 0 ns

TAVWL Address Valid Setup to Start of Write Time 0 ns

TWHAX Address Valid Hold after End of Write Time 0 ns

TWLQZ Write Enable to Output Disable Time 0 9 ns

TWHQX Write Disable to Output Enable Time 5 ns

TWHWL Write Disable to Write Enable Pulse Width (5) 5 ns

TEHWH Chip Enable to End of Write Time 20 ns

(1) Test conditions: input switching levels, VIL/VIH=0V/3V, input rise and fall times <1 ns/V, input and output timing reference levels

shown in the Tester AC Timing Characteristics table, capacitive output loading >50 pF, or equivalent capacitive load of 5 pF for

TWLQZ.

(2) Typical operating conditions: VDD=3.3 V, TA=25°C, pre-radiation.

(3) Worst case operating conditions: VDD=3.0 V to 3.6 V, -55 to 125°C, post total dose at 25°C.

(4) TAVAVW = TWLWH + TWHWL

(5) Guaranteed but not t est ed.

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DYNAMIC ELE CTRICAL CHARACTERISTICS

Read Cycle

The RAM is asynchronous in operation, allowing the

read cycle to be controlled by address, chip select

(NCS), or chip enable (CE) (refer to Read Cycle timing

diagram). To perform a valid read operation, both chip

select and output enable (NOE) must be low and chip

enable and write enable (NWE) must be high. The

output drivers can be controlled independently by the

NOE signal. Consecutive read cycles can be executed

with NCS held continuously low, and with CE held

continuously high, and toggling the addresses.

For an address activated read cycle, NCS and CE must

be vali d prior to or coinc ident with the act ivating addr ess

edge transition(s). Any amount of toggling or skew

between address edge transitions is permissible;

however, data outputs will become valid TAVQV time

following the latest occurring address edge transition.

The minimum address activated read cycle time is

TAVAV. When the RAM is operated at the minimum

address activated read cycle time, the data outputs will

remain valid on the RAM I/O until TAXQX time following

the next sequential address transition.

To control a read cycle with NCS, all addresses and CE

must be valid prior to or coincident with the enabling

NCS edge transition. Address or CE edge transitions

can occur later than the specified setup times to NCS,

however, the v alid dat a ac ces s tim e will b e del ayed. A ny

address edge transition, which occurs during the time

when NCS is low, will initiate a new read access, and

data outputs will not become valid until TAVQV time

following the address edge transition. Data outputs will

enter a high impedance state TSHQZ time following a

disabling NCS edge transition.

To control a read cycle with CE, all addresses and NCS

must be valid prior to or coincident with the enabling CE

edge transition. Address or NCS edge transitions can

occur later than the specified setup times to CE;

however, the v alid dat a ac ces s tim e will b e del ayed. A ny

address edge transition which occurs during the time

when CE is high will ini tiat e a ne w read acc es s, and data

outputs will not bec om e valid until T AVQV tim e follo wing

the address edge transition. Data outputs will enter a

high impedance state TELQZ time following a disabling

CE edge transition.

Write Cycle

The write operation is synchronous with respect to the

address bits, and control is governed by write enable

(NWE), chip select (NCS), or chip enable (CE) edge

transitions (refer to Write Cycle timing diagrams). To

perform a write operation, both NWE and NCS must be

low, and C E must be high. Consecutive write c ycles c an

be performed with NWE or NCS held continuously low,

or CE held continuously high. At least one of the cont rol

signals must transition to the opposite state between

consecuti ve wr ite oper ati ons.

The write mode can be controlled via three different

control signals: NWE, NCS, and CE. All three modes of

control are similar except the NCS and CE controlled

modes actually disable the RAM during the write

recover y pulse. Both CE a nd NCS fully disabl e the RAM

decode logic and input buffers for power savings. Only

the NWE controlled mode is shown in the table and

diagram on the previous page for simplicity. However,

each mode of control provides the same write cycle

timing characteristics. Thus, some of the parameter

names referenced below are not shown in the write cycle

table or diagram, but indicate which control pin is in

control as it switches high or low.

To write data into the R A M, NWE and NCS must be he ld

low and CE must be held high for at least

TW LW H/TSLSH/TEHEL t im e. Any amount of edge skew

between th e s ignals c an be tolerat ed, a nd any one of the

control signals can initiate or terminate the write

operatio n. For consecutive writ e operations, write p ulses

must be separated by the minimum specified

TWHWL/TSHSL/TELEH time. Address inputs must be

valid at least TAVWL/TAVSL/TAVEH time before the

enabling NWE/NCS/CE edge transition, and must

remain valid during the entire write time. A valid data

overlap of write pulse width time of

TDVWH/TDVSH/TDVEL, and an address valid to end of

write time of TAVWH/TAVSH/TAVEL also must be

provided for during the write operation. Hold times for

address inputs and data inputs with respect to the

disabling NWE/NCS/CE edge transition must be a

minimum of TWHAX/TSHAX/TELAX time and

TWHDX/TSHDX/TELDX time, respectively. The

minimum write cycle time is TAVAV.

HX6228

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TESTER AC TIMING CHARACTERISTICS

QUALITY AND RADIATION HARDNESS

ASSURANCE

Honeywell maintains a high level of product integrity

through process control, utilizing statistical process

control, a complete “Total Quality Assurance System,” a

computer data base process performance tracking

system, and a radiation- hardness assurance strategy.

The radiation hardness assurance strategy starts with a

technology that is resistant to the effects of radiation.

Radiation hardness is assured on every wafer by

irradiating test structures as well as SRAM product, and

then monitoring key parameters which are sensitive to

ionizing radiation. Conventional MIL-STD-883 TM 5005

Group E testin g, whic h includes total dose ex posure with

Cobalt 60, may also be performed as required. This

Total Quality approach ensures our customers of a

reliable product b y engineering in reliability, starting with

process development and continuing through product

qualification and screening.

SCREENING LEVELS

Honeywell offers several levels of device screening to

meet your system needs. “Engineering Devices” are

available with limited performance and screening for

breadboarding and/or evaluation testing. Hi-Rel Level B

and S devices undergo additional screening per the

requirements of MILSTD-883. As a QML supplier,

Honeywell also offers QML Class Q and V devices per

MIL-PRF-38535 and are available per the applicable

Standard M icr oc irc uit Dra w ing ( SMD) . QML de v ic es offer

ease of procurement by eliminating the need to create

detailed specifications and offer benefits of improved

quality and cost savings through standardization.

RELIABILITY

Honeywell understands the stringent reliability

requirements for space and defense systems and has

extensive experience in reliability testing on programs of

this nature. This experience is derived from

comprehensive testing of VLSI processes. Reliability

attributes of the SOI-IV process were characterized by

testing specially designed irradiated and non-irradiated

test structures from which specific failure mechanisms

were evaluated. These specific mechanisms included,

but were not lim ited to, hot carriers , electrom igration and

time dependent dielectric breakdown. This data was

then used to make changes to the design models and

process to ensure more reliable products.

In addition, the reliability of the SOI CMOS process and

product in a military environment was monitored by

testing irradiated and non-irradiated circuits in

accelerated dynamic life test conditions. Packages are

qualified for product use after undergoing Groups B & D

testing as outlined in MIL-STD-883, TM 5005, Class S.

The product is qualified by following a screening and

testing flow to meet the customer’s requirements. Quality

conformance testing is performed as an option on all

production lots to ensure the ongoing reliability of the

product.

HX6228

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PACKAGING

The 128K x 8 SRAM is offered in a 32-Lead or 40-Lead

Flatpack type pack age. Each package is constructed of

multilayer ceramic (Al2O3) and features internal power

and ground planes.

Ceram ic chip capacitor s can be m ounted to the pack age

by the user to maximize supply noise decoupling and

increase bo ard packing dens ity. These capacit ors attach

directly to the internal package power and ground

planes. This design minimizes resistance and

inductance of the bond wire and package. All NC (no

connect) pins must be connected to VDD, VSS or an

active driver to prevent charge build up in the radiation

environment.

32-LEAD FLATP ACK PINO UT 40-LEAD FP PINOUT

BURN-IN CONFIGURATION

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32-LEAD FLAT PACK

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40-LEAD FLAT PACK

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ORDERING I NFORMATION (1 )

The HX6228 may be ordered through the SMD Drawing 5962-98537.

(1) Orders may be faxed to 763-954-2257.

(2) Engineering Device description: Parameters are tested from -55 to 125°C, 24 hr burn-in, no radiation guaranteed.

FIND OUT MORE

For more information on Honeywell’s Microelectronic products, visit us online at www.honeywell.com/microelectronics

or contact us at 800-323-8295 (763-954-2474 internationally).

The application circuits herein constitute typical usage and interface of Honeywell product. Honeywell does not warranty or assume liability of customer-

designed circuits derived f rom t his descript i on or depiction.

Honeywell reserves the right to make changes to improve reliability, function or design. Honeywell does not assume any liability arising out of the

applicat i on or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the ri ghts of others.

Honeywell

12001 Highway 55

Plymouth, MN 55441

Tel: 800-323-8295

www.honeywell.com/microelectronics

Form #900918

July 2012

H X 6228 S H A

Source

H = Honeywell

Process

X = SOI

PACKAGE DESIGNATION

T = 32 Lead FP

A = 40 Lead FP

K = Known Good Die

- = Bare Die (no package)

Part Number

SCREEN LEVEL

V = QML Class V

W = QML Class Q+

S = C lass S

B = C lass B

E = Eng. Model (2) TOTAL DOSE HARDNESS

R = 1x105 rad (Si)

F = 3x105 rad (Si)

H = 1x106 rad (Si)

N = No Level Guaranteed (2)

H

Input Buffer Type

C = CMOS

T = TTL