HY57V28420A
Revision History
Revision 1.1 (Dec. 2000)
• Eleminated -10 Bining product.
• Changed DC Characteristics-ll.
- tCK to 15ns from min in Test condition
- -K IDD1 to 120mA from 110mA
- -K IDD4 CL2 to 120mA from 100mA.
- -K IDD5 to 240mA from 220mA.
- -S IDD4 CL2 to 90mA from 100mA
• Added Burst-Read-Single-Write commend in Commend Truth Table
1.2 : Hynix Change
1.3 : Burst read single write mode correction
HY57V28420A
4Banks x 8M x 4bits Synchronous DRAM
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 1.3/Aug. 01
DESCRIPTION
The Hynix HY57V28420A is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applica-
tions which require large memory density and high bandwidth. HY57V28420A is organized as 4banks of 8,388,608x4.
HY57V28420A is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
• Single 3.3±0.3V power supply
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
• All inputs and outputs referenced to positive edge of
system clock
• Data mask function by DQM
• Internal four banks operation
• Auto refresh and self refresh
• 4096 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full Page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No. Clock Frequency Power Organization Interface Package
HY57V28420AT-6 166MHz
Normal
4Banks x 8Mbits
x 4 LVTTL 400mil 54pin TSOP II
HY57V28420AT-K 133MHz
HY57V28420AT-H 133MHz
HY57V28420AT-8 125MHz
HY57V28420AT-P 100MHz
HY57V28420AT-S 100MHz
HY57V28420ALT-6 166MHz
Low power
HY57V28420ALT-K 133MHz
HY57V28420ALT-H 133MHz
HY57V28420ALT-8 125MHz
HY57V28420ALT-P 100MHz
HY57V28420ALT-S 100MHz
HY57V28420A
Rev. 1.3/Aug. 01 3
PIN CONFIGURATION
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
VSS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
VDD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
PIN DESCRIPTION
PIN PIN NAME DESCRIPTION
CLK Clock The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CS Chip Select Enables or disables all inputs except CLK, CKE and DQM
BA0, BA1 Bank Address Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11 Address Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9,CA11
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe, Col-
umn Address Strobe, Write
Enable
RAS, CAS and WE define the operation
Refer function truth table for details
DQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ3 Data Input/Output Multiplexed data input / output pin
VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers
NC No Connection No connection
HY57V28420A
Rev. 1.3/Aug. 01 4
FUNCTIONAL BLOCK DIAGRAM
8Mbit x 4banks x 4 I/O Synchronous DRAM
State Machine
A0
A1
A11
BA0
BA1
Address buffers
Address
Registers
Mode Registers
Row
Pre
Decoders
Column
Pre
Decoders
Column Add
Counter
Row active
Column
Active
Burst
Counter
Data Out Control
CAS Latency
X decoders
Internal Row
counter
DQ0
DQ1
DQ2
DQ3
refresh
Self refresh logic
& timer
Pipe Line Control
I/O Buffer & Logic
Bank Select
Sense AMP & I/O Gate
CLK
CKE
CS
RAS
CAS
WE
DQM
X decoders
X decoders
Memory
Cell
Array
Y decoders
X decoders
8Mx4 Bank 1
8Mx4 Bank 0
8Mx4 Bank 2
8Mx4 Bank3
HY57V28420A
Rev. 1.3/Aug. 01 5
ABSOLUTE MAXIMUM RATINGS
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION (TA=0 to 70°C)
Note :
1.All voltages are referenced to VSS = 0V
2.VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.
3.VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.
AC OPERATING TEST CONDITION (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)
Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output
load circuit
Parameter Symbol Rating Unit
Ambient Temperature TA0 ~ 70 °C
Storage Temperature TSTG -55 ~ 125 °C
Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V
Short Circuit Output Current IOS 50 mA
Power Dissipation PD1W
Soldering Temperature ⋅ Time TSOLDER 260 ⋅ 10 °C ⋅ Sec
Parameter Symbol Min Typ Max Unit Note
Power Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V 1
Input High voltage VIH 2.0 3.0 VDDQ + 0.3 V 1,2
Input Low voltage VIL -0.3 0 0.8 V 1,3
Parameter Symbol Value Unit Note
AC Input High / Low Level Voltage VIH / VIL 2.4/0.4 V
Input Timing Measurement Reference Level Voltage Vtrip 1.4 V
Input Rise / Fall Time tR / tF 1 ns
Output Timing Measurement Reference Level Voltage Voutref 1.4 V
Output Load Capacitance for Access Time Measurement CL50 pF 1
HY57V28420A
Rev. 1.3/Aug. 01 6
CAPACITANCE (TA=25°C, f=1MHz)
OUTPUT LOAD CIRCUIT
DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V)
Note :
1.VIN = 0 to 3.6V, All other pins are not under test = 0V
2.DOUT is disabled, VOUT=0 to 3.6V
Parameter Pin Symbol
-6/K/H -8/P/S
Unit
Min. Max. Min. Max.
Input Capacitance CLK CI1 2.5 3.5 2.5 4 pF
A0 ~ A11, BA0, BA1, CKE,
CS, RAS, CAS, WE, DQM
CI22.5 3.8 2.5 5 pF
Data Input / Output Capacitance DQ0 ~ DQ3 CI/O 46.546.5pF
Parameter Symbol Min. Max Unit Note
Input Leakage Current ILI -1 1 uA 1
Output Leakage Current ILO -1 1 uA 2
Output High Voltage VOH 2.4 - V IOH = -4mA
Output Low Voltage VOL -0.4VIOL =+4mA
Output
Vtt=1.4V
RT=250 Ω
50pF 50pF
Output
DC Output Load Circuit AC Output Load Circuit
HY57V28420A
Rev. 1.3/Aug. 01 7
DC CHARACTERISTICS II (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.
2.Min. of tRRC (Refresh RAS cycle time) is applied to HY57V28420AT-6/K/H/8/P/S which are listed on AC characteristic II.
3.HY57V28420AT-6/K/H/8/P/S
4.HY57V28420ALT-6/K/H/8/P/S
Parameter Symbol Test Condition
Speed
Unit Note
-6 -K -H -8 -P -S
Operating Current IDD1 Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA 120 120 110 100 100 100 mA 1
Precharge Standby Current
in Power Down Mode
IDD2P CKE ≤ VIL(max), tCK = 15ns 2
mA
IDD2PS CKE ≤ VIL(max), tCK = ∞2
Precharge Standby Current
in Non Power Down Mode
IDD2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
20
mA
IDD2NS CKE ≥ VIH(min), tCK = ∞
Input signals are stable. 10
Active Standby Current
in Power Down Mode
IDD3P CKE ≤ VIL(max), tCK = 15ns 7
mA
IDD3PS CKE ≤ VIL(max), tCK = ∞7
Active Standby Current
in Non Power Down Mode
IDD3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
40
mA
IDD3NS CKE ≥ VIH(min), tCK = ∞
Input signals are stable. 40
Burst Mode Operating
Current IDD4 tCK ≥ tCK(min), IOL=0mA
All banks active
CL=3 140 120 120 110 100 100
mA 1
CL=2 100 120 100 100 100 90
Auto Refresh Current IDD5 tRRC ≥ tRRC(min), All banks active 240 240 220 200 200 200 mA 2
Self Refresh Current IDD6 CKE ≤ 0.2V
2mA3
800 uA 4
HY57V28420A
Rev. 1.3/Aug. 01 8
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter
2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v
If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Parameter Symbol
-6 -K -H -8 -P -S
Unit Note
Min Max Min Max Min Max Min Max Min Max Min Max
System Clock
Cycle Time
CAS Latency = 3 tCK3 6
1000
7.5
1000
7.5
1000
8
1000
10
1000
10
1000
ns
CAS Latency = 2 tCK2 10 7.5 10 10 10 12 ns
Clock High Pulse Width tCHW 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1
Clock Low Pulse Width tCLW 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1
Access Time
From Clock
CAS Latency = 3 tAC3 - 5.4 - 5.4 - 5.4 - 6 - 6 - 6 ns
2
CAS Latency = 2 tAC2 - 6 - 5.4 - 6 - 6 - 6 - 6 ns
Data-Out Hold Time tOH 2.7 - 2.7 - 2.7 - 3 - 3 - 3 - ns
Data-Input Setup Time tDS 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1
Data-Input Hold Time tDH 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1
Address Setup Time tAS 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1
Address Hold Time tAH 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1
CKE Setup Time tCKS 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1
CKE Hold Time tCKH 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1
Command Setup Time tCS 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1
Command Hold Time tCH 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1
CLK to Data Output in Low-Z TimetOLZ 1-1-1-1 -1-1-ns
CLK to Data
Output in High-Z
Time
CAS Latency = 3 tOHZ3 2.7 5.4 2.7 5.4 2.7 5.4 3 6 3 6 3 6 ns
CAS Latency = 2 tOHZ2 2.7 5.4 2.7 5.4 3 6 3 6 3 6 3 6 ns
HY57V28420A
Rev. 1.3/Aug. 01 9
AC CHARACTERISTICS II
Note :
1. A new command can be given tRRC after self refresh exit.
Parameter Symbol
-6 -K -H -8 -P -S -10
Unit Note
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
RAS Cycle Time
Operation tRC 60 - 60 - 65 - 68 - 70 - 70 - 80 - ns
Auto Refresh tRRC 60 - 60 - 65 - 68 - 70 - 70 - 96 - ns
RAS to CAS Delay tRCD 18 - 15 - 20 - 20 - 20 - 20 - 30 - ns
RAS Active Time tRAS 42 100K 45 100K 45 100K 48 100K 50 100K 50 100K 50 100K ns
RAS Precharge Time tRP 18 - 15 - 20 - 20 - 20 - 20 - 30 - ns
RAS to RAS Bank Active Delay tRRD 12 - 15 - 15 - 16 - 20 - 20 - 20 - ns
CAS to CAS Delay tCCD 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK
Write Command to Data-In Delay tWTL 0 - 0 - 0 - 0 - 0 - 0 - 0 - CLK
Data-In to Precharge Command tDPL 2 - 2 - 2 - 1 - 1 - 1 - 1 - CLK
Data-In to Active Command tDAL 5-4-5-4-3-3-4-CLK
DQM to Data-Out Hi-Z tDQZ 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK
DQM to Data-In Mask tDQM 0-0-0-0-0-0-0-CLK
MRS to New Command tMRD 2-2-2-2-2-2-2-CLK
Precharge to Data
Output Hi-Z
CAS Latency = 3tPROZ33-3-3-3-3-3-3-CLK
CAS Latency = 2tPROZ22-2-2-2-2-2-2-CLK
Power Down Exit Time tPDE 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK
Self Refresh Exit Time tSRE 1-1-1-1-1-1-1-CLK1
Refresh Time tREF - 64 - 64 - 64 - 64 - 64 - 64 - 64 ms
HY57V28420A
Rev. 1.3/Aug. 01 10
IBIS SPECIFICATION
IOH Characteristics (Pull-up) 66MHz and 100MHz Pull-up
Voltage 100MHz
Min
100MHz
Max
66MHz
Min
(V) I (mA) I (mA) I (mA)
3.45 -2.4
3.3 -27.3
3.0 0.0 -74.1 -0.7
2.6 -21.1 -129.2 -7.5
2.4 -34.1 -153.3 -13.3
2.0 -58.7 -197.0 -27.5
1.8 -67.3 -226.2 -35.5
1.65 -73.0 -248.0 -41.1
1.5 -77.9 -269.7 -47.9
1.4 -80.8 -284.3 -52.4
1.0 -88.6 -344.5 -72.5
0.0 -93.0 -502.4 -93.0
IOL Characteristics (Pull-down) 66MHz and 100MHz Pull-down
Voltage 100MHz
Min
100MHz
Max
66MHz
Min
(V) I (mA) I (mA) I (mA)
0.0 0.0 0.0 0.0
0.4 27.5 70.2 17.7
0.65 41.8 107.5 26.9
0.85 51.6 133.8 33.3
1.0 58.0 151.2 37.6
1.4 70.7 187.7 46.6
1.5 72.9 194.4 48.0
1.65 75.4 202.5 49.5
1.8 77.0 208.6 50.7
1.95 77.6 212.0 51.5
3.0 80.3 219.6 54.2
3.45 81.4 222.6 54.9
-600
-500
-400
-300
-200
-100
0
00.511.522.533.5
Voltage (V)
I (mA)
Ioh Min (100MHz)
Ioh Min (66MHz)
Ioh Min (66 and 100MHz)
0
50
100
150
200
250
00.5 11.522.5 33.5
Voltage (V)
I (mA)
I (mA) 100 min
I (mA) 66 min
I (mA) 100 max
HY57V28420A
Rev. 1.3/Aug. 01 11
VDD Clamp @ CLK, CKE, CS, DQM & DQ
VDD (V) I(mA)
0.0 0.0
0.2 0.0
0.4 0.0
0.6 0.0
0.7 0.0
0.8 0.0
0.9 0.0
1.0 0.23
1.2 1.34
1.4 3.02
1.6 5.06
1.8 7.35
2.0 9.83
2.2 12.48
2.4 15.30
2.6 18.31
VSS Clamp @ CLK, CKE, CS, DQM & DQ
VSS (V) I (mA)
-2.6 -57.23
-2.4 -45.77
-2.2 -38.26
-2.0 -31.22
-1.8 -24.58
-1.6 -18.37
-1.4 -12.56
-1.2 -7.57
-1.0 -3.37
-0.9 -1.75
-0.8 -0.58
-0.7 -0.05
-0.6 0.0
-0.4 0.0
-0.2 0.0
0.0 0.0
0
5
10
15
20
0123
Voltage
mA
I (mA)
Minimum VDD clamp current
(Referenced to VDD)
-60
-50
-40
-30
-20
-10
0
-3 -2.5 -2 -1.5 -1 -0.5 0
Voltage
mA
I (mA)
Minimum VSS clamp current
HY57V28420A
Rev. 1.3/Aug. 01 12
DEVICE OPERATING OPTION TABLE
HY57V28420A(L)T-6
HY57V28420A(L)T-K
HY57V28420A(L)T-H
HY57V28420A(L)T-8
HY57V28420A(L)T-P
HY57V28420A(L)T-S
CAS Latency tRCD tRAS tRC tRP tAC tOH
166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.7ns
143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns
133MHz(7.5ns) 2CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
133MHz(7.5ns) 2CLKs 2CLKs 6CLKs 8CLKs 2CLKs 5.4ns 2.7ns
125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns
125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
83MHz(12ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
100MHz(10ns) 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns
HY57V28420A
Rev. 1.3/Aug. 01 13
COMMAND TRUTH TABLE
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high.
2. X = Dont care, H = Logic High, L= Logic Low, BA=Bank Address, RA = Row Address, CA = Column Address,
Opcode=Operand Code, NOP=No Operation
3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.
Command CKEn-1 CKEn CS RAS CAS WE DQM ADDR A10/
AP BA Note
Mode Register Set H X L L L L X OP code 1
No Operation H X
HXXX
XX
LHHH
Bank Active H X L L H H X RA V
Read
HXLHLHXCA
L
V
Read with Autoprecharge H
Write
HXLHLLXCA
L
V
Write with Autoprecharge H
Precharge All Banks
HXLLHLXX
HX
Precharge selected Bank LV
Burst Stop H X L H H L X X
DQM H X V X
Auto Refresh H H L L L H X X
Burst-Read-Single-
WRITE H X LLLLX A9 Pin High
(Other Pins OP code) 3
Self Refresh
Entry H L LLLLX
X
Exit L H
HXXX
X
LHHH
Precharge
power down
Entry H L
HXXX
X
X
LHHH
Exit L H
HXXX
X
LHHH
Clock
Suspend
Entry H L
HXXX
X
XLVVV
Exit L H X X
HY57V28420A
Rev. 1.3/Aug. 01 14
PACKAGE INFORMATION
400mil 54pin Thin Small Outline Package
Unit : mm(inch)
