HD74HC - Hitachi Semiconductor

HD74HC Series Common Information

September 2000

Customer Service Division

Semiconductor & Integrated Circuits

Hitachi, Ltd.

Disclaimer

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,

Hitachi bears no responsibility for problems that may arise with third party’s rights, including

intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi’s sales office before using the product in an application that demands especially high

quality and reliability or where its failure or malfunction may directly threaten human life or cause risk

of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,

traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation

conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used

beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable

failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-

safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other

consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor

products.

Outline of Hitachi High-Speed CMOS Logic

Features of High-Speed CMOS Logic

Hitachi’s HS-CMOS logics–the HD74HC series–and the HCT series based on the EIA/JEDEC

specification. Their specification are shown in the Maximum Ratings and the Electrical Characteristics

Tables. The HS-CMOS has the characteristics of both standard CMOS logic series and LS-TTL series.

The features of this logic are:

• High-Speed equivalent to the LS-TTL’s

• Capable of driving 10LS-TTL loads

(Capable of driving 15LS-TTL loads in bus drivers)

• Maximum input current of ± 1 µA at 6 V power supply

• Wide supply voltage range: HC series 2 to 6 V

HCT series 4.5 to 5.5 V

• Wide noise margin

• VCC assurance of Electrical Characteristics at 2.0, 4.5 and 6.0 V

• Low Static Power Consumption 1/2 of EIA/JEDEC

Type Name of High-Speed CMOS Logic

The JEDEC has divided the HS-CMOS’s into two types: HC and HCT. The HC type has the CMOS logic

level for inputs and outputs with buffers. The HCT type has the TTL logic level for inputs and the outputs

have buffers.

The industry-standarized maximum ratings and recommended operating range are shown below. Limits for

the static characteristics are shown below (right): Table 1 is in the industry-standard and Table 2 is the

Hitachi specifications.

The Hitachi specifications is used throughout this data book. Additional specification are shown in the

individual data sheets. Switching characteristics are specified under the following conditions:

• Input pulse voltage: + VCC

• Load capacitance: 50 pF

• Input pulse rise/fall time: 6 ns

Switching times measured from 50% point of input voltage to 50% point of output voltage

• Three different supply voltages: 2.0, 4.5 and 6.0 V

Outline of Hitachi High-Speed CMOS Logic

Input Levels of Each Series Type (VCC = 5 V)

Input level

Type VIH VIL Remarks

HC series 3.5 V 1.5 V —

HCT series 2.0 V 0.8 V TTL logic level for inputs

Type Name of HS-CMOS Logic

Package Code

(P : Plastic DIP,FP:Small outline package (EIAJ TYPE),

RP : Small outline package (JEDEC TYPE))

Individual device code

2 or 3-digit:same pin connection and function

with its corresponding device

in LS-TTL

4–digit:same pin connection and function

with the 14000B series CMOS)

Type code (HC,HCT)

HD74

Absolute Maximum Ratings (Voltages Referenced to GND)

Item Symbol Rating Unit

Supply voltage VCC –0.5 to +7 V

I/O voltage VIN, VOUT –0.5 to VCC +0.5 V

I/O diode current IIK, IOK ±20 mA

Output current IO±25 mA

VCC, GND current ICC, IGND ±50 mA

Power dissipation PT500 mW

Storage temperature Range Tstg –65 to +150 ˚C

Additional specification values are shown on the individual data sheets.

Outline of Hitachi High-Speed CMOS Logic

Recommended Operating Range

HD74HC

Item Symbol Rating Unit Condition

Supply voltage VCC 2 to 6 V

I/O voltage VIN, VOUT 0 to VCC V

Operating temperature Ta –40 to +85 ˚C

Input rise/fall time tr, tf 0 to 1000 ns VCC = 2.0 V

0 to 500 VCC = 4.5 V

0 to 400 VCC = 6.0 V

HD74HCT

Item Symbol Rating Unit Condition

Supply voltage VCC 4.5 to 5.5 V

I/O voltage VIN, VOUT 0 to VCC V

Operating temperature Ta –40 to +85 ˚C

Input rise/fall time tr, tf 0 to 1000 ns VCC = 2.0 V

0 to 500 VCC = 4.5 V

0 to 400 VCC = 6.0 V

HD74HC14, HC132

Item Symbol Rating Unit Condition

Input rise/fall time tr, tf 0 to unlimited ns VCC = 2.0 V

0 to unlimited VCC = 4.5 V

0 to unlimited VCC = 6.0 V

HD74HC123A, HC221, HC423A

Item Symbol Rating Unit Condition

A, B Input rise/fall time tr, tf 0 to unlimited ns VCC = 2.0 V

0 to unlimited VCC = 4.5 V

0 to unlimited VCC = 6.0 V

CLR Input rise/fall time tr, tf 0 to 1000 ns VCC = 2.0 V

0 to 500 VCC = 4.5 V

0 to 400 VCC = 6.0 V

Outline of Hitachi High-Speed CMOS Logic

HD74HC4538

Item Symbol Rating Unit Condition

A, B Input rise/fall time tr, tf 0 to unlimited ns VCC = 2.0 V

0 to unlimited VCC = 4.5 V

0 to unlimited VCC = 6.0 V

CD Input rise/fall time tr, tf 0 to 1000 ns VCC = 2.0 V

0 to 500 VCC = 4.5 V

0 to 400 VCC = 6.0 V

HD74HC540, HC541

Item Symbol Rating Unit Condition

A Input rise/fall time tr, tf 0 to unlimited ns VCC = 2.0 V

0 to unlimited VCC = 4.5 V

0 to unlimited VCC = 6.0 V

G Input rise/fall time tr, tf 0 to 1000 ns VCC = 2.0 V

0 to 500 VCC = 4.5 V

0 to 400 VCC = 6.0 V

Outline of Hitachi High-Speed CMOS Logic

Table 1 EIA/JEDEC Format for High-Speed CMOS Specifications

Limits

+25˚C –40 to

+85˚C

Parameters Symbol VCC(V) min max min max Unit Test Conditions

Input voltage HC Series VIH 2.0 1.5 — 1.5 — V

4.5 3.15 — 3.15 —

6.0 4.2 — 4.2 —

HCT Series 4.5 to

5.5 2.0 — 2.0 —

HC Series VIL 2.0 — 0.3 — 0.3 V

4.5 — 0.9 — 0.9

6.0 — 1.2 — 1.2

HCT Series 4.5 to

5.5 — 0.8 — 0.8

Output HC Standard VOH 2.0 1.9 — 1.9 — V Vin = VIH or VIL Iout = –20 µA

voltage Series type 4.5 4.4 — 4.4 —

6.0 5.9 — 5.9 —

4.5 3.98 — 3.84 — Iout = –4.0 mA

6.0 5.48 — 5.34 — Iout = –5.2 mA

Bus driver 2.0 1.9 — 1.9 — Vin = VIH or VIL Iout = –20 µA

type 4.5 4.4 — 4.4 —

6.0 5.9 — 5.9 —

4.5 3.98 — 3.84 — Iout = –6.0 mA

6.0 5.48 — 5.34 — Iout = –7.8 mA

HCT Standard 4.5 4.4 — 4.4 — Vin = VIH or VIL Iout = –20 µA

Series type 4.5 3.98 — 3.84 — Iout = –4.0 mA

Bus driver 4.5 4.4 — 4.4 — Vin = VIH or VIL Iout = –20 µA

type 4.5 3.98 — 3.84 — Iout = –6.0 mA

HC Standard VOL 2.0 — 0.1 — 0.1 V Vin = VIH or VIL Iout = 20 µA

Series type 4.5 — 0.1 — 0.1

6.0 — 0.1 — 0.1

4.5 — 0.26 — 0.33 Iout = 4.0 mA

6.0 — 0.26 — 0.33 Iout = 5.2 mA

Bus driver 2.0 — 0.1 — 0.1 Vin = VIH or VIL Iout = 20 µA

type 4.5 — 0.1 — 0.1

6.0 — 0.1 — 0.1

Outline of Hitachi High-Speed CMOS Logic

Limits

+25˚C –40 to

+85˚C

Parameters Symbol VCC(V) min max min max Unit Test Conditions

Output HC Bus driver 4.5 — 0.26 — 0.33 V Vin = VIH or VIL Iout = 6.0 mA

voltage Series type 6.0 — 0.26 — 0.33 Iout = 7.8 mA

HCT Standard 4.5 — 0.1 — 0.1 Vin = VIH or VIL Iout = 20 µA

Series type 4.5 — 0.26 — 0.33 Iout = 4.0 mA

Bus driver 4.5 — 0.1 — 0.1 Vin = VIH or VIL Iout = 20 µA

type 4.5 — 0.26 — 0.33 Iout = 6.0 mA

Input leakage HC Series II6.0 — ±0.1 — ±1.0 µA Vin = VCC or GND

current HCT Series 5.5 — ±0.1 — ±1.0

Analog switch off- HC Series IS(off) 6.0 — ±0.1 — ±1.0 µA Vin = VIH or VIL

state current HCT Series 5.5 — ±0.1 — ±1.0 |VS| = VCC or VCC – VEE

3-state output off- HC Series IOZ 6.0 — ±0.5 — ±5.0 µA Vin = VIH or VIL

state current HCT Series 5.5 — ±0.5 — ±5.0 Vout = VCC or GND

Quiescent HC SSI ICC 6.0 — 2.0 — 20 µA Vin = VCC or GND

supply Series FF 6.0 — 4.0 — 40 Iout = 0 µA

current MSI 6.0 — 8.0 — 80

HCT SSI 5.5 — 2.0 — 20

Series FF 5.5 — 4.0 — 40

MSI 5.5 — 8.0 — 80

Outline of Hitachi High-Speed CMOS Logic

Table 2 Hitachi High-Speed CMOS Series Specifications

Limits

+25˚C –40 to

+85˚C

Parameters Symbol VCC(V) min max min max Uni t Test Conditions

Input voltage HC Series VIH 2.0 1.5 — 1.5 — V

4.5 3.15 — 3.15 —

6.0 4.2 — 4.2 —

HCT Series 4.5 to

5.5 2.0 — 2.0 —

HC Series VIL 2.0 — 0.5 — 0.5 V

4.5 — 1.35 — 1.35

6.0 — 1.8 — 1.8

HCT Series 4.5 to

5.5 — 0.8 — 0.8

Output HC Standard VOH 2.0 1.9 — 1.9 — V Vin = VIH or VIL IOH = –20 µA

voltage Series type 4.5 4.4 — 4.4 —

6.0 5.9 — 5.9 —

4.5 4.18 — 4.13 — IOH = –4.0 mA

6.0 5.68 — 5.63 — IOH = –5.2 mA

Bus driver 2.0 1.9 — 1.9 — Vin = VIH or VIL IOH = –20 µA

type 4.5 4.4 — 4.4 —

6.0 5.9 — 5.9 —

4.5 4.18 — 4.13 — IOH = –6.0 mA

6.0 5.68 — 5.63 — IOH = –7.8 mA

HCT Standard 4.5 4.4 — 4.4 — Vin = VIH or VIL IOH = –20 µA

Series type 4.5 4.18 — 4.13 — IOH = –4.0 mA

Bus driver 4.5 4.4 — 4.4 — Vin = VIH or VIL IOH = –20 µA

type 4.5 4.18 — 4.13 — IOH = –6.0 mA

HC Standard VOL 2.0 — 0.1 — 0.1 V Vin = VIH or VIL IOL = 20 µA

Series type 4.5 — 0.1 — 0.1

6.0 — 0.1 — 0.1

4.5 — 0.26 — 0.33 V Vin = VIH or VIL IOL = 4.0 mA

6.0 — 0.26 — 0.33 IOL = 5.2 mA

Bus driver 2.0 — 0.1 — 0.1 Vin = VIH or VIL IOL = 20 µA

type 4.5 — 0.1 — 0.1

6.0 — 0.1 — 0.1

Outline of Hitachi High-Speed CMOS Logic

Limits

+25˚C –40 to

+85˚C

Parameters Symbol VCC(V) min max min max Uni t Test Conditions

Output HC Bus driver VOL 4.5 — 0.26 — 0.33 V Vin = VIH or VIL IOL = 6.0 mA

voltage Series type 6.0 — 0.26 — 0.33 IOL = 7.8 mA

HCT Standard 4.5 — 0.1 — 0.1 Vin = VIH or VIL IOL = 20 µA

Series type 4.5 — 0.26 — 0.33 IOL = 4.0 mA

Bus driver 4.5 — 0.1 — 0.1 Vin = VIH or VIL IOL = 20 µA

type 4.5 — 0.26 — 0.33 IOL = 6.0 mA

Input leakage HC Series II6.0 — ±0.1 — ±1.0 µA Vin = VCC or GND

current HCT Series 5.5 — ±0.1 — ±1.0

Analog Switch HC Series IS(off) 6.0 — ±0.1 — ±1.0 µA Vin = VIH or VIL

Off-state Current HCT Series 5.5 — ±0.1 — ±1.0 |VS| = VCC or VCC – VEE

3-state output Off- HC Series IOZ 6.0 — ±0.5 — ±5.0 µA Vin = VIH or VIL

state Current HCT Series 5.5 — ±0.5 — ±5.0 Vout = VCC or GND

Quiescent HC SSI ICC 6.0 — 1.0 — 10 µA Vin = VCC or GND

Supply Series FF 6.0 — 2.0 — 20 Iout = 0 µA

Current MSI 6.0 — 4.0 — 40

HCT SSI 5.5 — 1.0 — 10

Series FF 5.5 — 2.0 — 20

MSI 5.5 — 4.0 — 40

Outline of Hitachi High-Speed CMOS Logic

Symbols and Terms Defined for HD74HC Series

1. Explanation of Symbols Used in Electrical Characteristics and Recommended Operating

Conditions

1.1 DC characteristics

Symbol Term Description

VIH “H” level input voltage “H” level input voltage to ensure that a logic element

operates under some constraint.

VIL “L” level input voltage “L” level input voltage to ensure that a logic element

operates under some constraint.

VOL “L” level output voltage Output voltage in effect when, under the input condition for

bringing the output Low, the rated output current is allowed

to flow to the output terminal.

VOH “H” level output voltage Output voltage in effect when, under the input condition for

bringing the output High, the rated output current is allowed

to flow to the output terminal.

VT+Forward input threshold voltage Input voltage in effect when the operation of a logic element

varies as the input is allowed to go up from a voltage level

lower than the forward input threshold voltage VT-.

VT-Reverse input threshold voltage Input voltage in effect when the operation of a logic element

varies as the input is allowed to go up from a voltage level

lower than the reverse input threshold voltage VT+.

VHHysteresis voltage Differnce between forward input threshold voltage VT+ and

reverse threshold voltage VT-.

IOH “H” level output current Output current that flows out when, under the condition for

bringing the output High, the rated output voltage VOUT is

applied to the output terminal.

IOL “L” level output current Output current that flows out when, under the condition for

bringing the output High, the rated output voltage V

T is

applied to the output terminal.

IIN Input leakage current Input current that flows in when the rated maximum input

voltage is applied to the input terminal.

IIH “H” level input current Input current that flows in when the rated “H” level voltage is

applied to the input.

IIL “L” level input current Input current that flows out when the rated “L” level voltage

is applied to the input.

IOZ Off-state output current (high

impedance) Current that flows to the 3-state output of an element under

the input condition for briging the output to High impedance.

Is(off) Analog switch off-state current Current that flows to the analog switch of an element under

the input condition for bringing the switch to off-state.

ICC Quiescent supply current Current that flows to the supply terminal (V

) under the

rated input condition.

Outline of Hitachi High-Speed CMOS Logic

1.2 AC characteristics

Symbol Term Description

fmax Maximum clock frequency Maximum clock frequency that maintains the stable changes in

output logic level in the rated sequence under the I/O condition

allowing clock pulses to change the output state.

tTLH Rise (transient) time Rated time from “L” level to “H” level of a waveform during the

defined transient period changing from “L” level to “H” level.

tTHL Fall (transient) time Rated time from “H” level to “L” level of a waveform during the

defined transient period changing from “H” level to “L” level.

tPLH Output rise propagation delay

time Delay time between the rated voltage levels of an I/O voltage

waveform under a defined load condition, with the output

changing from “L” level to “H” level.

tPHL Output fall propagation delay

time Delay time between the rated voltage levels of an I/O voltage

waveform under a defined load condition, with the output

changing from “H” level to “L” level.

tHZ 3-state output disable time (“H”

level) Delay time between the rated voltage levels of an I/O voltage

waveform under a defined load condition, with the 3-state

output changing from “H” level to the high impedance state.

tLZ 3-state output disable time (“L”

level) Delay time between the rated voltatge levels of an I/O voltage

waveform under a defined load condition, with the 3-state

output changing from “L” level to the high impedance state

tZH 3-state output enable time (“H”

level) Delay time between the rated voltage levels of an I/O voltage

waveform under a defined load condition, with the 3-state

output changing from the high impedance state to “H” level.

tZL 3-state output enable time (“L”

level) Delay time between the rated voltage levels of an I/O voltage

waveform under a defined load condition, with the 3-state

output changing from the high impedance state to “L” level.

twPulse width Duration of time between the rated levels from a leading edge

to a trailing edge of a pulse waveform.

thHold time Time in which to hold date at the specified input terminal after

a change at another related input terminal (e.g., clock input).

tsu Setup time Time in which to set up and keep data at the specified input

terminal before a change at another related input terminal

(e.g., clock input).

trm Removal time Time period between the time when data at the specified input

terminal is released and the time when another related input

terminal (e.g., clock input) can be changed.

Cin Input capacitance Capacitance between GND terminal and an input terminal to

which 0 V is applied.

Outline of Hitachi High-Speed CMOS Logic

2. Explanation of Symbols Used in Function Table

Symbol Description

H High level (in steady state; noted "H" or “H” level in sentences)

L Low level (in steady state; noted "L" or “L” level in sentences)

Transition from L level to H level

Transition from H level to L level

X Either H or L

Z 3-state output off (high impedance)

a·····h Input level of steady state for each of inputs A-H

Q0Q level immediately before the indicated input condition is established

Q0Complement of Q

QnQ level immediately before the latest active change ( or ) occurs

Single H level pulse

Single L level pulse

TOGGLE Each output is changed to the complement of the preceding state by an active input

change ( or )

Measuring Method of AC Characteristics

Loading Circuit

Output Output Output

Measuring

point Measuring

point

Measuring

point

VCC

(a) CMOS output (b) Open drain output (c) 3-state output

Notes: 1. CL includes the floating capacitance of probe and jig.

2. RL = 1 kΩ (except for a particular specification)

Outline of Hitachi High-Speed CMOS Logic

Waveforms (Mutual relationship of waveforms)

Pulse Width (TW)

74HC Series

VCC

tr = 6ns tf = 6ns

tf = 6ns tr = 6ns

90% 90%

50% 50%

10% 10%

50% 50%

10% 10%

GND

H-level Pulse

L-level Pulse

74HCT Series

3.0V

tr = 6ns tf = 6ns

tf = 6ns tr = 6ns

2.7V 2.7V

1.3V 1.3V

0.3V 0.3V

1.3V 1.3V

0.3V 0.3V

GND

H-level Pulse

L-level Pulse

Outline of Hitachi High-Speed CMOS Logic

Setup Time and Hold Time

74HC Series

50%

90%

10%

50%

trVCC

GND

VOH

VOL

VOH

VOL

tsu th

Clock or Latch

Enable Input *1

Positive

Data

Input

Negative

Data

Input

74HCT Series

1.3V

90%

10%

1.3V

tr3.0V

GND

3.0V

GND

3.0V

GND

tsu th

Clock or Latch

Enable Input *1

Positive

Data

Input

Negative

Data

Input

Note: Waveform for negative edge sensitive circuits will be inverted.

Outline of Hitachi High-Speed CMOS Logic

Removal Time

74HC Series

50%

90%

50%

10%

50%

10%

90% tr

VCC

GND

VCC

GND

VCC

GND

Clock

Input *1

Active Low

Clear or

Enable

Active

High Clear or

Enable

trem

74HCT Series

1.3V

90%

1.3V

10%

1.3V

10%

90% tr

3.0V

GND

3.0V

GND

3.0V

GND

Clock

Input *1

Active Low

Clear or

Enable

Active

High Clear or

Enable

trem

Note: Waveform for negative edge sensitive circuits will be inverted.

Outline of Hitachi High-Speed CMOS Logic

Waveforms (Mutual relationship of waveforms)

Propagation Delay Time, Output Rise Time and Output Fall time

74HC Series

90%

50%

10%

90%

50%

10%

90%

90% 90%

50%

50% 50%

10%

90%

50%

10%

10% 10%

tr = 6ns tf = 6ns

tTLH

tTHL

tPHL

tPLH

tPHL

VCC

GND

VOH

VOL

VOH

VOL

Input

Same-phase Output

Inverse-phase Output

Outline of Hitachi High-Speed CMOS Logic

74 HCT Series

90%

1.3V

10%

2.7V

1.3V

0.3V

90%

90% 90%

1.3V

1.3V 1.3V

10%

2.7V

1.3V

0.3V

10% 10%

tr = 6ns tf = 6ns

tTLH

tTHL

tPHL

tPLH

tPHL

3.0V

GND

VOH

VOL

VOH

VOL

Input

Same-phase Output

Inverse-phase Output

Outline of Hitachi High-Speed CMOS Logic

Waveforms (Mutual relationship of waveforms)

Three-state Output, Enable Time and Disable Time

74HC Series

10%

50%

90%

10%

50%

90%

tLZ

tHZ

S1 : VCC

S1 : GNDS1 : GND

tZL

tZH 50%

50%

tf = 6ns tr = 6ns

Output Control

(L-level Enable)

Waveform 1

Waveform 2

VCC

GND

VOH

VOL

VOH

VOL

74HCT Series

10%

0.3V

1.3V

2.7V

0.3V

1.3V

2.7V

90%

tLZ

tHZ

S1 : VCC

S1 : GND

tZL

tZH 1.3V

1.3V

tf = 6ns tr = 6ns

Output Control

(L-level Enable)

Waveform 1

Waveform 2

3.0V

GND

VOH

VOL

VOH

VOL

Notes: 1. Waveform 1 is an output under the internal condition like “L” except for the output disabled by the

output control.

2. Waveform 2 is an output under the internal condition like “H” except for the output disabled by the

output control.

Precautions in System Design

In the system design, the problems to be considered are described in the following items:

1. Transfer Characteristics

Since the transfer characteristics of gate circuit varies with the number of working inputs, care must be

taken to the noise margin. In the multiple input NOR gate, the P channel MOS is connected to VCC in

series and the N channel MOS is connected to GND in parallel. In the NAND gate, the connection is

reverse. The output voltage VOUT in the transition area becomes a value obtained by distributing the supply

voltage at a split ratio according to the ON resistance of P channel MOS and N channel MOS. In the

multiple input NOR and NAND gates, the fall of transfer characteristic, that is, VIN(voltage noise margin)

that enters in the transition area changes according to the number of inputs as shown in Figure 1.

Number of inputs

1234

Vin

Vout

Number of inputs

1234

Vin

Vout

Figure 1

As seen from the above, it becomes clear that:

• In the NOR gate, “0” level noise margin VNL decreases, and “1” level noise margin VNH increases

according to the number of working inputs.

• In the NAND gate, the noise margins are fully reversed.

Precautions in System Design

2. Output Impedance

The output impedance of CMOS logic gate is influenced by the circuit configuration, the number of

working inputs, logical state and supply voltage. There are two regions of output impedance depending on

the operation:

• Constant impedance area in which P and N channel MOS’ operate in the nonsaturated state.

• Constant current area in which P and N channel MOS’ operate in the pinch-off state.

In designing a system including an interface circuit, the above must be considered.

3. Output Short-Circuit

Because no protective circuitry is provided to limit the output current, an output inadvertently shorted to

VCC or GND on the HS-CMOS logic IC is limited to the current value determined by the pinch-off effect of

the P-channel MOS and N-channel MOS for the output. Notice that such output short-circuit current, if

allowed to flow for a long time, could result in increased power dissipation or in a melted wire due to

excessive current density through metalization or other performance failures. For operating stability and

reliability, the maximum output current should remain within the maximum rating.

4. Unused Inputs

As shown in Figure 2, unused inputs must be:

(1) Directly connected to VCC for NAND gate circuits.

(2) Directly connected to GND for NOR gate circuits.

(3) Connected to VCC or GND through a proper resistor (10 kΩ or 100 kΩ.).

This is required because the extremely high input impedance of CMOS logic makes it subject to noise.

This noise causes the output logic level to be unstable. Furthermore, in some cases, if a gate is not used or

a flip-flop is not used, both p-channel MOS and n-channel MOS may conduct, causing ICC to flow.

VCC VCC VCC

100 kΩ

100 kΩGND

GND

Vout

Vin

Figure 2 Examples of Handling Unused Inputs

Precautions in System Design

5. Input Impedance

Since all the input protective diodes are biased reversely in the ordinary operations, the input impedance of

CMOS logic IC is extremely high. When converted into a leak current, it is about several tens (pA) at a

temperature of 25˚C or about one (nA) even at 100˚C. Thus, the matching for operating the CMOS logic

IC has only to be considered at a voltage level. In the actual interface to other IC’s, however, remember

that fan-out is limited according to a capacitance value because inputs measured in capacity.

6. Parallel Connection of Gate Circuits

If it is necessary to increase source or sinking current, the same type gate circuits can be connected in

parallel as shown in Figure 3.

IOS0

IOS1

Increase of

source current Increase of

sinking current Increase of

sinking current

Figure 3 Examples of Parallel Connection

The switching speed improved at the same time. The source and sinking current capacities also increase in

proportion to the number of inputs.

7. Wired OR Connection

The wired OR connection is unrecommendable and shall not be used in CMOS logic IC’s. The reason is

that if the two gate outputs are connected with A = B = 0 and C = D = 1 as shown in Figure 4, the output

voltage is a value with which the supply voltage is divided by each of the resistance values of active P and

N channel MOS’, on an about half level (VCC - GND).

Figure 4 Wired OR Connection

Precautions in System Design

8. Input Capacitance

In the CMOS logic IC, there is capacitance between the input and the GND. In addition to the major

capacitance between the gate and the substrate, the capacitance of package, leads and input protection

circuit are also included. The change input capacitance depending on the input voltage results mainly from

the capacitance between the gate and the substrate. This input capacitance has an advantage of temporarily

storing date in it by opening/closing the transmission gate. On the other hand, however, remember that the

input capacitance may slow down switching speed of mutually connected gate and also may increase the

power dissipation. The input capacitance is usually about 5 (pF) as specified in the standard.

9. Output Capacitance

The whole output capacitance of CMOS logic IC is the sum of the drain capacitance of output MOS and the

external load capacitance. It may be considered that the former is about 10 (pF) per output. The

propagation delay time increases linealy in proportion to the increase of external load capacitance as

described previously. The power dissipation also increases according to it. Especially, be careful in

attaching a large capacity of around 1 (1µF) outside.

The peak current at the gate transition, as described previously, is limited by the output characteristics of P

and N channel MOS’. In the buffer circuit, the peak current may increase (to 100 mA or more).

Pay sufficient attention to the fact that the rise of temperature in the chip may cause metal migration on the

metal wiring layer. If the peak current for gate circuit is set to about 50 mA and the one for buffer circuit is

set to about 100 mA, no consideration is required.

Precautions in System Design

10. Features of 3-state Output Circuit

In a system that requires bus configuration, the 3-state output element is brought from the necessity to place

unnecessary circuits in the high output impedance state through control input to operate necessary circuit

selectively when tow or more circuit is connected to one bus line. Figure 5 shows the typical 3-state

circuit. When the Disable input of control terminal is at “1” level, the output is at low impedance by the

switch operation. When at “0” level, the output is at extremely high impedance of 104 (MΩ) at a room

temperature. Remember that the number of 3-state elements connectable to one bus line is limited by the

switching speed and supply voltage.

Disable

VCC

Out

GND

Figure 5 3-state Output Circuit

Precautions in System Design

11. Static Power Dissipation

In the CMOS logic IC, the P channel MOS and N channel MOS are mutually connected each other.

Therefore, either P channel or N channel is cut off in the input potential level static state. There is no path

in which the current from the power supply flows. Actually, the reverse bias leak current in all the P-N

junction in the chip including parasitic P-N junction flows only. The supply current in this state is referred

to as static current consumption, and the power dissipation as static power dissipation. The static current

consumption is a total of leak currents, and its values are extremely small as listed in Table 1. Thus, the

static current consumption is almost proportional to the supply voltage and increases exponentially in

proportion to temperature.

Table 1

Static Current Consumption ICC(max)

Type VCC +25˚C –40 to +85˚C

HC series SSI 6.0 V 1.0 µA 10 µA

FF 2.0 µA 20 µA

MSI 4.0 µA 40 µA

HCT series SSI 5.5 V 1.0 µA 10 µA

FF 2.0 µA 20 µA

MSI 4.0 µA 40 µA

12. Dynamic Power Dissipation

Assuming that the square pulse waves (tr = tf = 0) as shown in Figure 7 are applied to the input of the

inverter shown in Figure 6, the output steps from “0” level to “1” level in response to the input fall from

“1” level to “0” level.

VCC

Vout

Vin

GND

ICC(P)

ICC(N)

Figure 6 Inveter circuit

Precautions in System Design

Vin

Vout

ICC(P)

ICC(N)

Figure 7 Operating Voltage and current of inverter circuit

Actually, VOUT is not converted into square waveforms. The reason is that the sum total CL of the outputs

such as external load capacitance and drain capacitance are inverted by charging them from 0 to VCC. For

charging, supply current ICC(P) flows through the active P channel MOS from VCC. Contrary to this, when

the input goes from “0” level to “1” level, CL discharges and ICC(N) flows into GND through the N channel

MOS. The supply current caused by the charge/discharge is dynamic current dissipation, and the power

dissipation is dynamic power dissipation. If the average power dissipation is taken as PT, it is obtained

theoritically as follows:

The power dissipation when ICC(P) flows into the P channel MOS in Figure 6 is ICC(P) (VCC - VOUT). If an

average is taken by the one cycle of input pulse, the average power dissipation PTP of P channel MOS is:

P = 1/T I (V - V ) dtTP CC(P) CC OUT

T⋅

∫

ICC(P) = CL · d(VCC - VOUT)/dt

In the same manner, the average power dissipation of N channel MOS is:

P = 1/T I (V - GND) dtTN CC(N) OUT

T⋅

∫

ICC(N) = CL · d(VOUT - GND)/dt

Thus, the average dynamic power dissipation PT is:

PT = PTP + PTN

= 1/T · CL · VCC2

= f · CL · VCC2

f : Input pulse frequency

It is clear that the dynamic power dissipation varies with the frequency, load capacitance and supply

voltage.

Figure 8 shows the aspect.

Precautions in System Design

Power Dissipation PT (mW)

Operating frequency f (Hz)

1 k 10 k 100 k 1 M 10 M 100 M

0.0001

0.001

0.01

0.1

1.0

100

CL = 150 pF

CL = 50 pF

CL = 15 pF

CL = OPEN

Figure 8 Power Dissipation VS. Operating Frequency

This relation shows a case where the square wave input with tr = tf = 0 is assumed. In an actual case, the

input pulse is considered a trapezoidal waveform. Thus, remember that the transition state in which both P

channel MOS and N channel MOS are simultaneously activate and DC current flows from VCC into GND

during this time. If input is used at an intermediate level, such as crystal oscillator circuit and a linear

amplifier, and if the circuits such as a differentiation circuit, an integration circuit and an oscillation circuit

process gentle waveforms, pay attention to the increase of power dissipation.

13. Caution of Supply Voltage

To decouple noises, the capacitance of 0.01 to 0.1 (µF) should be attached externally between VCC and

GND.

14. Caution of Fan-out

The number of fan-outs of CMOS logic IC is virtually unlimited in terms of DC. The reason is that the

input current is the P-N junction leak current of input protection circuit at most and its value is actually

approximate to 0 because the input is connected to the gate electrodes and insulated from the substrate.

Therefore, the number of fan-outs is not a problem in terms of DC. In AC, there is a slightly different

circumstance. Since the input has a capacity of about 5 (pF), the output capacitance increases if the input is

connected to the output. If the input capacitance is taken as 5 (pF), for example, the whole load

capacitance CL (pF) at the time the number of fan-outs is n and load capacitance is CO (pF) is:

CL = 5 • n + CO (pF)

On the other hand, the propagation delay time increases in proportion to the output load capacitance CL.

The operating speed decreases according to the number of inputs (fan-outs) connected to the output.

Therefore, remember that the number of fan-outs is fairly limited if a high-speed operation is required.

Precautions in System Design

15. Cautions on Actual Operation

(1) The rise time and fall time of input waveforms should be 500 ns or less. Since the voltage gain is very

high near the threshold, the slightest ripples on the input voltage may cause the output to produce a

corresponding waveform, making the output operation unstable.

(2) The power line should be sufficiently filtered for the device. The input threshold voltage of the IC

varies with the supply voltage. A ripple on the power line may change the input threshold, causing the

same malfunction as noted in (1) above.

(3) Beware of a ringing (waveform distortion). Because the switching from “1” level to “0” level on vice

versa is very fast, the load capacitance plus the wiring inductance may cause a ringing. Care should be

taken to arrange the circuit configuration, PCB layout and wiring appropriately.

Application Note

1. Input Protection Circuit

An Si-gate process is applied to Hitachi’s high-speed CMOS logic ICs.They have a thinner gate oxide

compared to conventional Al-gate CMOS logic ICs and are composed into finer patterns.

Therefore, an input protection circuit is necessary for the gate to be protected from surges at the input pins.

Since Al-gate CMOS logic ICs use a diffusion resistor as the input protection resistor (as shown in Figure

1a), input over-current flows directly to the power supply and the destruction of the protection diode may

occur.

On the other hand, using polysilicone as its input protection resistor (shown in Figure 1b), high-speed

CMOS logic ICs take the role of a current limiter to counter input over voltage.

GND

Poly-Si

resistor

Input

VCC

GND

VCC

GND

P well

(a) Al-gate CMOS logic

(b) Si-gate CMOS logic

N+diffusion

resistor

N+

P+diffusion

resistor P+diffusion

resistor

P+

Poly-Si

resistor

Input Internal logic circuit

N+diffusion

resistor

Internal

logic

circuit

Internal

logic

circuit

N sub VCC

Figure 1 Input Protection Deevice and Equivalent Circuit

Application Note

2. Electric Static Discharge Immunity (ESD Immunity)

ESD immunity is evaluated by the capacitor discharge method shown in the test circuit of Figure 2. The

capacitor is 200 pF, accounting for the electrostatic capacitance of human bodies. Figure 3 shows an

example of ESD immunity of integrated circuits for each products series.

The ESD for high-speed CMOS logic is over ±200 V, which is the same level or better than LS-TTL.

C = 200 pF

Test Pin

GND

Figure 2 ESD Immunity Test Circuit

0 200 400100 300 500

Applied voltage (V)

Accumulated failure rate

HD74HC/HCT Series (HS-CMOS)

HD74S Series (S-TTL)

HD74LS Series (LS-TTL)

HD14000B Series (CMOS Logic)

HD17000 Series (industrial linear)

8-bit microcomputer (CMOS)

256k DRAM (NMOS)

Figure 3 ESD Immunity for Each Series

Application Note

3. Latch-Up

3.1 Latch-up

Latch-up is an inevitable phenomenon occurring from the basical structure of CMOS logic ICs.

Since CMOS has PMOS and NMOS on one chip, NPN and PNP transistors are made. These two types of

transistors are combined into a PNPN structure, in which a parasitic thyristor is formed (see Figure 4).

If excessive noise is applied to the input or output pins when the IC is operating, the parasitic thyristor will

turn on and the abnormal current will flow through the power supply pin to ground.

If the power supply is turned off, the IC will be restored to its normal state, however, the internal AI wiring

of the IC may melt thus causing the IC to be destroyed.

There are countermeasures to prevent latch-up as listed below

(1) Separate PMOS from NMOS.

(2) Shut down electrical paths between PNP and NPN transistors which form parasitic thyristors by its

layout pattern.

(3) Isolate each MOS transistor with an insulator to prevent the formation of parasitic thyristors.

Hitachi’s high-speed CMOS logic utilizes method (2)

VCC

Out

N-sub

(a) Parasitic PNP, NPN transistor (b) Equivalent circuit

Q1Q2Q2

γB2

γB1

P+P+P+

N+N+

P+

Figure 4 Parasitic Thyristor

Application Note

3.2 Latch-Up immunity

Latch-up immunity is evaluated by the test circuit shown in Figure 5.

Table 1 lists the test results of latch-up immunity of Hitachi’s high-speed CMOS logic.

The starting voltage of high-speed CMOS logic is over ±300 V which causes almost no problems for

practical use.

All other input

pins are conne-

cted to either

VCC or GND.

Test pin

VCC

GND

C = 200pF

VCC = 7V

ICC

Figure 5 Latch-Up Immunity Test Circuit

Table 1 Latch-Up Starting Voltage Test Results

Latch-up starting voltage

Positive Over 300 V

Negative Over 300 V

Measured samples

HD74HC00

HD74HC02

HD74HC04

HD74HC08

HD74HC14

HD74HC32

HD74HC74

Application Note

HD74HC138

HD74HC139

HD74HC157

HD74HC158

HD74HC175

HD74HC273

HD74HC373

HD74HC533

5 pieces per type

4. Electrical Characteristics

4.1 DC characteristics

(1) Logic threshold voltage (VTH)

The Logic threshold voltage (VTH) of Hitachi’s high-speed CMOS logic ICs (HD74HC Series) is at half

the level of VCC in order to set up the widest noise margin possible.

(2) Output current characteristics

Hitachi’s high-speed CMOS logic ICs have symmetrical characteristics between IOH and IOL. Thus, the

balance between tPLH and tPHL is mostly kept even when connecting with a comparatively large load

capacitance.

Figures 7 and 8 show the output current characteristics.

Application Note

246

Input voltage VIN (V)

Output voltage VOUT (V)

VCC = 6 V

VCC = 4.5 V

VCC = 2 V

Figure 6 Output Voltage vs Input Voltage

0246

Low output voltage VOL (V)

100

120

Low output current IOL (mA)

VCC = 6 V

4.5 V

2 V

(b) Standard output (HD74HC00)

0246

Low output voltage VOL (V)

100

120

Low output current IOL (mA)

VCC = 6 V

4.5 V

2 V

(b) Bus driver output (HD74HC244)

Figure 7 Output Current vs Voltage (Low Level)

Application Note

0642

High output voltage VOH (V)

–100

–80

–60

–20

–40

High output voltage IOH (mA)

VCC = 2 V

4.5 V

6 V

(a) Standard output (HD74HC00)

0642

High output voltage VOH (V)

(b) Bus driver output (HD74HC244)

–100

–80

–60

–20

–40

High output voltage IOH (mA)

VCC = 2 V

4.5 V

6 V

Figure 8 Output Current vs Voltage (High Level)

4.2 AC characteristics

tPLH and tPHL of Hitachi’s high-speed CMOS logic ICs are set up to be about the same to simplify system

timing design.

(1) Propagation delay time, output rise and fall time vs supply voltage characteristics.

0246

Supply voltage VCC (V)

50 Ta = 25°C

CL = 50 pF

Propagation delay time tPLH, tPHL (ns)

tPLH

tPHL

(a) Standard output (HD74HC00)

0246

Supply voltage VCC (V)

Ta = 25°C

CL = 50 pF

Propagation delay time tPLH, tPHL (ns)

tPHL

tPLH

(b) Bus driver output (HD74HC244)

Figure 9 Propagation Delay Time vs Supply Voltage

Application Note

Ta = 25°C

CL = 50 pF

0246

Supply voltage VCC (V)

Output rise and fall time tTLH, tTHL (ns)

tTHL

tTLH

Ta = 25°C

CL = 50 pF

0246

Supply voltage VCC (V)

Output rise and fall time tTLH, tTHL (ns)

tTHL

tTLH

Figure 10 Output Rise and Fall Time vs Supply Voltage

(2) Propagation delay time, output rise and fall time vs load capacitance characteristics.

0 50 200100 150

Load capacitance CL (pF)

20 VCC = 4.5 V

Ta = 25°C

Propagation delay time tPLH, tPHL (ns)

tPHL

tPLH

(a) Standard output (HD74HC00)

0 50 200100 150

Load capacitance CL (pF)

20 VCC = 4.5 V

Ta = 25°C

Propagation delay time tPLH, tPHL (ns)

tPHL

tPLH

(b) Bus driver output (HD74HC244)

Figure 11 Propagation Delay Time vs Load Capacitance

Application Note

25 VCC = 4.5 V

Ta = 25°C

0 50 200100 150

Load capacitance CL (pF)

Output rise and fall time tTLH, tTHL (ns)

tTHL

tTLH

25 VCC = 4.5 V

Ta = 25°C

0 50 200100 150

Load capacitance CL (pF)

Output rise and fall time tTLH, tTHL (ns)

tTHL

tTLH

(b) Bus driver output (HD74HC244)

(a) Standard output (HD74HC00)

Figure 12 Output Rise and Fall Time vs Load Capacitance

Application Note

5. Power Dissipation

5.1 Calculating the power dissipation

The power dissipation PT of high-speed CMOS logic can be calculated by (1). From this equation, the

power dissipation depends on the load capacitance, frequency and supply voltage.

PT = (CL + CPD)· f · VCC2 (1)

Figure 13 shows examples of the operating frequency with the power supply current.

0101.0

Operating frequency f (MHz)

0.01

0.1

1.0

LS-TTL HD74LS74

Power supply current (per circuit) (mA)

High-speed CMOS logic HD74HC74

= 50 pF

= 0 pF

CL = 50 pF

CL = 0 pF

Figure 13 Operating Frequency vs Power Supply Current

Application Note

5.2 Power dissipation capacitance

Power dissipation capacitance (Cpd) can be calculated by the following equations,

PT1 = CPD · VCC2 · f1 = ICC1 · VCC (2)

PT2 = CPD · VCC2 · f2 = ICC2 · VCC (3)

therefore,

C= P–P

V(f–f)

=I–I

V(f–f)

PD T2 T1

CC221

CC2CC1

CC 2 1

⋅

(4)

then,

• ICC1 : Supply current at frequency f1

• ICC2 : Supply current at frequency f2

Table 2 lists the power dissipation capacitance of Hitachi’s high-speed CMOS logic.

Furthermore, the power dissipation capacitance differs according to the input conditions.

Table 3 shows typical examples.

Table 2 Power Dissipation Capacitance of High-Speed CMOS

Function Product part no. Note 1 Power dissipation capacitance typ. (pF)

Gate HD74HC00 * 27

HD74HC04 * 24

Flip-Flop D-type HD74HC74 * 41

J-K-type HD74HC76 * 49

COMPARATOR HD74HC85 P 48

DECORDER HD74HC138 P 90

COUNTER HD74HC161 P 57

BUFFER HD74HC240 * 42

MULTIPLEXER HD74HC258 P 78

LATCH HD74HC373 P 57

Notes: 1. *:Per circuit; P:Per package.

2. Measurement circuit is shown in figure 14.

Application Note

VCC

P.G. Y

P.G. A

HD74HC00 HD74HC04

VCC

P.G.1

P.G.2

CLR

fPG1

fPG2

fPG2=1/2PG1

HD74HC74

VCC

P.G.

CLR

HD74HC76

VCC VCC

A = B

P.G.

A < B

A > B

A = B

Other

Inputs

P.G.

G2A

G2B

HD74HC85 HD74HC138

Figure 14 Measurement Circuits for Dynamic Power Supply Current

Application Note

VCC

P.G. P.G.

CLR

LD QA

Carry

HD74HC161 HD74HC240

VCC VCC

P.G.

Other

Inputs

4Y P.G.

HD74HC258 HD74HC373

Measurement conditions

Ta = 25°C

VCC = 6V

f1 = 1MHz

f2 = 5MHz

duty = 50%

tr = tf = 6ns

trtr

90%

10% 10%

90%

Figure 14 Measurement Circuits for Dynamic Power Supply Current (cont)

Application Note

Table 3 Power Dissipation Capacitance by Input Conditions

Product part no. Input conditions Power dissipation capacitance (pF)

HD74HC00 Single input

VCC

P.G. A

Double input

VCC

P.G. A

HD74HC161 Counting operation VCC

P.G.

CLR

LD QA

Carry

Preset operation

VCC

P.G.1

P.G.2

CLR QA

Carry

113

Application Note

6. Decoupling

CMOS logic ICs have current spikes when switching. These spikes are produced by the repeated charging

and discharging of the output capacitance when charging the output level from low to high or high to low.

Because of the current spikes the potentials of VCC and GND change, and large current spikes flow when

switching. Therefore ringing is produced at the output. (See Figure 15 a.)

To prevent this, decoupling capacitors must be provided externally between VCC and GND.

This is proven to be useful in instantly absorbing the current and ringing at the output as shown in Figure

15 b.

Output voltage

waveform

VCC current

waveform

GND current

waveform

(a) No decoupling capacitor (b) Decoupling capacitor (0.1 µF)

Vertical

Horizontal 20 mA/div

100 ns/div

Vertical

Horizontal 2 V/div

100 ns/div

GND

Figure 15 HD74HC00 Spike Current Waveform

7. Precautions on Board Design

High-speed CMOS logic has different electrical characteristics, such as switching speed and output current

drivability, from the conventional standard logics (Al-gate CMOS, LS-TTL). The system design requires

an application technique for high-speed CMOS logic.

Here an interfacing technique between high-speed CMOS logic and LS-TTL will be explained.

7.1 Transmission line reflection

(1) Analysis of transmission signals by the Bergeron diagram The Bergeron diagram is commonly used for

the analysis of transmission signals in high-speed digital systems.

Figure 17 is the analysis result of an actual transmission model which is shown in Figure 16.

Application Note

As for the analysis conditions, Z0 = 125 Ω considering the standard system board, and the wiring length (l)

is 1.5 m.

The output impedance of the HD74HC04, which operates as a driver becomes the IOH - VOH characteristic

curve when the output is high, and the input impedance of the HD74LS04 which operates as a receiver

becomes the IIH - VIH characteristic curve.

On the other hand, when the output level of the HD74HC04 is low, the output impedance becomes the IOL -

VOL characteristic curve and the input impedance becomes the IF - VF characteristic curve.

The drawing of load line Z0 as these input/output impedance curves enables the reflection of the

transmission signal to be analyzed.

The intersection coordinates in Figure 17 shows the voltage and current values at the drive end of 2T (T

being the propagation delay from the driver end to the receiver end) intervals when the coordinates are even

numbers (2T, 4T) or zero, or the voltage and current values at the receiver end when the coordinates are

odd numbers (T, 3T, 5T).

Figure 18 shows the analysis result of the voltage waveform at the receiver end.

Application Note

–VP1

–VP2

+VP2

+VP1

Voltage (V)

time t

(b) Receiver waveform model

Driver Receiver

HD74LS04

HD74HC240

: 1.5 m

: 125 Ω

50 Ω

(a) Digiral signal transmission model circuit

Note: The model circuit above (Figure 16a) is used for analysis when the high-speed CMOS logic

HD74HC240 is connected as a driver, and the LS-TTL HD74LS04 as a receiver

The waveform model for overshoot and undershoot at the receiver end is shown in Figure 16b.

Figure 16 Digital Signal Transmission

Application Note

V (V)

–1

–2

–100 –80 –60 –40 40 60 80 100

HD74LS04

IF – VF

characteristics

HD74HC240

IOL – VOL

characteristics

HD74HC240

IOH – VOH

characteristics

Z0 load line

I (mA)

: 1.5 m

: 125 Ω

: 25°C

–20

Figure 17 Bergeron Diagram Analysis of the Transmission Model

500

–1

Voltage (V)

+VP2

0 100 200 300

Time t (ns)

400 600 700 800

Figure 18 Analysis Results of the Waveform at the Receiver End

(2) An example for measuring the reflection on the transmission line Figure 19 shows the measured results

of the reflection of the transmission line using three types of transmission line media such as 1) coaxial

cable (Z0 = 50 Ω), 2) twisted pair cable (Z0 = 120 Ω), and 3) single lead wire (Z0 = 150 to 200 Ω).

Figure 19 shows that the drivers and receivers operate normally with a wiring length of up to 2 m.

However, careful precautions should be taken when considering impedance in practical system designing.

Application Note

Transmission

line

midium

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Receiver

HD74HC240

Driver

HD74HC240 Receiver

HD74HC240

Driver

HD74HC240

Coaxial cable

(

= 2m)

Twisted pair cable

(

= 2m)

Single lead wire

(

= 2m)

50 Ω

Waveform Waveform Waveform

Waveform , ,

Vertical

Horizontal 5 V/div

100 ns/div

HD74HC240

HD74LS04

Receiver

Driver

HD74HC240 Wiring length l = 2 m

Driving pulse

for all inputs

( )

CL = 50 pF

= 1 kΩ

VCC

Measurement conditions

VCC = 5 V

Ta = 25°C

f = 1 MHz

duty = 50%

tr = tf = 6 ns

Note:The load circuit shown on the

right is used when the HD74LS04 is

used as a receiver.

Figure 19 Reflection Ringing Waveforms (Driver: HD74HC240)

Application Note

7.2 Crosstalk

Crosstalk is the capacitative coupling of signals from one line to another.

Figure 20 shows an example of crosstalk noise levels using a twisted pair cable.

Figure 20 also shows that the wiring length beyond 1 m causes malfunction.

Careful precautions should be taken especially when the spacing between circuits is narrow.

Application Note

Waveform

Waveform3

Waveform2

Driver and receiver : HD74HC240

Wiring length l

50 Ω

= 50 pF

Vin

Measurement conditions

= 5 V

Ta = 25°C

f = 1 MHz

duty = 50%

= t

= 6 ns

Waveform

Vertical

Horizontal 5 V/div

100 ns/div

Waveform ,

Vertical

Horizontal 2 V/div

100 ns/div

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Waveform

GND

Wiring

lenght

l = 2m

l = 1m

= 0.5m

Vin = Low Vin = High

Figure 20 Crosstalk Noise Waveform (Driver: HD74HC240)

Application Note

8. Multivibrator

The output pulse width (twq) of a multivibrator is determined by the external capacitance (cext) and external

resistor (Rext), and calculated by the equation twq = K · Rext · Cext.

The value of constant K determines the part number according to the JEDEC committee as listed in Table

Hitachi has 4 types of high-speed CMOS logic, HD74HC123A, 221, 423A, 4538.

Constant K changes from the values of Table 4 when Cext is less than 0.01 µF.

Figure 21 and 22 graph the output pulse width vs external capacitance, constant K vs power supply voltage

characteristics of the HD74HC123A.

Table 4 JEDEC SP of Multivibrators

Product part no. Output pulse width

74HC123 tWQ = 0.45 · (Rext) · (Cext)

123A* tWQ = 1.0 · (Rext) · (Cext)

74HC221* tWQ = 0.7 · (Rext) · (Cext)

221A tWQ = 1.0 · (Rext) · (Cext)

74HC423 tWQ = 0.45 · (Rext) · (Cext)

423A* tWQ = 1.0 · (Rext) · (Cext)

74HC4538* tWQ = 0.7 · (Rext) · (Cext)

Note: *Presently under mass production at Hitachi.

Application Note

Output pulse width tWQ (s)

0.001 µ0.01 µ0.1 µ1.0 µ

External capacitance Cext (F)

0.0001 µ0.00001 µ

100 n

1 µ

10 µ

100 µ

1 m

10 m

100 m Ta = 25°C

VCC = 5 V Rext = 1000 kΩ

100 kΩ

10 kΩ

1 kΩ

Figure 21 Output Pulse Width vs External Capacitance and Resistance

Constant K

Supply voltage VCC (V)

0.8

1.0

1.2

1.4

Cext = 0.001 µF

Rext = 10 kΩ

Cext = 1 µF

Note: In order to prevent any malfunctions due to noise, connect a high-frequency performance

capacitor between VCC and GND, and keep the wiring between the external components and

Cext, Rext/Cext pins as short as possible.

Figure 22 Constant K vs Supply Voltage

Application Note

9. Interfacing

Hitachi’s high-speed CMOS logic has two types of input voltage levels, 74HC and 74HCT.

The 74HC has a CMOS-type input level and the 74HCT has a TTL-type input level.

Interfacing from high-speed CMOS logic to LS-TTL

Since the output level of high-speed CMOS logic is of CMOS, the use of an interfacing circuit is not

necessary.

This is the same case for a microcomputer and memory IC with TTL input levels.

VOH = 4.13V min > VIH = 2.0V min

VOL = 0.37V max < VIL = 0.8V max

VCC

GND

LS TTL74HC or 74HCT

Figure 23 Interfacing HS-CMOS to LS-TTL

Interfacing from LS-TTL to high-speed CMOS logic (74HCT type)

An interfacing circuit is not necessary.

This is the same case for a microcomputer and memory IC with TTL output levels.

VOH = 2.7V min > VIH = 2.0V min

VOL = 0.4V max < VIL = 0.8V max

VCC

GND

LS TTL 74HCT

Figure 24 Interfacing LS-TTL to 74HCT

Interfacing from LS-TTL to high-speed CMOS logic (74HC type)

A pull-up resistor should be added as shown in Figure 25.

The output voltage of LS-TTL (VOH) is 2.7 V (min), where as the input voltage of 74HC (VIH) is 3.15 V

(min.).

Application Note

This implies that LS-TTL cannot drive 74HC types directly.

This is the same case for a microcomputer and memory ICs with TTL output levels.

VOH = 2.7V min < VIH = 3.15V min

VOL = 0.4V max < VIL = 1.35V max

VCC

GND

LS TTL 74HC

Pull-up resistor

Figure 25 Interfacing LS-TTL to 74HC

Interfacing from LS-TTL with 3-state output to high-speed CMOS logic.

A pull-up or pull-down resistor should be added as shown in Figure 26.

When the output of a LS-TTL is in the high-impedance state, the input of the high-speed CMOS becomes

unstable.

This is the same case for all devices with a tri-state output structure.

VCC

GND

LS TTL with

3-state output 74HC

74HCT

Figure 26 Interfacing LS-TTL with 3-state Output to 74HC or 74HCT

Application Note

10. Surface Mount Package

10.1 Mounting small outline packages (SOP, TSSOP)

The explanation on the mounting of SOPs describes the characteristics and reliabilities of the small IC

package.

(1) Dip Soldering

Initially, the package is temporarily fixed on to the board by an adhesive.

Adhesive agent applied

Adhesive agent Cured

Residual flux removed

SOP attached

Adhesive

agent PCB

SOP

Direction of movement

Finished product

Wave solder

(solder vessel

for surface

mounting)

Dip soldering

Assembly completed

Electrode

Figure 27 Process Flow for Dip Soldering SOP

With the component side of the board downward, the package is then passed through molten solder. Figure

27 depicts the process flow for dip soldering SOP. As compared with reflow methods, this method exerts

an extremely high thermal stress on the semiconductor chips. The adverse effects from this thermal should

be avoided by providing a preheating zone to lessen the thermal shock and by minimizing the soldering

time. Figure 28 shows a typical temperature profile for dip soldering.

The dip soldering temperature is 260˚C maximum at a period of 10 seconds maximum (2 to 4 seconds is

recommended).

Application Note

Natural or

forced air

cooling

Solder melting point

Time

PCB surface temperature

Cooling

Dipping

Preheating 1 to 3 min

2 to 4 sec

80 to 150°C

T(max) = 260°C

Temperature

Figure 28 Temperature Profile of Dip Soldering

(2) Reflow Soldering

Reflow soldering is the basic method of mounting the SOP on to a board.

The solder composition to be used is Sn63/Pb37 or Sn62/Pb36/Ag2 with a melting point of 183˚C to

193˚C.

A recommended pasty flux is solder cream SP210-2 by Tamura Kaken. A pasty flux and organic solvent

are also used during the process.

Be careful to reflow solder at a low temperature for short periods of time. The recommended conditions

are shown below. The allowable board temperature is 230˚C maximum and the maximum heating time is

15 sec.

(3) Footprint dimension vs solderability

The failure rate of soldering is affected by footprint dimensions. Figure 29 shows the soldering failure with

the footprint dimension.

The recommended dimensions are within the safety zone of this figure.

When reflow sordering SOPs, the recommended thickness of a footprint is 0.2 mm min.

Application Note

Displacement

Safety

Bridge formed by solder

Lack of solder

Width of footprint W (mm)

Length of footprint L (mm)

0.1

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

SOP

Foot print

Notes: 1. Pin pitch = 1.27 mm

2. Recommended spacings between footprint centers.

e1 = 7.62 mm (SOP-14, 16)

e1 = 9.53 mm (SOP-20)

3. Both W and L are footprint dimensions based on the lead direction of the SOP.

Figure 29 Recommended Dimension of Footprint

(4) Thermal Resistance of SOP

Figure 30 shows the derating curves for SOPs of high-speed CMOS logic, and Table 6 lists the thermal

resistance (θj-a) for SOPs.

Application Note

25 30 35 40 45 50 55 60 65 70 75 80 85

Operating Ambient Temperature Ta (°C)

Maximnm continuous dissipation Pt (mW)

Derating curve of 14/16-pin SOP

1136

1000

961

785

681

576

500

468 at Tj (max) = 150 °C

at Tj (max) = 100 °C

No.

(1)

(2)

(3)

Wind

velocity Derating

factor

0m/s

1m/s

3m/s

6.3mW/°C

7.7mW/°C

9.1mW/°C

No.

(1)

(2)

(3)

Wind

velocity Derating

factor

0m/s

1m/s

3m/s

6.7mW/°C

9.1mW/°C

10.5mW/°C

25 30 35 40 45 50 55 60 65 70 75 80 85

Operatin

Ambient Temperature Ta

(

°C

)

Maximnm continuous dissipation Pt (mW)

Derating curve of 20-pin SOP

1312

1000

1137

835

767

682

500

502 at Tj (max) = 150 °C

at Tj (max) = 100 °C

(3)

(1)

(2)

(3)

(1)

(2)

(3)

(2)

(1)

Note: When Ta is below 25˚C, PT becomes the same value as at Ta = 25˚C being independent of Ta.

The data above was measured by using the ∆ VBE method on a glass-epoxy board (40×40×1.0

mm) with wiring density of 10%.

Careful considerations are required for input and load conditions, Ta, cooling, etc., during actual

use.

Figure 30 Derating Curves of SOP

Application Note

Table 6 Thermal Resistance of SOPs

Maximum continuous dissipation Ta = 25˚C

Number of

pins Wind velocity Derating factor Thermal

resistance Tj(max) = 150˚C Tj(max) = 100˚C

14 0 m/s 6.3 mW/˚C 160 ˚C/W 785 mW 468 mW

16 1 m/s 7.7 mW/˚C 130 ˚C/W 961 mW 576 mW

3 m/s 9.1 mW/˚C 110 ˚C/W 1136 mW 681 mW

20 0 m/s 6.7 mW/˚C 150 ˚C/W 835 mW 502 mW

1 m/s 9.1 mW/˚C 110 ˚C/W 1137 mW 682 mW

3 m/s 10.5 mW/˚C 95 ˚C/W 1312 mW 787 mW

(5) Thermal Resistance of TSSOP

Figure 31 shows the derating curve of TSSOP with HD74BC/AC/HC devices, table 7 shows the thermal

resistance (θj-a) and figure 32 shows the mounting method.

Derating Curves of Thin Small Outline Package

(14, 16, 20 and 24 Pins) at Tj (max) = 100°C

1000

500

300

25 30 35 40 45 50 55 60 65 70 75 80 85

Operatin

Temperature Ta

(

°C

)

Operatin

Temperature Ta

(

°C

)

1000

500

757

862

25 30 35 40 45 50 55 60 65 70 75 80 85

Tolerable Power Dissipation P

T (mW)

Tolerable Power Dissipation P

T (mW)

24 pin

20 pin

Derating Curves of Thin Small Outline Package

(14, 16, 20 and 24 Pins) at Tj (max) = 150°C

454

517

24 pin

20 pin

14/16 pin

Note: Fore the ambient temperature less than 25˚C, the power dissipation at 25˚C is applied. The data

above are measured by ∆ VBE method mounting on glass epoxy board (40 × 40 × 1.6 mm) with

10% of wiring density. In the actual application, using conditions, ambient temperature and

forced air-cooling conditions should be sufficiently examined.

Figure 31 Derating Curve of TSSOP

Application Note

Table 7 Thermal Resistance of TSSOP Package

Tolerable power dissipation

Number of

pins Wind velocity Derating factor Thermal

resistance at Tj(max) = 150˚C at Tj(max) = 100˚C

14 0 m/s 4.0 mW/˚C 250˚C/W 500 mW 300 mW

20 0 m/s 6.1 mW/˚C 165˚C/W 757 mW 454 mW

24 0 m/s 6.9 mW/˚C 145˚C/W 862 mW 517 mW

(6) TSSOP Solder Mounting

235°C

max 10sec max

140 to 160°C

≅ 60sec 1 to 4°C/sec

1 to 5°C/sec

Surface Temperature of Package

Time

Infrared-ray Reflow

Recommended Conditions

215°C30sec max

140 to 160°C

≅ 60sec

1 to 5°C/sec

Surface Temperature of Package

Time

Vapor-phase Reflow

Recommended Conditions

Recommended:For the whole heating on solder mounting, infrared-ray reflow and vapor-phase reflow are

recommended. (Solder-dipping is not recommended.)

Figure 32 Mounting Method of TSSOP

Application Note

(7) Marking on Package

(a) Small outline Package (EIAJ) 14, 16, 20 pins

YMWC

BC A

HD74BC Series

YMWC

HD74AC Series

YMWC

HD74HC Series

Lot No.

Type No.

(b) Small outline Package (JEDEC) 14, 16, 20 pins

YMWC

BC A

HD74BC Series

YMWC

HD74AC Series

YMWC

HD74HC Series

Lot No.

Type No.

Note: Meaning of marking on package example device name:

HD74BC245AT

Y: Year code (the last digit of year)

M: Month code

W: Week code

C: Control code

Type No.: delete HD74 and package code (T) from device name

YMWC

HD74BC Series

YMWC CA

HD74AC Series

YMWC

HD74HC Series

Lot No.

Type No.

• 14, 16, 20 pins

Note: Meaning of marking on package example device name:

HD74BC245AT

Y: Year code (the last digit of year)

M: Month code

W: Week code

C: Control code

Type No.: delete HD74 and package code (T) from device name