DS64BR111 www.ti.com SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 DS64BR111 Ultra Low Power 6.4 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis Check for Samples: DS64BR111 FEATURES DESCRIPTION * The DS64BR111 is an extremely low power, high performance dual-channel repeater for serial links with data rates up to 6.4 Gbps. The DS64BR111 pinout is configured as one bidirectional lane (one transmit, one receive channel). 1 2 * * * * * * * Two Channel Repeater for up to 6.4 Gbps - DS64BR111 : 1x Bidirectional Lane Low 65mW/Channel (Typical) Power Consumption, with Option to Power Down Unused Channels Advanced Signal Conditioning Features - Receive Equalization up to +25 dB - Transmit De-Emphasis up to -12 dB - Transmit VOD Control: 700 to 1200 mVp-p - < 0.2 UI of Residual DJ at 6.4 Gbps Programmable via Pin Selection, EEPROM or SMBus Interface Single Supply Operation Selectable: 2.5V or 3.3v Flow-Thru Pinout in 4mmx4mm 24-Pin Leadless WQFN Package >5kV HBM ESD Rating Industrial -40 to 85C Operating Temperature Range APPLICATIONS * * High-Speed Active Copper Cable Modules and FR-4 Backplane in Communication Systems FC, SAS, SATA 3/6 Gbps (with OOB Detection), InfiniBand, CPRI, OBSAI, RXAUI and Many Others The DS64BR111 features a powerful 4-stage continuous time linear equalizer (CTLE) to provide a boost of up to +25 dB at 3.2 GHz and open an input eye that is completely closed due to inter-symbol interference (ISI) induced by the interconnect mediums such as an FR-4 backplane or AWG-30 cables. The transmitter features a programmable output de-emphasis driver with up to -12 dB and allows amplitude voltage levels to be selected from 700 mVp-p to 1200 mVp-p to suit multiple application scenarios. The programmable settings can be applied via pin settings, SMBus (I2C) protocol or an external EEPROM. When operating in the EEPROM mode, the configuration information is automatically loaded on power up - This eliminates the need for an external microprocessor or software driver. Part of TI's PowerWise family of energy efficient devices, the DS64BR111 consumes just 65 mW/channel (typical), and allow the option to turn-off unused channels. This ultra low power consumption eliminates the need for external heat sinks and simplifies thermal management in active cable applications. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011-2013, Texas Instruments Incorporated DS64BR111 SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 www.ti.com Typical Application DS64BR111 Interconnect Cable ASIC/FPGA DS64BR111 ASIC/FPGA Block Diagram - Detail View Of Channel (1 Of 2) VOD/ DE-EMPHASIS CONTROL VOD VDD SMBus 50: DEM 50: SMBus EQ OUTBUF IN+ IN- OUT+ OUT- Tx IDLE Enable EQ[1:0] SMBus IDLE DETECT 2 Channel Status and Control Submit Documentation Feedback LOS SD_TH TX_DIS MODE Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 DS64BR111 www.ti.com SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 (1) SCL/DEMB SDA/DEMA ENSMB EQB1/AD2 EQB0/AD3 4 3 2 1 TX_DIS 5 6 Pin Diagram OUTA+ 7 24 INA+ OUTA- 8 23 INA- 22 VDD 21 VDD AD1/EQA1 9 AD0/EQA0 10 INB+ 11 20 OUTB+ INB- 12 19 OUTB- 14 15 16 17 18 SD_TH VIN VDD_SEL VOD_SEL / READEN# MODE / DONE# 13 LOS SMBUS AND CONTROL The center DAP on the package bottom is the device GND connection. This pad must be connected to GND through multiple (minimum of 4) vias to ensure optimal electrical and thermal performance. DS64BR111 Pin Diagram 24 lead PIN DESCRIPTIONS Pin Name Pin Number I/O, Type (1) Pin Description Differential High Speed I/O's INA+, INA- , INB+, INB-, 24, 23 11, 12 I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 50 termination resistor connects INx+ to VDD and INx- to VDD when enabled. OUTA+, OUTA-, OUTB+, OUTB-, 7, 8 20, 19 O,CML Inverting and non-inverting 50 driver outputs with de-emphasis. Compatible with AC coupled CML inputs. 3 I, LVCMOS Float System Management Bus (SMBus) enable pin Tie HIGH = Register Access, SMBus Slave mode FLOAT = SMBus Master read from External EEPROM Tie LOW = External Pin Control Mode Control Pins ENSMB ENSMB = 1 (SMBUS MODE) SCL 5 I, LVCMOS O, Open Drain ENSMB Master or Slave mode SMBUS clock input pin is enabled. A clock input in Slave mode. Can also be a clock output in Master mode. SDA 4 I, LVCMOS, O, OPEN Drain ENSMB Master or Slave mode The SMBus bidirectional SDA pin is enabled. Data input or open drain (pulldown only) output. (1) LVCMOS inputs without the "Float" conditions must be driven to a logic low or high at all times or operation is not specified. Unless the "Float" level is desired; 4-Level input pins require a minimum 1K resistor to GND, VDD (in 2.5V mode), or VIN (in 3.3V mode). For additional information, Table 1 Table 5 Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10-90% Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 3 DS64BR111 SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin Name Pin Number I/O, Type (1) Pin Description AD0-AD3 10, 9, 2, 1 I, LVCMOS Float (4-Levels) ENSMB Master or Slave mode SMBus Slave Address Inputs. In SMBus mode, these pins are the user set SMBus slave address inputs. There are 16 addresses supported by these pins. Pins must be tied LOW or HIGH when used to define the device SMBus address. Note: Setting VOD_SEL = High in SMBus Mode will force the Address = B0'h READEN# 17 I, LVCMOS When using an External EEPROM, a transition from high to low starts the load from the external EEPROM DONE# 18 IO, LVCMOS, Float (4-Levels) EEPROM Download Status HIGH indicates Error / Still Loading LOW indicates download complete. No Error. EQA0, EQA1 EQB0, EQB1 10, 9 1, 2 I, LVCMOS, Float EQA/B ,0/1 control the level of equalization of each channel. The EQA/B pins (4-Levels) are active only when ENSMB is de-asserted (LOW). When ENSMB goes high the SMBus registers provide independent control of each lane, and the EQB0/B1 pins are converted to SMBUS AD2/AD3 inputs. DEMA, DEMB 4, 5 IO, LVCMOS, Float (4-Levels) DEMA/B controls the level of de-emphasis. The DEMA/B pins are only active when ENSMB is de-asserted (LOW). Each of the 4 A/B channels have the same level unless controlled by the SMBus control registers. When ENSMB goes high the SMBus registers provide independent control of each lane and the DEM pins are converted to SMBUS SCL and SDA pins. TX_DIS 6 I, LVCMOS DS64BR111 High = OUTA Enabled / OUTB Disabled Low = OUTA/B Enabled VOD_SEL 17 I, LVCMOS, Float EQ Mode and VOD select. (4-Levels) High = (VOD = 1.1V/1.3V) Float = (VOD = 1.0 V) 20K = (VOD = 1.2 V) Low = (VOD = 700m V) Note: DS64BR111 OUTA is limited to 700mV in pin mode, see Table 4 for additional information. Note: Setting VOD_SEL = High in SMBus Mode will force the SMBus Address = B0'h VDD_SEL 16 I, Internal Pull-up Enables the 3.3V to 2.5V internal regulator Low = 3.3 V Operation Float = 2.5 V Operation MODE 18 I, LVCMOS Controls Device Mode of Operation High = Continuous Talk Float = Slow OOB 20K = eSATA Mode, Fast OOB, Auto Low Power on 100 uS of inactivity. SD stays active. Low = SAS Mode, Fast OOB 13 O, Open Drain Indicates Loss of Signal (Default is LOS on INA). Can be modified via SMBus registers. 14 I, LVCMOS, Float The SD_TH pin controls LOS threshold setting; (4-Levels) Assert (mV), Deassert (mV) 20K = 160 mV, 100 mV Float = 180 mV, 110 mV (Default) High = 190 mV, 130 mV Low = 210 mV, 150 mV Note: Using values less than the default level can extend the time required to detect LOS and are not recommended. ENSMB = 0 (PIN MODE) Status Output LOS LOS Threshold Input SD_TH Power 4 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 DS64BR111 www.ti.com SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 PIN DESCRIPTIONS (continued) Pin Name Pin Number I/O, Type (1) Pin Description VDD 21, 22 Power Power supply pins 2.5V mode connect to 2.5V 3.3V mode do not connect to any supply voltage. Should be used to attach external decoupling to device. 100 - 200 nF recommended. Note: See APPLICATION INFORMATION for additional information. VIN 15 Power VIN = 3.3V +/-10% (input to internal LDO regulator) Note: Must FLOAT for 2.5V operation. See APPLICATION INFORMATION for additional information. GND DAP Power Ground pad (DAP - die attach pad). These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) Supply Voltage (VDD) -0.5V to +2.75V Supply Voltage (VIN) -0.5V to +4.0V LVCMOS Input/Output Voltage -0.5V to +4.0V CML Input Voltage -0.5V to (VDD+0.5) CML Input Current -30 to +30 mA Junction Temperature 125C Storage Temperature -40C to +125C ESD Rating HBM, STD - JESD22-A114F > 5 kV MM, STD - JESD22-A115-A 100 V CDM, STD - JESD22-C101-D 1250 V Package Thermal Resistance JC 3.2C/W JA, No Airflow, 4 layer JEDEC 33.0C/W For soldering specifications: See product folder at www.ti.com http://www.ti.com/lit/SNOA549 (1) (2) "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute Maximum Numbers are specified for a junction temperature range of -40C to +125C. Models are validated to Maximum Operating Voltages only. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for availability and specifications. RECOMMENDED OPERATING CONDITIONS Min Typ Max Units Supply Voltage (2.5V Mode) 2.375 2.5 2.625 V Supply Voltage (3.3V Mode) 3.0 3.3 3.6 V Ambient Temperature -40 25 +85 C 3.6 V SMBus (SDA, SCL) Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 5 DS64BR111 SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Min Typ Max Units Power Supply Current IDD Supply Current TX_DIS = LOW, EQ = ON VOD_SEL = Float ( 1000 mV) 50 63 Auto Low Power Mode TX_DIS = LOW, MODE = 20K VID CHA and CHB = 0.0V VOD_SEL = Float (1000 mV) 12 15 TX_DIS = HIGH 25 mA 35 LVCMOS DC Specifications VIH Voltage Input High VIL Voltage Input Low VOH Voltage Output High IOH = -4.0 mA (1) VOL Voltage Output Low IOL = 4.0 mA IIN Input Leakage Current Vinput = 0V or VDD VDD_SEL = Float IIN-P Input Leakage Current 4-Level Input 2.0 VDD V GND 0.7 V 2.0 V 0.4 V -15 +15 uA Vinput = 0V or VIN VDD_SEL = Low -15 +15 Vinput = 0V or VDD - 0.05 V VDD_SEL = Float Vinput = 0V or VIN - 0.05 V VDD_SEL = Low -160 +80 uA LOS and ENABLE / DISABLE Timing TLOS_OFF Input IDLE to Active See (2) RX_LOS response time 0.035 uS TLOS_ON Input Active to IDLE See (2) RX_LOS response time 0.4 uS TOFF TX Disable assert Time TX_DIS = HIGH to Output OFF See (2) 0.005 uS TON TX Disable negateTime See (2) TX_DIS = LOW to Output ON 0.150 uS TLP_EXIT Auto Low Power Exit ALP to Normal Operation See (2) 150 nS TLP_ENTER Auto Low Power Enter Normal Operation to Auto Low Power See (2) 100 uS CML RECEIVER INPUTS VTX Source Transmit Launch Signal Level Default power-up conditions ENSMB = 0 or 1 VOD_SEL = Float RLRX-IN RX return loss SDD11 @ 4.1 GHz 190 800 -12 SDD11 @ 11.1 GHz -8 SCD11 @ 11.1 GHz -10 1600 mV dB HIGH SPEED TRANSMITTER OUTPUTS (1) (2) 6 VOH only applies to the DONE# pin; LOS, SCL, and SDA are open-drain outputs that have no internal pull-up capability. DONE# is a full LVCMOS output with pull-up and pull-down capability Parameter not tested in production. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 DS64BR111 www.ti.com SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Conditions VOD1 Output Voltage Differential Swing OUT+ and OUT- AC coupled and terminated by 50 to GND VOD_SEL = LOW (700 mV setting) DE = LOW Min 500 Typ 650 800 VOD2 Output Voltage Differential Swing OUT+ and OUT- AC coupled and terminated by 50 to GND VOD_SEL = FLOAT (1000 mV setting) DE = LOW 800 1000 1100 VOD3 Output Voltage Differential Swing OUT+ and OUT- AC coupled and terminated by 50 to GND VOD_SEL = 20K (1200 mV setting) DE = LOW 950 1150 1350 VOD_DE1 De-Emphasis Levels OUT+ and OUT- AC coupled and terminated by 50 to GND VOD_SEL = FLOAT (1000 mV setting) DE = FLOAT -3 dB VOD_DE2 De-Emphasis Levels OUT+ and OUT- AC coupled and terminated by 50 to GND VOD_SEL = FLOAT (1000 mV setting) DE = 20K -6 dB VOD_DE3 De-Emphasis Levels OUT+ and OUT- AC coupled and terminated by 50 to GND VOD_SEL = FLOAT (1000 mV setting) DE = HIGH -9 dB VCM-AC Output Common-Mode Voltage AC Common Mode Voltage DE = 0 dB, VOD <= 1000 mV 4.5 mV (RMS) VCM-DC Output DC CommonMode Voltage DC Common Mode Voltage VIDLE TX IDLE Output Voltage RLTX-DIFF TX return loss 0 SDD22 @ 4.1 GHz Max 1.1 -13 SDD22 @ 11.1 GHz -9 SCC22 @ 2.5 GHz -22 SCC22 @ 11.1 GHz delta ZM Transmitter Termination DC, IFORCE = +/- 100 uA Mismatch TR/F Transmitter Rise and Fall Time TPD TCCSK Units mVp-p 1.9 V 30 mV dB -10 (3) 2.5 % 20% - 80% (4) 38 Propagation Delay Measured at 50% crossing 230 ps Channel to Channel Skew T = 25C, VDD = 2.5V 7 ps TPPSK Part to Part Channel Skew T = 25C, VDD = 2.5V 20 ps TDI Time to transition to valid electrical IDLE after an active burst in OOB signaling 6.5 ns TID Time to transition to valid active burst after leaving electrical IDLE in OOB signaling 3.2 ns (3) (4) Force +/- 100 uA on output, measure delta V on the Output and calculate impedance. Mismatch is the percentage difference of OUTn+ and OUTn- impedance driving the same logic state. Default VOD used for testing. DE = -1.5 dB level used to compensate for fixture attenuation. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 7 DS64BR111 SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Conditions Min Typ Max TENVELOPE_DISTO Active OOB timing distortion, input active RT time vs. output active time Units 3.3 ns 0.35 ps (RMS) 0.065 UI OUTPUT JITTER SPECIFICATIONS (5) RJ Random Jitter DJ1 No Media Source Amplitude = 700 mV, PRBS15 pattern, 6.4 Gbps VOD = Default, EQ = minimum, DE = 0 dB Deterministic Jitter Equalization DJE1 DJE2 Residual Deterministic Jitter 10.3125 Gbps 8 meter 30AWG Cable on Input Source = 700 mV, PRBS15 pattern EQ = 0F'h; See Figure 15 0.15 UI Residual Deterministic Jitter 6.4 Gbps 30" FR4 on Inputs Source = 800 mV, PRBS15 pattern EQ = 16'h; See Figure 13 0.10 UI Residual Deterministic Jitter 6.4 Gbps 10" 4 mil stripline FR4 on Outputs Source = 700 mV, PRBS15 pattern EQ = 00 (Min), DE = 010'b See Figure 17 0.085 UI De-emphasis DJD1 (5) Typical jitter reported is determined by jitter decomposition software on a DSA8200 Oscilloscope. ELECTRICAL CHARACTERISTICS -- SERIAL MANAGEMENT BUS INTERFACE Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ Max Units 0.8 V 3.6 V SERIAL BUS INTERFACE DC SPECIFICATIONS: (1) VIL Data, Clock Input Low Voltage VIH Data, Clock Input High Voltage IPULLUP Current Through Pull-Up Resistor or Current Source VDD Nominal Bus Voltage ILEAK-Bus Input Leakage Per Bus Segment See (2) CI Capacitance for SDA and SCL See (2) and RTERM External Termination Resistance pull to VDD = 2.5V 5% OR 3.3V 10% 2.1 High Power Specification 4 mA 2.375 3.6 V -200 +200 A 10 pF (3) (4) Pullup VDD = 3.3V (2) (3) (5) Pullup VDD = 2.5V (2) (3) (5) 2000 1000 SERIAL BUS INTERFACE TIMING SPECIFICATIONS FSMB Bus Operating Frequency ENSMB = VDD (Slave Mode) ENSMB = FLOAT (Master Mode) (2) TBUF (1) (2) (3) (4) (5) 8 Bus Free Time Between Stop and Start Condition 280 1.3 400 400 kHz 520 kHz s EEPROM interface requires 400 KHz capable EEPROM device. Recommended value. Recommended maximum capacitance load per bus segment is 400pF. Specified by Design and/or characterization. Parameter not tested in production. Maximum termination voltage should be identical to the device supply voltage. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 DS64BR111 www.ti.com SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS -- SERIAL MANAGEMENT BUS INTERFACE (continued) Over recommended operating supply and temperature ranges unless other specified. Symbol THD:STA Parameter Hold time after (Repeated) Start Condition. After this period, the first clock is generated. Conditions Min Typ Max Units At IPULLUP, Max 0.6 s TSU:STA Repeated Start Condition Setup Time 0.6 s TSU:STO Stop Condition Setup Time 0.6 s THD:DAT Data Hold Time 0 ns TSU:DAT Data Setup Time 100 ns TLOW Clock Low Period THIGH Clock High Period See (6) tF Clock/Data Fall Time See (6) 1.3 (6) tR Clock/Data Rise Time See tPOR Time in which a device must be operational after power-on reset See (6) and (6) 0.6 s 50 s 300 ns 300 ns 500 ms (4) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common AC specifications for details. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 9 DS64BR111 SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 www.ti.com TIMING DIAGRAMS Figure 1. CML Output Transition Times Figure 2. Propagation Delay Timing Diagram Figure 3. Idle Timing Diagram tLOW tR tHIGH SCL tHD:STA tBUF tHD:DAT tF tSU:STA tSU:DAT tSU:STO SDA SP ST SP ST Figure 4. SMBus Timing Parameters 10 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 DS64BR111 www.ti.com SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 FUNCTIONAL DESCRIPTION The DS64BR111 is a high performance circuit capable of delivering excellent performance. Careful attention must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer to the information below and Revision 4 of the LVDS Owner's Manual for more detailed information on high speed design tips to address signal integrity design issues. The control pins have been enhanced to have 4 different levels and provide a wider range of control settings. Refer to Table 1 Table 1. 4-Level Control Pin Settings Pin Setting Description 0 Tie pin to GND through a 1 K resistor R Tie pin to ground through 20 K resistor Float Float the pin (no connection) 1 Tie pin to VDD through a 1 K resistor Note: 4-Level IO pins require a 1K resistance to GND or VDD/VIN. It is possible to tie mulitple 4-level IO pins together with a single resistor to GND or VDD/VIN. When multiple IOs are connected in parallel, the resistance to GND or VDD/VIN should be adjusted to compensate. For 2 pins the optimal resistance is 500 Ohms, 3 pins = 330 Ohms, and 4 pins = 250 Ohms. Note: For 2.5V mode the control pin logic 1 level is VDD (pins 21 and 22), in 3.3V mode the control pin logic 1 level is defined by VIN (pin 15). Table 2. Equalizer Settings Level EQA1/EQB1 EQA0/EQB0 EQ -- 8 bits [7:0] dB Boost at 3.2 Ghz Suggested Media 1 0 0 0000 0000 = 0x00 3.7 FR4 < 5 inch trace 2 0 R 0000 0001 = 0x01 6.0 FR4 5 inch trace 3 0 Float 0000 0010 = 0x02 7.5 FR4 10 inch trace 4 0 1 0000 0011 = 0x03 8.5 FR4 15 inch trace 5 R 0 0000 0111 = 0x07 11 FR4 20 inch trace 6 R R 0001 0101 = 0x15 12 FR4 25 inch trace 7 R Float 0000 1011 = 0x0B 14 FR4 25 inch trace 8 R 1 0000 1111 = 0x0F 15 7m 30AWG Cable 9 Float 0 0101 0101 = 0x55 15 FR4 30 inch trace 10 Float R 0001 1111 = 0x1F 18 8m 30 AWG Cable FR4 35 inch trace 11 Float Float 0010 1111 = 0x2F 20 10m 30 AWG Cable 12 Float 1 0011 1111 = 0x3F 22 10m - 12m, Cable 13 1 0 1010 1010 = 0xAA 23 14 1 R 0111 1111 = 0x7F 25 15 1 Float 1011 1111 = 0xBF 27 16 1 1 1111 1111 = 0xFF 28 Note: Settings are approximate and will change based on PCB material, trace dimensions, and driver waveform characteristics. Table 3. De-emphasis and Output Voltage Settings Level VOD_SEL DEMA/B SMBus Register DEM Level SMBus Register VOD Level VOD (mV) 1 0 0 000 000 700 DEM (dB) 0 2 0 Float 010 000 700 - 3.5 3 0 R 011 000 700 -6 4 0 1 101 000 700 -9 5 Float 0 000 011 1000 0 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 11 DS64BR111 SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 www.ti.com Table 3. De-emphasis and Output Voltage Settings (continued) 6 Float Float 010 011 1000 - 3.5 7 Float R 011 011 1000 -6 8 Float 1 101 011 1000 -9 9 R 0 000 101 1200 -0 10 R Float 010 101 1200 - 3.5 11 R R 011 101 1200 -6 12 R 1 101 101 1200 -9 13 1 0 000 100 1100 0 14 1 Float 001 100 1100 - 1.5 15 1 R 001 110 1300 - 1.5 16 1 1 010 110 1300 - 3.5 Note: The DS64BR111 VOD for OUTPUT A is limited to 700 mV in pin mode (ENSMB=0). With ENSMB = 1 or FLOAT, the VOD for OUTPUT A can be adjusted with SMBus register 0x23 [4:2] as shown in the SMBus Register Table. Note: In SMBus Mode if VOD_SEL is in the Logic 1 state (1K resistor to VIN/VDD) the DS64BR111 AD0-AD3 pins are internally forced to 0'h Table 4. Signal Detect Threshold Level SD_TH SMBus REG bit [3:2] and [1:0] Assert Level (Typical) De-assert Level (Typical) 0 10 210 mV 150 mV 20K to GND 01 160 mV 100 mV Float (Default) 00 180 mV 110 mV 1 11 190 mV 130 mV Note: VDD = 2.5V, 25C, and 010101 pattern at 6.4 Gbps 12 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 DS64BR111 www.ti.com SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 APPLICATION INFORMATION 4-Level Input Configuration Guidelines The 4-level input pins utilize a resistor divider to help set the 4 valid levels. There is an internal 30K pull-up and a 60K pull-down connected to the package pin. These resistors, together with the external resistor connection combine to achieve the desired voltage level. Using the 1K pull-up, 1K pull-down, no connect, and 20K pull-down provide the optimal voltage levels for each of the four input states. Table 5. 4-Level Input Voltage * Level Setting 3.3V Mode 2.5V Mode 0 01K to GND 0.1 V 0.08 V R 20K to GND 0.33 * VIN 0.33 * VDD F FLOAT 0.67 * VIN 0.67 * VDD 1 1K to VDD/VIN VIN - 0.05V VIN - 0.04V Typical 4-Level Input Thresholds - Level 1 - 2 = 0.2 VIN or VDD - Level 2 - 3 = 0.5 VIN or VDD - Level 3 - 4 = 0.8 VIN or VDD In order to minimize the startup current associated with the integrated 2.5V regulator the 1K pull-up / pull-down resistors are recommended. If several 4 level inputs require the same setting, it is possible to combine two or more 1K resistors into a single lower value resistor. As an example; combining two inputs with a single 500 resistor is a good way to save board space. PCB Layout Guidelines The CML inputs and outputs have been optimized to work with interconnects using a controlled differential impedance of 85 - 100. It is preferable to route differential lines exclusively on one layer of the board, particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever differential vias are used the layout must also provide for a low inductance path for the return currents as well. Route the differential signals away from other signals and noise sources on the printed circuit board. See AN1187 (SNOA401) for additional information on WQFN packages. Different transmission line topologies can be used in various combinations to achieve the optimal system performance. Impedance discontinuities at vias can be minimized or eliminated by increasing the swell around each hole and providing for a low inductance return current path. When the via structure is associated with thick backplane PCB, further optimization such as back drilling is often used to reduce the detrimental high frequency effects of stubs on the signal path. Power Supply Configuration Guidelines The DS64BR111 can be configured for 2.5V operation or 3.3V operation. The lists below outline required connections for each supply selection. 1. 2. 3. 4. 5. 3.3V Mode of Operation Tie VDD_SEL = 0 with 1K resistor to GND. Feed 3.3V supply into VIN pin. Local 1.0 uF decoupling at VIN is recommended. See information on VDD bypass below. SDA and SCL pins should connect pull-up resistor to VIN Any 4-Level input which requires a connection to "Logic 1" should use a 1K resistor to VIN 6. 7. 8. 9. 2.5V Mode of Operation VDD_SEL = Float VIN = Float Feed 2.5V supply into VDD pins. See information on VDD bypass below. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 13 DS64BR111 SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 www.ti.com 10. SDA and SCL pins connect pull-up resistor to VDD for 2.5V uC SMBus IO 11. SDA and SCL pins connect pull-up resistor to VIN for 3.3V uC SMBus IO 12. Any 4-Level input which requires a connection to "Logic 1" should use a 1K resistor to VIN Note: The DAP (bottom solder pad) is the GND connection. Power Supply Bypass Two approaches are recommended to ensure that the DS64BR111 is provided with an adequate power supply. First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with distributed capacitance. Second, careful attention to supply bypassing through the proper use of bypass capacitors is required. A 0.1 F bypass capacitor should be connected to each VDD pin such that the capacitor is placed as close as possible to the device. Smaller body size capacitors can help facilitate proper component placement. System Management Bus (SMBus) and Configuration Registers The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB must be pulled high to enable SMBus mode and allow access to the configuration registers. The DS64BR111 has AD[3:0] inputs in SMBus mode. These pins are the user set SMBus slave address inputs. When pulled low the AD[3:0] = 0000'b, the device default address byte is B0'h. Based on the SMBus 2.0 specification, this configuration results in a 7-bit slave address of 1011000'b. The LSB is set to 0'b (for a WRITE), thus the 8-bit value is 1011 0000'b or B0'h. The device address byte can be set with the use of the AD[3:0] inputs. Shown in the form of an expression: Slave Address [7:4] = The DS64BR111 hardware address (1011'b) + Address pin AD[3] Slave Address [3:1] = Address pins AD[2:0] Slave Address [0] = 0'b for a WRITE or 1'b for a READ Slave Address Examples: * AD[3:0] = 0001'b, the device slave address byte is B2'h - Slave Address [7:4] = 1011'b + 0'b = 1011'b or B'h - Slave Address [3:1] = 001'b - Slave Address [0] = 0'b for a WRITE * AD[3:0] = 0010'b, the device slave address byte is B4'h - Slave Address [7:4] = 1011'b + 0'b = 1011'b or B'h - Slave Address [3:1] = 010'b - Slave Address [0] = 0'b for a WRITE * AD[3:0] = 0100'b, the device slave address byte is B8'h - Slave Address [7:4] = 1011'b + 0'b = 1011'b or B'h - Slave Address [3:1] = 100'b - Slave Address [0] = 0'b for a WRITE * AD[3:0] = 1000'b, the device slave address byte is C0'h - Slave Address [7:4] = 1011'b + 1'b = 1100'b or C'h - Slave Address [3:1] = 000'b - Slave Address [0] = 0'b for a WRITE TRANSFER OF DATA VIA THE SMBus During normal operation the data on SDA must be stable during the time when SCL is High. There are three unique states for the SMBus: START: A High-to-Low transition on SDA while SCL is High indicates a message START condition. STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition. 14 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 DS64BR111 www.ti.com SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 IDLE: If SCL and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they are High for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state. SMBus TRANSACTIONS The device supports WRITE and READ transactions. See Register Description table for register address, type (Read/Write, Read Only), default value and function information. WRITING A REGISTER To 1. 2. 3. 4. 5. 6. 7. write a register, the following protocol is used (see SMBus 2.0 specification). The Host drives a START condition, the 7-bit SMBus address, and a "0" indicating a WRITE. The Device (Slave) drives the ACK bit ("0"). The Host drives the 8-bit Register Address. The Device drives an ACK bit ("0"). The Host drive the 8-bit data byte. The Device drives an ACK bit ("0"). The Host drives a STOP condition. The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur. READING A REGISTER To read a register, the following protocol is used (see SMBus 2.0 specification). 1. The Host drives a START condition, the 7-bit SMBus address, and a "0" indicating a WRITE. 2. The Device (Slave) drives the ACK bit ("0"). 3. The Host drives the 8-bit Register Address. 4. The Device drives an ACK bit ("0"). 5. The Host drives a START condition. 6. The Host drives the 7-bit SMBus Address, and a "1" indicating a READ. 7. The Device drives an ACK bit "0". 8. The Device drives the 8-bit data value (register contents). 9. The Host drives a NACK bit "1"indicating end of the READ transfer. 10. The Host drives a STOP condition. The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur. Please see SMBus Register Map Table for more information for more information. Register Address Slave Address S Device + A3 ID A 2 A 1 A 0 a 0 c k 7 6 5 4 3 2 1 Slave Address 0 a c k S Device + A3 ID A 2 A 1 Data A 0 1 a c k 7 6 5 4 3 2 1 0 a c k P Figure 5. Typical SMBus Write Operation EEPROM Modes in DS64BR111 Device The DS64BR111 device supports reading directly from an external EEPROM device by implementing SMBus Master mode. When using the SMBus master mode, the DS64BR111 will read directly from specific location in the external EEPROM. When designing a system for using the external EEPROM, the user needs to follow these specific guidelines. * Set the DS64BR111 into SMBus Master Mode - Float ENSMB (PIN 3) * The external EEPROM device address byte must be 0xA0'h * Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is B0'h. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 15 DS64BR111 SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 * * * * www.ti.com Based on the SMBus 2.0 specification, a device can have a 7-bit slave address of 1011 000'b. The LSB is set to 0'b (for a WRITE). The bit mapping for SMBus is listed below: - [7:5] = Reserved Bits from the SMBus specification - [4:1] = Usable SMBus Address Bits - [0] = Write Bit The DS64BR111 devices have AD[3:0] inputs in SMBus mode (pins 1, 2, 9, 10). These pins set SMBus slave address. The AD[3:0] pins do not have any internal pull resistors. When the AD[3:0] = 0001'b, the device address byte is B2'h. - [7:5] = 4b'101 - [4:1] = Address of 4'b0001 - [0] = Write Bit, 1'b0 The device address can be set with the use of the AD[3:0] input up to 16 different addresses. Use the example below to set each of the SMBus addresses. - AD[3:0] = 0001'b, the device address byte is B2'h - AD[3:0] = 0010'b, the device address byte is B4'h - AD[3:0] = 0011'b, the device address byte is B6'h - AD[3:0] = 0100'b, the device address byte is B8'h The master implementation in the DS64BR111, support multiple devices reading from 1 EEPROM. When tying multiple devices to the SDA and SCL pins, use these guidelines: - Use adjacent SMBus addresses for the 4 devices - Use a pull-up resistor on SDA; value = 4.7K - Use a pull-up resistor on SCL: value = 4.7K - Daisy-chain READEN# (pin 17) and DONE# (pin18) from one device to the next device in the sequence 1. Tie READEN# of the 1st device in the chain (U1) to GND 2. Tie DONE# of U1 to READEN# of U2 3. Tie DONE# of U2 to READEN# of U3 4. Tie DONE# of U3 to READEN# of U4 5. Optional: Tie DONE# of U4 to a LED to show each of the devices have been loaded successfully Master EEPROM Mode in the DS100BR111 Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS100BR111 device. The first 3 bytes of the EEPROM always contain a header common and necessary to control initialization of all devices connected to the I2C bus. CRC enable flag to enable/disable CRC checking. There is a MAP bit to flag the presence of an address map that specifies the configuration data start in the EEPROM. If the MAP bit is not present the configuration data start address is derived from the DS100BR111 address and the configuration data size. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the EEPROM. There are 37 bytes of data size for each DS100BR111 device. 16 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 DS64BR111 www.ti.com SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 :1000000000002000000407002FED4002FED4002FC4 :10001000AD4002FAD400005F568005F5A8005F5AE9 :100020008005F5A800005454F100000000000000A8 :1000300000000000000000000000000000000000C0 :1000400000000000000000000000000000000000B0 :1000500000000000000000000000000000000000A0 :100060000000000000000000000000000000000090 :100070000000000000000000000000000000000080 :100080000000000000000000000000000000000070 :100090000000000000000000000000000000000060 :1000A0000000000000000000000000000000000050 :1000B0000000000000000000000000000000000040 :1000C0000000000000000000000000000000000030 :1000D0000000000000000000000000000000000020 :1000E0000000000000000000000000000000000010 :1000F0000000000000000000000000000000000000 :00000001FF CRC-8 based on 40 bytes of data in this shaded area CRC Polynomial = 0x07 Insert the CRC value here MAX EEPROM Burst = 32 Figure 6. Typical EEPROM Data Set The CRC-8 calculation is performed on the first 3 bytes of header information plus the 37 bytes of data for the DS64BR111 or 40 bytes in total. The result of this calculation is placed immediately after the DS64BR111 data in the EEPROM which ends with "5454". The CRC-8 in the DS64BR111 uses a polynomial = x8 + x2 + x + 1 In SMBus master mode the DS64BR111 reads its initial configuration from an external EEPROM upon power-up. Some of the pins of the DS64BR111 perform the same functions in SMBus master and SMBus slave mode. Once the DS64BR111 has finished reading its initial configuration from the external EEPROM in SMBus master mode it reverts to SMBus slave mode and can be further configured by an external controller over the SMBus. The connection to an external SMBus master is optional and can be omitted for applications were additional security is desirable. There are two pins that provide unique functions in SMBus master mode. * DONE# * READEN# When the DS64BR111 is powered up in SMBus master mode, it reads its configuration from the external EEPROM when the READEN# pin goes low. When the DS64BR111 is finished reading its configuration from the external EEPROM, it drives the DONE# pin low. In applications where there is more than one DS64BR111 on the same SMBus, bus contention can result if more than one DS64BR111 tries to take control of the SMBus at the same time. The READEN# and DONE# pins prevent this bus contention. The system should be designed so that the READEN# pin from one DS64BR111 in the system is driven low on power-up. This DS64BR111 will take command of the SMBus on power-up and will read its initial configuration from the external EEPROM. When it is finished reading its configuration, it will drive the DONE# pin low. This pin should be connected to the READEN# pin of another DS64BR111. When this DS64BR111 senses its READEN# pin driven low, it will take command of the SMBus and read its initial configuration from the external EEPROM, after which it will set its DONE# pin low. By connecting the DONE# pin of each DS64BR111 to the READEN# pin of the next DS64BR111, each DS64BR111 can read its initial configuration from the EEPROM without causing bus contention. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 17 DS64BR111 SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 www.ti.com EEPROM GND GND GND AD0 AD1 3.3V SDA SCL AD2 One or both of these lines should float for EEPROM larger than 256 bytes. Note: Set AD[3:0] of each DS64BR111 to unique SMBus Address. SDA SCL SCL SDA ENSMB AD2 AD3 4 3 2 1 AD3 1 TX_DIS AD2 2 5 ENSMB 3 FLOAT 6 SCL SDA 4 AD3 1 TX_DIS AD2 2 5 ENSMB 3 FLOAT 6 SCL SDA 4 TX_DIS 5 6 FLOAT From External SMBus Master OUTA+ 7 24 INA+ OUTA+ 7 24 INA+ OUTA+ 7 24 OUTA- 8 23 INA- OUTA- 8 23 INA- OUTA- 8 23 INA- AD1 9 22 VDD AD1 9 22 VDD AD1 9 22 VDD AD0 10 21 VDD 21 VDD SMBUS AND CONTROL 13 14 15 16 17 18 SD_TH VIN VDD_SEL READEN# DONE# 18 OUTB- DONE# 19 READEN# 12 17 INB- 16 OUTB- 15 19 VDD_SEL 12 VIN OUTB+ INB- 14 20 SD_TH 11 13 10 INB+ LOS AD0 OUTB+ DONE# VDD 20 18 21 11 17 10 READEN# AD0 INB+ GND 16 OUTB- VDD_SEL 19 15 12 VIN INB- 14 OUTB+ 13 20 LOS 11 SD_TH INB+ SMBUS AND CONTROL LOS SMBUS AND CONTROL INA+ Figure 7. Typical multi-device EEPROM connection diagram 18 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 DS64BR111 www.ti.com SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 Table 6. Multi-Device EEPROM Register Map Overview Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BIt 0 0 CRC EN Address Map EEPROM > 256 Bytes Reserved COUNT[3] COUNT[2] COUNT[1] COUNT[0] 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 2 EE Burst[7] EE Burst[6] EE Burst[5] EE Burst[4] EE Burst[3] EE Burst[2] EE Burst[1] EE Burst[0] Device 0 Info 3 CRC[7] CRC[6] CRC[5] CRC[4] CRC[3] CRC[2] CRC[1] CRC[0] 4 EE AD0 [7] EE AD0 [6] EE AD0 [5] EE AD0 [4] EE AD0 [3] EE AD0 [2] EE AD0 [1] EE AD0 [0] Device 1 Info 5 CRC[7] CRC[6] CRC[5] CRC[4] CRC[3] CRC[2] CRC[1] CRC[0] 6 EE AD1 [7] EE AD1 [6] EE AD1 [5] EE AD1 [4] EE AD1 [3] EE AD1 [2] EE AD1 [1] EE AD1 [0] Device 2 Info 7 CRC[7] CRC[6] CRC[5] CRC[4] CRC[3] CRC[2] CRC[1] CRC[0] 8 EE AD2 [7] EE AD2 [6] EE AD2 [5] EE AD2 [4] EE AD2 [3] EE AD2 [2] EE AD2 [1] EE AD2 [0] Device 3 Info 9 CRC[7] CRC[6] CRC[5] CRC[4] CRC[3] CRC[2] CRC[1] CRC[0] 10 EE AD3 [7] EE AD3 [6] EE AD3 [5] EE AD3 [4] EE AD3 [3] EE AD3 [2] EE AD3 [1] EE AD3 [0] Device 0 Addr 3 11 RES RES RES RES RES RES RES RES Device 0 Addr 4 12 RES RES PDWN Inp PDWN OSC RES eSATA CHA eSATA CHB Ovrd TX_DIS Device 0 Addr 38 46 RES RES RES RES RES RES RES RES Device 0 Addr 39 47 RES RES RES RES RES RES RES RES Device 1 Addr 3 48 RES RES RES RES RES RES PWDN CH B PWDN CH A Device 1 Addr 4 49 RES RES PDWN Inp PDWN OSC RES eSATA CHA eSATA CHB Ovrd TX_DIS Device 1 Addr 38 83 RES RES RES RES RES RES RES RES Device 1 Addr 39 84 RES RES RES RES RES RES RES RES Device 2 Addr 3 85 RES RES RES RES RES RES PWDN CH B PWDN CH A Device 2 Addr 4 86 RES RES PDWN Inp PDWN OSC RES eSATA CHA eSATA CHB Ovrd TX_DIS Device 2 Addr 38 120 RES RES RES RES RES RES RES RES Device 2 Addr 39 121 RES RES RES RES RES RES RES RES Device 3 Addr 3 122 RES RES RES RES RES RES PWDN CH B PWDN CH A Device 3 Addr 4 123 RES RES PDWN Inp PDWN OSC RES eSATA CHA eSATA CHB Ovrd TX_DIS Device 3 Addr 38 157 RES RES RES RES RES RES RES RES Device 3 Addr 39 158 RES RES RES RES RES RES RES RES Header * * * * CRC EN = 1; Address Map = 1 EEPROM > 256 Bytes = 0 COUNT[3:0] = 0011'b Note: Multiple DS64BR111 devices may point at the same address space if they have identical programming values. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 19 DS64BR111 SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 www.ti.com Table 7. Single EEPROM Header + Register Map with Default Value EEPROM Address Byte Bit 7 0 CRC EN Address Map EEPROM > Present 256 Bytes RES COUNT[3] COUNT[2] COUNT[1] COUNT[0] 0 0 0 0 0 0 0 0 RES RES RES RES RES RES RES RES 0 0 0 0 0 0 0 0 Description Max EEPROM Burst size[7] Max EEPROM Burst size[6] Max EEPROM Burst size[5] Max EEPROM Burst size[4] Max EEPROM Burst size[3] Max EEPROM Burst size[2] Max EEPROM Burst size[1] Max EEPROM Burst size[0] Value 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x01[7] 0x01[6] 0x01[5] 0x01[4] 0x01[3] 0x01[2] 0x01 [1] 0x01 [0] 0 0 0 0 0 0 0 0 Ovrd_LOS LOS_Value PDWN Inp PWDN Osc Reserved eSATA Enable A eSATA Enable B Ovrd TX_DIS Register 0x02[5] 0x02[4] 0x02 [3] 0x02 [2] 0x02 [0] 0x04 [7] 0x04 [6] 0x04 [5] Value 0 0 0 0 0 0 0 0 TX_DIS CHA TX_DIS CHB Reserved EQ Stage 4 CHB EQ Stage 4 CHA Reserved Overide IDLE_th Reserved Register 0x04 [4] 0x04 [3] 0x04 [2] 0x04 [1] 0x04 [0] 0x06[4] 0x08 [6] 0x08 [5] Value 0 0 0 0 0 1 0 0 Ovrd_IDLE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register 0x08 [4] 0x08[3] 0x08 [2] 0x08[1] 0x08[0] 0x0B[6] 0x0B[5] 0x0B[4] Value 0 0 0 0 0 1 1 1 Reserved Reserved Reserved Reserved Idle auto A Idle sel A Reserved Reserved Register 0x0B[3] 0x0B[2] 0x0B[1] 0x0B[0] 0x0E [5] 0x0E [4] 0x0E[3] 0x0E[2] Value 0 0 0 0 0 0 0 0 CHA EQ[7] CHA EQ[6] CHA EQ[5] CHA EQ[4] CHA EQ[3] CHA EQ[2] CHA EQ[1] CHA EQ[0] 0x0F [7] 0x0F [6] 0x0F [5] 0x0F [4] 0x0F [3] 0x0F [2] 0x0F [1] 0x0F [0] 0 0 1 0 1 1 1 1 A Sel scp A Out Mode Reserved Reserved Reserved Reserved Reserved Reserved 0x10 [7] 0x10 [6] 0x10 [5] 0x10 [4] 0x10 [3] 0x10[2] 0x10[1] 0x10[0] 1 1 1 0 1 1 0 1 DEMA[1] DEMA[0] CHA Slow IDLE thA[1] IDLE thA[0] IDLE thD[1] IDLE thD[0] 0x11 [2] 0x11 [1] 0x11 [0] 0x12 [7] 0x12 [3] 0x12 [2] 0x12 [1] 0x12 [0] 0 1 0 0 0 0 0 0 Idle sel B Reserved Reserved CHB EQ[7] CHB EQ[6] CHB EQ[5] CHB EQ[4] Description Value Description 1 Value 2 Description 3 Register Value Description Description Description Description Description 4 5 6 7 8 Register Value Description Register Value Description Register Value Description 9 10 DEMA[2] 11 Idle auto B Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register 0x15 [5] 0x15 [4] 0x15[3] 0x15[2] 0x16 [7] 0x16 [6] 0x16 [5] 0x16 [4] Value 0 0 0 0 0 0 1 0 Description CHB EQ[2] CHB EQ[1] CHB EQ[0] B Sel scp B Out Mode Reserved Reserved Register 0x16 [3] 0x16 [2] 0x16 [1] 0x16 [0] 0x17 [7] 0x17 [6] 0x17 [5] 0x17 [4] Value 1 1 1 1 1 1 1 0 Description 12 CHB EQ[3] Reserved Reserved Reserved CHB DEM[2] CHB DEM[1] CHB DEM[0] CHB Slow Register 0x17 [3] 0x17[2] 0x17[1] 0x17[0] 0x18 [2] 0x18 [1] 0x18 [0] 0x19 [7] Value 1 1 0 1 0 1 0 0 Reserved Reserved Reserved Reserved 0 0 0 0 Description 13 Reserved IDLE thA[0] IDLE thD[1] IDLE thD[0] Register 0x19 [3] 0x19 [2] 0x19 [1] 0x19 [0] Value 0 0 0 0 20 14 IDLE thA[1] Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 DS64BR111 www.ti.com SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 Table 7. Single EEPROM Header + Register Map with Default Value (continued) EEPROM Address Byte Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 15 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 1 0 1 1 1 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 1 0 1 1 0 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1 0 0 0 0 0 0 A VOD[2] A VOD[1] A VOD[0] Reserved Reserved Reserved Reserved 0x23 [4] 0x23 [3] 0x23 [2] 0 0 0 0 0 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1 1 1 1 0 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Value Description 0 16 Reserved Register Value Description 1 17 Reserved Register Value Description 0 18 Reserved Register Value Description 0 19 Reserved Register Value Description 0x25 [4] 1 20 Reserved Register 0x25 [3] 0x25 [2] Value 1 1 0 1 0 1 0 0 Reserved Reserved Reserved ovrd fst idle en hi idle th A en hi idle th B en fst idle A 0x28 [6] 0x28 [5] 0x28 [4] 0x28 [3] 0 0 0 0 0 0 1 sd mgain A sd mgain B Reserved Reserved Reserved Reserved Reserved Description 21 Reserved Register Value Description 0 22 en fst idle B Register 0x28 [2] 0x28 [1] 0x28 [0] Value 1 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1 0 1 1 1 1 1 Reserved Reserved Reserved B VOD[2] B VOD[1] B VOD[0] Reserved 0x2D [4] 0x2D 3] 0x2D [2] Description 23 Reserved Register Value Description 0 24 Reserved Register Value Description 0 25 Reserved 1 0 1 1 0 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 1 0 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1 1 1 0 1 0 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 1 0 1 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 Register Value Description 1 26 Reserved Register Value Description 0 27 Reserved Register Value Description 1 28 Reserved Register Value Description 1 29 Reserved Register Value 0 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 21 DS64BR111 SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 www.ti.com Table 7. Single EEPROM Header + Register Map with Default Value (continued) EEPROM Address Byte Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 30 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1 0 1 1 1 1 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1 0 1 1 0 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 1 0 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1 1 1 0 1 0 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 1 0 1 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1 0 1 0 1 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1 0 1 0 1 0 0 Register Value 0 Description 31 Reserved Register Value 0 Description 32 Reserved Register Value 1 Description 33 Reserved Register Value 0 Description 34 Reserved Register Value 1 Description 35 Reserved Register Value 1 Description 36 Reserved Register Value 0 Description 37 Reserved Register Value 0 Description 38 Reserved Register Value 0 Description 39 Reserved Register Value 0 Below is an example of a 2 kbits (256 x 8-bit) EEPROM Register Dump in hex format for a multi-device DS64BR111 application. Table 8. Multi DS100BR111 EEPROM Data EEPROM Address Address (Hex) EEPROM Data Comments 0 00 0x43 1 01 0x00 2 02 0x08 EEPROM Burst Size 3 03 0x00 CRC not used 4 04 0x0B Device 0 Address Location 5 05 0x00 CRC not used 6 06 0x30 Device 1 Address Location 7 07 0x00 CRC not used 8 08 0x30 Device 2 Address Location 9 09 0x00 CRC not used 22 CRC_EN = 0, Address Map = 1, Device Count = 3 (Devices 0, 1, 2, and 3) Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 DS64BR111 www.ti.com SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 Table 8. Multi DS100BR111 EEPROM Data (continued) EEPROM Address Address (Hex) EEPROM Data Comments 10 0A 0x0B Device 3 Address Location 11 0B 0x00 Begin Device 0 and Device 3 - Address Offset 3 12 0C 0x00 13 0D 0x04 14 0E 0x07 15 0F 0x00 16 10 0x2F 17 11 0xED 18 12 0x40 19 13 0x02 Default EQ CHB 20 14 0xFE Default EQ CHB 21 15 0xD4 22 16 0x00 23 17 0x2F 24 18 0xAD 25 19 0x40 26 1A 0x02 27 1B 0xFA 28 1C 0xD4 29 1D 0x01 30 1E 0x80 31 1F 0x5F 32 20 0x56 33 21 0x80 34 22 0x05 35 23 0xF5 36 24 0xA8 37 25 0x00 38 26 0x5F 39 27 0x5A 40 28 0x80 41 29 0x05 42 2A 0xF5 43 2B 0xA8 44 2C 0x00 45 2D 0x00 46 2E 0x54 47 2F 0x54 End Device 0 and Device 3 - Address Offset 39 48 30 0x00 Begin Device 1 and Device 2 - Address Offset 3 49 31 0x00 50 32 0x04 51 33 0x07 52 34 0x00 53 35 0x2F 54 36 0xED 55 37 0x40 56 38 0x02 Default EQ CHA BR111 CHA VOD = 700 mV BR111 CHB VOD = 1000 mV Default EQ CHA Default EQ CHB Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 23 DS64BR111 SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 www.ti.com Table 8. Multi DS100BR111 EEPROM Data (continued) EEPROM Address Address (Hex) EEPROM Data 57 39 0xFE 58 3A 0xD4 59 3B 0x00 60 3C 0x2F 61 3D 0xAD 62 3E 0x40 63 3F 0x02 64 40 0xFA 65 41 0xD4 66 42 0x01 67 43 0x80 68 44 0x5F 69 45 0x56 70 46 0x80 71 47 0x05 72 48 0xF5 73 49 0xA8 74 4A 0x00 75 4B 0x5F 76 4C 0x5A 77 4D 0x80 78 4E 0x05 79 4F 0xF5 80 50 0xA8 81 51 0x00 82 52 0x00 83 53 0x54 84 54 0x54 24 Comments Default EQ CHB BR111 CHA VOD = 700 mV BR111 CHB VOD = 1000 mV End Device 1 and Device 2 - Address Offset 39 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 DS64BR111 www.ti.com SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 Table 9. SMBus Register Map Address 0x00 0x01 0x02 0x04 Register Name Device ID Control 1 Control 2 Control 3 Bits Field Type R/W Default EEPROM Reg Bit 0x00 Description 7 Reserved 6:3 I2C Address [3:0] R [6:3] SMBus strap observation 2 EEPROM reading done R 1: EEPROM Loading 0: EEPROM Done Loading 1 Reserved RWS C set bit to 0 0 Reserved RWS C set bit to 0 7:6 Idle Control R/W 5:3 Reserved R/W Set bits to 0 2 LOS Select R/W LOS Monitor Selection 1: Use LOS from CH B 0: Use LOS from CH A 1:0 Reserved R/W 7 Reserved R/W 6 Reserved 5 LOS override Yes LOS pin override enable (1); Use Normal Signal Detection (0) 4 LOS override value Yes 1: Normal Operation 0: Output LOS 3 PWDN Inputs Yes 2 PWDN Oscillator Yes 1: PWDN 0: Normal Operation 1 Reserved 0 Reserved 7:6 eSATA Mode Enable 5 TX_DIS Override Enable 1: Override Use Reg 0x04[4:3] 0: Normal Operation - uses pin 4 TX_DIS Value Channel A 1: TX Disabled 0: TX Enabled 3 TX_DIS Value Channel B 2 Reserved Set bit to 0 1:0 EQ CONTROL [1]: Channel B - EQ Stage 4 ON/OFF [0]: Channel A - EQ Stage 4 ON/OFF 0x00 set bit to 0 Yes Control [7]: Continuous talk ENABLE (Channel A) [6]: Continuous talk ENABLE (Channel B) [2]: LOS SEL Channel B Set bits to 00'b 0x00 Set bit to 0 Set bit to 0 R/W 0x00 Yes Set bit to 0 Yes [7] Channel A (1) [6] Channel B (1) 0x05 CRC 1 7:0 CRC[7:0] R/W 0x00 Slave Mode CRC Bits 0x06 CRC 2 7 Disable EEPROM CFG R/W 0x10 Disable Master Mode EEPROM Configuration 6:5 Reserved 4 Reserved 3 CRC Slave Mode Disable [1]: CRC Disable (No CRC Check) [0]: CRC Check ENABLE Note: With CRC check DISABLED register updates take immediate effect on high speed data path. With CRC check ENABLED register updates will NOT take effect until correct CRC value is loaded 2:1 Reserved Set bits to 0 0 CRC Enable Slave CRC Trigger Set bits to 0 Yes Set bit to 1 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 25 DS64BR111 SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 www.ti.com Table 9. SMBus Register Map (continued) Address 0x07 0x08 0x0C Register Name Digital Reset and Control Pin Override CH A Analog Override 1 Bits Field Type R/W Default EEPROM Reg Bit 7 Reserved 6 Reset Regs Self clearing reset for registers Writing a [1] will return register settings to default values. 5 Reset SMBus Master Self clearing reset for SMBus master state machine 4:0 Reserved Set bits to '0001b 7 Reserved 6 Override Idle Threshold Yes [1]: Override by Channel - see Reg 0x13 and 0x19 [0]: SD_TH pin control 5 Reserved Yes Set bit to 0 4 Override IDLE Yes [1]: Force IDLE by Channel - see Reg 0x0E and 0x15 [0]: Normal Operation 3 Reserved Yes Set bit to 0 2 Override Out Mode 1 Override DEM 0 Reserved 7 Reserved 6 Reserved Set bit to 0 5 Reserved Set bit to 0 4 Reserved Set bit to 0 3:0 Reserved R/W 0x01 Description Set bit to 0 0x00 Set bit to 0 [1]: Enable Output Mode control for individual outputs. See register locations 0x10[6] and 0x17[6]. [0]: Disable - Outputs are kept in the normal mode of operation allowing VOD and DE adjustments. Yes Yes R/W 0x00 Set bit to 0 Set bit to 0 Set bits to 0000'b.. 0x0D CH A Reserved 7:0 Reserved R/W 0x00 Set bits to 00'h. 0x0E CH A Idle Control 7:6 Reserved R/W 0x00 5 Idle Auto Yes Auto IDLE value when override bit is set (reg 0x08 [4] = 1) 4 Idle Select Yes Force IDLE value when override bit is set (reg 0x08 [4] = 1) 3 Reserved Yes Set bit to 0. Set bits to 00'b. 2:0 Reserved 0x0F CH A EQ Setting 7:0 BOOST [7:0] R/W 0x2F Yes EQ Boost Default to 24 dB See EQ Table for Information 0x10 CH A Control 1 7 Sel_scp R/W 0xED Yes 1 = Short Circuit Protection ON 0 = Short Circuit Protection OFF 6 Reserved Yes Set bit to 1 5:3 Reserved Yes Set bits to = 101'b 2:0 Reserved Yes Set bits to = 101'b 26 Set bits to 0. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 DS64BR111 www.ti.com SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 Table 9. SMBus Register Map (continued) Address 0x11 0x12 0x13 Register Name CH A Control 2 CH A Idle Threshold CH B Analog Override 1 Bits Field Type Default EEPROM Reg Bit 0x82 Description 7:5 Reserved R 4 Reserved R/W Set bits to = 100'b 3 Reserved 2:0 DEM [2:0] 7 Slow OOB 6:4 Reserved 3:2 idle_thA[1:0] Yes Assert Thresholds Use only if register 0x08 [6] = 1 00 = 180 mV (Default) 01 = 160 mV 10 = 210 mV 11= 190 mV 1:0 idle_thD[1:0] Yes De-assert Thresholds Use only if register 0x08 [6] = 1 00 = 110 mV (Default) 01 = 100 mV 10 = 150 mV 11= 130 mV 7 Reserved 6 Reserved Set bit to 0 5 Reserved Set bit to 0 4 Reserved Set bit to 0 3:0 Reserved Set bit to 0 Set bit to 0 R/W 0x00 Yes De-Emphasis (Default = -3.5 dB) 000'b = -0.0 dB 001'b = -1.5 dB 010'b = -3.5 dB 011'b = -6.0 dB 100'b = -8.0 dB 101'b = -9.0 dB 110'b = -10.5 dB 111'b = -12.0 dB Yes Slow OOB Enable (1); Disable (0) Set bits to 000'b. R/W 0x00 Set bit to 0 Set bits to 0000'b. 0x14 CH B Reserved 7:0 Reserved R/W 0x00 0x15 CH B Idle Control 7:6 Reserved R/W 0x00 5 Idle Auto Yes Auto IDLE value when override bit is set (reg 0x08 [4] = 1) 4 Idle Select Yes Force IDLE value when override bit is set (reg 0x08 [4] = 1) 3:2 Reserved Yes Set bits to 00'b. 1:0 Reserved 7:0 BOOST [7:0] 0x16 CH B EQ Setting Set bits to 00'h. Set bits to 00'b Set bits to 00'b. R/W 0x2F Yes EQ Boost Default to 24 dB See EQ Table for Information Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 27 DS64BR111 SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 www.ti.com Table 9. SMBus Register Map (continued) Address 0x17 0x18 0x19 0x23 0x25 0x28 28 Register Name CH B Control 1 CH B Control 2 CH B Idle Threshold BR111 CH A VOD Reserved Idle Control Bits Field 7 Sel_scp 6 Type R/W Default 0xED EEPROM Reg Bit Description Yes 1 = Short Circuit Protection ON 0 = Short Circuit Protection OFF Reserved Yes Set bit to 1 5:3 Reserved Yes Set bits to = 101'b 2:0 Reserved 7:5 Reserved R 4 Reserved R/W 3 Reserved 2:0 DEM [2:0] 7 Slow OOB 6:4 Reserved 3:2 idle_thA[1:0] Yes Assert Thresholds Use only if register 0x08 [6] = 1 00 = 180 mV (Default) 01 = 160 mV 10 = 210 mV 11= 190 mV 1:0 idle_thD[1:0] Yes De-assert Thresholds Use only if register 0x08 [6] = 1 00 = 110 mV (Default) 01 = 100 mV 10 = 150 mV 11= 130 mV 7:6 Reserved 4:2 VOD_CH0[2:0] 1:0 Reserved 7:5 Reserved 4:2 Reserved 1:0 Reserved 7 Reserved 6 Override Fast Idle Yes 5:4 en_high_idle_th[1:0] Yes Enable high SD thresholds [5]: CH A [4]: CH B 3:2 en_fast_idle[1:0] Yes Enable Fast IDLE [3]: CH A [2]: CH B 1:0 Reserved Yes Set bits to 00'b. Set bits to = 101'b 0x82 Set bits to = 100'b Set bit to 0 Set bit to 0 R/W 0x00 Yes De-Emphasis (Default = -3.5 dB) 000'b = -0.0 dB 001'b = -1.5 dB 010'b = -3.5 dB 011'b = -6.0 dB 100'b = -8.0 dB 101'b = -9.0 dB 110'b = -10.5 dB 111'b = -12.0 dB Yes Slow OOB Enable (1); Disable (0) Set bits to 000'b. R/W 0x00 Set bits to 00'b. Yes DS64BR111 VOD Controls for CH A (Default = 000'b) 000'b = 700 mV 001'b = 800 mV 010'b = 900 mV 011'b = 1000 mV 100'b = 1100 mV 101'b = 1200 mV 110'b = 1300 mV Set bits to 00'b. R/W 0xAD Set bits to 101'b. Yes Set bits to 011'b. Set bits to 01'b. R/W 0x00 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 DS64BR111 www.ti.com SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 Table 9. SMBus Register Map (continued) Address 0x2D 0x51 Register Name CH B VOD Control Device Information Bits Field 7:5 Reserved 4:2 VOD_CH0[2:0] 1:0 Reserved 7:5 Version[2:0] 4:0 Device ID[4:0] Type R/W Default EEPROM Reg Bit 0xAD Description Set bits to 101'b. Yes VOD Controls for CH B (Default = 011'b) 000'b = 700 mV 001'b = 800 mV 010'b = 900 mV 011'b = 1000 mV 100'b = 1100 mV 101'b = 1200 mV 110'b = 1300 mV Set bits to '01b R 0x47 Read bits = 010'b BR111 = '0 0111b Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 29 DS64BR111 SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 www.ti.com TYPICAL DC PERFORMANCE CHARACTERISTICS The following data was collected at 25C 100 SUPPLY CURRENT (mA) 90 80 3.3V Mode 70 60 50 40 2.5V Mode 30 20 10 0 700 800 900 1000 1100 1200 1300 OUTPUT VOLTAGE (mV) Figure 8. Supply Current vs. Output Voltage Setting SUPPLY CURRENT (mA) 60 VOD = 700 mV Temp = 25C 56 52 2.5V Mode 48 44 40 2.0 2.2 2.4 2.6 2.8 SUPPLY VOLTAGE (V) 3.0 Figure 9. Supply Current vs. Supply Voltage 1500 OUTPUT VOLTAGE (mV) 1400 1300 1200 1100 1000 900 800 700 600 500 0 1 2 3 4 5 VOD SETTING 6 7 Figure 10. Output Voltage vs. Output Voltage Setting 30 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 DS64BR111 www.ti.com SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 TYPICAL AC PERFORMANCE CHARACTERISTICS NO MEDIA: Device DS100BR111 @ 10.3125 Gbps Random Jitter (Rj) Deterministic Jitter (Dj) 340 fs 9.5 ps Dj Component Breakdown Total Jitter (Tj @ 1E12) DDJ = 7.4 ps 12.3 ps DCD = 1.0 ps DDPWS = 6.3 ps PJ = 0.81 ps Figure 11. No Media; D3186 driving device directly The following lab setups were used to collect typical performance data on FR4 and Cable media. Signal Generator D3186 Oscilloscope FR4 100 Ohm Differential Stripline BR111 EVK DSA8200 20 GHz Bandwidth Figure 12. Equalization Test Setup for FR4 EQUALIZATION RESULTS: Figure 13. Equalization Performance with 30" of 4 mil FR4 using EQ settting 0x16 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 31 DS64BR111 SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 www.ti.com EQUALIZATION RESULTS: Oscilloscope D3186 Cable Cable Adapter Cable Adapter Signal Generator BR111 EVK DSA8200 20 GHz Bandwidth Figure 14. Equalization Test Setup for Cables CABLE TRANSMIT and RECEIVE RESULTS: Figure 15. 8M 30AWG Cable Performance with 700mV Launch VOD and Rx EQ setting 0x0F Oscilloscope Signal Generator BR111 EVK D3186 FR4 100 Ohm Differential Impedance DSA8200 20 GHz Bandwidth Figure 16. De-Emphasis Test Setup DE-EMPHASIS RESULTS: Figure 17. De-Emphasis Performance with 10" of 4 mil FR4 using DE settting 0x02 32 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 DS64BR111 www.ti.com SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 DE-EMPHASIS RESULTS: Figure 18. 10" of 4 mil FR4 Without De-Emphasis Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 33 DS64BR111 SNLS343C - SEPTEMBER 2011 - REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C * 34 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 32 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS64BR111 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) DS64BR111SQ/NOPB ACTIVE WQFN RTW 24 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 85 64BR111 DS64BR111SQE/NOPB ACTIVE WQFN RTW 24 250 RoHS & Green SN Level-3-260C-168 HR -40 to 85 64BR111 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Sep-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS64BR111SQ/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 DS64BR111SQE/NOPB WQFN RTW 24 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Sep-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS64BR111SQ/NOPB WQFN RTW 24 1000 210.0 185.0 35.0 DS64BR111SQE/NOPB WQFN RTW 24 250 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE RTW0024A WQFN - 0.8 mm max height SCALE 3.000 PLASTIC QUAD FLATPACK - NO LEAD 4.1 3.9 A B PIN 1 INDEX AREA 4.1 3.9 C 0.8 MAX SEATING PLANE 0.05 0.00 0.08 C 2X 2.5 7 20X 0.5 6 13 2X 2.5 25 2.6 0.1 1 PIN 1 ID (OPTIONAL) (0.1) TYP EXPOSED THERMAL PAD 12 18 24 19 0.5 24X 0.3 24X 0.3 0.2 0.1 0.05 C A B C 4222815/A 03/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT RTW0024A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 2.6) SYMM 24 19 24X (0.6) 1 18 24X (0.25) (1.05) 25 SYMM (3.8) 20X (0.5) (R0.05) TYP 13 6 ( 0.2) TYP VIA 7 12 (1.05) (3.8) LAND PATTERN EXAMPLE SCALE:15X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4222815/A 03/2016 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com EXAMPLE STENCIL DESIGN RTW0024A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4X ( 1.15) (0.675) TYP (R0.05) TYP 24 19 24X (0.6) 1 18 24X (0.25) (0.675) TYP 25 20X (0.5) SYMM (3.8) 13 6 METAL TYP 7 SYMM 12 (3.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 25: 78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4222815/A 03/2016 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. 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