1
FEATURES
DESCRIPTION
3
2
4
5
(TOP VIEW)
1
VCC
GND
Z
D
Y
SN65LVDS1
DBV Package
3
2
4
5
(TOP VIEW)
1
VCC
GND
A
R
B
SN65LVDS2 and SN65LVDT2
DBV Package
VCC
D
NC
GND
Z
Y
NC
NC
SN65LVDS1
D Package
(TOP VIEW)
1
2
3
4
8
7
6
5
B
A
NC
NC
VCC
R
NC
GND
SN65LVDS2 and SN65LVDT2
D Package
(TOP VIEW)
1
2
3
4
8
7
6
5
PART NUMBER INTEGRATED
TERMINATION PACKAGE
SOT23-5
PACKAGE
MARKING
SN65LVDS1DBV
SN65LVDS1D
SN65LVDS2DBV
SN65LVDS2D
SN65LVDT2DBV
SN65LVDT2D
√
√
SOIC-8
SAAI
LVDS1
SABI
LVDS2
SACI
LVDT2
AVAILABLE OPTIONS
SOT23-5
SOT23-5
SOIC-8
SOIC-8
110-Ω Resistor for LVDT Only
110-Ω Resistor for LVDT Only
SN65LVDS1
SN65LVDS2
SN65LVDT2
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.................................................................................................................................................... SLLS373K – JULY 1999 – REVISED NOVEMBER 2008
HIGH-SPEED DIFFERENTIAL LINE DRIVER/RECEIVERS
•Meets or Exceeds the ANSI TIA/EIA-644AStandard
•Designed for Signaling RatesThe signaling rate of a line is the number of voltage transitions thatare made per second expressed in the units bps (bits per second)up to:– 630 Mbps Drivers– 400 Mbps Receivers•Operates From a 2.4-V to 3.6-V Supply•Available in SOT-23 and SOIC Packages•Bus-Terminal ESD Exceeds 9 kV•Low-Voltage Differential Signaling With TypicalOutput Voltages of 350 mV Into a 100- ΩLoad•Propagation Delay Times– 1.7 ns Typical Driver– 2.5 ns Typical Receiver•Power Dissipation at 200 MHz– 25 mW Typical Driver– 60 mW Typical Receiver•LVDT Receiver Includes Line Termination•Low Voltage TTL (LVTTL) Level Driver Input Is5-V Tolerant
•Driver Is Output High Impedance WithV
CC
< 1.5 V•Receiver Output and Inputs Are HighImpedance With V
CC
< 1.5 V•Receiver Open-Circuit Fail Safe•Differential Input Voltage Threshold Less Than100 mV
The SN65LVDS1, SN65LVDS2, and SN65LVDT2 aresingle, low-voltage, differential line drivers andreceivers in the small-outline transistor package. Theoutputs comply with the TIA/EIA-644A standard andprovide a minimum differential output voltagemagnitude of 247 mV into a 100- Ωload at signalingrates up to 630 Mbps for drivers and 400 Mbps forreceivers.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
DESCRIPTION CONTINUED
INPUT OUTPUTS
D
H
L
Open
Y Z
H
L
L
L
H
H
DRIVER
INPUTS OUTPUT
R
H
?
L
VID = VA − VB
VID ≥ 100 mV
−100 mV < VID < 100 mV
VID ≤ −100 mV
Open H
H = high level, L = low level , ? = indeterminate
RECEIVER
FUNCTION TABLES
DRIVER EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
300 kΩ
50 Ω
VCC
7 V
D Input 5 Ω
10 kΩ
7 V
Y or Z
Output
VCC
SN65LVDS1
SN65LVDS2
SN65LVDT2
SLLS373K – JULY 1999 – REVISED NOVEMBER 2008 ....................................................................................................................................................
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
When the SN65LVDS1 is used with an LVDS receiver (such as the SN65LVDT2) in a point-to-point connection,data or clocking signals can be transmitted over printed-circuit-board traces or cables at very high rates with verylow electromagnetic emissions and power consumption. The packaging, low power, low EMI, high ESDtolerance, and wide supply voltage range make the device ideal for battery-powered applications.
The SN65LVDS1, SN65LVDS2, and SN65LVDT2 are characterized for operation from – 40 ° C to 85 ° C.
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Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2
RECEIVER EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
7 V
VCC
7 V
R Output
VCC
5 Ω
A Input
300 kΩ300 kΩ
7 V
B Input
110-Ω LVDT Only
ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
SN65LVDS1
SN65LVDS2
SN65LVDT2
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.................................................................................................................................................... SLLS373K – JULY 1999 – REVISED NOVEMBER 2008
over operating free-air temperature range (unless otherwise noted)
(1)
PARAMETER RATINGS
Supply voltage range, V
CC
(2)
– 0.5 V to 4 V(A or B) – 0.5 V to 4 VInput voltage range, V
I
(D) – 0.5 V to V
CC
+ 2 VOutput voltage, V
O
(Y or Z) – 0.5 V to 4 VDifferential input voltage
SN65LVDT2 only 1 Vmagnitude, |V
ID
|Receiver output current, I
O
-12 mA to 12 mAHuman-body model electrostatic discharge, HBM ESD
(3)
All pins 4000 VBus pins (A, B, Y, Z) 9000 VMachine-model electrostatic discharge, MM ESD
(4)
400 VField-induced-charge device model electrostatic discharge, FCDM ESD
(5)
1500 VContinuous total power dissipation, P
D
See Dissipation Rating TableStorage Temperature Range (non operating) – 65 ° C to 150 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential I/O bus voltages are with respect to network ground terminal.(3) Test method based upon JEDEC Standard 22, Test Method A114-A. Bus pins stressed with respect to GND and V
CC
separately.(4) Test method based upon JEDEC Standard 22, Test Method A114-A.(5) Test method based upon EIA-JEDEC JESD22-C101C.
T
A
≤25 ° C DERATING FACTOR T
A
= 85 ° CPACKAGE
POWER RATING ABOVE T
A
= 25 ° C
(1)
POWER RATING
D 725 mW 5.8 mW/ ° C 402 mWDBV 385 mW 3.1 mW/ ° C 200 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-K) and withno air flow.
Copyright © 1999 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2
RECOMMENDED OPERATING CONDITIONS
SN65LVDS1
SN65LVDS2
SN65LVDT2
SLLS373K – JULY 1999 – REVISED NOVEMBER 2008 ....................................................................................................................................................
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PARAMETER MIN NOM MAX UNIT
V
CC
Supply voltage 2.4 3.3 3.6 VV
IH
High-level input voltage 2 5 VV
IL
Low-level input voltage 0 0.8 VT
A
Operating free-air temperature – 40 85 ° C|V
ID
| Magnitude of differential input voltage 0.1 0.6 VInput voltage (any combination of input or common-mode voltage) 0 V
CC
– 0.8 V
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Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2
DRIVER ELECTRICAL CHARACTERISTICS
DRIVER SWITCHING CHARACTERISTICS
SN65LVDS1
SN65LVDS2
SN65LVDT2
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.................................................................................................................................................... SLLS373K – JULY 1999 – REVISED NOVEMBER 2008
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN
(1)
TYP
(2)
MAX UNIT
R
L
= 100 Ω, 2.4 ≤V
CC
< 3 V 200 350 454|V
OD
| Differential output voltage magnitude
R
L
= 100 Ω, 3 ≤V
CC
< 3.6 V 247 350 454
mVChange in differential output voltage magnitudeΔ|V
OD
| See Figure 2 – 50 50between logic statesV
OC(SS)
Steady-state common-mode output voltage 1.125 1.375 VChange in steady-state common-mode output voltageΔV
OC(SS)
See Figure 2 – 50 50 mVbetween logic statesV
OC(PP)
Peak-to-peak common-mode output voltage 25 100 mVV
I
= 0 V or V
CC
, No load 2 4I
CC
Supply current mAV
I
= 0 V or V
CC
, R
L
= 100 Ω5.5 8I
IH
High-level input current V
IH
= 5 V 2 20 µAI
IL
Low-level input current V
IL
= 0.8 V 2 10 µAV
OY
or V
OZ
= 0 V 3 10I
OS
Short-circuit output current mAV
OD
= 0 V 10I
O(OFF)
Power-off output current V
CC
= 1.5 V, V
O
= 3.6 V – 1 1 µAC
i
Input capacitance V
I
= 0.4 Sin (4E6 πt)+0.5 V 3 pF
(1) The algebraic convention, in which the least positive (most negative) limit is designated as a minimum, is used in this data sheet.(2) All typical values are at 25 ° C and with a 3.3-V supply.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 1.5 3.1 nst
PHL
Propagation delay time, high-to-low-level output 1.8 3.1 nsR
L
= 100 Ω, C
L
= 10 pF,t
r
Differential output signal rise time 0.6 1 nsSee Figure 5t
f
Differential output signal fall time 0.7 1 nst
sk(p)
Pulse skew (|t
PHL
- t
PLH
|)
(2)
0.3 ns
(1) All typical values are at 25 ° C and with a 3.3-V supply.(2) t
sk(p)
is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
Copyright © 1999 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2
RECEIVER ELECTRICAL CHARACTERISTICS
RECEIVER SWITCHING CHARACTERISTICS
SN65LVDS1
SN65LVDS2
SN65LVDT2
SLLS373K – JULY 1999 – REVISED NOVEMBER 2008 ....................................................................................................................................................
www.ti.com
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN
(1)
TYP
(2)
MAX UNIT
V
ITH+
Positive-going differential input voltage threshold 100See Figure 3 mVV
ITH –
Negative-going differential input voltage threshold – 100I
OH
= – 8 mA, V
CC
= 2.4 V 1.9V
OH
High-level output voltage VI
OH
= – 8 mA, V
CC
= 3 V 2.4V
OL
Low-level output voltage I
OL
= 8 mA 0.25 0.4 VI
CC
Supply current No load, Steady state 4 7 mAV
I
= 0 V, other input = 1.2 V – 20 – 2LVDS2
V
I
= 2.2 V, other input = 1.2 V,
– 3 – 1.2V
CC
= 3.0 VI
I
Input current (A or B inputs) µAV
I
= 0 V, other input open – 40 -4LVDT2
V
I
= 2.2 V, other input open, V
CC
= 3.0 V – 6 – 2.4I
ID
Differential input current (I
IA
– I
IB
) LVDS2 V
IA
= 2.4 V V
IB
= 2.3 V – 2 2 µALVDS2 V
CC
= 0 V, V
IA
= V
IB
= 2.4 V 20I
I(OFF)
Power-off input current (A or B inputs) µALVDT2 V
CC
= 0 V, V
IA
= V
IB
= 2.4 V 40R
T
Differential input resistance LVDT2 V
IA
= 2.4 V V
IB
= 2.2 V 90 111 132 Ω
C
I
Input Capacitance V
I
= 0.4sin(4E6 πt) + 0.5V 5.8 pFC
O
Output Capacitance V
I
= 0.4sin(4E6 πt) + 0.5V 3.4 pF
(1) The algebraic convention, in which the least positive (most negative) limit is designated as a minimum, is used in this data sheet.(2) All typical values are at 25 ° C and with a 2.7-V supply.
over recommended operating conditions (unless otherwise noted)
TYP
(PARAMETER TEST CONDITIONS MIN MAX UNIT1)
Propagation delay time, low-to-high-levelt
PLH
1.4 2.6 3.6 nsoutput
Propagation delay time, high-to-low-levelt
PHL
1.4 2.5 3.6 nsC
L
= 10 pF, See Figure 6outputt
sk(p)
Pulse skew (|t
pHL
– t
pLH
|)
(2)
0.1 0.6 nst
r
Output signal rise time 0.8 1.4 nst
f
Output signal fall time 0.8 1.4 nsV
CC
= 3.0 V - 3.6 V 2.2 3 5.5 V/nst
r(slew)
Output slew rate (rising)
V
CC
= 2.4 V - 2.7 V 1.5 1.9 2.9 V/nsC
L
= 10 pF
V
CC
= 3.0 V - 3.6 V 2.7 3.8 6 V/nst
f(slew)
Output slew rate (falling)
V
CC
= 2.4 V - 2.7 V 2.1 2.3 3.9 V/ns
(1) All typical values are at 25 ° C and with a 2.7-V supply.(2) t
sk(p)
is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
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Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2
PARAMETER MEASUREMENT INFORMATION
VOD
VOZ
VOY
VOC
VI
IOY
IOZ
IID
Z
Y
VOY )VOZ
2
VOC
Z
Y
Input
50 pF
1.4 V
1 V
VOC(PP) VOC(SS)
VOC
49.9 Ω, ±1% (2 Places)
VI
VI
VIB
VID
VIA
VIC VO
A
B
R
VIA )VIB
2
IIA
IIB
IO
SN65LVDS1
SN65LVDS2
SN65LVDT2
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.................................................................................................................................................... SLLS373K – JULY 1999 – REVISED NOVEMBER 2008
Figure 1. Driver Voltage and Current Definitions
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T. The measurement of V
OC(PP)
is made on test equipment with a – 3 dB bandwidth of at least 300 MHz.
Figure 2. Driver Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Figure 3. Receiver Voltage and Current Definitions
Copyright © 1999 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2
VID
VO
10 pF,
2 Places 15 pF
100 Ω†
1000 Ω
1000 Ω
100 Ω
VIC
VID
VO
VID
VO
VIT+
0 V
−100 mV
100 mV
0 V
VIT−
†Remove for testing LVDT device.
NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of < 1 ns.
NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns.
+
−
SN65LVDS1
SN65LVDS2
SN65LVDT2
SLLS373K – JULY 1999 – REVISED NOVEMBER 2008 ....................................................................................................................................................
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PARAMETER MEASUREMENT INFORMATION (continued)
Figure 4. V
IT+
and V
IT-
Input Voltage Threshold Test Circuit and Definitions
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Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2
2 V
1.4 V or 1.2 V (see Note B)
0.8 V
100%
80%
20%
0%
0 V
VOD(H)
VOD(L)
Output
Input
VOD
Z
Y
Input 100 Ω
±1%
CL = 10 pF
(2 Places)
tPHL
tPLH
tftr
SN65LVDS1
SN65LVDS2
SN65LVDT2
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.................................................................................................................................................... SLLS373K – JULY 1999 – REVISED NOVEMBER 2008
PARAMETER MEASUREMENT INFORMATION (continued)
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T.B. This point is 1.4 V with V
CC
= 3.3 V or 1.2 V with V
CC
= 2.7 V.
Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
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Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2
VOH
VOL
0.45 VCC
VO
VIA
VIB
VID
1.4 V
1 V
0.4 V
0 V
−0.4 V
tPHL tPLH
tr
tf
20%
80%
VIB
VID
VIA VO
CL
10 pF
SN65LVDS1
SN65LVDS2
SN65LVDT2
SLLS373K – JULY 1999 – REVISED NOVEMBER 2008 ....................................................................................................................................................
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PARAMETER MEASUREMENT INFORMATION (continued)
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. C
L
includes instrumentation and fixture capacitance within 0,06 m of theD.U.T.
Figure 6. Receiver Timing Test Circuit and Waveforms
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Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2
TYPICAL CHARACTERISTICS
1.8
1.4
1
2.2
2
1.6
1.2
−20 0 40−40 20
tPHL − Driver High-to-Low Propagation
60 80 100
2.4
VCC = 3 V
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.3 V
VCC = 3.6 V
2.6
Delay Times − ns
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
1.4
1.2
1
1.6
1.5
1.3
1.1
−20 0 40−40 20 60 80 100
1.7
1.8
1.9
VCC = 3.3 V
VCC = 3 V
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.6 V
tPLH − Driver High-to-Low Propagation
Delay Times − ns
IOH − High-Level Output Current − mA
− Receiver High-Level Output Voltage − V
3
2.5
2
1.5
1
0.5
−40−50 −30−60
VOH
−20 0
−70
4
3.5
0−10
VCC = 2.7 V
VCC = 3.3 V
3
2.5
2
1.5
1
0.5
3020 4010 50 70
0
4
3.5
0
IOL − Low-Level Output Current − mA
− Receiver Low-Level Output Voltage − V
OL
V
60
VCC = 2.7 V
VCC = 3.3 V
SN65LVDS1
SN65LVDS2
SN65LVDT2
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.................................................................................................................................................... SLLS373K – JULY 1999 – REVISED NOVEMBER 2008
DRIVER HIGH-TO-LOW LEVEL DRIVER LOW-TO-HIGH LEVELPROPAGATION DELAY TIMES PROPAGATION DELAY TIMESvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 7. Figure 8.
RECEIVER HIGH-LEVEL OUTPUT VOLTAGE RECEIVER LOW-LEVEL OUTPUT VOLTAGEvs vsHIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
Figure 9. Figure 10.
Copyright © 1999 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2
TA − Free-Air Temperature − °C
2.6
2.4
2.2
2.8
2.7
2.5
2.3
−20 0 40−40 20 60 80 100
2.9 VCC = 2.4 V
VCC = 2.7 V
VCC = 3.6 V
3
VCC = 3.3 V
VCC = 3 V
tPLH − Receiver Low-to-High Level Propagation
Delay time s − ns
TA − Free-Air Temperature − °C
2.6
2.5
2.4
2.7
2.65
2.55
2.45
−20 0 40−40 20
tPHL − Receiver High-to-Low level Propagation
60 80
2.75
VCC = 3 V
VCC = 2.4 V
2.8
VCC = 3.6 V
VCC = 2.7 V
2.85
2.9
VCC = 3.3 V
Delay Times − ns
CL − Capacitive Load − pF
1000
105 15 20 25
0
1400
1200
0
Rise Time
VCC = 2.5 V
tr, tf − Rise/Fall T ime − ps
Fall Time
800
600
400
200
CL − Capacitive Load − pF
1000
105 15 20 25
0
1200
0
Rise Time
VCC = 3.3 V
tr, tf − Rise/Fall T ime − ps
Fall Time
800
600
400
200
SN65LVDS1
SN65LVDS2
SN65LVDT2
SLLS373K – JULY 1999 – REVISED NOVEMBER 2008 ....................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)
RECEIVER HIGH-TO-LOW LEVEL RECEIVER LOW-TO-HIGH LEVELPROPAGATION DELAY TIMES PROPAGATION DELAY TIMESvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 11. Figure 12.
RISE/FALL TIME RISE/FALL TIMEvs vsCAPACITIVE LOAD CAPACITIVE LOAD
Figure 13. Figure 14.
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Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2
APPLICATION INFORMATION
FAIL-SAFE
Rt = 100 Ω (Typ)
300 kΩ300 kΩ
VCC
VIT ≈ 2.3 V
A
BY
SN65LVDS1
SN65LVDS2
SN65LVDT2
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.................................................................................................................................................... SLLS373K – JULY 1999 – REVISED NOVEMBER 2008
One of the most common problems with differential signaling applications is how the system responds when nodifferential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in thatits output logic state can be indeterminate when the differential input voltage is between – 100 mV and 100 mVand within its recommended input common-mode voltage range. However, TI's LVDS receiver is different in howit handles the open-input circuit situation.
Open circuit means that there is little or no input current to the receiver from the data line itself. This could bewhen the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiverpulls each line of the signal pair to near V
CC
through 300-k Ωresistors as shown in Figure 15 . The fail-safefeature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force theoutput to a high level regardless of the differential input voltage.
Figure 15. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver is valid with less than a 100 mV differential inputvoltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as itis connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeatthe pullup currents from the receiver and the fail-safe feature.
Copyright © 1999 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2
100 Ω100 Ω
Parallel Terminated
100 Ω
Point to Point
100 Ω
Multidrop
SN65LVDS1
SN65LVDS2
SN65LVDT2
SLLS373K – JULY 1999 – REVISED NOVEMBER 2008 ....................................................................................................................................................
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Figure 16. Typical Application Circuits
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Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2
PACKAGE OPTION ADDENDUM
www.ti.com 19-Oct-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN65LVDS1D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDS1DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDS1DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDS1DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDS1DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDS1DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDS1DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDS1DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDS2D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDS2DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDS2DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDS2DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDS2DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDS2DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDS2DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDS2DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDT2D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
PACKAGE OPTION ADDENDUM
www.ti.com 19-Oct-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN65LVDT2DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDT2DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDT2DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDT2DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDT2DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDT2DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
SN65LVDT2DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 19-Oct-2011
Addendum-Page 3
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LVDS1DBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
SN65LVDS1DBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
SN65LVDS1DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65LVDS2DBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
SN65LVDS2DBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
SN65LVDS2DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65LVDT2DBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
SN65LVDT2DBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
SN65LVDT2DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Feb-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LVDS1DBVR SOT-23 DBV 5 3000 182.0 182.0 20.0
SN65LVDS1DBVT SOT-23 DBV 5 250 182.0 182.0 20.0
SN65LVDS1DR SOIC D 8 2500 340.5 338.1 20.6
SN65LVDS2DBVR SOT-23 DBV 5 3000 182.0 182.0 20.0
SN65LVDS2DBVT SOT-23 DBV 5 250 182.0 182.0 20.0
SN65LVDS2DR SOIC D 8 2500 340.5 338.1 20.6
SN65LVDT2DBVR SOT-23 DBV 5 3000 182.0 182.0 20.0
SN65LVDT2DBVT SOT-23 DBV 5 250 182.0 182.0 20.0
SN65LVDT2DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Feb-2009
Pack Materials-Page 2
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