1
DS3106
Line Card Timing IC
General D es cription
The DS3106 is a low-cost timing IC for telecom line
cards. T he device accepts two reference clocks from
dual redundant system timing cards, continually
monitor s both inputs, and p erforms manual refer ence
switching if the primary reference fails. The highly
programm able DS 3106 s uppor ts num erous input and
output frequencies including frequencies required for
SONET/SDH, Synchronous Ethernet (1G, 10G, and
100Mbps), wireless base stations, and CMTS
systems. PLL bandwidths from 18Hz to 400Hz are
supported, and a wide variety of PLL characteristics
and device features can be configured to meet the
needs of many different applications.
The DS3106 re gister s et is back ward c om patible with
Semtech’s ACS8526 line card timing IC. The DS3106
pinout is sim ilar but not ide ntic a l to the ACS85 26.
Applications
SONET/SDH, Synchronous Ethernet, PDH, and
Other Line Cards in WAN Equipment Including
MSPPs, Ethernet Switches, Routers, DSLAMs,
and Wireless Base Stations
Simplified Functional Diagram
Features
♦ Advanced DPLL Technology
♦ Programmable PLL Bandwidth: 18Hz to 400Hz
♦ Manual Reference Switching
♦ Holdover on Loss of All Input References
♦ Frequency Conversion Among SONET/SDH,
PDH, Ethernet, Wireless, and CMTS Rates
♦ Two Input Clocks
♦ CMOS/TTL Signal Format (≤ 125MHz)
♦ Numerous Input Clock Frequencies Supported
Ethernet xMII: 2.5, 25, 125, 156.25MHz
SONET/SDH: 6.48, N x 19.44, N x 51.84MHz
PDH: N x DS1, N x E1, N x DS2, DS 3, E3
Frame Sync: 2kHz, 4kHz, 8kHz
Custom Clock Rates: Any Multiple of 2kHz Up
to 125MHz
♦ Two Output Clocks
♦ One CMOS/TTL Output (≤ 125MHz)
♦ One LVDS/LVPECL Output (≤ 312.50MHz)
♦ Two Optional Frame-Sync Outputs: 2kHz, 8kHz
♦ Numerous Output Clock Frequencies Supported
Ethernet xMII: 2.5, 25, 125, 156.25, 312. 5MHz
SONET/SDH: 6.48, N x 19.44, N x 51.84MHz
PDH: N x DS1, N x E1, N x DS2, DS 3, E3
Other: 10, 10.24, 13, 30.72MHz
Frame Sync: 2kHz, 8kHz
Custom Clock Rates: Any Multiple of 2kHz Up to
77.76MHz, Any Multiple of 8kHz Up to
311.04MHz, Any Multiple of 10kHz Up to
388.79MHz
♦ General
♦ Suitable Line Card IC for Stratum 3/3E/4, SMC,
SEC
♦ Internal Compensation for Master Clock Oscillator
♦ SPI™ Processor Interface
♦ 1.8V Operation with 3.3V I/O (5V Tolerant)
♦ Industrial Operating Temperature Range
Order ing Information
PART
TEMP RANGE
PIN-PACKAGE
DS3106LN
-40
°
C to +85
°
C
64 LQFP
DS3106LN+
-40°C to +85°C
64 LQFP
+Denotes a lead(Pb)-free/RoHS-compliant pack age.
OC3
LOCAL
OSCILLATOR
CONTROL
STATUS
DS3106
IC4
IC3
FSYNC
MFSYNC
OC6 LVDS/LVPECL
Data Sheet
April 2012
DS3106
2
Table of Cont ents
1. STANDARDS COMPLIANCE ....................................................................................................... 6
2. APPLICAT IO N EXAMPLE ............................................................................................................ 7
3. BLOCK DIAGRAM ........................................................................................................................ 7
4. DETAILED DESCRI P TION ............................................................................................................ 8
5. DETAILED FEATURES ................................................................................................................. 9
5.1 INPUT CLOCK FEATURES .............................................................................................................. 9
5.2 DPLL FEATURES .......................................................................................................................... 9
5.3 OUTPUT APLL FEATURES ............................................................................................................. 9
5.4 OUTPUT CLOCK FEATURES ........................................................................................................... 9
5.5 GENERAL FEATURES .................................................................................................................... 9
6. PIN DESCRIPTIONS ................................................................................................................... 10
7. FUNCTIONAL DESCRIPTION .................................................................................................... 14
7.1 OVERVIEW ................................................................................................................................. 14
7.2 DEVICE IDENTIFICATION AND PROTECTION ................................................................................... 14
7.3 LOCAL OSCILLA TOR AND MASTER CLOCK CONFIGURATION ........................................................... 14
7.4 INPUT CLOCK CONFIGURATION .................................................................................................... 15
7.4.1 Signal Format Configuration ................................................................................................................ 15
7.4.2 Frequency Configuration ...................................................................................................................... 15
7.5 INPUT CLOCK MONITORING ......................................................................................................... 16
7.5.1 Fr equency Mon itori ng .......................................................................................................................... 16
7.5.2 Ac tiv ity M on it oring ................................................................................................................................ 16
7.5.3 Selec ted Ref er enc e Activ ity Monitoring ............................................................................................... 17
7.6 INPUT CLOCK PRIORITY AND SWITCHING ...................................................................................... 18
7.7 DPLL ARCHITECTURE AND CONFIGURATION ................................................................................ 19
7.7.1 T0 DPLL Stat e Mac hin e ....................................................................................................................... 20
7.7.2 Bandwidth ............................................................................................................................................ 23
7.7.3 Damping Factor .................................................................................................................................... 23
7.7.4 Phase Detec t or s ................................................................................................................................... 23
7.7.5 Loss-of-Lock Detection ........................................................................................................................ 24
7.7.6 Fr equency and Phas e Mea sur ement ................................................................................................... 25
7.7.7 Input Jitter Tolerance ........................................................................................................................... 25
7.7.8 Jitter Transfer ....................................................................................................................................... 25
7.7.9 Output Jitter and Wander ..................................................................................................................... 25
7.8 OUTPUT CLOCK CONFIGURATION ................................................................................................ 25
7.8.1 Signal Format Configuration ................................................................................................................ 26
7.8.2 Frequency Configuration ...................................................................................................................... 26
7.9 MICROPROCESSOR INTERFACE ................................................................................................... 34
7.10 RESET LOGIC .......................................................................................................................... 37
7.11 POWER-SUPPLY CONSIDERATIONS .......................................................................................... 37
7.12 INITIALIZATION......................................................................................................................... 37
8. REGISTER DESCRI PTIONS ....................................................................................................... 38
8.1 STATUS BITS .............................................................................................................................. 38
8.2 CONFIGURATION FIELDS ............................................................................................................. 38
8.3 MULTIREGISTER FIELDS .............................................................................................................. 38
8.4 REGISTER DEFINITIONS .............................................................................................................. 39
DS3106
3
9. JTAG TEST ACCESS PORT AND BOUNDARY SCAN.............................................................. 74
9.1 JTAG DESCRIPTION ................................................................................................................... 74
9.2 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION ............................................................. 75
9.3 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS ...................................................................... 77
9.4 JTAG TEST REGISTERS .............................................................................................................. 78
10. ELECT RICAL CHARACT ERISTICS ........................................................................................... 79
10.1 DC CHARACTERISTICS ............................................................................................................ 79
10.2 INPUT CLOCK TIMING ............................................................................................................... 82
10.3 OUTPUT CLOCK TIMING ........................................................................................................... 82
10.4 SPI INTERFACE TIMING ............................................................................................................ 83
10.5 JTAG INTERFACE TIMING ........................................................................................................ 85
10.6 RESET PIN TIMING .................................................................................................................. 86
11. PIN ASSIGNMENTS .................................................................................................................... 87
12. PACKAGE INFORMATI ON ......................................................................................................... 89
13. THERMAL INFO RMATION ......................................................................................................... 89
14. ACRO NYMS AND ABBREVIATIONS ......................................................................................... 90
15. DATA SHEET REVISION HISTORY ........................................................................................... 91
DS3106
4
List of Figures
Figure 2-1. Typical Application Example ..................................................................................................................... 7
Figure 3-1. Block Diagram ........................................................................................................................................... 7
Figure 7-1. DPLL Block Diagram ............................................................................................................................... 19
Figure 7-2. T0 DPLL State Transition Diagram ......................................................................................................... 21
Figure 7-3. FSYNC 8kHz Options .............................................................................................................................. 33
Figure 7-4. SPI Clock Phase Options ........................................................................................................................ 36
Figure 7-5. SPI Bus Transactions .............................................................................................................................. 36
Figure 9-1. JTAG Block Diagram ............................................................................................................................... 74
Figure 9-2. JTAG TAP Controller State Machine ...................................................................................................... 76
Figure 10-1. Recommended Termination for LVDS Output Pins .............................................................................. 81
Figure 10-2. Recommended Termination for LVPECL-Compatible Output Pins ...................................................... 81
Figure 10-3. SPI Interface Timing Diagram ............................................................................................................... 84
Figure 10-4. JTAG Timing Diagr am ........................................................................................................................... 85
Figure 10-5. Reset Pin Timing Diagram .................................................................................................................... 86
Figure 11-1. Pin Ass ignment Diagram ....................................................................................................................... 88
DS3106
5
List of Tables
Table 1-1. Applicable Telecom Standards ................................................................................................................... 6
Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 10
Table 6-2. Output Clock Pin Descriptions .................................................................................................................. 10
Table 6-3. Global Pin Descriptions ............................................................................................................................ 11
Table 6-4. SPI Bus Mode Pin Descriptions ............................................................................................................... 12
Table 6-5. JTAG Interface Pin Descriptions .............................................................................................................. 12
Table 6-6. Pow er-Supply Pin Descriptions ................................................................................................................ 13
Table 7-1. Input Clock Capabilities ............................................................................................................................ 15
Table 7-2. Input Clock Default Frequency Configuration ........................................................................................... 15
Table 7-3. Locking Frequen cy Modes ....................................................................................................................... 15
Table 7-4. Damping Factors and Peak Jitter/Wander Gain ....................................................................................... 23
Table 7-5. Output Clock Capabilities ......................................................................................................................... 25
Table 7-6. Digital1 Frequencies ................................................................................................................................. 27
Table 7-7. Digital2 Frequencies ................................................................................................................................. 27
Table 7-8. APLL Frequency to Output Frequencies (T0 APLL and T4 APLL) .......................................................... 28
Table 7-9. T0 APLL Frequency Configuration ........................................................................................................... 28
Table 7-10. T0 APLL2 Frequency Configuration ....................................................................................................... 28
Table 7-11. T4 APLL Frequency Configuration ......................................................................................................... 29
Table 7-12. OC3 and OC6 Output Frequency Selection ........................................................................................... 29
Table 7-13. Standard Frequencies for Programmable Outputs ................................................................................ 30
Table 7-14. T0FREQ Default Settings ....................................................................................................................... 32
Table 7-15. T4FREQ Default Settings ....................................................................................................................... 32
Table 7-16. OC6 Default Frequency Configuration ................................................................................................... 32
Table 7-17. OC3 Default Frequency Configuration ................................................................................................... 33
Table 8-1. Register Map ............................................................................................................................................ 39
Table 9-1. JTAG Instruction Codes ........................................................................................................................... 77
Table 9-2. JTAG ID Code .......................................................................................................................................... 78
Table 10-1. Recommended DC Operating Conditions .............................................................................................. 79
Table 10-2. DC Characteristics .................................................................................................................................. 79
Table 10-3. CMOS/TTL Pins ..................................................................................................................................... 80
Table 10-4. LVDS Output Pins .................................................................................................................................. 80
Table 10-5. LVPECL Level-Compatible Output Pins ................................................................................................. 81
Table 10-6. Input Clock Timing .................................................................................................................................. 82
Table 10-7. Input Clock to Output Clock Delay ......................................................................................................... 82
Table 10-8. Output Clock Phase Alignment, Frame-Sync Alignment Mode.............................................................. 82
Table 10-9. SPI Interface Timing ............................................................................................................................... 83
Table 10-10. JTAG Interface Timing.......................................................................................................................... 85
Table 10-11. Reset Pin Timing .................................................................................................................................. 86
Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................... 87
Table 13-1. LQFP Package Thermal Properties, Natural Convection ....................................................................... 89
Table 13-2. LQFP Theta-JA (θJA) vs. Airflow ............................................................................................................. 89
DS3106
6
1.
Standards Compliance
Table 1-1. Applicable Telecom St and ard s
SPECIFICATION SPECIFICATION TITLE
ANSI
T1.101
Synchronization Interface Standard, 1999
TIA/EIA-644-A
Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, 2001
ETSI
EN 300 417-6-1
Transmission and Multiplexing (TM); Generic requirements of transport functionality of
equipment; Par t 6-1: Synchronization layer functions, v1.1.3 (1999-05)
EN 300 462-3-1
Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part
3-1: The control of jitter and wander within synchronization networks, v1.1.1 (1998-05)
EN 300 462-5-1
Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part
5-1: Timing characteristics of slave cocks suitable for operation in Synchronous Digital
Hierarchy (SDH) Equipment, v1.1.2 (1998-05)
IEEE
IEEE 1149.1
Standard Test Access Port and Boundary-Scan Architecture, 1990
ITU-T
G.783
Characteristics of synchronous digital hierarchy (SDH) equipment functional blocks (10/2000
plus Amendment 1 06/2002 and Corrigendum 2 03/2003)
G.813
Timing characteristics of SDH equipment slave clocks (SEC) (03/2003)
G.823
The control of jitter and wander within digital networks which are based on the 2048 kbit/s
hierarchy (03/2000)
G.824
The control of jitter and wander within digital networks which are based on the 1544 kbit/s
hierarchy (03/2000)
G.825
The control of jitter and wander within digital networks which are based on the synchronous
digital hierarchy (SDH) (03/2000)
G.8261
Timing and synchronization aspects in packet networks (05/2006, prepublished)
G.8262
Timing characteristics of synchronous Ethernet equipment slave clock (EEC) (08/2007,
prepublished)
TELCORDIA
GR-253-CORE
SONET Transport Systems: Common Generic Criteria, Issue 3, September 2000
GR-1244-CORE
Clocks for the Synchronized Network: Common Generic Criteria, Issue 2, December 2000
DS3106
7
2.
Applicat ion Exampl e
Figure 2-1. Typ ic al Appl ic at ion Exam pl e
To SONET/SDH framers,
Clock Multiplying APLLs, etc.
on the Line Card
T0 DPLL
Input Clock
Selector,
Divider,
Monitor
From Master Timing Card IC3
IC4
OC3
19.44 MHz
OC6
prog. bandwidth,
manual reference switching,
holdover, etc.
DS3106
Output
Clock
Synthesizer
and Selector
19.44 MHz 155.52MHz differential
19.44 MHz
XO or
TCXO
From Slave Timing Card
3.
Block Diagr am
Figure 3-1. Block Diagram
T0 DPLL
(Filtering, Hol dover,
Frequency Conversion)
Master Clock
Generator
OC6 POS/ NEG
FSYNC
MFSYNC
IC3
IC4
Microprocessor Port
(SPI Serial)
and HW Contr ol and Status P ins
Local
Oscillator
RST*
CS
CPHA
SCLK
SDI
SDO
INTREQ / SRFAIL
SONSDH / GPIO4
SRCSW
REFCLK
JTAG
Input
Clock
Selector,
Divider
and
Monitor
Output
Clock
Synthesizer
and
Selector
(Muxes,
7 DFS Blocks,
3 APLLs,
Output Dividers)
TEST
O3F[1] / SRFAIL
O3F[2] / LOCK
OC3
JTRST*
JTMS
JTCLK
JTDI
JTDO
O6F[2:0] / GPIO[3:1]
O3F[0]
IPF[2:0]
DS3106
DS3106
8
4.
Detail ed Des cription
Figure 3-1 illustrates the blocks described in this sec tion and how the y r elate to one anoth er. Section 5 provides a
detailed feature list.
The DS3106 is a complete line card timing IC. At the core of this device is a digital phase-locked loop (DPLL).
DPLL technology makes use of digital-signal processing (DSP) and digital-frequency synthesis (DFS) techniques to
implement PLLs that are precise, flexible, and have consistent performance over voltage, temperature, and
manufacturing process variations. The DS3106’s T01 DPLL is digitally configurable for input and output
frequenc ies, loo p band widt h, dam ping f actor , pull-in/hold-in ran ge, an d a var iet y of other fac tors. T he T 0 DPLL can
directly lock to many common telecom frequencies and also can lock at 8kHz to any multiple of 8kHz up to
156.25MHz. The DPLL can also tolerate and filter significant amounts of jitter and wander.
In typical line card applications, the T0 DPLL takes reference clock signals from two redundant system timing
cards, monitors both, selects one, and uses that reference to produce a variety of clocks that are needed to time
the outgo ing traffic inter faces of the li ne card (SONET /SDH, Synchron ous Ethernet, etc .). To perform this role in a
variety of systems with diverse performance requirements, the T0 DPLL has a sophisticated feature set and is
highly configurable. T0 can automatically transition among free-run, locked, and holdover states without software
intervention. In free-run, T0 generates a stable, low-noise clock with the same frequency accurac y as the external
oscillator connected to the REFCLK pin. With software calibration the DS3106 can even improve the accuracy to
within ±0.02ppm . W hen the selec ted in put refer ence cloc k has been validated , T0 tr ansitions to the locked s tate in
which its output clock accuracy is equal to the accuracy of the input reference. While in the locked state, T0
acquires an average frequency value to use as the holdover frequency. When its selected reference fails, T0 can
very quic kly detect the f ailure and en ter the holdo ver state to a void aff ecting its output clock. From holdover it c an
be manuall y switch ed to an other i nput refer ence. When all input r eferenc es are lo st, T 0 stays in the hol dover state,
in which it g enerates a s table low-noise c lock with init ial frequenc y accurac y equal to its stored holdo ver value and
drift performance determined by the quality of the external oscillator.
At the front end of the T0 DPLL is the Input Clock Selector, Divider, and Monitor (ICSDM) block. This block
continuously monitors both input clocks for activity and coarse frequency accuracy. In addition, ICSDM can
manually select one of the input clocks to be the selected reference for the T0 DPLL. The ICSDM block can also
divide the selected clock down to a lower rate as needed by the DPLL.
The Output Clock Synthesizer and Selector (OCSS) block shown in Figure 3-1 and in more detail in Figure 7-1
contains three output APLLs—T0 APLL, T0 APLL2, and T4 APLL—and their associated DFS engines and output
divider logic plus several additional DFS engines. The APLL DFS blocks perform frequency translation, creating
clocks of other frequencies that are phase/frequency locked to the output clock of the T0 DPLL. The APLLs multiply
the clock rates from the APLL DFS blocks and simultaneously attenuate jitter. Altogether the output blocks of the
DS3106 can produce more than 90 different output frequencies including common SONET/SDH, PDH, and
Synchronous Ethernet rates plus 2kHz and 8kHz frame-sync pulses.
The entire chip is clocked from the external oscillator connected to the REFCLK pin. Thus, the free-run and
holdover stability of the DS3106 is entirely a function of the stability of the external oscillator, the performance of
which can be selected to match the application: typically XO or TCXO. The 12.8MHz clock from the external
oscillator is multipli ed b y 16 by the Master C loc k Gener ator b lock to create the 204 .8MH z master cloc k used b y the
remainder of the device.
1 The labels T0 and T4 in this document are adapted from output ports of the SETS function s pecified in ITU-T and ETSI standards such as
ETSI EN 300 462-2-1. Although strictl y speaking these names are appropriate only for t iming card ICs such as the DS3100 that can serve as
the SETS function, the names have been carried over to the DS3106 so that all of the products in Maxim’s timing IC product line have
consist ent nomencl ature.
DS3106
9
5.
Detail ed Features
5.1
Input Clock Feat ures
• Two programmable-frequency CMOS/TTL input clocks
• Input clocks accept any multiple of 2kHz up to 125MHz
• All input clocks are constantly monitored by programmable activity monitors
5.2
DPLL Features
• High-resolution DPLL plus three low-jitter output AP LL s
• Sophisticated state machine automatically transitions between free-run, locked, and holdover states
• Programmable bandwidth from 18Hz to 400Hz
• Separately configurable acquisition bandwidth and locked bandwidth
• Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10, or 20
• Multiple phase detectors: phase/frequency, early/late, and multicycle
• Phase/frequency locking (±360° capture) or nearest edge phase locking (±180° capture)
• Multicycl e phase detec t ion and loc k ing (up to ±8191UI) improves jitter tolerance and lock time
• High-resolution frequency and phase measurement
• Holdover frequency averaging over 1 second interval
• Fast detection of input clock failure and transition to holdover mode
• Low-jitter frame sync (8kHz) and multiframe sync (2kHz) aligned with output clocks
5.3
Output APLL Features
• Three separate clock-multiplying, jitter attenuating APLLs can simultaneously produce SONET/SDH rates,
Fast/Gigabit Ethernet rates, and 10G Ethernet rates, all locked to a common reference clock
• The T0 APLL has frequency options suitable for N x 19.44MHz, N x DS1, N x E1, N x 25MHz, and
N x 62.5MHz
• The T4 APLL has frequency options suitable for N x 19.44MHz, N x DS1, N x E1, N x DS2, DS3, E3,
N x 10MHz, N x 10.24MHz, N x 13MHz, N x 25MHz, and N x 62.5MHz
• The T0 APLL2 produces 312.5MHz for 10G Synchronous Ethernet applications
5.4
Output Clock Features
• Two output clocks: one CMOS/TTL (≤ 125MHz) and one LVDS/LVPECL (≤ 312.50MHz)
• Output clock rates include 2kHz, 8kHz, N x DS1, N x E1, DS2, DS3, E3, 6.48MHz, 19.44MHz, 38.88MHz,
51.84MH z, 77.7 6MH z, 155. 52MH z, 311. 04 MHz, 2.5MH z, 25MHz, 125 MH z, 156. 25MH z, 312.50MHz,
10MHz, 10.24MHz, 13MHz, 30.72MHz, and various multiples and submultiples of these rates
• Custom clock rates also available: any multiple of 2kHz up to 77.76MHz, any multiple of 8kHz up to 311.04MHz,
and any multiple of 10kHz up to 388.79MHz
• All outputs have < 1ns peak-to-peak output jitter; outputs from APLLs have < 0.5ns peak-to-peak
• 8kHz frame-sync and 2kHz multiframe-sync outputs have programmable polarity and pulse width, and can
be disciplined by a 2kHz or 8kHz sync input
5.5
General Feat ures
• Operates from a single external 12.800MHz local oscillator (XO or TCXO)
• SPI serial microprocessor interface
• Four general-purpose I/O pins
• Register set can be wr ite protec ted
DS3106
10
6.
Pin Descriptions
Table 6-1. Input Clock Pin Descriptions
PIN NAME(1) TYPE(2) PI N DE S CRIPTION
REFCLK I
Reference Clock. Connect to a 12.800MHz, high-accuracy , high-stability, low-noise local
oscillator (XO or TCXO). See Section 7.3.
IC3 IPD
Input Clock 3. CMOS/TTL. Programmable frequency. Default frequency selected by IPF[2:0]
pins when the
RST
pin goes high, 8kHz if IPF[2:0] pins left open.
IC4 IPD
Input Clock 4. CMOS/TTL. Programmable frequency. Default frequency selected by IPF[2:0]
pins when the
RST
pin goes high, 8kHz if IPF[2:0] pins left open.
Table 6-2. Output Clock Pin Descriptions
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
OC3 O
Output Clock 3. CMOS/TTL. Programmable frequency. Default frequency selected by
O3F[2:0] pins when the RST pin goes high, 19.44MHz if O3F[2:0] pins left open. See Table
7-17.
OC6POS,
OC6NEG ODIFF
Output Clock 6. LVDS/LVPECL. Programmable frequency. Default frequency selected by
O6F[2:0] pins when the RST pin goes high, 38.88MHz if O6F[2:0] pins left open. The output
mode is selected by MCR8.OC6SF[1:0]. See Table 10-4, Table 10-5, Figure 10-1, and Figure
10-2.
FSYNC O3
8kHz FSYNC. CMOS/TTL. 8kHz frame sync or clock (default 50% duty cycle clock,
noninverted). The pulse polarity and width are selectable using FSCR1.8KINV and
FSCR1.8KPUL.
MFSYNC O3
2kHz MFSYNC. CMOS/TTL. 2kHz frame sync or clock (default 50% duty cycle clock,
noninverted). The pulse polarity and width are selectable using FSCR1.2KINV and
FSCR1.2KPUL.
DS3106
11
Table 6-3. Global Pin Descriptions
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
RST IPU
Reset (Active Low). When this global asynchronous reset is pulled low, all internal circuitry is
reset to default values. The device is held in reset as long as RST is low. RST should be held
low for at leas t two REFCLK cycles after the external oscillator has stabilized and is providing
valid clock signal s.
SRCSW IPD
Source Switching. Input reference selection pin. Selects IC3 when high and IC4 when low.
See Section 7.6.
TEST
IPD
Factory Test Mode Select. Wi re this pin to VSS for normal operation.
IPF0 IPD
Input Frequency Select 0. Together with IPF1 and IPF2, this pin sets the default frequency of
the IC3 and IC4 input clock pins . The value is sampled when RST goes high, and the
FREQ[3:0] fields of ICR3 and ICR4 are set accordingly. See Table 7-2. After RST goes high this
pin is ignored.
IPF1 IPD
Input Frequency Select 1. Together with IPF0 and IPF2, this pin sets the default frequency of
the IC3 and IC4 input clock pins . The value is sampled when RST goes high, and the
FREQ[3:0] fields of ICR3 and ICR4 are set accordingly. See Table 7-2. After RST goes high this
pin is ignored.
IPF2 IPD
Input Frequency Select 2. Together with IPF0 and IPF1, this pin sets the default frequency of
the IC3 and IC4 input clock pins . The value is sampled when RST goes high, and the
FREQ[3:0] fields of ICR3 and ICR4 are set accordingly. See Table 7-2. After RST goes high this
pin is ignored.
O3F0 IPU
OC3 Frequency Select 0. This pin is sampled when the RST pin goes high and the value is
used as O3F0, which, together with O3F2 and O3F1, sets the default frequency of the OC3
output clock pin. See Table 7-17. After RST goes high this pin is ignored.
O3F1/SRFAIL IOPU
OC3 Frequency Select 1/SRFAIL Status Pin. This pin is sampled when the RST pin goes high
and the value is used as O3F1, which, together with O3F2 and O3F0, sets the default
frequency of the OC3 output clock pin. See Table 7-17. After RST goes high, if MCR10:SRFPIN
= 1, this pin follows the state of the SRFAIL status bit in the MSR2 register. This gives the
system a very fast indication of the failure of the selected reference. When MCR10:SRFPIN = 0,
SRFAIL is disabled (high impedance).
O3F2/LOCK IOPD
OC3 Frequency Select 2/T0 DPLL LOCK Status. This pin is sampled when the RST pin goes
high and the value is used as O3F2, which, together with O3F1 and O3F0, sets the default
frequency of the OC3 output clock pin. See Table 7-17. After RST goes high, if
MCR1.LOCKPIN = 1, this pin indicates the lock state of the T0 DPLL. When MCR1.LOCKPIN =
0, LOCK is disabled (low).
0 = Not locked
1 = Locked
O6F0/GPIO1 IOPD
OC6 Frequency Select 0/General-Purpose I/O Pin 1. This pin is sampled when the RST pin
goes high and the value is used as O6F0, which, together with O6F2 and O6F1, sets the
default frequency of the OC6 output clock pin. See Table 7-16. After RST goes high, this pi n
can be used as a general-purpose I/O pin. GPCR:GPIO1D configures this pin as an input or an
output. GPCR:GPIO1O specifies the output value. GPSR:GPIO 1 indicat es the stat e of the p in.
O6F1/GPIO2 IOPD
OC6 Frequency Select 1/General-Purpose I/O Pin 2. This pin is sampled when the RST pin
goes high and the value is used as O6F1, which, together with O6F2 and O6F0, sets the
default frequency of the OC6 output clock pin. See Table 7-16. After RST goes high, this pin
can be used as a general-purpose I/O pin. GPCR:GPIO2D configures this pin as an input or an
output. GPCR:GPIO2O specifies the output value. GPSR:GPIO 2 indicat es the stat e of the p in.
O6F2/GPIO3 IOPU
OC6 Frequency Select 2/General-Purpose I/O Pin 3. This pin is sampled when the RST pin
goes high and the value is used as O6F2, which, together with O6F1 and O6F0, sets the
default frequency of the OC6 output clock pin. See Table 7-16. After RST goes high, this pi n
can be used as a general-purpose I/O pin. GPCR:GPIO3D configures this pin as an input or an
output. GPCR:GPIO3O specifies the output value. GPSR:GPIO 3 indicat es the stat e of the p in.
DS3106
12
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
SONSDH/
GPIO4 IOPD
SONET/SDH Frequency Select Input/General-Purpose I/O 4. When RST goes high the state
of this pin sets the reset-default state of MCR3:SONSDH, MCR6:DIG1SS, and MCR6:DIG2SS.
After RST goes high, this pin can be used as a general-purpose I/O pin. GPCR:GPIO4D
configures this pin as an input or an output. GPCR:GP IO 4O specifi es the outp ut value.
GPSR:GPIO4 indicates the state of the pin.
Reset latched value s:
0 = SDH rates (N x 2.048MHz)
1 = SONET rates (N x 1.544MHz)
INTREQ/LOS O3
Interrupt Request/Loss of Signal. Programmable (default: INTREQ). The INTCR:LOS bit
determines whether the pin indicates interrupt reques ts or loss of signal (i.e., loss of selected
reference).
INTCR:LOS = 0: INTREQ mode
The behavior of this pin is conf igur ed in the INTCR register. Polarity can be active high or
active low. Drive action can be push-pull or open drain. The pin can also be configured as
a general-purpose output if the interrupt request function is not needed.
INTCR:LOS = 1: LOS mode
This pin indicates the real-time state of the selec ted reference activity monitor (see Section
7.5.3).
Table 6-4. SPI Bus Mode Pin Descriptions
See Section 7.9 for functional descript i on and Section 10.4 for timing specifications.
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
CS IPU Chip Select. This pin must be asserted (low) to read or write internal registers.
SCLK
I
Serial Clock. SCLK is always driven by the SPI bus master.
SDI
I
Serial Data Input. The SPI bus master trans mits data to the device on this pin.
SDO
O
Serial Data Output. The device transmits data to the SPI bus master on this pin.
CPHA I Clock Phase. See Figure 7-4.
0 = Data is latched on the leading edge of the SCLK pulse.
1 = Data is latched on the trailing edge of the SCLK pulse.
Table 6-5. JTAG Interface Pin Descriptions
See Section 9 for functional descripti on and Secti on 10.5 for timing specifications.
PIN NAME(1)
TYPE(2)
PIN DESCRIPTION
JTRST IPU
JTAG Test Reset (Active Low). Asynchronous ly resets the test access port (TAP) controller. If
not used, JTRST can be held low or high.
JTCLK I
JTAG Clock. Shifts data into JTDI on the rising edge and out of JTDO on the falli ng edge. If
not used, JTCLK can be held low or high.
JTDI IPU
JTAG Test Data Input. T est instru cti ons and dat a are clocked in on this pin on the rising edge
of JTCLK. If not used, JTDI can be held low or high.
JTDO O3
JTAG Test Data Output. Test instructions and data are clocked out on this pin on the falling
edge of JTCLK. If not used, le av e unconnected.
JTMS IPU
JTAG Test Mode Select. Sampled on the rising edge of JTCLK and is used to place the port
into the various defined IEEE 1149.1 states. If not used connect to VDDIO or leave
unconnected.
DS3106
13
Table 6-6. Power-Supply Pin Descriptions
PIN NAME(1)
TYPE(2)
PIN DESCRIPTION
VDD
P
Core Power Supply. 1.8V ±10%.
VDDIO
P
I/O Power Supply. 3.3V ±5%.
VSS
P
Ground Reference
AVDD_DL
P
Power Supply for OC6 Digital Logic. 1.8V ±10%.
AVSS_DL
P
Return for OC6 Digital Logic
VDD_OC6
P
Power Supply for Differential Output OC6POS/NEG. 1.8V ±10%.
VSS_OC6
P
Return for LVDS Differential Output OC6POS/NEG
AVDD_PLL1
P
Power Supply for Master Clock Generator APLL. 1.8V ±10%.
AVSS_PLL1
P
Return for Master Clock Generator APLL
AVDD_PLL2
P
Power Supply for T0 APLL. 1.8V ±10%.
AVSS_PLL2
P
Return for T0 APLL
AVDD_PLL3
P
Power Supply for T4 APLL. 1.8V ±10%.
AVSS_PLL3
P
Return for T4 APLL
AVDD_PLL4
P
Power Supply for T0 APLL2. 1.8V ±10%.
AVSS_PLL4
P
Return for T0 APLL2
Note 1: All pin names with an overbar (e.g., RST) are active low.
Note 2: All pins, except power and analog pins, are CMOS/TTL, unless otherwise specified in the pin description.
PIN TYPES
I = input pin
IDIFF = input pin that is LVDS/ LVPECL diff erential signal compati bl e
IPD = input pin with internal 50kΩ pulldown
IPU = input pin with internal 50kΩ pullup
I/O = input/output pin
IOPD = input/output pin with internal 50kΩ pulldown
IOPU = input/output pin with internal 50kΩ pullup
O = output pin
O3 = output pin that can be placed in a high-impedanc e state
ODIFF = output pin that is LVDS/LVPECL differential signal compatible
P = power-supply pin
Note 3: All digital pins, except OCn, are I/O pins in JTAG mode. OCn pins do not have JTAG functionality.
DS3106
14
7.
Functional D es cription
7.1
Overview
The DS310 6 has two i nput c locks, t wo output clock s, and a high-per form ance DPLL k nown as T0. Figure 3-1. T he
two input clocks are CMOS/TTL (5V tolerant) and can accept signals from 2kHz to 125MHz. Each input clock is
monitored continually for activity. SRFAIL is set or cleared based on the activity of the selected input.
The T0 DPLL can directly lock to many common datacom and telecom frequencies, including, but not limited to,
8kHz, DS1, E1, 10MHz, 19.44MHz, and 38.88MHz, as well as Ethernet frequencies including 25MHz, 62.5MHz,
and 125MHz. The DPLL can also lock to multiples of the standard direct-lock frequencies including 8kHz. The T0
DPLL has all the features needed for synchronizing a line card to dual redundant system timing cards.
The T0 DPLL includes these features:
A full state machine for automatic transitions among free-run, locked, and holdover states
Adjustable PLL characteristics, including bandwidth, pull-in range, and damping factor
Six bandwidth selections from 18Hz to 400Hz
Frequency conversion between input and output using digital frequency synthesis
Combined performance of a stable, consistent digital PLL and low-jitter analog output PLLs
Ability to lock to several common telecom and Ethernet frequencies plus multiples of the standard direct lock
frequencies including 8kHz
Instant digit al one-second averaging and free-run holdover modes
T ypically, the inter na l state machine controls the T0 DPLL, but manual control by system software is also available.
The outputs of the T 0 D PLL can be c onnec te d to s even output DF S en gines . Se e Figure 7-1. Three of these out p ut
DFS engines are associated with high-speed APLLs t hat multiply the DPLL clock rate and filter DPLL output jitter.
The outputs of the APLLs are divided down to m ak e a wide variet y of possible frequencies available at the output
clock pins.
The OC3 and OC6 output clocks can be configured for a variety of different frequencies that are frequency- and
phase-lock ed to the T0 DPLL. T he OC6 output is LVDS/L VPECL. The O C3 output is CMOS/TT L. Altogether m ore
than 60 output frequencies are possible, ranging from 2kHz to 312.5MHz. The FSYNC output clock is always 8kHz,
and the MFSYNC output clock is always 2kHz.
7.2
Device I denti fi cat ion and Protection
The 16-bit read-only ID field in the ID1 and ID2 regist ers is set to 0C22h = 31 06 decim al. The device revision ca n
be read from the REV register. Contact the factory to interpret this value and determine the latest revision. The
register set can be protected from inadvertent writes using the PROT register.
7.3
Local Oscil lator and Master Clock Configuration
The T0 DPLL a nd the o utp ut D FS en gi nes oper a te f r om a 204.8MH z master clock. The master clock is synthesi zed
from a 12.800MHz clock originating from a local oscillator attached to the REFCLK pin. The stability of the T0 DPLL
in free-run or holdo ver is e quiva lent t o the s tabi lity of the loca l osci llator. Select ion of an a ppro priate loca l osc illator
is therefore of crucial importance if the telecom standards listed in Table 1-1 are to be met. Simple XOs can be
used in less stringent cases, but TCXOs or even OCXOs may be required in the most demanding applications.
Careful e va lua tion of the l o c al osc illat or component is nec es s ar y to ens ur e pr o per performance. Cont ac t Microsemi
timing products technical support for recommended oscillators.
The stabilit y of the local oscillator is ver y im portant, but its absolute frequenc y accuracy is less im portant because
the DPLLs can compensate for frequency inaccuracies when synthesizing the 204.8MHz master clock from the
DS3106
15
local oscillator clock . T he MCLKFREQ field in registe rs MCLK1 and MCLK2 specifies the frequency adjustm ent to
be applied. The adjust can be from -771ppm to +514ppm in 0.0196229ppm (i.e., ~0.02ppm) steps.
7.4
Input Clock Configuration
The DS3106 has two input clocks: IC3 and IC4. Table 7-1 provides summary information about each clock,
including s igna l form at and avail able fr equenc ies. T he device to lerates a wide r ange of duty cyc les on inp ut clock s ,
out to a minimum high time or minimum low time of 3ns or 30% of the clock period, whichever is smaller.
7.4.1
Sign al Format Con figurat ion
Both IC3 and IC4 accept TTL and 3.3V CMOS levels. One key configuration bit that affects the available
frequencies is the SONSDH bit in MCR3. When SONSDH = 1 (SONET mode), the 1.544MHz frequency is
availab le. W hen SONSDH = 0 (SD H m ode), the 2. 048MH z frequ ency is av ailab le. Durin g reset th e def ault valu e of
this bit is latched from the SONSDH pin.
Table 7-1. Input Clock Capabilities
INPUT CLOCK
SIGNAL
FORMATS
FREQUENCIES
(MHz)
DEFAULT FREQUENCY
IC3
CMOS/TTL
Up to 125(1)
Determined by IPF[2:0] and SONSDH pins, see Table 7-2.
IC4
CMOS/TTL
Up to 125(1)
Determined by IPF[2:0] and SONSDH pins, see Table 7-2.
Note 1: Available frequencies f or CMOS/TTL input cl ocks are: 2kHz, 4kHz, 8kHz, 1.544MHz (SONET mode), 2.048MHz (SDH mode),
6.312MHz, 6.48MHz, 19.44MHz, 25.0MHz, 25. 92MHz, 38. 88MHz, 51. 84MHz, 62. 5MHz, 77. 76MHz, and any multi pl e of 2kHz up to 125MHz.
Table 7-2. Input Clock Default Frequency Configuration
IPF[2:0] SONSDH
DEFAULT FREQUENCY,
LOCK MODE
000
X
8kHz, direct lock
001
0
2.048MHz, direct lock
001
1
1.544MHz, direct lock
010
X
6.48MHz, direct lock
011
X
19.44MHz, direct lock
100
X
25.92MHz, direct lock
101
X
38.88MHz, direct lock
110
X
51.84MHz, direct lock
111
X
77.76MHz, direct lock
7.4.2
Frequency C onfi gurati on
Input cloc k f requenc ies ar e conf igure d in t he FR EQ fie ld of the ICR re gisters . T he DIVN and LOCK 8K bi ts of these
same registers specify the locking frequency mode, as shown in Table 7-3.
Table 7-3. Locking Frequency Modes
DIVN LOCK8K
LOCKING FREQUENCY
MODE
0
0
Direct Lock
0
1
LOCK8K
1
0
DIVN
1
1
Alternate Direct Lock
DS3106
16
7.4.2.1
Direct Lock Mode
In direct lock mode, the T0 DPLL locks to the selected reference at the frequency specified in the corresponding
ICR register . D irec t l oc k mode can on ly be us ed f or inp ut cloc ks with th ese s pecific frequencies: 2k Hz, 4kH z, 8kHz,
1.544MHz, 2.048MHz, 5MHz, 6.312MHz, 6.48MHz, 19.44MHz, 25.92MHz, 31.25MHz, 38.88MHz, 51.84MHz, and
77.76MHz. The DIVN mode can be used to divide an input down to any of these frequencies except 155.52MHz.
MTIE figures may be marginally better in direct lock mode because the higher frequencies allow more frequent
phase updates .
7.4.2.2
Alternate D irect Lock Mode
Alternate direct lock mode is the same as direct lock mode except an alternate list of direct lock frequencies is used
(see the FREQ field definition in the ICR register description). The alternate frequencies are included to support
clock rates found in Ethernet, CMTS, wireless, and GPS applications. The alternate frequencies are: 10MHz,
25MHz, 62. 5MHz, and 125MHz. T he frequencies 62.5MHz an d 125MHz ar e internall y divided do wn to 31.2 5MHz,
while 10MHz and 25MHz are internally divided down to 5MHz.
7.4.2.3
LOCK 8K Mode
In LOCK8K m ode, an i nternal divider is conf igured t o divide th e select ed referen ce down to 8k Hz. The DP LL locks
to the 8kHz output of the divider. LOCK8K mode can only be used for input clocks with the standard direct lock
frequencies: 8kHz, 1.544MHz, 2.048MHz, 5MHz, 6.312MHz, 6.48MHz, 19.44MHz, 25.0MHz, 25.92MHz,
31.25MHz, 38.88MHz, 51.84MHz, 62.5MHz, and 77.76MHz. LOCK8K mode is enabled for a particular input clock
by setting the LOCK8K bit in the corresponding ICR register.
LOCK8K mode gives a greater tolerance to input jitter when the multicycle phase detector is disabled because it
uses lower frequencies for phase comparisons. The clock edge to lock to on the selected reference can be
configured using the 8KPOL bit in the TEST1 register. For 2kHz and 4kHz clocks the LOCK8K bit is ignored and
direct-lock mode is used.
7.4.2.4
DIVN Mode
In DIVN mode, an interna l divider is configured from the value stored in the DIVN registers. T he DIVN value must
be chose n so that when the s elected ref erence is divided by DIVN+ 1, the resu lting clock f requency is the sam e as
the standard direct lock frequency selected in the FREQ field of the ICR register. The DPLL locks to the output of
the divider. DIVN mode can only be used for input clocks whose frequency is less than or equal to 125MHz. The
DIVN register field can range from 0 to 65,535 inclusive. The same DIVN+1 factor is used for all input clocks
configured for DIVN mode.
7.5
Input Clock M onit or ing
Each inpu t clock is continu ously monitor ed for activit y. Activit y m onitoring is described in Sect ions 7.5.2 and 7.5.3.
The valid/invalid state of each input clock is reported in the corresponding real-tim e status bit in register VALSR1.
When the valid/invalid state of a clock changes, the corresponding latched status bit is set in register MSR1, and
an interrupt request occurs if the corresponding interrupt enable bit is set in register IER1. Input clocks marked
invalid cannot be automatically selected as the reference for either DPLL.
7.5.1
Frequency Monit oring
The DS3106 monitors the frequency of each input clock and invalidates any clock whose frequency is more than
10,000ppm away from nominal. The fr equenc y ran ge monitor can be disabled b y cleari ng the MCR1.F REN b it. The
frequency range measurement uses the internal 204.8MHz master clock as the frequency reference.
7.5.2
Activity Monitoring
Each input clock is monitored for activity and proper behavior using a leaky bucket accumulator. A leaky bucket
accumulator is sim ilar to an analog integrat or: the output amplitude increases in the presence of input events and
DS3106
17
gradually decays in the absence of events. When events occur infrequently, the accumulator value decays fully
between e vents and no alarm is declared. W hen events oc cur close enough tog ether, the accum ulator increm ents
faster than it can decay and eventually reaches the alarm threshold. After an alarm has been declared, if events
occur infrequently enough, the accumulator can decay faster than it is incremented and eventually reaches the
alarm clear threshold. The leaky bucket events come from the frequency range and fast activity monitors.
There is one leaky bucket configuration common to both inputs that has programmable size, alarm declare
threshold, alarm clear threshold, and decay rate, all of which are specified in the LB0x registers.
Activit y monitorin g is divi ded into 1 28m s intervals. T he ac cum ulator is incr em ented once f or each 128m s inter val in
which the input clock is inactive for more than two cycles (more than four cycles for 125MHz, 62.5MHz, 25MHz,
and 10MHz input clocks). Thus, the “fill” rate of the bucket is at most 1 unit per 128ms, or approximately 8
units/second. During each period of 1, 2, 4, or 8 intervals (programmable), the accumulator decrements if no
irregularities occur. Thus, the “leak” rate of the bucket is approximately 8, 4, 2, or 1 units/second. A leak is
prevented when a fill event occurs in the same interval.
W hen the value of an ac cu mulator r eaches the al ar m threshold ( LB0U register), the c orr es pond ing AC T alar m bit is
set to 1 in the ISR2 register, and the clock is marked invalid in the VALSR1 register. When the value of an
accumulator reaches the alarm clear threshold (LB0L register), the activity alarm is cleared by clearing the c lock’s
ACT bit. The accumulator cannot increment past the size of the bucket specified in the LB0S register. The decay
rate of the accumulator is specified in the LB0D register. The values stored in the leaky bucket configuration
registers must have the following relationship at all times: LB0S ≥ LB0U > LB0L.
When the leaky bucket is empty, the minimum time to declare an activity alarm in seconds is LB0U / 8. The
minim um time to c lear an a ctivity alar m in sec onds is 2^LB 0D × (LB0S – LB 0L) / 8. As an exam ple, assum e LB0U
= 8, LB0L = 1, LB0S = 10, and LB 0D = 0. The minimum time to declare an acti vity alarm would be 8 / 8 = 1 second.
The minimum time to clear the activity alarm would be 2^0 × (10 – 1) / 8 = 1.125 seconds.
7.5.3
Sele ct ed Re ference Acti vity Monitoring
The input clock that T0 DPLL is currently locked to is called the selected reference. The quality of a DPLL’s
selected reference is exceedingly important, since missing cycles and other anomalies on the selected reference
can cause unwanted jitter, wander, or frequency offset on the output clocks. When anomalies occur on the selected
referenc e, they must be detec ted as soon as possi ble to give the DPLL op portunity to tem porarily disconnec t from
the reference until the reference is available again. By design, the regular input clock activity monitor (Section
7.5.2) is too s low to be suit able for monitorin g the selected ref erence. Instea d, each DPLL has its o wn fast activit y
monitor that detects that the frequency is within range (approximately 10,000ppm) and detects inactivity within
approximately two missing reference clock cycles (approximately four missing cycles for 125MHz, 62.5MHz,
25MHz, and 10MHz references ) .
When the T0 DPLL detects a no-activity event, it immediately enters mini-holdover mode to isolate itself from the
selected reference and sets the SRFAIL latched status bit in MSR2. The setting of the SRFAIL bit can cause an
interrupt request if the corresponding enable bit is set in IER2. If MCR10:SRFPIN = 1, the SRFAIL output pin
follows th e stat e of th e SRFAIL s ta tus b it. When PHLIM1:N ALOL = 0 (def au lt), th e T 0 DPLL d oes no t declar e loss -
of-lock during no-act ivity events. If the s elected ref eren ce becom es available aga in bef ore an y alarm s are declar ed
by the activity monitor, the T0 DPLL continues to track the selected reference using nearest edge locking (±180°)
to avoid cycle slips. When NALOL = 1, the T0 DPLL declares loss-of-lock during no-activity events. This causes the
T0 DPLL state machine to transition to the loss-of-lock state, which sets the MSR2:STATE bit and causes an
interrupt request if enabled. If the selected reference becomes available again before any alarms are declared by
the activity monitor, the T0 DPLL tr acks the selecte d reference using phase/f requency locking ( ±360°) until phase
lock is reestablished.
DS3106
18
7.6
Input Clock Pr iority and Switching
The SRCSW input pin controls reference switching between two clock inputs. In this mode, if the SRCSW pin is
high, the T0 DPLL is forced to lock to input IC3. If the SRCSW pin is low the device is forced to lock to input IC4.
The currently selected reference is indicated in the PTAB1:SELREF field.
DS3106
19
7.7
DPLL Archi tecture and Confi gur ati on
The T0 DPLL is a digital PLL with separate analog PLLs (APLLs) as output stages as well as some outputs that are
not cleaned up by an APLL. This architecture combines the benefits of both PLL types. See Figure 7-1.
Figure 7-1. DPLL Block Diagram
T0 DPLL
Locking
Frequency
T0
PFD and
Loop Filter
T0
Foward
DFS
T0
Feedback
DFS
DIG12
DFS
T0 selected
reference
OC3, OC6
T0CR1:T0FREQ[2:0]
OCRm:OFREQn[3:0]
OCR5:AOFn
T4CR1:T4FREQ[3:0]
T0CR1:T0FT4[2:0]
APLL
Output
Dividers
T0
Output
APLL
T0
APLL
DFS
APLL
Output
Dividers
T4
Output
APLL
T4
APLL
DFS
DIG12
DFS
2K8K
DFS
MCR6:DIG2SS
MCR6:DIG2F[1:0]
MCR6:DIG2AF
MCR6:DIG1SS
MCR6:DIG1F[1:0]
OUTPUT DFS
FSYNC
DFS
DIG2
DIG1
2K8K
ICRn:FREQ[3:0]
APLL
Output
Dividers
T0
Output
APLL2
T0
APLL2
DFS
2
2FSYNC,
MFSYNC
OCR4:FSEN, MFSEN
FSCR1:8KI NV, 2KINV
FSCR1:8KP O L , 2KPOL
DS3106
20
Digital PLLs have two key benefits: (1) stable, repeatable performance that is insensitive to process variations,
temperature, and voltage; and (2) flexible behavior that is easily programmed through the configuration registers.
DPLLs use digital frequency synthesis (DFS) to generate various clocks. In DFS a high-speed master clock
(204.8MHz) is multiplied up from the 12.800MHz local oscillator clock applied to the REFCLK pin. This master
clock is then digitally divided down to the desired output frequency. The DFS output clock has jitter of about 1ns pk-
pk.
The analog PLLs filter the jitter from the DPLLs, reducing the 1ns pk-pk jitter to less than 0.5ns pk-pk and 60ps
RMS, typical, measured broadband (10Hz to 1GHz).
The DPLLs in the device are configurable for many PLL parameters including bandwidth, damping factor, input
frequency, pull-in/hold-in range, and more. No knowledge of loop equations or gain parameters is required to
configure and operate the device. No external components are required for the DPLL or the APLLs except the
high-qua li t y local osci ll ator c onnec te d to the REFC LK pin.
The T0 DPLL has a full free-run/locked/holdover state machine and full programmability.
7.7.1
T0 DPLL State Machine
The T0 DPLL has three main timing modes: locked, holdover, and free-run. The control state machine for the T0
DPLL has s tates f or each ti ming m ode as well as three tem porar y states: pre locked, pre locked 2, and loss-of-lock.
The stat e transition diagra m is shown in Figure 7-2. Desc riptions of each s tate are give n in the paragraph s below.
During norm al operation the state machine controls state transitions. When necessary, however, the state can be
forced using the T0STATE field of the MCR1 register.
Whenever the T0 DPLL changes state, the STATE bit in MSR2 is set, which can cause an interrupt request if
enabled. The current T0 DPLL state can be read from the T0STATE field of the OPSTATE register.
7.7.1.1
Free-R un State
Free-run mode is the reset default state. In free-run all output clocks are derived from the 12.800 MHz local
oscillator attached to the REFCLK pin. The frequency of each output clock is a specific multiple of the local
oscillator. The frequency accuracy of each output clock is equal to the frequency accuracy of the master clock,
which can be calibrated using the MCLKFREQ field in registers MCLK1 and MCLK2 (see Section 7.3). The state
machine transitions from free-run to the prelocked state when at least one input clock is valid.
7.7.1.2
Prelocked State
If phase lock (see Section 7.7.5) is achieved for 2 seconds during this period, the state machine transitions to
locked m ode. If the selected reference becom es inactive for 2 secon ds then the state machine transitions back to
the free-run state.
DS3106
21
Figure 7-2. T0 DPLL State Transition Diagram
FREE-RUN
(001)
PRE-LOCKED
(110)
RESET
SELECTED REFERENCE ACTIVE
SELECTED REFERENCE
INACTIVE > 2s
LOCKED
(100)
PHASE-LOCKED TO SELECTED
REFE RE NCE > 2s
LOSS-OF-
LOCK
(111)
HOLDOVER
(010)
LOSS-OF-LOCK ON
SELECTED REFERENCE
PHASE-LOCK REGAINED O N
SELECTED REFERENCE > 2s
PRE-LO CK E D 2
(101)
SELECTED REFERENCE
INACTIVE > 2s
SELECTED REFERENCE SWITCH
SELECTED REFERENCE INACTIVE > 2s
SELECTED REFERENCE ACTIVE
SELECTED REFERENCE
INACTIVE > 2s
SELECTED REFERENCE SWITCH
SELECTED REFERENCE
PHASE-LOCKE D > 2s
Note 1:
Phase lock is declared i nternally when the DPLL has maintained phase lock continuously for approximately 1 to 2 seconds.
Note 2:
When selected reference is invalid and the DPLL is not in free-run or holdover, the DPLL is in a temporary holdover state.
DS3106
22
7.7.1.3
Lock ed State
The T0 DPLL state machine can reach the locked state from the prelocked, prelocked 2, or loss-of-lock states
when the D PLL has loc ked to the s elected r eference f or at least 2 s econds (see Section 7.7.5). In the locked s tate
the output clocks track the phase and frequency of the selected reference.
If the MCR1.LOCKPIN bit is set, the LOCK pin is driven high when the T0 DPLL is in the locked state.
W hile in the locked stat e, if the selecte d referenc e becom es inactive and an acti vit y alarm is raised (corr esponding
ACT bit set in the ISR2 register), the selected reference is marked invalid (ICn bit goes low in the VALSR1
register), and the LOS pi n i s ass erted. If the input sta ys inac tive f or 2 secon ds, th e stat e m achine transit ions to the
holdover state. If the DPLL is switched to the other input and that input is active, the state machine transitions to
the prelocked 2 state.
7.7.1.4
Loss-of-Loc k S tate
When the loss-of-lock detectors (see Section 7.7.5) indicate loss-of-phase lock, the state machine immediately
transitions from the lock ed state to the loss-of-lock state. If phase lock is r egained duri ng that per iod for m ore than
2 seconds while in the loss -of-lock state, the state machine transitions back to the locked state.
While in the loss-of-lock state, if the selected reference is becomes inactive, an activity alarm is raised
(corresponding ACT bit set in the ISR2 register), the selected reference is marked invalid (ICn bit goes low in the
VALSR1 register), and the LOS pin is asserted. If the input stays inactive for 2 seconds, the state machine
transitions to the holdover state. If the DPLL is switched to the other input and that input is active, the state
machine transitions to the prelocked 2 state.
7.7.1.5
Prelocked 2 S t ate
The prelocked and prelocked 2 states are similar. If phase lock (see Section 7.7.5) is achieved for more than 2
seconds, the state m achine transitions to locked mode. W hile in the prelocked 2 state, if the selected reference is
becomes inactive, an activity alarm is raised (corresponding ACT bit set in the ISR2 register), the selected
reference is marked invalid (ICn bit goes low in the VALSR1 register), and the LOS pin is asserted. If the input
stays inactive for 2 seconds, the state machine transitions to the holdover state.
7.7.1.6
Holdover St ate
The device reaches the holdover state when it declares its selected reference invalid for 2 seconds. During
holdover th e T0 DPLL is not phase-locked to any input clock but instead generates its output frequenc y based on
previous frequencies while it was locked. When the selected reference becomes active, the state machine
immediately transitions from holdover to the prelocked 2 state, and tries to lock to the selected reference.
7.7.1.6.1Automatic Holdover
For autom atic holdover (FRUNHO = 0 in MCR3), the device can be further configured for instantaneous mode or
average d mode. In instantaneous mode (AVG = 0 in HOCR3) , the holdover fr equency is set to the DPLL’s current
frequenc y 50m s to 100ms before entr y into holdo ver (i.e., the va lue of the FREQ field in the FREQ1, FREQ2, and
FREQ3 registers). The FREQ field is the DPLL’s integral path and, therefore, is an average frequency with a rate of
change inversely proportional to the DPLL bandwidth. The DPLL’s proportional path is not used in order to
minimize the effect of recent phase disturbances on the holdover frequency.
In avera ged mode (AVG = 1 in HOCR3 and F RUNHO = 1 in MCR3), t he holdov er f requency is s et to a n inte rnally
averaged value. During locked operation the frequency indicated in the FREQ field is internally averaged over a
one-secon d per iod . The T0 D PL L indicates th at it h as ac quire d a va lid holdo ver v alue by settin g th e HO RDY st atus
bit in MSR4 (latched status). If the T0 DPLL must enter holdover before the one-second average is available, an
instantaneous value 50ms to 100ms old from the integral path is used instead.
7.7.1.6.2Free-Run Holdover
For free-run holdover (FRUNHO = 1 in MCR3), the output frequency accuracy is generated with the accuracy of
the external oscillator frequency. The actual frequency is the frequency of the external oscillator plus the value of
the MCLK offset specified in the MCLKFREQ field in registers MCLK1 and MCLK2 (see Section 7.3). When
MCR3.FRUNHO is set the HOCR3:AVG bit is ignored.
DS3106
23
7.7.1.7
Mini-Holdover
W hen the selected ref erence f ails, the fas t activit y monitor (Sec tion 7.5.3) is olate s the T0 DPLL f rom the refer ence
within one or t wo c lock c ycles to avoid adv erse ef fec ts on the DPLL fr equenc y. W hen this fast is olation occ urs, the
DPLL enters a temporary mini-holdover mode, with a frequency equal to an instantaneous value 50ms to 100 ms
old from the integral path of the loop filter. Mini-holdover lasts until the selected reference becomes active or the
state machine enters the holdover state. If the free-run holdover mode is set (FRUNHO = 1 in MCR3), the mini-
holdover frequency accuracy is exactly the same as the external oscillator accuracy plus the offset set by the
MCLKFREQ field in registers MCLK1 and MCLK2 (see Section 7.3).
7.7.2
Bandwidth
The bandwidth of the T0 DPLL is configured in the T0ABW and T0LBW registers for various values from 18Hz to
400Hz. The AUTOBW bit in the MCR9 register controls automatic bandwidth selection. When AUTOBW = 1, the
T0 DPLL uses the T0ABW bandwidth during acquisition (not phase-locked) and the T0LBW bandwidth when
phase-locked. When AUTOBW = 0 the T0 DPLL uses the T0LBW bandwidth all the time, both during acquisition
and when phase-locked.
When LIMINT = 1 in the MCR9 register, the DPLL’s integral path is limited (i.e., frozen) when the DPLL reaches
minimum or maximum frequency. Setting LIMINT = 1 minimizes overshoot when the DPLL is pulling in.
7.7.3
Dampi ng Fa ctor
The damping factor for the T0 DPLL is configured in the DAMP field of the T0CR2 register. The reset default
damping f actor is chosen to gi ve a m aximum j itter/wander gain peak of appr oximatel y 0.1dB . Availa ble sett ings are
a function of DPLL bandwidth (configured in the T0ABW and T0LBW registers). See Table 7-4.
Table 7-4. Damping Factors and Peak Jitter/Wander Gain
BANDWIDTH
(Hz) DAMP[2:0]
VALUE DAMPING
FACTOR GAIN PEAK
(dB)
18
1
1.2
0.4
2
2.5
0.2
3, 4, 5
5
0.1
35
1
1.2
0.4
2
2.5
0.2
3
5
0.1
4, 5
10
0.06
70 to 400
1
1.2
0.4
2
2.5
0.2
3
5
0.1
4
10
0.06
5
20
0.03
7.7.4
Phas e Detectors
Phase detectors are used to compare a PLL’s feedback clock with its input clock. Several phase detectors are
available in the T0 DPLL:
Phase/frequency detector (PFD)
Early/late phase detector (PD2) for fine resolution
Multicycle phase detector (MCPD) for large input jitter tolerance and/or faster lock times
These detectors can be used in combination to give fine phase resolution combined with large jitter tolerance. As
with the rest of the DPLL logic, the phase detectors operate at input frequencies up to 77.76MHz. The multicycle
DS3106
24
phase det ector d etects and rem em bers phas e diff erenc es of man y cycles ( up to 8191UI) . When lock ing to 8kH z or
lower, the normal phase/frequency detectors are always used.
The T0 DPLL phase detectors can be configured for normal phase/frequency locking (±360° capture) or nearest
edge phase locking (±180° capture). With nearest edge detection the phase detectors are immune to occasional
missing c lock c ycles. The D PLL aut omaticall y s witches to near es t ed ge loc k ing when the m ultic yc le phas e d etec tor
is disabled and the other phase detectors determine that phase lock has been achieved. Setting D180 = 1 in the
TEST1 register disables nearest edge locking and forces the T0 DPLL to use phase/frequency locking.
The early/late phase detector, also k nown as phase detector 2, is enabled and configured in the PD2 fields of the
T0CR2 register. The reset default settings of this register is appropriate for all operating m odes. Adjustments only
affect small signal overshoot and bandwidth.
The multicycle phase detector is enabled by setting MCPDEN = 1 in the PHLIM2 register. The range of the
MCPD—from ±1UI up to ±8191UI—is configured in the COARSELIM field of PHLIM2. The MCPD tracks phase
position over m an y clock c ycles, giving high j itter to ler ance. T hus, th e use of the MCPD is an a lternat ive to the us e
of LOCK8 K mode for j itter tolerance. W hen a DPLL is dir ect locking to 8k Hz, 4kHz, or 2kHz, or in LOC K8K m ode,
the multicycle phase detector is automatically disabled.
W hen USEMC PD = 1 in PHLIM2, the M CPD is used in the DPLL l oop, giving f aster pull-in bu t more overs hoot. In
this m ode the loop has s imilar behav ior to LOCK8 K mode. In both cases lar ge phase dif ferences c ontribute to the
dynamics of the loop. When enabled by MCPDEN = 1, the MCPD tracks the phase position whether or not it is
used in the DPLL loop.
W hen the input clock is divided b efore being s ent to the phas e detector, t he divid er output clock edge gets a ligned
to the feedb ack clock edge before t he DPLL starts to lock to a new inp ut clock signal or after the inp ut cloc k signal
has a temporary signal loss. This helps ensure locking to the nearest input clock edge, which reduces output
transients and decreases lock times.
7.7.5
Loss-of-Loc k Detect ion
Loss-of-lock can be triggered by any of the following in the T0 DPLL:
The fine phase-lock detector (measures phase between input and feedback clocks)
The coarse phase-lock detector (measures whole cycle slips)
Hard frequency limit detector
Inactivity detector
The fine phase-lock detector is enabled by setting FLEN = 1 in the PHLIM1 register. The fine phase limit is
configured in the FINELIM field of PHLIM1.
The coarse phase-lock detector is enabled b y setting CLEN = 1 in the PHLIM2 register. The coarse phase lim it is
configured in the COARSELIM field of PHLIM2. This coarse phase-lock detector is part of the multicycle phase
detector (MCPD) described in Section 7.7.4. The COARSELIM field sets both the MCPD range and the coarse
phase limit, since the two are equivalent. If loss-of-lock should not be declared for multiple-UI input jitter, the fine
phase-lock detector should be disabled and the coarse phase-lock detector should be used instead.
The hard frequency limit detector is enabled by setting FLLOL = 1 in the DLIMIT3 register. The hard limit is
configured in registers DLIMIT1 and DLIMIT2. When the DPLL frequency reaches the hard limit, loss-of-lock is
declared. The DLIMIT3 register also has the SOFTLIM field to specify a soft frequency limit. Exceeding the soft
frequenc y lim it does not caus e loss -of-lock to be dec lared. When the T 0 DPLL f requenc y reach es the s oft lim it, the
T0SOFT status bit is set in the OPSTATE register.
The inact ivity detector is enab led by settin g NALOL = 1 in the PHLIM1 re gister. W hen this detect or is enabl ed the
DPLL declares loss-of-lock after one or two missing clock cycles on the selected reference. See Section 7.5.3.
W hen the T0 DPLL dec lares loss-of-lock , the state m achine imm ediately trans itions t o the loss-of-lock state, whic h
sets the STATE bit in the MSR2 register and requests an interrupt if enabled.
DS3106
25
7.7.6
Frequency and Phase Measur ement
Accurate measurement of frequency and phase can be accomplished using the T0 DPLL. The REFCLK signal
accuracy after being adjusted with MCLKFREQ is used for the frequency reference.
DPLL f requency m eas urements c an b e rea d from the F REQ f ield s pan ni ng r eg ist er s FREQ1, FREQ2, and FREQ3.
This field indicates the frequency of the selected reference. This frequency measurement has a resolution of
0.0003068p pm over a ±8 0ppm range. The v alue re ad f rom the FREQ f ield is the DPLL’s inte gral pat h val ue, whic h
is an averaged measurement with an averaging time inversely proportional to DPLL bandwidth.
DPLL phase measurements can be read from the PHASE field spanning registers PHASE1 and PHASE2. This
field indicates the phase difference seen by the phase detector. This phase measurement has a resolution of
approximately 0.703 degrees and is internally averaged with a -3dB attenuation point of approximately 100Hz.
Thus, for low DPLL bandwidths the PHASE field gives input phase wander in the frequency band from the DPLL
corner frequency up to 100Hz. This information could be used by software to compute a crude MTIE measurement.
7.7.7
Input Ji tter T olerance
The device is compliant with the jitter tolerance requirem ents of the standards listed in Table 1-1. W hen using the
±360°/±180° PFD, jitter c an be tolerat ed up to the po int of e ye closure. Eith er LO CK8K m ode ( see Sectio n 7.4.2.2)
or the multicycle phase detector (see Section 7.7.4) should be used for high jitter tolerance.
7.7.8
Jitter T ransfer
The transfer of jitter from the selected reference to the output clock s has a programmable transfer function that is
determined by the DPLL bandwidth. (See Section 7.7.2.) In the T0 DPLL, the 3dB corner frequency of the jitter
transfer function can be set to any of 7 positions from 18Hz to 400Hz.
7.7.9
Output Jit ter and W an der
Several factors contribute to jitter and wander on the output clocks, including:
Jitter and wander amplitude on the selected reference (while in the locked state)
The jitter transfer characteristic of the device (while in the locked state)
The jitter and wander on the local oscillator clock signal (especially wander while in the holdover state)
The DPLL in the d evice ha s progr amm able bandwi dth (s ee Section 7.7.2) . W ith respect to j itter, the DPLL b ehaves
as a lowpass filter with a programmable pole. The bandwidth of the DPLL is low enough to strongly attenuate jitter
7.8
Output Clock Configuration
A total of four output clock pins, OC3, OC6, FSYNC, and MFSYNC, are available on the device. Output clocks OC3
and OC6 are individually configurable for a variety of frequencies. Output clocks FSYNC and MFSYNC are more
specialized, serving as an 8kHz fram e sync (FSYNC) and a 2k Hz m ultiframe syn c (MFSYNC). Table 7-5 provides
more detail on the capabilities of the output clock pins.
Table 7-5. Output Clock Capabilities
OUTPUT
CLOCK
SIGNAL
FORMAT
FREQU EN C IE S SUP PO RT ED
OC3 CMOS/TTL Frequency selection per Section 7.8.2.3 and Table 7-6 to Table 7-12.
OC6 LVDS/LVPECL
FSYNC
CMOS/TTL
8kHz frame sync with programmable pulse width and polarity.
MFSYNC
2kHz multif rame sync with program mable pulse width and pol ar ity.
DS3106
26
7.8.1
Sign al Format Con figuration
Output cl ock OC6 is an LVD S-compatible, LVPECL leve l-c om patible outputs. The t ype of outp ut can be s e le c ted or
the output can be disabled us ing th e OC6SF conf igura tion b its in t he MCR8 register . The LVPECL lev el-compatible
mode generates a differential signal that is large enough for most LVPECL receivers. Some LVPECL receivers
have a limited common-mode signal range that can be accommodated for by using an AC-coupled signal. The
LVDS elec trica l spec ificatio ns are l isted in Table 10-4, and the r ecommended LVDS term inat ion is show n in Figure
10-1. The LVPECL level-compatible electrical specifications are listed in Table 10-5, and the recommended
LVPECL r eceiver ter minati on is sho wn in Figure 10-2. T hese differ ential outp uts can be easil y interfac ed to LVDS,
LVPECL, and CM L inputs on neighboring ICs using a few external passive components. See App Note HFAN-1.0
for details.
Output clocks OC3, FSYNC, and MFSYNC are CMOS/TTL signal format.
7.8.2
Frequency C onfi gurati on
The f requenc y of outpu t clo cks OC3 and O C6 is a f unction of the se ttings used t o configur e the c om ponents of the
T0 PLL paths. These components are shown in the detailed block diagram of Figure 7-1.
The DS310 6 uses digita l frequenc y synthes is (DFS) to gen erate various clock s. In DFS a high-sp eed mas ter clock
(204.8MHz) is divided down to the desired output frequency by adding a number to an accumulator. The DFS
output is a c oding of the cl ock output phase that is us ed b y a special c ircuit t o de term ine where to put t he edges of
the output clock between the clock edges of the master clock. The edges of the output clock, however, are not
ideally located in time, resulting in jitter with an amplitude typically less than 1ns pk-pk.
7.8.2.1
T0 DPLL and Feedb ack DFS D etail s
See Figure 7-1. The T0 forward-DFS block uses the 204.8MHz master clock and DFS technology to synthesize
internal clocks from which the output and feedback clocks are derived.
The f eedback DFS bloc k synthes izes the ap propriate locking freque ncies for use by the phase-f requency detector
(PFD). See Section 7.4.2.
7.8.2.2
Output DFS and APL L Detai ls
See Figure 7-1. The output clock frequencies are determined by two 2kHz/8kHz DFS blocks, two DIG12 DFS
blocks , and three APLL DF S block s. T he T0 APLL, th e T0 APLL 2, and th e T4 A PLL (and th eir out put divid ers) get
their freque ncy referenc es f rom three as s ociated A PL L DF S b locks. All the output DF S bloc ks are c onnec ted to the
T0 DPLL.
The 2K8K DFS and FSYNC DFS blocks generate both 2k Hz and 8k Hz signals, which have about 1 ns pk-pk jitter.
The FSYNC ( 8kHz) and MFSYNC (2 k Hz) sig nals com e fr om the FSYN C DFS block . The 2k Hz and 8 kHz signals
that can be output on OC3 or OC6 always come from the 2K8K DFS.
The DIG 1 DFS c an ge nerat e an N x DS 1 or N x E1 s ig nal with abo ut 1ns pk -pk jitter. T he DIG2 DFS c an gen erat e
an N x DS1, N x E1, 6.312 MHz, 10MH z, or N x 19.44MH z clock with approx imat ely 1ns pk -pk jitter. The frequenc y
of the DIG1 c loc k is c onf igured b y the DIG 1S S bit in MCR6 and the DIG 1F[1 :0] field in MCR7. T he frequenc y of the
DIG2 clock is configured by the DIG2AF and DIG2SS bits in MCR6 and the DIG2F[1:0] field in MCR7. DIG1 and
DIG2 can be independently configured for any of the frequencies shown in Table 7-6 and Table 7-7, respectively.
The APLL DFS blocks and their associated output APLLs and output dividers can generate many different
frequencies. The T0 APLL frequencies that can be generated are listed in Table 7-9. The T0 APLL2 frequency is
always 312.500MHz. The T4 APLL frequencies that can be generated are listed in Table 7-11. The output
frequencies that can be generated from the APLL circuits are listed in Table 7-8.
DS3106
27
7.8.2.3
OC3 and OC6 C onfigurati on
The following is a step-by-step procedure for configuring the frequencies of output clocks OC3 and OC6:
Use Table 7-8 to select a set of output frequencies for each APLL, T0 and T4. Each APLL can only
generate one set of output frequencies. (In SONET/SDH equipment, the T0 APLL is typically
configured for a frequency of 311.04MHz to get N x 19.44MHz output clocks to for use on line cards.)
Determ ine from Table 7-8 the T 0 and T4 APLL frequenc ies required for the frequency sets chos en in step
2.
Configure the T0FREQ field in register T0CR1 as shown in Table 7-9 for the T0 APLL frequency
determ ined in st ep 3. C onf igure fie lds T4CR1:T4FREQ, T0CR1:T4APT 0, and T0CR1:T0FT 4 as shown
in Table 7-11 for the T4 APLL frequency determined in step 3.
Using Table 7-8 and Table 7-12, c onfigure t he frequen cies of out put clock s OC3 and OC6 in the OFREQ n
fields of registers OCR2 and OCR4 and the AOF n bits in the OCR5 register.
Table 7-13 lists all standard frequencies for the output clocks and specifies how to configure the T0 APLL and/or
the T4 APLL to obtain each frequency. Table 7-13 also indicates the expected jitter amplitude for each frequency.
Table 7-6. Digita l1 Frequencies
DIG1F[1:0]
SETTING IN
MCR7
DIG1SS
SETTING IN
MCR6
FREQUENCY
(MHz)
JITTER
(pk-pk, ns,
typ)
00
0
2.048
< 1
01
0
4.096
< 1
10
0
8.192
< 1
11
0
16.384
< 1
00
1
1.544
< 1
01
1
3.088
< 1
10
1
6.176
< 1
11
1
12.352
< 1
Table 7-7. Digital2 Frequencies
DIG2AF
SETTING
IN MCR6
DIG2F[1:0]
SETTING
IN MCR7
DIG2SS
SETTING
IN MCR6
FREQUENCY
(MHz)
JITTER
(pk-pk,
ns, typ)
1
00
0
6.312
< 1
1
10
0
10.000
<1
1
00
1
19.440
< 1
1
01
1
38.880
< 1
0
00
0
2.048
< 1
0
01
0
4.096
< 1
0
10
0
8.192
< 1
0
11
0
16.384
< 1
0
00
1
1.544
< 1
0
01
1
3.088
< 1
0
10
1
6.176
< 1
0
11
1
12.352
< 1
DS3106
28
Table 7-8. APLL Frequency to Output Freque ncies (T0 APLL and T4 APLL)
APLL
FREQUENCY
APLL/
2
APLL/
4
APLL/
5
APLL/
6
APLL/
8
APLL/
10
APLL/
12
APLL/
16
APLL/
20
APLL/
48
APLL/
64
312.5
156.25
—
62.5
—
—
31.25
—
—
—
—
—
311.04
155.52
77.76
62.208
51.84
38.88
31.104
25.92
19.44
15.552
6.48
4.86
274.944
137.472
68.376
—
45.824
34.368
—
22.912
17.184
—
5.728
4.296
250
125
62.5
50
—
31.25
25
—
—
12.5
—
—
178.944
89.472
44.736
—
29.824
22.368
—
14.912
11.184
—
3.728
2.796
160
80
40
32
—
20
16
—
10
8
—
2.5
148.224
74.112
37.056
—
24.704
18.528
—
12.352
9.264
—
3.088
2.316
131.072
65.536
32.768
—
—
16.384
—
—
8.192
—
—
2.048
122.88
61.44
30.72
24.576
20.48
15.36
12.288
10.24
7.68
6.144
2.56
1.92
104
52
26
20.8
—
13
10.4
—
6.5
5.2
—
—
100.992
50.496
25.248
—
16.832
12.624
—
8.416
6.312
—
2.104
1.578
98.816
49.408
24.704
—
—
12.352
—
—
6.176
—
—
1.544
98.304
49.152
24.576
—
16.384
12.288
—
8.192
6.144
—
2.048
1.536
Note: All frequenc i es i n MHz. Common telecom, datacom, and synchroni zation frequenc i es are in bold type.
Table 7-9. T0 AP LL Fr equency Configuration
T0 APLL
FREQUENCY (MHz)
T0 APLL DFS
FREQUENCY (MHz)
T0 APLL
FREQUENCY MODE
T0FREQ[2:0] SETTING
IN T0CR1
OUTPUT JITTER
(pk-pk, ns, typ)
311.04
77.76
77.76MHz
000
< 0.5
311.04
77.76
77.76MHz
001
< 0.5
98.304
24.576
12 x E1
010
< 0.5
131.072
32.768
16 x E1
011
< 0.5
148.224
37.056
24 x DS1
100
< 0.5
98.816
24.704
16 x DS1
101
< 0.5
100.992
25.248
4 x 6312kHz
110
< 0.5
250.000
62.500
GbE ÷ 16
111
< 0.5
Table 7-10. T0 APLL2 Fr equency Configuration
T0 APLL2
FREQUENCY (MHz)
T0 APLL2 DFS
FREQUENCY(MHz)
OUTPUT JITTER
(pk-pk, ns, typ)
312.500 62.500 < 0.5
DS3106
29
Table 7-11. T4 APLL Frequency Configuration
T4 APLL
FREQUENCY
(MHz)
T4 APLL DFS
FREQUENCY
(MHz)
T4 APLL
FREQUENCY
MODE
T4APT0
SETTING IN
T0CR1
T4FREQ[3:0]
SETTING IN
T4CR1
T0FT4[2:0]
SETTING IN
T0CR1
OUTPUT
JITTER
(pk-pk, ns, typ)
Disabled
77.76
Squelched
0
0000
XXX
< 0.5
311.04
77.76
77.76MHz
0
0001
XXX
< 0.5
98.304
24.576
12 x E1
0
0010
XXX
< 0.5
131.072
32.768
16 x E1
0
0011
XXX
< 0.5
148.224
37.056
24 x DS1
0
0100
XXX
< 0.5
98.816
24.704
16 x DS1
0
0101
XXX
< 0.5
274.944
68.736
2 x E3
0
0110
XXX
< 0.5
178.944
44.736
DS3
0
0111
XXX
< 0.5
100.992
25.248
4 x 6312kHz
0
1000
XXX
< 0.5
250.000
62.500
GbE ÷ 16
0
1001
XXX
< 0.5
122.880
30.720
3 x 10.24
0
1010
XXX
< 0.5
160.000
40.000
4 x 10
0
1011
XXX
< 0.5
104.000
26.000
2 x 13
0
1100
XXX
< 0.5
98.304
24.576
T0 12 x E1
1
XXXX
000
< 0.5
250.000
62.500
T0 GbE ÷ 16
1
XXXX
001
< 0.5
131.072
32.768
T0 16 x E1
1
XXXX
010
< 0.5
148.224
37.056
T0 24 x DS1
1
XXXX
100
< 0.5
98.816
24.704
T0 16 x DS1
1
XXXX
110
< 0.5
100.992
25.248
T0 4 x 6312kHz
1
XXXX
111
< 0.5
Table 7-12. OC3 and OC6 Output Frequency Selection
AOF BIT OFREQ(1)
FREQUENCY
OC3
OC6
0
0000
Disabled
Disabled
0
0001
2kHz
2kHz
0
0010
8kHz
8kHz
0
0011
Digital2
T0 / 2
0
0100
Digital1
Digital1
0
0101
T0 / 48
T0 / 1
0
0110
T0 / 16
T0 / 16
0
0111
T0 / 12
T0 / 12
0
1000
T0 / 8
T0 / 8
0
1001
T0 / 6
T0 / 6
0
1010
T0 / 4
T0 / 4
0
1011
T4 / 64
T4 / 64
0
1100
T4 / 48
T4 / 48
0
1101
T4 / 16
T4 / 16
0
1110
T4 / 8
T4 / 8
0
1111
T4 / 4
T4 / 4
1
0000
Disabled
Disabled
1
0001
T0 / 64
T4 / 5
1
0010
T4 / 20
T4 / 2
1
0011
T4 / 12
T4 / 1
1
0100
T4 / 10
T02 / 5
1
0101
T4 / 5
T02 / 2
1
0110
T4 / 2
T02 / 1
Note 1: The value of the OFREQn field (in the OCR2 and OCR3 registers) c orresponding t o output clock OCn.
DS3106
30
Table 7-13. Standard Frequencies for Pr ogramm able Outputs
FREQUENCY (MHz)
T0 APLL T4 APLL
OFREQn
JITTER
(TYP)
T0FREQ T4FT0 T4FREQ RMS
(ps) pk-pk
(ns)
2kHz
2kHz
100
1.00
8kHz
8kHz
100
1.00
1.536
Not OC6 from T0 APLL
12 x E1
12 x E1
12 x E1
APLL/64
100
1.00
1.544
Not OC6 from DIG2
DIG1, DIG2
100
1.00
1.544
Not OC6 from T0 APLL
16 x DS1
16 x DS1
16 x DS1
APLL/64
75
0.75
1.578
Not OC6 from T0 APLL
4 x 6.312
4 x 6.312
4 x 6.312
APLL/64
60
0.60
2.048
Not OC6 from DIG2
DIG1, DIG2
100
1.00
2.048
Not OC6 from T0 APLL
12 x E1
12 x E1
12 x E1
APLL/48
100
1.00
2.048
Not OC6 from T0 APLL
16 x E1
16 x E1
16 x E1
APLL/64
70
0.70
2.104
Not OC6 from T0 APLL
4 x 6.312
4 x 6.312
4 x 6.312
APLL/48
60
0.60
2.316
Not OC6 from T0 APLL
24 x DS1
24 x DS1
24 x DS1
APLL/64
60
0.60
2.500
4 x 10
APLL/64
80
0.80
2.560
3 x 10.24
APLL/48
90
0.90
2.796
DS3
APLL/64
50
0.50
3.088
Not OC6 from DIG2
DIG1, DIG2
100
1.00
3.088
Not OC6 from T0 APLL
24 x DS1
24 x DS1
24 x DS1
APLL/48
60
0.60
3.728
DS3
APLL/48
50
0.50
4.096
Not OC6 from DIG2
DIG1, DIG2
100
1.00
4.296
2 x E3
APLL/64
70
0.70
4.860
Not OC6 from T0 APLL
77.76
77.76
APLL/64
50
0.50
5.200
OC3 only
2 x 13
APLL/20
90
0.90
5.728
2 x E3
APLL/48
70
0.70
6.144
OC3 only
3 x 10.24
APLL/20
90
0.90
6.144
12 x E1
12 x E1
12 x E1
APLL/16
100
1.00
6.176
Not OC6 from DIG2
DIG1, DIG2
100
1.00
6.176
16 x DS1
16 x DS1
16 x DS1
APLL/16
75
075
6.312
OC3 only
DIG2
100
1.00
6.312
4 x 6.312
4 x 6.312
4 x 6.312
APLL/16
60
0.60
6.480
Not OC6 from T0 APLL
77.76
77.76
APLL/48
60
0.6
8.000
OC3 only
4 x 10
APLL/20
80
0.80
8.192
Not OC6 from DIG2
DIG1, DIG2
100
1.00
8.192
12 x E1
APLL/12
100
1.00
8.192
16 x E1
16 x E1
16 x E1
APLL/16
70
0.70
8.416
4 x 6.312
APLL/12
60
0.60
9.264
24 x DS1
24 x DS1
24 x DS1
APLL/16
60
0.60
10.000
Not OC6
DIG2
100
1.00
10.000
4 x 10
APLL/16
80
0.80
10.240
OC3 only
3 x 10.24
APLL/12
90
0.90
10.400
OC3 only
3 x 10.24
APLL/10
90
0.90
11.184
DS3
APLL/16
50
0.50
12.288
12 x E1
12 x E1
12 x E1
APLL/8
100
1.00
12.288
OC3 only
2 x 13
APLL/10
90
0.90
12.352
24 x DS1
APLL/12
60
0.60
12.352
16 x DS1
16 x DS1
16 x DS1
APLL/8
75
0.75
12.352
Not OC6 from DIG2
DIG1, DIG2
100
1.00
12.500
OC3 only
GbE ÷ 16
GbE ÷ 16
APLL/20
60
0.60
12.624
4 x 6.312
4 x 6.312
4 x 6.312
APLL/8
60
0.60
13.000
2 x 13
APLL/8
90
0.90
15.360
3 x 10.24
APLL/8
90
0.90
15.552
OC3 only
77.76
APLL/20
50
0.50
16.000
OC3 only
4 x 10
APLL/10
80
0.80
16.384
Not OC6 from DIG2
DIG1, DIG2
100
1.00
16.384
12 x E1
APLL/6
100
1.00
DS3106
31
FREQUENCY (MHz)
T0 APLL T4 APLL
OFREQn
JITTER
(TYP)
T0FREQ T4FT0 T4FREQ RMS
(ps) pk-pk
(ns)
16.384
16 x E1
16 x E1
16 x E1
APLL/8
70
0.70
16.832
4 x 6.312
APLL/6
60
0.60
17.184
2 x E3
APLL/16
70
0.70
18.528
24 x DS1
24 x DS1
24 x DS1
APLL/8
60
0.60
19.440
OC3 only
DIG2
100
1.00
19.440
77.76
77.76
APLL/16
50
0.50
20.000
4 x 10
APLL/8
80
0.80
20.800
2 x 13
APLL/5
90
0.90
22.368
DS3
APLL/8
50
0.50
24.576
12 x E1
12 x E1
12 x E1
APLL/4
100
1.00
24.576
3 x 10.24
APLL/5
90
0.90
24.704
24 x DS1
APLL/6
60
0.60
24.704
16 x DS1
16 x DS1
16 x DS1
APLL/4
75
0.75
25.000
OC3 only
GbE ÷ 16
GbE ÷ 16
APLL/10
60
0.60
25.248
4 x 6.312
4 x 6.312
4 x 6.312
APLL/4
60
0.60
25.920
77.76
APLL/12
50
0.50
26.000
2 x 13
APLL/4
90
0.90
30.720
3 x 10.24
APLL/4
90
0.90
31.104
OC3 only
77.76
APLL/10
50
0.50
31.250
GbE ÷ 16
GbE ÷ 16
GbE ÷ 16
APLL/8
60
0.60
31.250
APLL/10
60
0.60
32.000
4 x 10
APLL/5
80
0.80
32.768
16 x E1
16 x E1
16 x E1
APLL/4
70
0.70
34.368
2 x E3
APLL/8
70
0.70
37.056
24 x DS1
24 x DS1
24 x DS1
APLL/4
60
0.60
38.880
77.76
77.76
APLL/8
50
0.50
40.000
4 x 10
APLL/4
80
0.80
44.736
DS3
APLL/4
50
0.50
49.152
Not OC3 from T0 APLL
12 x E1
12 x E1
12 x E1
APLL/2
100
1.00
49.408
Not OC3 from T0 APLL
16 x DS1
16 x DS1
16 x DS1
APLL/2
75
0.75
50.000
GbE ÷ 16
GbE ÷ 16
APLL/5
60
0.60
50.496
Not OC3 from T0 APLL
4 x 6.312
4 x 6.312
4 x 6.312
APLL/2
60
0.60
51.840
77.76
APLL/6
50
0.50
52.000
2 x 13
APLL/2
90
0.90
61.440
3 x 10.24
APLL/2
90
0.90
62.208
77.76
APLL/5
50
0.50
62.500
GbE ÷ 16
GbE ÷ 16
GbE ÷ 16
APLL/4
60
0.60
62.500
OC6 only from T0 APLL2
APLL/5
60
0.60
65.536
Not OC3 from T0 APLL
16 x E1
16 x E1
16 x E1
APLL/2
70
0.70
68.736
2 x E3
APLL/4
70
0.70
74.112
Not OC3 from T0 APLL
24 x DS1
24 x DS1
24 x DS1
APLL/2
60
0.60
77.76
77.76
77.76
APLL/4
50
0.50
80.000
4 x 10
APLL/2
80
0.80
89.472
DS3
APLL/2
50
0.50
98.304
OC6 only
12 x E1
12 x E1
12 x E1
APLL/1
100
1.00
98.816
OC6 only
16 x DS1
16 x DS1
16 x DS1
APLL/1
75
0.75
100.992
OC6 only
4 x 6312 kHz
4 x 6312 kHz
4 x 6312 kHz
APLL/1
60
0.60
104.000
OC6 only
2 x 13
APLL/1
90
0.90
122.880
OC6 only
3 x 10.24
APLL/1
90
0.90
125.000
Not OC3 from T0 APLL
GbE ÷ 16
GbE ÷ 16
GbE ÷ 16
APLL/2
60
0.60
131.072
OC6 only
16 x E1
16 x E1
16 x E1
APLL/1
70
0.70
137.472
OC6 only
2 x E3
APLL/2
70
0.70
148.224
OC6 only
24 x DS1
24 x DS1
24 x DS1
APLL/1
60
0.60
155.520
Not OC3 from T0 APLL
77.76
77.76
APLL/2
50
0.50
156.250
OC6 only from T0 APLL2
APLL/2
60
0.60
160.000
OC6 only
4 x 10
APLL/1
80
0.80
DS3106
32
FREQUENCY (MHz)
T0 APLL T4 APLL
OFREQn
JITTER
(TYP)
T0FREQ T4FT0 T4FREQ RMS
(ps) pk-pk
(ns)
178.944
OC6 only
DS3
APLL/1
50
0.50
250.000
OC6 only
GbE ÷ 16
APLL/1
60
0.60
274.944
OC6 only
70
0.70
311.040
OC6 only
77.76
APLL/1
50
0.50
312.500
OC6 only from T0 APLL2
APLL/2
60
0.60
7.8.2.4
OC3 and OC6 D efault Frequency Select Pins
There ar e two s ets of f r equenc y se lect pi ns , O 3F[2: 0] and O6F[ 2:0], t hat c o ntr ol t he res et d efault freque nc ie s of the
OC3 and OC6 output clock pins, respectively. The SONSDH pin also selects the output frequencies for some of the
pin settings. There is also an interaction between O3F[2:0] and O6F[2:0] when O6F[2:0] uses some internal
resourc e that is needed to generate certa in f r eque ncie s . Af ter res et the O 3F[2:0] and O6F [ 2:0] p ins c an be u sed as
GPIO pins an d s tatus out p ut pins. The default o utp ut frequenc ies are af f ec ted b y chang ing th e regis t er bit v al ues of
four registers: OCR2, OCR3, T0CR1, and T4CR1. The register defaults can be changed after reset using the
microprocessor interface.
Table 7-14. T0FREQ Defa u lt Setting s
O6F[2:0]
O3F[2:0]
SONSDH
T0CR1.T0FREQ
=001 =001
0
010
12 x E1 DFB
1
100
24 x DS1 DFB
!=001
X
X
001
77.76 AFB
X
!=001
X
001
77.76 AFB
Table 7-15. T4FREQ Defa u lt Setting s
O6F[2:0]
O3F[2:0]
SONSDH
T4CR1.T4FREQ
=001 X
0
0110
E3
1
0111
DS3
X =010
0
0110
E3
1
0111
DS3
!=001 !=010
0
0011
16 x E1
1
0101
16 x DS1
Table 7-16. OC6 Default Frequency Configuration
O6F[2:0] SONSDH FREQUENCY
(MHz) OCR3.
OFREQ6 APLL
SRC
000
X
0
0000
—
001
0
68.736
1111
T4
1
22.368
1110
T4
010
X
19.44
0110
T0
011
X
25.92
0111
T0
100*
X
38.88
1000
T0
101
X
51.84
1001
T0
110
X
77.76
1010
T0
111
X
155.52
0011
T0
*Occurs when O6F[2:0] are left unconnected.
DS3106
33
Table 7-17. OC3 Default Frequency Configuration
O3F[2:0] SONSDH FREQUENCY
(MHz) O6F[2:0]
=001 OCR2.
OFREQ3 APLL
SRC
000
X
0
X
0000
—
001
0
8.192
FALSE
1101
T4
1
6.176
1101
T4
001
001
0
8.192
TRUE
0111
T0
1
12.352
0111
T0
010
0
68.736
X
1111
T4
010
1
22.368
X
1110
T4
011*
X
19.44
X
0110
T0
100
X
25.92
X
0111
T0
101
X
38.88
X
1000
T0
110
X
51.84
X
1001
T0
111
X
77.76
X
1010
T0
*Occurs when O3F[2:0] are left unconnected.
7.8.2.5
FSYNC and MF S YNC Config ur ation
The FSYNC out put is enabled b y setting F SEN = 1 in the OCR4 reg ister, while the MF SYNC output is ena bled by
setting MFSEN = 1 in OCR4. When disabled, these pins are driven low.
When 8KPUL = 0 in FSCR1, FSYNC is configured as an 8kHz clock with 50% duty cycle. When 8KPUL = 1,
FSYNC is an 8kHz frame sync that pulses low once every 125µs with pulse width equal to one cycle of output
clock OC3. When 8KINV = 1 in FSCR1, the clock or pulse polarity of FSYNC is inverted.
When 2KPUL = 0 in FSCR1, MFSYNC is configured as an 2kHz clock with 50% duty cycle. When 2KPUL = 1,
MFSYNC is a 2kHz frame sync that pulses low once every 500µs with pulse width equal to one cycle of output
clock OC3. When 2KINV = 1 in FSCR1, the clock or pulse polarity f MFSYNC is inverted.
If either 8K PUL = 1 or 2 KP UL = 1, outp ut clock O C3 m ust be generated f rom the T 0 DPLL and m ust be configur ed
for a f requency of 1.544M Hz or higher or th e FSYNC/MFSYN C pulses m ay not be generat ed correctl y. Figure 7-3
shows how the 8KPUL and 8KINV control bits affect the FSYNC output. The 2KPUL and 2KINV bits have an
identical effect on MFSYNC.
Figure 7-3. FSYNC 8kHz Options
OC3 OUTPUT CLOCK
FSYNC, 8KPUL=0, 8KINV=0
FSYNC, 8KPUL=0, 8KINV=1
FSYNC, 8KPUL=1, 8KINV=0
FSYNC, 8KPUL=1, 8KINV=1
DS3106
34
7.8.2.6
Custom Output Frequencies
In addition to the many standard frequencies available in the device, any of the seven output DFS blocks can be
configured to generate a custom frequency. Possible custom frequencies include any multiple of 2kHz up to
77.76MH z, an y multiple of 8kH z up to 311.04MH z, an d any multip le of 10kHz up to 388. 79MH z. (An APLL m ust be
used to achieve frequencies above 77.76MHz.) Any of the programmable output clocks can be configured to output
the custom frequency or submultiples thereof. Contact Microsemi timing products technical support for help with
custom frequencies.
7.9
Microprocessor Interface
The DS3106 presents an SPI interface on the CS, SCLK, SDI, and SDO pins. SPI is a widely used master/slave
bus protocol that allows a master device and one or more slave devices to communicate over a serial bus. The
DS3106 is always a slave device. Masters are typically microprocessors, ASICs, or FPGAs. Data transfers are
always initiated b y th e master devic e, which als o generates the SCLK sign al. The DS3106 receives s erial data on
the SDI pin and transmits serial data on the SDO pin. SDO is high impedance except when the DS3106 is
transmitting data to the bus master.
Bit Ord er. W hen both bit 3 and bit 4 are low at de vice address 3FF Fh, the register addres s and all data b ytes ar e
transmitted MSB first on both SDI and SDO. When either bit 3 or bit 4 is set to 1 at device address 3FFFh, the
register address and all data bytes are transmitted LSB first on both SDI and SDO. The reset default setting and
Motorola SPI convention is MSB first.
Clock Polar it y and Phase . SCL K is nor m ally low and pulses h igh duri ng bus tra nsactions . The C PHA pi n sets the
phase (active edge) of SCLK. When CPHA = 0, data is latched in on SDI on the leading edge of the SCLK pulse
and updated on SDO on the trailing edge. When CPHA = 1, data is latched in on SDI on the trailing edge of the
SCLK puls e an d up dat ed o n SDO on the f ol lo wing le a din g ed ge. SCL K do es not hav e to t ogg le b et ween ac cesses ,
i.e., when CS is high. See Figure 7-4.
Device Selection. Each SPI device has its own chip-select line. To select the DS3106, pull its CS pin lo w.
Control Word. After CS is pulled low, the bus m aster transmits the contr ol word dur ing the f irst 16 SCLK c ycles. In
MSB-first mode the control word has the form:
R/W A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BURST
where A[1 3:0] is the reg iste r addres s, R/W is the d ata direc tion bit (1 = read , 0 = wri te), a nd BUR ST is the b urst bit
(1 = burst access, 0 = single-byte access). In LSB-first mode the order of the 14 address bits is reversed. In the
discussion that follows, a c ontrol word with R/W = 1 is a read control word, while a control word with R/W = 0 is a
write control word.
Single-Byte Writes. See Figure 7-5. After CS goes low, the bus master transmits a write control word with
BURST = 0, followed by th e data byte to be wr itten. The bus m aster then term inates the transac tion by pull ing CS
high.
Single-Byte Reads. See Figure 7-5. After CS goes low, the bus master transmits a read control word with
BURST = 0. The DS3106 then responds with the requested data byte. The bus master then terminates the
transaction by pulling CS high.
Burst Writes. See Figure 7-5. After CS goes low, the bus master transmits a write control word with BURST = 1
followed by the first data byte to be written. The DS3106 receives the first data byte on SDI, writes it to the
specif ied register , increm ents its interna l address r egister , and prep ares to rec eive the next data b yte. If the m aster
continues t o trans mit, the DS3106 c o nti nues t o write the data rec e iv ed and i ncr em ent its ad dres s c ount er. Af ter the
address counter reaches 3FFFh it rolls over to address 0000h and continues to increment.
Burst Reads. See Figure 7-5. After CS goes low, the bus master transmits a read control word with BURST = 1.
The DS310 6 then respond s with the reques ted data byte o n SDO, increm ents its address c ounter, and pref etches
DS3106
35
the next data byte. If the bu s m aster c ontinues to d emand data, t he D S31 06 c ont i nues to provide the da ta on SDO,
increment its address counter, and prefetch the following byte. After the address counter reaches 3FFFh, it rolls
over to address 0000h and continues to increment.
Early Termination of Bus Transactions. The bus master can terminate SPI bus transactions at any time by
pulling CS high. In response to ear ly term inations, the DS3106 resets its SPI inte rface logic and waits for the start
of the next transaction. If a write transaction is terminated prior to the SCLK edge that latches the LSB of a data
byte, the data byte is not written.
Design Option: Wiring SDI and SDO Together. Because communication between the bus master and the
DS3106 is half-duplex, the SDI and SDO pins can be wired together externally to reduce wire count. To support
this option, the bus master must not drive the SDI/SDO line when the DS3106 is transmitting.
AC Timing. See Table 10-9 and Figure 10-3 for AC timing specifications for the SPI interface.
DS3106
36
Figure 7-4. SPI Clock Phase Options
CS
MSB
LSB
6
5
4
3
2
1
SDI/SDO
CLOCK EDGE USED FOR DATA CAPTURE (ALL MODES)
CPHA = 0
CPHA = 1
SCLK
SCLK
Figure 7-5. SPI Bus Transactions
R/WRegist er A ddress Burst Data B yt e
SDI
CS
SDO
Single-Byte Write
Single-Byte Read
R/WRegist er A ddress Burst
Data Byte
R/WRegist er A ddress Burst Data B yt e 1
Burst Write
SDI
CS
SDO
SDI
CS
SDO
0 (Write) 0 (single-byte)
1 (Read) 0 (single-byte)
0 (Write) 1 (burst)
Data Byte N
R/WRegist er A ddress Burst
Data Byte 1
Burst Read
SDI
CS
1 (Read) 1 (burst)
Data Byte N
DS3106
37
7.10
Reset Logi c
The device has three reset controls: the RST pin, the RST bit in MCR1, and the JTAG reset pin JTRST. The RST
pin asynchronously resets the entire device, except for the JTAG logic. When the RST pin is low all internal
registers are r ese t to the ir def ault va lu es , inc lud in g th os e f ields t hat latch the ir de f ault v alues f r om , or based on, t h e
states of configuration input pins when the RST goes high. The
RST
pin must be asserted once after power-up
while the external oscillator is stabilizing.
The MCR1:RST bit resets the entire dev ice (except for the microproc essor interface, the JT AG logic, and the RST
bit itse lf ), but w he n R ST is ac tive, t he reg is ter f ields wi th p in-pr o gram med def aults do not l atch their v al ues from , or
based on, th e c or res po nd in g i npu t p ins. Inst ea d, thes e f ields are rese t to the default va lues that wer e latch ed when
the RST pin was last active.
Microsemi recommends holding RST low while the external oscillator starts up and stabilizes. An incorrect reset
condition could result if RST is released before the oscillator has started up completely.
Important: System software must wait at least 100µs after reset (RST pin or RST bit) is deasserted before
initializing the device as described in Section 7.12.
7.11
Power-Supply Considerations
Due to the DS3106’s dual-power-supply nature, some I/Os have parasitic diodes between a 1.8V supply and a
3.3V supp ly. W hen ramping po wer suppli es up or do wn, care m ust be tak en to avoid f orward-bias ing thes e diodes
because it could c ause latc hup. T wo methods are avai lable to pr event th is. The f irst m ethod is to p lace a Sc hottk y
diode ex ternal to t he de v ice b et we en the 1. 8V s upp l y and t he 3. 3V suppl y to for c e th e 3 .3 V s up ply to be within on e
parasitic diode drop below the 1.8V supply (i.e., VDDIO > VDD - ~0.4V). The second m ethod is to ram p up the 3.3V
supply first and then ramp up the 1.8V supply.
7.12
Initialization
After power-up or reset, a series of writes must be done to the DS3106 to tune it for optimal performance. This
series of writes is c alled th e initiali zatio n s c ript. Eac h D S31 06 d ie rev is ion has a di ff er ent initia li za tion s c ript. F or the
latest initialization scripts contact Microsemi timing products technical support.
Important: System software must wait at least 100µs after reset (RST pin or RST bit) is deasserted before
initializi ng the de vice .
DS3106
38
8.
Register Descriptions
The DS3 106 has an overa ll ad dress r ange f rom 000h t o 1FFh . Table 8-1 i n Section 8.4 shows the register map. In
each register, bit 7 is the MSB and bit 0 is the LSB. Register addresses not listed and bits marked “—“ are reserved
and must be written with 0. Writing other values to these registers may put the device in a factory test mode
resulting in undefined operation. Bits labeled “0” or “1” must be written with that value for proper operation. Register
fields with underlined names are read-only fields; writes to these fields have no effect. All other fields are read-
write. Register fields are described in detail in the register descriptions that follow Table 8-1.
Note: Systems must be able to access the entire address range from 0 to 01FFh. Proper device initialization
requires a sequence of writes to addresses in the range 0180-01FFh.
8.1
Status Bits
The device has two types of status bits. Rea l-time s tatus bits are read-on ly and indicate th e state of a s ignal at the
time it is read. Latched status bits are set when a signal changes state (low-to-high, high-to-low, or both, depending
on the bit) and c leared whe n written with a l ogic 1 va lue. W riting a 0 h as no ef fect. W hen set, som e latched s tatus
bits can cause an interrupt request on the INTREQ pin if enabled to do so by corresponding interrupt enable bits.
ISR#.LOCK # are specia l-case latched st atus bits bec ause they cann ot create an interrupt reques t on the IN TREQ
pin and a “write 0” is needed to clear them.
8.2
Confi gur ati on Fields
Configuration fields are read-write. During reset, each configuration field reverts to the default value shown in the
register definition. Configuration register bits marked “—” are reserved and must be written with 0.
8.3
Multir egister Fields
Multiregister fields—such as FREQ[18:0] in registers FREQ1, FREQ2, and FREQ3—must be handled carefully to
ensure that the bytes of the field remain consistent. A write access to a multiregister field is accomplished by
writing all the registers of the field in any order, with no other accesses to the device in between. If the write
sequence is inter rupted b y anot her acc ess, non e of the bytes ar e written and the MSR4:MRAA latc hed stat u s bit is
set to indicate the write was aborted. A read access from a multiregister field is accomplished by reading the
registers of the field in any order, with no other accesses to the device in between. When one register of a
multiregister field is read, the other register(s) in the field are frozen until after they are all read. If the read
sequence is interrupted by another access, the registers of the multibyte field are unfrozen and the MSR4:MRAA
bit is set to indicate the read was aborted. For best results, interrupt servicing should be disabled in the
microprocessor before a multiregister access and then enabled again after the access is complete. The
multiregister fields are:
FIELD
REGISTERS
ADDRESSES
TYPE
FREQ[18:0]
FREQ1, FREQ2, FREQ3
0Ch, 0Dh, 07h
Read Only
MCLKFREQ[15:0] MCLK1, MCLK2 3Ch, 3Dh Read/Write
HARDLIM[9:0]
DLIMIT1, DLIMIT2
41h, 42h
Read/Write
DIVN[15:0]
DIVN1, DIVN2
46h, 47h
Read/Write
PHASE[15:0]
PHASE1, PHASE2
77h, 78h
Read Only
DS3106
39
8.4
Regist er D efi nit ions
Table 8-1. Register Map
Note: Regist er names are hyperl i nks to register def i niti ons. Underlined fields are read-only.
ADDR
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
00h
ID1
ID[7:0]
01h
ID2
ID[15:8]
02h
REV
REV[7:0]
03h
TEST1
PALARM
D180
—
RA
0
8KPOL
0
0
05h
MSR1
—
—
—
—
IC4
IC3
—
—
06h
MSR2
STATE
SRFAIL
—
—
—
—
—
—
07h
FREQ3
—
—
—
—
—
FREQ[18:16]
09h
OPSTATE
—
—
T0SOFT
—
—
T0STATE[2:0]
0Ah
PTAB1
—
—
—
—
SELREF[3:0]
0Ch
FREQ1
FREQ[7:0]
0Dh
FREQ2
FREQ[15:8]
0Eh
VALSR1
—
—
—
—
IC4
IC3
—
—
11h
ISR2
—
—
ACT4
—
—
—
ACT3
—
17h
MSR4
—
HORDY
MRAA
—
—
—
—
—
22h
ICR3
DIVN
LOCK8K
—
—
FREQ[3:0]
23h
ICR4
DIVN
LOCK8K
—
—
FREQ[3:0]
32h
MCR1
RST
—
FREN
LOCKPIN
—
T0STATE[2:0]
34h
MCR3
—
—
XOEDGE
FRUNHO
—
SONSDH
—
—
38h
MCR6
DIG2AF
DIG2SS
DIG1SS
—
—
—
—
—
39h
MCR7
DIG2F[1:0]
DIG1F[1:0]
—
—
3Ah
MCR8
—
—
—
—
—
—
OC6SF[1:0]
3Bh
MCR9
AUTOBW
—
—
—
LIMINT
—
—
—
3Ch
MCLK1
MCLKFREQ[7:0]
3Dh
MCLK2
MCLKFREQ[15:8]
40h
HOCR3
AVG
—
—
—
—
—
—
—
41h
DLIMIT1
HARDLIM[7:0]
42h
DLIMIT2
—
—
—
—
—
—
HARDLIM[9:8]
43h
IER1
—
—
—
—
IC4
IC3
—
—
44h
IER2
STATE
SRFAIL
—
—
—
—
—
IC9
46h
DIVN1
DIVN[7:0]
47h
DIVN2
DIVN[15:8]
48h
MCR10
—
SRFPIN
—
—
—
—
—
—
4Dh
DLIMIT3
FLLOL
SOFTLIM[6:0]
4Eh
IER4
—
HORDY
—
—
—
—
—
—
4Fh
OCR5
—
—
AOF6
—
—
AOF3
—
—
50h
LB0U
LB0U[7:0]
51h
LB0L
LB0L[7:0]
52h
LB0S
LB0S[7:0]
53h
LB0D
—
—
—
—
—
—
LB0D[1:0]
61h
OCR2
—
—
—
—
OFREQ3[3:0]
62h
OCR3
OFREQ6[3:0]
—
—
—
—
63h
OCR4
MFSEN
FSEN
—
—
—
—
—
—
64h
T4CR1
—
—
—
—
T4FREQ[3:0]
DS3106
40
ADDR
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
65h
T0CR1
—
T4APT0
T0FT4[2:0]
T0FREQ[2:0]
67h
T0LBW
—
—
—
RSV1
RSV2
T0LBW[2:0]
69h
T0ABW
—
—
—
RSV1
RSV2
T0ABW[2:0]
6Bh
T0CR2
—
PD2G8K[2:0]
—
DAMP[2:0]
6Dh
T0CR3
PD2EN
—
—
—
—
PD2G[2:0]
6Eh
GPCR
GPIO4D
GPIO3D
GPIO2D
GPIO1D
GPIO4O
GPIO3O
GPIO2O
GPIO1O
6Fh
GPSR
—
—
—
—
GPIO4
GPIO3
GPIO2
GPIO1
73h
PHLIM1
FLEN
NALOL
1
—
—
FINELIM[2:0]
74h
PHLIM2
CLEN
MCPDEN
USEMCPD
—
COARSELIM[3:0]
76h
PHMON
NW
—
—
—
—
77h
PHASE1
PHASE[7:0]
78h
PHASE2
PHASE[15:8]
7Ah
FSCR1
—
—
—
—
8KINV
8KPUL
2KINV
2KPUL
7Dh
INTCR
—
—
—
—
LOS
GPO
OD
POL
7Eh
PROT
PROT[7:0]
7Fh-
1FFh
reserved — — — — — — — —
Register Map Color Coding
Device Identification and Protection
Local Oscillator and Master Clock Configuration
Input Clock Configuration
Input Clock Monitoring
Input Clock Selection
DPLL Configuration
DPLL State
Output Clock Configuration
Frame/Multiframe-Sync Configuration
DS3106
41
Register Name:
ID1
Register Description:
Device Identification Register, LSB
Register Address:
00h
Bit #
7
6
5
4
3
2
1
0
Name
ID[7:0]
Default
0
0
1
0
0
0
0
0
Bits 7 to 0: Device ID (ID[7:0]). ID[15:0] = 0C22h = 3106 decim al.
Register Name:
ID2
Register Description:
Device Id entification Register, MSB
Register Address:
01h
Bit #
7
6
5
4
3
2
1
0
Name
ID[15:8]
Default
0
0
0
0
1
1
0
0
Bits 7 to 0: Device ID (ID[15:8]). See the ID1 register description.
Register Name:
REV
Register Description:
Device Rev ision Register
Register Address:
02h
Bit #
7
6
5
4
3
2
1
0
Name
REV[7:0]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Device Revision (REV[7:0]). Contact the factory to interpret this value and determine the latest
revision.
DS3106
42
Register Name:
TEST1
Register Description:
Test Register 1 (Not Normally Used)
Register Address:
03h
Bit #
7
6
5
4
3
2
1
0
Name
PALARM
D180
—
RA
0
8KPOL
0
0
Default
0
0
0
1
0
1
0
0
Bit 7: Phase Alarm (PALARM). This real-time status bit indicates the state of the T0 DPLL phase-lock detector.
See Section 7.7.5. (Note: This is not the same as T0STATE = locked.)
0 = T0 DPLL phase-lock parameters are met (FLEN, CLEN, NALOL, FLLOL)
1 = T0 DPLL loss-of-phase lock
Bit 6: Di sable 180 (D1 80). W hen lock ing to a new ref erence, the T 0 DPLL firs t tries nearest e dge lock ing (±180°)
for the first two seconds. If unsuccessful, it tries full phase/frequency locking (±360°). Disabling the nearest edge
locking can reduce lock time by up to two seconds but may cause an unnecessary phase shift (up to 360°) when
the new reference is close in frequency/phase to the old reference. See Section 7.7.4.
0 = Normal operation: try nearest edge locking then phase/frequency lock ing
1 = Phase/frequency locking only
Bit 4: Resync Analog Dividers (RA). W hen this bit is set the analog output dividers are always synchronized to
ensure that low-frequency outputs are in sync with the higher frequency clock from the DPLL.
0 = Synchronized for the first two seconds after power-up
1 = Always synchronized
Bits 3, 1, and 0: Leave set to zero (test control).
Bit 2: 8kHz Edge Polarity (8KPOL). Specif ies the input clock edge to lock to on the select ed reference whe n it is
configured for LOCK8K mode. See Section 7.4.2.
0 = Falling edge
1 = Rising edge
DS3106
43
Register Name:
MSR1
Register Description:
Master Status Register 1
Register Address:
05h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
IC4
IC3
—
—
Default
1
0
1
1
1
1
1
1
Bits 3 and 2: Input Clock Status Change (IC[3:2]). Each of these latched status bits is set to 1 when the VALSR1
status bit changes state (set or cleared). Each bit is cleared when written with a 1 and not set again until the
VALSR1 bit ch anges state again. W hen one of these l atched s tatus bits is set, i t c an cause an interrupt requ est on
the INTREQ pin if the corres ponding i nterrupt e nable b it is set in the IER1 regist er. See Section 7.5 for in put c lock
validation/invalidation criteria.
Register Name:
MSR2
Register Description:
Master Status Register 2
Register Address:
06h
Bit #
7
6
5
4
3
2
1
0
Name
STATE
SRFAIL
—
—
—
—
—
—
Default
0
0
0
0
0
0
0
1
Bit 7: T0 DPLL State Change (STAT E). This lat ched s tatus bit is s et to 1 wh en t he op er at ing sta te of the T0 D P L L
changes. STATE is cleared when writt en with a 1 a nd not set again unt il the oper ating state changes again. When
STATE is set it can cause an interrupt request on the INTREQ pin if the STATE interrupt enable bit is set in the
IER2 register. The current operating state can be read from the T0STATE field of the OPSTATE register. See
Section 7.7.1.
Bit 6: Selected Reference Failed (SRFAIL). This latc hed status bit is s et to 1 when the s elected referenc e to the
T0 DPLL f ails, ( i.e., n o cloc k edges in tw o UI). SRFAIL is clear ed when written with a 1 . W hen SRFAIL is s et it ca n
cause an int errupt requ est on the INTREQ pin if the SRFAIL i nterrupt e nable b it is s et in the IER2 register. SR FAIL
is not set in free-run mode or holdover mode. See Section 7.5.3.
Register Name:
FREQ3
Register Description:
Frequency Register 3
Register Address:
07h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
FREQ[18:16]
Default
0
0
0
0
0
0
0
0
Bits 2 to 0: Current DPLL Frequency (FR EQ[18:16]). S ee the FREQ1 register description.
DS3106
44
Register Name:
OPSTATE
Register Description:
Operating State Register
Register Address:
09h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
T0SOFT
—
—
T0STATE[2:0]
Default
1
0
0
0
0
0
0
1
Bit 5: T0 DPLL Frequency Soft Alarm (T0SOFT). This real-time status bit indicates whether the T0 DPLL is
tracking its reference within the soft alarm limits specified in the SOFT[6:0] field of the DLIMIT3 register. See
Section 7.7.5.
0 = No alarm; frequency is within the soft alarm limits
1 = Soft alarm; frequency is outside the soft alarm limits
Bits 2 to 0: T0 DPLL Operating State (T0STATE[2:0]). This real-tim e s tatus field indicates th e c ur rent s tat e of the
T0 DPLL state machine. Values not listed below correspond to invalid (unused) states. See Section 7.7.1.
001 = Free-run
010 = Holdover
100 = Locked
101 = Prelocked 2
110 = Prelocked
111 = Loss-of-lock
Register Name:
PTAB1
Register Description:
Priority Table Register 1
Register Address:
0Ah
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
SELREF[3:0]
Default
0
0
0
0
see below
Bits 3 to 0: Selected Reference (SELREF[3:0]). This real-time status field indicates the current selected
referenc e for the T0 D PLL. T he default v alue f or this f ield is 0011b if the SR CSW pin is 1 dur ing res e t and 01 00b if
SRCSW is 0 during reset.
0000 = No valid input reference available
0001 to 0010 = {unused values}
0011 = Input IC3
0100 = Input IC4
0101 to 1111 = {unused values}
DS3106
45
Register Name:
FREQ1
Register Description:
Frequency Register 1
Register Address:
0Ch
Bit #
7
6
5
4
3
2
1
0
Name
FREQ[7:0]
Default
0
0
0
0
0
0
0
0
Note: The FREQ1, FREQ2, and FREQ3 registers must be read consecutively. See Secti on 8.3.
Bits 7 to 0: Current DPLL Frequency (FREQ[7:0]). The full 19-bit FREQ[18:0] field spans this register, FREQ2,
and FREQ3. FREQ is a two’s-complement signed integer that expresses the current frequency as an offset with
respect to the m aster clock f requency (see S ection 7.3) . Because the value in th is register field is deri ved from the
DPLL integr al path, it can be cons idered an average frequenc y with a r ate of change inversel y proportional to the
DPLL bandwidth. If LIMINT = 1 in the MCR9 register, the value of FREQ freezes when the DPLL reaches its
minimum or maximum frequency. The frequency offset in ppm is equal to FREQ[18:0] × 0.0003068. See Section
7.7.1.6.
Applicatio n N o te: Fr e que nc y meas ur ements are r el ati ve, i. e., t hey measur e the f r e quency of the s elect ed r ef e r ence
with resp ect to the local os cillator. As s uch, when a freque ncy differ ence exists, i t is difficult to dis tinguish wheth er
the selected reference is off frequency or the local oscillator is off frequency. In systems with timing card
redundancy, the use of two tim ing car ds, m aster and s lave, ca n addr ess th is diff icult y. Bot h m aster and s lave have
separate local oscillators, and each measures the selected reference. These two measurements provide the
necessary information to distinguish which reference is off frequency, if we make the simple assumption that at
most one reference has a significant frequency deviation at any given time (i.e., a single point of failure). If both
master and slave indicate a significant frequency offset, then the selected reference must be off frequency. If the
master indicates a f requenc y off set but th e slav e do es not, then th e m aster’s local os cillat or m ust be of f frequenc y.
Likewise, if the slave indicates a frequency offset but the master does not, the slave’s local oscillator must be off
frequency.
Register Name:
FREQ2
Register Description:
Frequency Register 2
Register Address:
0Dh
Bit #
7
6
5
4
3
2
1
0
Name
FREQ[15:8]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Current DPLL Frequency (FR EQ[15:8]). See the FREQ1 register description.
DS3106
46
Register Name:
VALSR1
Register Description:
Input Clock Valid Status Register 1
Register Address:
0Eh
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
IC4
IC3
—
—
Default
0
0
0
0
0
0
0
0
Bits 3 and 2: Input Clock Valid Status (IC[3:2]). Each of these real-time status bits is set to 1 when the
corresponding input clock is valid. An input is valid if it has no active alarms (ACT = 0 in the ISR2 register). See
also the MSR1 register and Section 7.5.
0 = Invalid
1 = Valid
Register Name:
ISR2
Register Description:
Input Status Register 2
Register Address:
11h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
ACT4
—
—
—
ACT3
—
Default
0
0
1
0
0
0
1
0
Bit 5: Activity Alarm for Input Clock 4 (ACT4). This real-time status bit is set to 1 when the leaky bucket
accum ulator for IC4 re aches the alarm thres hold sp ecif ied in the LBxU regist er ( where x i n LBxU is spec ified in the
BUCKET field of ICR4). An activity alarm clears the IC4 status bit in the VALSR1 register, invalidating the IC4
clock. See Section 7.5.2.
Bit 1: Activity Alarm for Input Clock 3 (ACT3). This bit has the same behavior as the ACT4 bit but for the IC3
input clock.
Register Name:
MSR4
Register Description:
Master Status Register 4
Register Address:
17h
Bit #
7
6
5
4
3
2
1
0
Name
—
HORDY
MRAA
—
—
—
—
—
Default
0
0
0
0
0
0
0
0
Bit 6: Holdover F requency Ready (HORDY). This l atc hed stat us bit is se t to 1 when the T 0 D PLL has a h oldover
value that has been averaged over the one-second holdover averaging period. HORDY is cleared when written
with a 1. When HORDY is set it can cause an interrup t request on the I NTREQ pin if the HORD Y interrupt e nable
bit is set in the IER4 register. See Section 7.7.1.6.
Bit 5: Multiregister Access Aborted (MRAA). T his latched s tatus bit is set t o 1 when a m ultib yte ac cess (r ead or
write) is int errupted b y an other access to the device. MRAA is c leared when wri tten with a 1. MRA A cannot caus e
an interrupt to occur. See Section 8.3.
DS3106
47
Register Name:
ICR3, ICR4
Register Description:
Input Configuration Register 3, 4
Register Address:
22h, 23h
Bit #
7
6
5
4
3
2
1
0
Name
DIVN
LOCK8K
—
—
FREQ[3:0]
Default
0
0
0
0
see below
Note: These registers are identical in function. ICRx is the control register for input clock ICx.
Bit 7: DIVN Mode (DIVN). When DIVN is set to 1 and LOCK8K = 0, the input clock is divided down by a
programm able pred ivider. The resultin g output c lock is then passed t o the DPLL. All input clocks for which DIVN =
1 are divided b y the fac tor spec ified in DIVN1 and DIVN2. W hen D IVN = 1 and LOCK8 K = 0 in an ICR r egister , the
FREQ field of that register must be set to the input frequency divided by the divide factor. When DIVN = 1 and
LOCK8K = 1 in an ICR register, the FREQ field of that register is decoded as the alternate frequencies. See
Sections 7.4.2.2 and 7.4.2.4.
0 = Disabled
1 = Enabled
Bit 6: LOCK8K Mode (LOCK8K). When LOCK8K is set to 1 and DIVN = 0, the input clock is divided down by a
preset predivider. The resulting output clock, which is always 8kHz, is then passed to the DPLL. LOCK8K is
ignored whe n DI VN = 0 an d FREQ [ 3:0] = 1 001 ( 2kHz) or 1 010 (4k Hz). When DIV N = 1 and LO C K8 K = 1 i n an ICR
register, the FREQ field of that register is decoded as the alternate frequencies. See Sections 7.4.2.2 and 7.4.2.3
0 = Disabled
1 = Enabled
Bits 3 to 0: Input Clock Frequency (FREQ[3:0]). W hen DIVN = 0 an d LOCK8K = 0 ( standard direc t-lock m ode),
this field specifies the input clock’s nominal frequency for direct-lock operation. When DIVN = 0 and LOCK8K = 1
(LOCK8K mode), this field specifies the input clock’s nominal frequency for LOCK8K operation. When DIVN = 1
and LOCK8K = 0 (DIVN mode), this field specifies the frequency after the DIVN divider (i.e., input frequency
divided by DIVN + 1). W hen DIVN = 1 and LOC K8K = 1 (alternate direct-lock frequencies), this f ield specifies th e
input clock’s nominal frequency for direct-lock operation.
DIVN = 0 or LOCK8K = 0: (Standard direct-lock mode, LOCK8K mode, or DIVN mode)
0000 = 8kHz
0001 = 1544kHz or 2048kHz (as determined by SONSDH bit in the MCR3 register)
0010 = 6.48MHz
0011 = 19.44MHz
0100 = 25.92MHz
0101 = 38.88MHz
0110 = 51.84MHz
0111 = 77.76MHz
1000 = 155.52MHz (only valid for LVDS inputs)
1001 = 2kHz
1010 = 4kHz
1011 = 6312kHz
1100 = 5MHz
1101 = 31.25 MHz (not a multiple of 8 kHz and therefore not valid for LOCK8K mode)
1110–1111 = undefined
DIVN = 1 and LOCK8K = 1: (Alternate direct-lock frequency decode)
0000 = 10MHz (internally divided down to 5MHz)
0001 = 25MHz (internally divided down to 5MHz)
0010 = 62.5MHz (internally down to 31.25MHz)
0011 = 125MHz (internally down to 31.25MHz)
0101–1111 = undefined
FREQ[3:0] D efault Values:
DS3106
49
Register Name:
MCR1
Register Description:
Master Configuration Register 1
Register Address:
32h
Bit #
7
6
5
4
3
2
1
0
Name
RST
—
FREN
LOCKPIN
—
T0STATE[2:0]
Default
0
0
1
0
0
0
0
0
Bit 7: Dev ice Reset (RST ) . When this b it is high the e ntire de vice is h eld i n res et, and al l re gis ter f ie lds, ex c ept th e
RST bit itse lf , ar e r eset t o t heir def au lt s tat es . When RST is acti ve , th e r e gister fie lds w ith pin -programmed defaults
do not latc h their values f rom the c orresponding input pins . Instea d these f ields are r eset to th e default values tha t
were latche d from the pins when the RST pin was last active. See Sec t ion 7.10.
0 = Normal operation
1 = Reset
Bit 5: Frequency Range Detect Enable (FREN). When this bit is high the frequency of each input clock is
measured and used to quickly declare the input inactive. See Section 7.5.1.
0 = Frequency range detect disabled.
1 = Frequency range detect enabled.
Bit 4: T0 DPLL LOCK Pin Enable (LOCKPIN). When this bit is high the LOCK pin indicates when the T0 DPLL
state machine is in the LOCK state (OPSTATE.T0STATE = 100).
0 = LOCK pin is not driven.
1 = LOCK pin is driven high when the T0 DPLL is in the lock state.
Bits 2 to 0: T0 DPLL State Control (T0STAT E[2:0]). This field allows th e T0 D PLL state mac hine to be f orced to
a specified state. The state machine remains in the forced state, and, therefore, cannot react to alarms and other
events as long as T0STATE is not equal to 000. See Section 7.7.1.
000 = Automatic (normal state machine operation)
001 = Free-run
010 = Holdover
011 = {unused valu e}
100 = Locked
101 = Prelocked 2
110 = Prelocked
111 = Loss-of-lock
DS3106
50
Register Name:
MCR3
Register Description:
Master Configuration Register 3
Register Address:
34h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
XOEDGE
FRUNHO
—
SONSDH
—
—
Default
1
1
0
0
0
see below
1
0
Bit 5: Local Oscillator Edge (XOEDGE). This bit specifies the significant clock edge of the local oscillator clock
signal on the REFCLK input pin. The faster edge should be selected for best jitter performance. See Section 7.3.
0 = Rising edge
1 = Falling edge
Bit 4: Free-Run Holdover (FRUNHO). W hen this b it is set to 1 the T 0 DPLL holdover fr equenc y is set to 0 ppm so
the output frequency accuracy is set by the external oscillator accuracy. This affects both mini-holdover and the
holdover state.
0 = Digital holdover
1 = Free-run holdover, 0ppm
Bit 2: SONET or SDH Frequencies (SONSDH). This bit s pec if ies the c lock rate for input cloc k s with FREQ = 0001
in the ICR registers (20h to 28h). During reset the default value of this bit is latched from the SONSDH pin. See
Section 7.4.2.
0 = 2048kHz
1 = 1544kHz
Register Name:
MCR6
Register Description:
Master Configuration Register 6
Register Address:
38h
Bit #
7
6
5
4
3
2
1
0
Name
DIG2AF
DIG2SS
DIG1SS
—
—
—
—
—
Default
0
see below
see below
1
1
1
1
1
Bit 7: Digital Alternate Frequency (DIG2AF). Selects alternative frequencies.
0 = Digital2 N x E1 or N x DS1 frequency specified by DIG2SS and MCR7:DIG2F.
1 = Digital2 6.312MHz, 10MHz, or N x 19.44MHz frequency specified by DIG2SS and MCR7:DIG2F.
Bit 6: Digital2 SONET or SDH Frequencies (DIG2SS). This bit specifies whet h er the c lock rates gener ate d b y the
Digital2 clock synthesizer are multiples of 1.544MHz (SONET compatible) or multiples of 2.048MHz (SDH
compatible) or alternate frequencies. The specific multiple is set in the DIG2F field of the MCR7 register. When
RST = 0 the default value of this bit is latched from the SONSDH pin.
DIG2AF = 0:
0 = Multiples of 2048kHz
1 = Multiples of 1544kHz
DIG2AF = 1:
6.312MHz, 10MHz, or N x 19.44MHz
Bit 5: Digital1 SONET or SDH Frequencies (DIG1SS). This bit specifies whet h er the c lock rates gener ate d b y the
Digital1 clock synthesizer are multiples of 1544kHz (SONET compatible) or multiples of 2048kHz (SDH
compatib le). The sp ecif ic m ult iple is s et in the DIG 1F field of the MCR7 register. When RST = 0 the defaul t value of
this bit is latched from the SONSDH pin.
0 = Multiples of 2048kHz
1 = Multiples of 1544kHz
DS3106
51
Register Name:
MCR7
Register Description:
Master Configuration Register 7
Register Address:
39h
Bit #
7
6
5
4
3
2
1
0
Name
DIG2F[1:0]
DIG1F[1:0]
—
—
—
—
Default
0
0
0
0
1
0
0
0
Bits 7 and 6: Digital2 Frequency (DIG2F[1:0]). This field, MCR6:DIG2SS, and MCR6:DIG2AF configure the
frequency of the Digital2 clock synthesizer.
DIG2AF = 0
DIG2AF = 1
DIG2SS = 1
DIG2SS = 0
DIG2SS = 1
DIG2SS = 0
00 = 1544kHz
00 = 2048kHz
00 = 19.44MHz
00 = 6.312MHz
01 = 3088kHz
01 = 4096kHz
01 = 38.88MHz
01 = undefined
10 = 6176kHz
10 = 8192kHz
10 = undefined
10 = 10MHz
11 = 12,352kHz
11 = 16,384kHz
11 = undefined
11 = undefined
Bits 5 and 4: Digital1 Frequency (DIG1F[1:0]). This field and MCR6:DIG1SS configure the frequency of the
Digital1 clock synthesizer.
DIG1SS = 1
DIG1SS = 0
00 = 1544kHz
00 = 2048kHz
01 = 3088kHz
01 = 4096kHz
10 = 6176kHz
10 = 8192kHz
11 = 12,352kHz
11 = 16,384kHz
DS3106
52
Register Name:
MCR8
Register Description:
Master Configuration Register 8
Register Address:
3Ah
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
OC6SF[1:0]
Default
0
0
0
0
0
0
1
0
For Rev A2 devices, in LVPECL mode the differential output voltage will be higher than the MAX VODPECL spec in
Table 10-5 unless an adjustment register is written with the proper value. If differential voltages larger than
VODPECL,MAX are unacceptable, the following procedures must be followed when writing the OC6SF fields in this
register. If differential voltages larger than VODPECL,MAX are acceptable, only the OC6SF field must be written.
Procedure to configure OC6 for LVPECL mode:
1) Set the OC6SF[1:0] field to 01b.
2) Write 01h to address 01FFh.
3) Write 55h to the adjustment register at address 01D8h.
4) Write 00h to address 01FFh.
Procedure to configure OC6 for LVDS mode:
1) Set the OC6SF[1:0] field to 10b.
2) Write 01h to address 01FFh.
3) Write 00h to the adjustment register at address 01D8h.
4) Write 00h to address 01FFh.
Bits 1 a n d 0: Output Clock 6 Signa l Format (OC6SF[1:0]). See Sect ion 7.8.1.
00 = Output disabled (powered down)
01 = 3V LVPECL level compatible
10 = 3V LVDS compatible (default)
11 = 3V LVDS compatible
Register Name:
MCR9
Register Description:
Master Configuration Register 9
Register Address:
3Bh
Bit #
7
6
5
4
3
2
1
0
Name
AUTOBW
—
—
—
LIMINT
—
—
—
Default
1
1
1
1
1
0
1
1
Bit 7: Automa tic Bandwidth Selection (AUTOBW). See Section 7.7.2.
0 = Always selects locked bandwidth from the T0LBW register.
1 = Automatically selects either locked bandwidth (T0LBW register) or acquisition bandwidth (T0ABW
register) as appropriate.
Bit 3: Limit Integral Path (LIMINT). When this bit is set to 1, the T0 DPLL’s integral path is limited (i.e., frozen)
when the DPLL reaches m inim um or maximum frequenc y, as set by the HARDLIM field in DLIMIT1 and DLIMIT2.
When the integral path is frozen, the current DPLL frequency in registers FREQ1, FREQ2, and FREQ3 is also
frozen. Setting LIMINT = 1 minimizes overshoot when the DPLL is pulling in. See Section 7.7.2.
0 = Do not freeze integral path at min/max frequency.
1 = Freeze integral path at min/max frequency.
DS3106
53
Register Name:
MCLK1
Register Description:
Master Clock Frequency Adjustment Register 1
Register Address:
3Ch
Bit #
7
6
5
4
3
2
1
0
Name
MCLKFREQ[7:0]
Default
1
0
0
1
1
0
0
1
Note: The MCLK1 and MCLK2 registers must be read consecutively and written c onsecut ively. S ee Secti on 8.3.
Bits 7 to 0: Master Clock Frequency Adjustment (MCLKFREQ[7:0]). The full 16-bit MCLKFREQ[15:0] field
spans this register and MCLK2. MCLKFREQ is an unsigned integer that adjusts the frequency of the internal
204.8MHz master clock with respect to the frequency of the local oscillator clock on the REFCLK pin by up to
+514ppm and -771ppm. The master clock adjustment has the effect of speeding up the master clock with a positive
adjustment and slowing it down with a negative adjustment. For example, if the oscillator connected to REFCLK
has an offset of +1ppm, the adjustment should be -1ppm to correct the offset.
The formulas below translate adjustments to register values and vice versa. The default register value of 39,321
corresponds to 0ppm. See Section 7.3.
MCLKFREQ[15:0] = adjustment_in_ppm / 0.0196229 + 39,321
adjustment_in_ppm = (MCLKFREQ[15:0] – 39,321) × 0.0196229
Register Name:
MCLK2
Register Description:
Master Clock Frequency Adjustment Register 2
Register Address:
3Dh
Bit #
7
6
5
4
3
2
1
0
Name
MLCKFREQ[15:8]
Default
1
0
0
1
1
0
0
1
Bits 7 to 0: Master Clock Frequency Adjustment (MCLKFREQ[15:8]). See the MCLK1 register description.
Register Name:
HOCR3
Register Description:
Holdover Configuration Register 3
Register Address:
40h
Bit #
7
6
5
4
3
2
1
0
Name
AVG
—
—
—
—
—
—
—
Default
1
0
0
0
1
0
0
0
Note: See Section 8.3 for important information about writing and reading this register.
Bit 7: Av eraging (AVG). When this bit is set t o 1 the T0 DPLL us es the a verage d fr equency val ue durin g hold over
mode. When FRUNHO = 1 in the MCR3 register, this bit is ignored. See Section 7.7.1.6.
0 = Not averaged frequency; holdover frequency is either free-run (FRUNHO = 1) or instantaneously
frozen.
1 = Averaged frequency over the last one second while locked to the input.
DS3106
54
DS3106
55
Register Name:
DLIMIT1
Register Description:
DPLL Frequency Limit Register 1
Register Address:
41h
Bit #
7
6
5
4
3
2
1
0
Name
HARDLIM[7:0]
Default
1
1
1
1
1
1
1
1
Note: The DLIMIT1 and DLIMIT2 registers must be read consecutively and written consecutively. See Section 8.3.
Bits 7 to 0: DPLL Hard Frequency Limit (HARDLIM[7:0]). The f ull 10-bit HARDLIM[9:0] field spans this register
and DLIMIT2. HARDLIM is an uns igne d integer that s pec ifies the hard f r equenc y lim it or pull-in/hold-in rang e of the
T0 DPLL. When frequency limit detection is enabled by setting FLLOL = 1 in the DLIMIT3 register. If the DPLL
frequency exceeds the hard limit the DPLL declares loss-of-lock. The hard frequency limit in ppm is
±HARDLIM[9:0] × 0.0782. The default value is normally ±79.794ppm (3FFh). See Sec ti on 7.7.5.
Register Name:
DLIMIT2
Register Description:
DPLL Frequency Limit Register 1
Register Address:
42h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
HARDLIM[9:8]
Default
0
0
0
0
0
0
1
1
Bits 1 a n d 0: DPLL Hard Frequency Lim it (HARDLIM[9:8]). See the DLIMIT1 register des c ript ion.
DS3106
56
Register Name:
IER1
Register Description:
Interrupt Enable Register 1
Register Address:
43h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
IC4
IC3
—
—
Default
0
0
0
0
0
0
0
0
Bits 3 and 2: Interrupt Enable for Input Clock Status Change (IC[3:2]). Each of these bits is an inter rupt enab le
control for the corresponding bit in the MSR1 register.
0 = Mask the interrupt
1 = Enable the interrupt
Register Name:
IER2
Register Description:
Interrupt Enable Register 2
Register Address:
44h
Bit #
7
6
5
4
3
2
1
0
Name
STATE
SRFAIL
—
—
—
—
—
—
Default
0
0
0
0
0
0
0
0
Bit 7: Interrupt Enable for T0 DPLL State Change (STATE). This bit is an interrupt enable for the STATE bit in
the MSR2 register.
0 = Mask the interrupt
1 = Enable the interrupt
Bit 6: Interrupt Enable for Selected Reference Failed (SRFAIL). This bit is an interrupt enable for the SRFAIL bit
in the MSR2 register.
0 = Mask the interrupt
1 = Enable the interrupt
DS3106
57
Register Name:
DIVN1
Register Description:
DIVN Register 1
Register Address:
46h
Bit #
7
6
5
4
3
2
1
0
Name
DIVN[7:0]
Default
1
1
1
1
1
1
1
1
Note: The DIVN1 and DIVN2 registers must be read consecutiv ely and written consecutively. See Section 8.3.
Bits 7 to 0: DIVN Factor (DIVN[7:0]). The full 16-bit DIVN[15:0] field spans this register and DIVN2. This field
contains the integer value used to divide the frequency of input clocks that are configured for DIVN mode. The
frequency is divided by DIVN[15:0] + 1. See Section 7.4.2.4.
Register Name:
DIVN2
Register Description:
DIVN Register 2
Register Address:
47h
Bit #
7
6
5
4
3
2
1
0
Name
DIVN[15:8]
Default
0
0
1
1
1
1
1
1
Bits 7 to 0: DIVN Factor (DIVN[15:8]). See the DIVN1 register description.
Register Name:
MCR10
Register Description:
Master Configuration Register 10
Register Address:
48h
Bit #
7
6
5
4
3
2
1
0
Name
—
SRFPIN
—
—
—
—
—
—
Default
1
0
0
1
0
0
0
0
Bit 6: SRFAIL Pin Enable (SRFPIN). When this bit is set to 1, the SRFAIL pin is enabled. When enabled the
SRFAIL pin follows the state of the SRFAIL status bit in the MSR2 register. This gives the system a very fast
indication of the failure of the current reference. See Section 7.5.3.
0 = SRFAIL pin disabled (high impedance)
1 = SRFAIL pin enabled
DS3106
58
Register Name:
DLIMIT3
Register Description:
DPLL Frequency Limit Register 3
Register Address:
4Dh
Bit #
7
6
5
4
3
2
1
0
Name
FLLOL
SOFTLIM[6:0]
Default
1
0
0
0
1
1
1
0
Bit 7: Frequency Limit Loss-of-Lock (FLLOL). W hen this bit is s et to 1, the T0 DPLL int ernally declares loss-of-
lock when the hard frequency limit in the DLIMIT1 and DLIMIT2 registers is reached. See Section 7.7.5.
0 = DPLL declares loss-of-lock normally.
1 = DPLL also declares loss-of-lock when the hard frequency limit is reached.
Bits 6 to 0: DPLL Soft Frequency Limit (SOFTLIM[6:0]). This field is an uns igned integer that specifies the soft
frequenc y limit for the T 0 DPLL. The soft lim it is only used for monitoring; exceed ing this lim it does not cause loss -
of-lock . The limit in ppm is ±SOFTLIM[6:0] × 0.628. T he default value is ±8. 79ppm. When the T0 DPLL frequency
reaches the soft limit, the T0SOFT status bit is set in the OPSTATE register. See Section 7.7.5.
Register Name:
IER4
Register Description:
Interrupt Enable Register 4
Register Address:
4Eh
Bit #
7
6
5
4
3
2
1
0
Name
—
HORDY
—
—
—
—
—
—
Default
0
0
0
0
0
0
0
0
Bit 6: Interrupt Enable for Holdover Frequency Ready (HORDY). This bit is an interrupt enable f or the HORDY
bit in the MSR4 register.
0 = Mask the interrupt
1 = Enable the interrupt
Register Name:
OCR5
Register Description:
Output Configuration Register 1
Register Address:
4Fh
Bit #
7
6
5
4
3
2
1
0
Name
—
—
AOF6
—
—
AOF3
—
—
Default
0
0
0
0
0
0
0
0
Bit 5: Alternate Output Frequency Mode Select 6 ( AOF 6). T his bit contr ols th e decoding of the OCR3.OFREQ6
field for the OC6 pin.
0 = Standard decodes
1 = Alternate decodes
Bit 2: Alternate Output Frequency Mode Select 3 (AOF3). T his bit contr ols th e decoding of the OCR2.OFREQ3
field for the OC3 pin.
0 = Standard decodes
1 = Alternate decodes
DS3106
59
Register Name:
LB0U
Register Description:
Leaky Bucket 0 Upper Threshold Register
Register Address:
50h
Bit #
7
6
5
4
3
2
1
0
Name
LB0U[7:0]
Default
0
0
0
0
0
1
1
0
Bits 7 to 0: Leaky Bucket 0 Upper Threshold (LB0U[7:0]). W hen the leaky bucket accumulator is equal to the
value stored in this field, the activity monitor declares an activity alarm by setting the input clock’s ACT bit in the
ISR2 r egister. Register s LB0U, LB0L, LB0S, and LB0D together specif y l eaky bucket c onfiguration 0. See Section
7.5.2.
Register Name:
LB0L
Register Description:
Leaky Bucket 0 Lower Threshold Register
Register Address:
51h
Bit #
7
6
5
4
3
2
1
0
Name
LB0L[7:0]
Default
0
0
0
0
0
1
0
0
Bits 7 to 0: Leaky Bucket 0 Lower Threshold (LB0L[7:0]). When the leaky bucket accumulator is equal to the
value store d in th is field, the activ ity monitorin g log ic c l ears the ac ti vit y alarm (if previously decl ared) by clearing the
input clock’s ACT bit in the ISR2 register. Registers LB0U, LB0L, LB0S, and LB0D together specify leaky bucket
configuration 0. See Sectio n 7.5.2.
Register Name:
LB0S
Register Description:
Leaky Bucket 0 Size Register
Register Address:
52h
Bit #
7
6
5
4
3
2
1
0
Name
LB0S[7:0]
Default
0
0
0
0
1
0
0
0
Bits 7 to 0: Leaky Bucket 0 Size (LB0S[7:0]). This field specifies the maximum value of the leaky bucket. The
accumulator cannot increment past this value. Registers LB0U, LB0L, LB0S, and LB0D together specify leaky
bucket configuration 0. See Section 7.5.2.
Register Name:
LB0D
Register Description:
Leaky Bucket 0 Decay Rate Register
Register Address:
53h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
LB0D[1:0]
Default
0
0
0
0
0
0
0
1
Bits 1 and 0: Leaky Bucket 0 Decay Rate (LB0D[1:0]). This field specifies the decay or “leak” rate of the leak y
bucket accumulator. For each period of 1, 2, 4, or 8 128m s intervals in which no irregularities are detected on the
input clock, the accumulator decrements by 1. Registers LB0U, LB0L, LB0S, and LB0D together specify leaky
bucket configuration 0. See Section 7.5.2.
00 = decrement every 128ms (8 units/second)
01 = decrement every 256ms (4 units/second)
10 = decrement every 512ms (2 units/second)
11 = decrement every 1024ms (1 unit/second)
DS3106
60
DS3106
61
Register Name:
OCR2
Register Description:
Output Configuration Register 2
Register Address:
61h
Bit #
7
6
5
4
3
2
1
0
Name
0
0
0
0
OFREQ3[3:0]
Default
0
0
0
0
see below
Bits 3 to 0: Output Frequency of OC3 (OFREQ3[3:0]). This field specifies the frequency of output clock OC3.
The frequenc ies of the T 0 APLL and T4 APLL are c onfigur ed in the T0CR1 and T4CR1 register s. The Digit al1 and
Digital2 frequencies are conf igured in the MCR7 register. See Section 7.8.2.3. The default frequency is set by the
O3F[2:0] bits. Se e Table 7-17. The decode of this field is controlled by the value of the OCR5.AOF3 bit.
AOF3 = 0: (standard decodes)
0000 = Output disabled (i.e., low)
0001 = 2kHz
0010 = 8kHz
0011 = Digital2 (see Table 7-7)
0100 = Digital1 (see Table 7-6)
0101 = T0 APLL frequency divided by 48
0110 = T0 APLL frequency divided by 16
0111 = T0 APLL frequency divided by 12
1000 = T0 APLL frequency divided by 8
1001 = T0 APLL frequency divided by 6
1010 = T0 APLL frequency divided by 4
1011 = T4 APLL frequency divided by 64
1100 = T4 APLL frequency divided by 48
1101 = T4 APLL frequency divided by 16
1110 = T4 APLL frequency divided by 8
1111 = T4 APLL frequency divided by 4
AOF3 = 1: (alternate decodes)
0000 = Output disabled (i.e., low)
0001 = T0 APLL frequency divided by 64
0010 = T4 APLL frequency divided by 20
0011 = T4 APLL frequency divided by 12
0100 = T4 APLL frequency divided by 10
0101 = T4 APLL frequency divided by 5
0110 = T4 APLL frequency divided by 2
0111 = undefined
1000 = T0 selected reference (after dividing)
1001–1111 = undefined
DS3106
62
Register Name:
OCR3
Register Description:
Output Configuration Register 3
Register Address:
62h
Bit #
7
6
5
4
3
2
1
0
Name
OFREQ6[3:0]
0
0
0
0
Default
see below
0
0
0
0
Bits 7 to 4: Output Frequency of OC6 (OFREQ6[3:0]). This field specifies the frequency of output clock output
OC6. The frequencies of the T0 APLL and T4 APLL are configured in the T0CR1 and T4CR1 registers. The
Digital1 and Digital2 frequencies are configured in the MCR7 register. See Section 7.8.2.3. The default frequency is
set by the OC6[2:0] bits. See Table 7-16. The decode of this field is controlled by the value of the OCR5.AOF6 bit.
AOF6 = 0: (standard decodes)
0000 = Output disabled (i.e., low)
0001 = 2kHz
0010 = 8kHz
0011 = T0 APLL frequency divided by 2
0100 = Digital1 (see Table 7-6)
0101 = T0 APLL frequency
0110 = T0 APLL frequency divided by 16
0111 = T0 APLL frequency divided by 12
1000 = T0 APLL frequency divided by 8
1001 = T0 APLL frequency divided by 6
1010 = T0 APLL frequency divided by 4
1011 = T4 APLL frequency divided by 64
1100 = T4 APLL frequency divided by 48
1101 = T4 APLL frequency divided by 16
1110 = T4 APLL frequency divided by 8
1111 = T4 APLL frequenc y divided b y 4
AOF6 = 1: (alternate decodes)
0000 = Output disabled (i.e., low)
0001 = T4 APLL frequency divided by 5
0010 = T4 APLL frequency divided by 2
0011 = T4 APLL frequency
0100 = T0 APLL2 frequency divided by 5
0101 = T0 APLL2 frequency di vi de d by 2
0110 = T0 APLL2 frequency
0111 = T4 selected reference (after dividing)
1000 = T0 selected reference (after dividing)
1001–1111 = undefined
DS3106
63
Register Name:
OCR4
Register Description:
Output Configuration Register 4
Register Address:
63h
Bit #
7
6
5
4
3
2
1
0
Name
MFSEN
FSEN
0
0
0
0
0
0
Default
1
1
0
0
0
0
0
0
Bit 7: MFSYNC Enable (MFSEN). This configuration bit enables the 2kHz output on the MFSYNC pin . See Secti o n
7.8.2.5.
0 = Disabled, driven low
1 = Enabled, output is 2k H z
Bit 6: FSYNC Enable (FSEN). This configuration bit enables the 8kHz output on the FSYNC pin. See Section
7.8.2.5.
0 = Disabled, driven low
1 = Enabled, output is 8k H z
Register Name:
T4CR1
Register Description:
T4 DPLL Configuration Register 1
Register Address:
64h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
T4FREQ[3:0]
Default
0
0
0
0
see below
Bits 3 to 0: T4 APLL Frequency (T4FREQ[3:0]). When T0CR1:T4APT0 = 0, this field configures the T4 APLL
DFS frequency. The T4 APLL DFS frequency affects the frequency of the T4 APLL which, in turn, affects the
availab le output frequencies on th e o utp ut c loc k pins (see the OCR registers) . S e e S ec tio n 7.8.2. T he def au l t va lue
of this field is controlled by the O6F[2:0] and O3F[2:0] pins as described in Table 7-15.
T4FREQ[3:0] T4 APLL DFS FREQUENCY T4 APLL FREQUENCY (4 x T4 A PLL D F S)
0000
APLL output disabled
Disabled, output is low
0001
77.76MHz
311.04MHz (4 x 77.76MHz)
0010
24.576MHz (12 x E1)
98.304MHz (48 x E1)
0011
32.768MHz (16 x E1)
131.072MHz (64 x E1)
0100
37.056MHz (24 x DS1)
148.224MHz (96 x DS1)
0101
24.704MHz (16 x DS1)
98.816MHz (64 x DS1)
0110
68.736MHz (2 x E3)
274.944MHz (8 x E3)
0111
44.736MHz (DS3)
178.944MHz (4 x DS3)
1000
25.248MHz (4 x 6312kHz)
100.992MHz (16 x 6312kHz)
1001
62.500MHz (GbE ÷ 16)
250.000MHz (GbE ÷ 4)
1010
30.720MHz (3 x 10.24)
122.880MHz (12 x 10.24)
1011
40.000MHz (4 x 10MHz)
160.000MHz (16 x 10MHz)
1100
26.000MHz (2 x 13MHz)
104.000MHz (8 x 13MHz)
1101–1111
{unused valu es }
{unused valu es }
DS3106
64
Register Name:
T0CR1
Register Description:
T0 DPLL Configuration Register 1
Register Address:
65h
Bit #
7
6
5
4
3
2
1
0
Name
—
T4APT0
T0FT4[2:0]
T0FREQ[2:0]
Default
0
0
0
0
0
see below
Bit 6: T4 APLL Source from T0 (T4APT0). When this bit is set to 0, T4CR1:T4FREQ configures the T4 APLL DFS
frequenc y. The T4 APLL D FS frequenc y aff ects the frequenc y of th e T4 APLL, which, in turn, aff ects the available
output f requencies on the o utput cloc k pins (see the OCR register s). W hen this bi t is set t o 1, th e frequenc y of the
T4 APLL DFS is configured by the T0CR1:T0FT4[2:0] field below. See Section 7.8.2.
0 = T4 APLL frequency is determined by T4FREQ.
1 = T4 APLL frequency is determined by T0FT4.
Bits 5 to 3: T0 Frequency to T4 APLL (T0FT4[2:0]). When the T4APT0 bit is set to 1, this field specifies the
frequenc y of the T 4 APLL DFS. This frequenc y can be diff erent than the frequenc y specified by T0CR1:T0FREQ.
See Section 7.8.2.
T0FT4
T4 APLL DFS FREQUENCY
T4 APLL FREQUENCY (4 x T4 APLL DFS)
000 =
24.576MHz (12 x E1)
98.304MHz (48 x E1)
001 =
62.500MHz (GbE ÷ 16)
250.000MHz (GbE ÷ 4)
010 =
32.768MHz (16 x E1)
131.072MHz (64 x E1)
011 =
{unused valu e}
{unused valu e}
100 =
37.056MHz (24 x DS1)
148.224MHz (96 x DS1)
101 =
{unused valu e}
{unused valu e}
110 =
24.704MHz (16 x DS1)
98.816MHz (64 x DS1)
111 =
25.248MHz (4 x 6312kHz)
100.992MHz (16 x 6312kHz)
Bits 2 to 0: T0 DPLL Output Frequency (T0FREQ[2:0]). This field configures the T0 APLL DFS frequency. The
T0 APLL DFS frequency affects the frequency of the T0 APLL, which, in turn, affects the available output
frequencies on the output clock pins (see the OCR registers). See Section 7.8.2. The default frequency is
controlled by the O6F[2:0] and O3F[2:0] pins as described in Table 7-14.
T0FREQ
T0 APLL DFS FREQUENCY
T0 APLL FREQUENCY (4 x T0 APLL DFS)
000 =
77.76MHz
311.04MHz (4 x 77.76MHz)
001 =
77.76MHz
311.04MHz (4 x 77.76MHz)
010 =
24.576MHz (12 x E1)
98.304MHz (48 x E1)
011 =
32.768MHz (16 x E1)
131.072MHz (64 x E1)
100 =
37.056MHz (24 x DS1)
148.224MHz (96 x DS1)
101 =
24.704MHz (16 x DS1)
98.816MHz (64 x DS1)
110 =
25.248MHz (4 x 6312kHz)
100.992MHz (16 x 6312kHz)
111 =
62.500MHz (GbE ÷ 16)
250.000MHz (GbE ÷ 4)
DS3106
65
Register Name:
T0LBW
Register Description:
T0 DPLL Locked Bandwidth Register
Register Address:
67h
Bit #
7
6
5
4
3
2
1
0
Name
0
0
0
RSV1
RSV2
T0LBW[2:0]
Default
0
0
0
0
0
0
0
0
Bits 4 and 3: Reserved Bit 1 and 2 (RSV[1:2]). These bi ts are reser ved for f uture use, a nd ca n be writt en to and
read back.
Bits 2 to 0: T0 DPLL Locked Bandwidth (T0LBW[2:0]). This f ield conf ig ures th e ba nd w idt h of the T 0 D PL L whe n
locked to an input clock. When AUTOBW = 0 in the MCR9 register, the T0LBW bandwidth is used for acquisition
and for locked operation. When AUTOBW = 1, T0ABW bandwidth is used for acquisition while T0LBW bandwidth
is used for locked operation. See Section 7.7.2.
111 = 18Hz
000 = 35Hz (default)
001 = 70Hz
010 = {unused value, undefined}
011 = 18Hz
100 = 120Hz
101 = 250Hz
110 = 400Hz
Register Name:
T0ABW
Register Description:
T0 DPLL Acquisition Bandwidth Reg ister
Register Address:
69h
Bit #
7
6
5
4
3
2
1
0
Name
0
0
0
RSV1
RSV2
T0ABW[2:0]
Default
0
0
0
0
0
0
0
1
Bits 4 and 3: Reserved Bit 1 and 2 (RSV[1:2]). These bi ts are reser ved for f uture use, a nd can b e written to an d
read back.
Bits 2 to 0: T0 DPLL Acq uisition Bandwidth (T0 AB W[2:0]). This f ield configures the bandwidth of the T0 DPL L
when acquiring lock . W hen AUTOBW = 0 in the MCR9 register, the T0LBW bandwidth is used f or acquisition and
for locked operation. When AUTOBW = 1, T0ABW bandwidth is used for acquisition while T0LBW bandwidth is
used for locked operation. See Section 7.7.2.
111 = 18Hz
000 = 35Hz
001 = 70Hz (default)
010 = {unused value, undefined}
011 = 18Hz
100 = 120Hz
101 = 250Hz
110 = 400Hz
DS3106
66
Register Name:
T0CR2
Register Description:
T0 Configuratio n Register 2
Register Address:
6Bh
Bit #
7
6
5
4
3
2
1
0
Name
—
PD2G8K[2:0]
—
DAMP[2:0]
Default
0
0
0
1
0
1
0
0
Bits 6 to 4: Ph ase Det ecto r 2 Ga in, 8kH z (PD 2G8K[ 2:0] ). T his field sp ecif ies th e gain of the T 0 phas e det ector 2
with an inpu t clock of 8kHz or les s. T his value is o nl y used if autom atic gain s election is ena bled b y setting PD2EN
= 1 in the T0CR3 r egister. See Sect ion 7.7.4.
Bits 2 to 0: Damping Factor (DAMP[2:0]). This field configures the damping factor of the T0 DPLL. Damping
factor is a function of both DAMP[2:0] and the T0 DPLL bandwidth (T0ABW and T0LBW). The default value
corresponds to a damping factor of 5. See Section 7.7.3.
18Hz
35Hz
≥ 70Hz
001 =
1.2
1.2
1.2
010 =
2.5
2.5
2.5
011 =
5
5
5
100 =
5
10
10
101 =
5
10
20
000, 110, and 111 =
{unused valu es }
The gain peak for each damping factor is shown below:
DAMPING
FACTOR
GAIN PEAK (dB)
1.2
0.4
2.5
0.2
5
0.1
10
0.06
20
0.03
Register Name:
T0CR3
Register Description:
T0 Configuratio n Register 3
Register Address:
6Dh
Bit #
7
6
5
4
3
2
1
0
Name
PD2EN
—
—
—
—
PD2G[2:0]
Default
1
1
0
0
0
0
1
0
Bit 7: Phase D etector 2 Gain Enab le (PD2EN). W hen this bit is s et to 1, the T0 phase det ector 2 is enable d and
the gain is det ermined by the input lock ing frequency. If the frequenc y is greater than 8kHz, the gain is set by the
PD2G field. If the frequency is less than or equal to 8kHz, the gain is set by the PD2G8K field in the T0CR2
register. See Section 7.7.4.
0 = Disable
1 = Enable
Bits 2 to 0: Phase Detecto r 2 Gain (PD2G [2:0]) . This field specif ies the gain of the T 0 phase detector 2 when the
input frequency is greater than 8kHz. This value is only used if automatic gain selection is enabled by setting
PD2EN = 1. See Section 7.7.4.
DS3106
67
Register Name:
GPCR
Register Description:
GPIO Configuration Register
Register Address:
6Eh
Bit #
7
6
5
4
3
2
1
0
Name
GPIO4D
GPIO3D
GPIO2D
GPIO1D
GPIO4O
GPIO3O
GPIO2O
GPIO1O
Default
0
0
0
0
0
0
0
0
Bit 7: GPIO4 Direction (GPIO4D). This bit configures the data direction for the GPIO4 pin. When GPIO4 is an
input, its current state can be read from GPSR:GPIO4. When GPIO4 is an output, its value is controlled by the
GPIO4O configuration bit.
0 = Input
1 = Output
Bit 6: GPIO3 Direction (GPIO3D). This bit configures the data direction for the GPIO3 pin. When GPIO3 is an
input, its current state can be read from GPSR:GPIO3. When GPIO3 is an output, its value is controlled by the
GPIO3O configuration bit.
0 = Input
1 = Output
Bit 5: GPIO2 Direction (GPIO2D). This bit configures the data direction for the GPIO2 pin. When GPIO2 is an
input, its current state can be read from GPSR:GPIO2. When GPIO2 is an output, its value is controlled by the
GPIO2O configuration bit.
0 = Input
1 = Output
Bit 4: GPIO1 Direction (GPIO1D). This bit configures the data direction for the GPIO1 pin. When GPIO1 is an
input, its current state can be read from GPSR:GPIO1. When GPI13 is an output, its value is controlled by the
GPIO1O configuration bit.
0 = Input
1 = Output
Bit 3: GPIO4 Output Value (GPIO4O). When GPIO4 is configured as an output (GPIO4D = 1), this bit specifies
the output value.
0 = Low
1 = High
Bit 2: GPIO3 Output Value (GPIO3O). When GPIO3 is configured as an output (GPIO3D = 1), this bit specifies
the output value.
0 = Low
1 = High
Bit 1: GPIO2 Output Value (GPIO2O). When GPIO2 is configured as an output (GPIO2D = 1), this bit specifies
the output value.
0 = Low
1 = High
Bit 0: GPIO1 Output Value (GPIO1O). When GPIO1 is configured as an output (GPIO1D = 1), this bit specifies
the output value.
0 = Low
1 = High
DS3106
68
Register Name:
GPSR
Register Description:
GPIO Statu s Register
Register Address:
6Fh
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
GPIO4
GPIO3
GPIO2
GPIO1
Default
0
0
0
0
0
1
0
0
Bit 3: GPI O4 State (GPIO4). This bit indicates the current state of the GPIO4 pin.
0 = Low
1 = High
Bit 2: GPI O3 State (GPIO3). This bit indicates the current state of the GPIO3 pin.
0 = Low
1 = High
Bit 2: GPI O2 State (GPIO2). This bit indicates the current state of the GPIO2 pin.
0 = Low
1 = High
Bit 1: GPI O1 State (GPIO1). This bit indicates the current state of the GPIO1 pin.
0 = Low
1 = High
DS3106
69
Register Name:
PHLIM1
Register Description:
Phase Limit Register 1
Register Address:
73h
Bit #
7
6
5
4
3
2
1
0
Name
FLEN
NALOL
1
—
—
FINELIM[2:0]
Default
1
0
1
0
0
0
1
0
Bit 7: Fine Phase Limit Enable (FLEN). This configuration bit enables the fine phase limit specified in the
FINELIM[2:0] field. The fine limit must be disabled for multi-UI jitter tolerance (see PHLIM2 fields). See Section
7.7.5.
0 = Disabled
1 = Enabled
Bit 6: No Activity Loss-of-Lock (NALOL). T he T0 and the T4 DPLLs c an det ec t that an input c lock has no ac tivit y
very quickly (within two clock cycles). When NALOL = 0, loss-of-lock is not declared when clock cycles are missing,
and nearest edge locking (±180°) is used when the clock recovers. This gives tolerance to missing cycles. When
NALOL = 1 , l oss -of-lock is indicat ed as soon as n o ac t i vit y is detected, and the de vice switches to ph as e/f requency
locking (±360°). See Sections 7.5.3 and 7.7.5.
0 = No activity does not trigger loss-of-lock.
1 = No activity does trigger loss-of-lock.
Bit 5: Leave set to 1 (test control).
Bits 2 to 0: Fine Phase Limit (FINELIM[2:0]). This field specifies the fine phase limit window, outside of which
loss-of-lock is declared. The FLEN bit enables this feature. The phase of the input clock has to be inside the fine
limit wind o w for two seconds before phase lock is dec lared. Los s -of-lock is declared im mediatel y if the phas e of t he
input clock is outside the phase limit window. The default value of 010 is appropriate for most situations. See
Section 7.7.5.
000 = Always indicates los s -of-phase lock—do not use
001 = Small phase limit window, ±45° to ±90°
010 = Normal phase limit window, ±90° to ±180° (default)
100, 101, 110, 111 = Proportionately larger phase limit window
DS3106
70
Register Name:
PHLIM2
Register Description:
Phase Limit Register 2
Register Address:
74h
Bit #
7
6
5
4
3
2
1
0
Name
CLEN
MCPDEN
USEMCPD
—
COARSELIM[3:0]
Default
1
1
1
0
0
1
0
1
Bit 7: Coarse Phase Limit Enable (CLEN). This configuration bit enables the coarse phase limit specified in the
COARSELIM[3:0] field. See Section 7.7.5.
0 = Disabled
1 = Enabled
Bit 6: Multicycle Phase Detector Enable (MCPDEN). This conf igur at ion bit en a bles t he multic ycle phas e d etec tor
and allows th e DPLL to tolerat e large-am plitude jitter and wander. T he range of this phas e detector is the sam e as
the coarse phase limit specified in the COARSELIM[3:0] field. See Section 7.7.4.
0 = Disabled
1 = Enabled
Bit 5: Use Multicycle Phase Detector in the DPLL Algorithm (USEMCPD). This configuration bit enables the
DPLL algorit hm to use the multicycle ph ase det ec tor s o that a l arge p has e measurement drives faster DPLL pul l -in.
When USEMCPD = 0, phase measurem ent is limited to ±360°, giving slower pull-in at higher frequencies but with
less over shoot. W hen US EMCPD = 1, phase measur em ent is set as spec ified in t he CO ARSEL IM[3:0] f ield , gi ving
faster pull-in. MCPDEN should be set to 1 when USEMCPD = 1. See Section 7.7.4.
0 = Disabled
1 = Enabled
Bits 3 to 0: Coarse Phase Limit (COARSELIM[3:0]). This field specifies the coarse phase limit and the tracking
range of the multicycle phase detector. The CLEN bit enables this feature. If jitter tolerance greater than 0.5UI is
required and the input clock is a high-frequency signal, the DPLL can be configured to track phase errors over
many UI using the multicycle phase detector. See Section 7.7.4 and 7.7.5.
0000 = ±1UI
0001 = ±3UI
0010 = ±7UI
0011 = ±15UI
0100 = ±31UI
0101 = ±63UI
0110 = ±127UI
0111 = ±255UI
1000 = ±511UI
1001 = ±1023UI
1010 = ±2047UI
1011 = ±4095UI
1100–1111 = ±8191UI
DS3106
71
Register Name:
PHMON
Register Description:
Phase Monitor Register
Register Address:
76h
Bit #
7
6
5
4
3
2
1
0
Name
NW
—
—
—
—
—
—
—
Default
0
0
0
0
0
1
1
0
Bit 7: Low-Frequency Input Clock Noise Window (NW). For 2kHz, 4kH z, or 8k Hz input clock s, this conf iguration
bit enables a ±5% tolerance noise window centered around the expected clock edge location. Noise-induced edges
outside th is windo w are ign ored, red ucin g the pos sibil ity of phas e hits on t he ou tput c lock s. This onl y applies to the
T0 DPLL a nd s h oul d b e e n abl ed o nly when the T 0 DPLL is loc ked to an i nput an d the 1 80° phas e detector is being
used (TEST1.D180=0).
0 = All edges are recognized by the T0 DPLL.
1 = Only edges within the ±5% tolerance window are recognized by the T0 DPLL.
Register Name:
PHASE1
Register Description:
Phase Register 1
Register Address:
77h
Bit #
7
6
5
4
3
2
1
0
Name
PHASE[7:0]
Default
0
0
0
0
0
0
0
0
Note: The PHASE1 and PHASE2 registers must be read consecutively. S ee Secti on 8.3.
Bits 7 to 0: Current DPLL Phase (PHASE[7:0]). The full 16-bit PHASE[15:0] field spans this register and the
PHASE2 register. PHASE is a two’s-complement signed integer that indicates the current value of the phase
detector. The value is the output of the phase averager. The averaged phase difference in degrees is equal to
PHASE × 0.707. See Section 7.7.6.
Register Name:
PHASE2
Register Description:
Phase Register 2
Register Address:
78h
Bit #
7
6
5
4
3
2
1
0
Name
PHASE[15:8]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Current DPLL Phase (PHASE[15:8]). See the PHASE1 register description.
DS3106
72
Register Name:
FSCR1
Register Description:
Frame-Sync Configuration Register 1
Register Address:
7Ah
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
8KINV
8KPUL
2KINV
2KPUL
Default
0
0
0
0
0
0
0
0
Bit 3: 8kHz Invert (8KINV). When this bit is set to 1, the 8kHz signal on clock output FSYNC is inverted. See
Section 7.8.2.5.
0 = FSYNC not inverted
1 = FSYNC inverted
Bit 2: 8kHz Pu lse (8K PUL) . W hen this bit is set t o 1, the 8kH z signal on cloc k out put FSYNC is pulsed r ather than
50% duty cycle. In this mode output clock OC3 must be enabled, and the pulse width of FSYNC is equal to the
clock period of OC3. See Section 7.8.2.5.
0 = FSYNC not pulsed; 50% duty cycle
1 = FSYNC pulsed, with pulse width equal to OC3 period
Bit 1: 2kHz Invert (2KINV). When this bit is set to 1, the 2kHz signal on clock output MFSYNC is inverted. See
Section 7.8.2.5.
0 = MFSYNC not invert ed
1 = MFSYNC inverte d
Bit 0: 2kHz Pulse (2KPUL). When this bit is set to 1, the 2kHz signal on clock output MFSYNC is pulsed rather
than 50% duty c ycle. In this mode output clock OC3 m ust be enabled , and the pulse width of MFS YNC is equal to
the clock period of OC3. See Section 7.8.2.5.
0 = MFSYNC not pulsed; 5 0% dut y cycle
1 = MFSYNC pulsed, with puls e wid th equa l to OC3 p eriod
DS3106
73
Register Name:
INTCR
Register Description:
Interrupt Configuration Register
Register Address:
7Dh
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
LOS
GPO
OD
POL
Default
0
0
0
0
1
0
1
0
Bit 3: INTREQ Pin Mode (LOS). When GPO = 0, this bit selects the function of the INTREQ pin.
0 = The INTREQ/LOS pin indicates interrupt requests.
1 = The INTREQ/LOS pin indicates the real-time state of the selected reference activity monitor (see
Section 7.5.3).
Bit 2: INTREQ Pin General-Purpose Output Enable (GPO). When set to 1, this bit configures the interrupt
request pin to be a general-purpose output w hose va lu e is set by the POL bit.
0 = INTREQ is function determined by the LOS bit.
1 = INTREQ is a general-purpose output.
Bit 1: INTREQ Pin Open-Drain Enable (OD)
When GPO = 0:
0 = INTREQ is driven in both inactive and active states.
1 = INTREQ is driven high or low in the active state but is high impedance in the inactive state.
When GPO = 1:
0 = INTREQ is driven as specified by POL.
1 = INTREQ is high impedance and POL has no effect.
Bit 0: INTREQ Pin Polarity (POL)
When GPO = 0:
0 = INTREQ goes low to signal an interrupt request or LOS = 1 (active low).
1 = INTREQ goes high to signal interrupt request or LOS = 1 (active high).
When GPO = 1:
0 = INTREQ driven low.
1 = INTREQ driven high.
Register Name:
PROT
Register Description:
Protection Register
Register Address:
7Eh
Bit #
7
6
5
4
3
2
1
0
Name
PROT[7:0]
Default
1
0
0
0
0
1
0
1
Bits 7 to 0: Protection Control (PROT[7:0]). This field can be used to protect the rest of the register set from
inadvertent writes. In protected mode writes to all other registers are ignored. In single unprotected mode, one
register (ot her than P ROT) can be written , but after t hat write the device rever ts to protec ted mode (and the value
of PROT is internall y changed to 00 h). In ful ly unprot ected m ode all register s can be wr itten withou t lim itation. See
Section 7.2.
1000 0101 = Fully unprotected mode
1000 0110 = Single unprotected mode
All other values = Protected mode
DS3106
74
9.
JTAG Tes t Access Por t and Boundary Scan
9.1
JTAG Description
The DS3106 supp ort s the standar d inst ruc t ion codes SAM PL E/PR ELOAD, B YPA SS, and EX TEST. O ptiona l public
instructio ns included are HI GHZ, CLAMP, and ID CODE. Figure 9-1 shows a bl ock diagram . The DS3106 contains
the follo wing items, which meet the requir ements s et b y the I EE E 11 49. 1 St and a r d T es t Ac ces s Port and B o undary
Scan Architecture:
Test Access Port (TAP)
Bypass Register
TAP Controller
Boundary Scan Register
Instruction Register
Device Identification Register
The TAP has the necessar y interface pins, namely JTCLK, JTRST, JTDI, JTDO, and JTMS. Details on these pins
can be found in Table 6-5. Details about the boundary scan architecture and the TAP can be found in IEEE 1149.1-
1990, IEEE 1149.1a-1993, and IEEE 1149. 1 b-1994.
Figure 9-1. JTAG Block Diagram
BOUNDARY SCAN
REGISTER
DEVICE
IDENTIFICATION
REGISTER
BYPASS REGISTER
INSTRUCTION
REGISTER
TEST ACCESS PORT
CONTROLLER
MUX
SELECT
THREE-STATE
JTDI
50k
JTMS
50k
JTCLK
JTRST
50k
DS3106
75
9.2
JTAG TAP Controller State Machine Description
This section discusses the operation of the TAP controller state machine. The TAP controller is a finite state
machine that responds to the logic level at JTMS on the rising edge of JTCLK. Each of the states denoted in
Figure 9-2 is described in the following paragraphs.
Test-Logic-Reset. Upon device power-up, the TAP controller starts in the Test-Logic-Reset state. The instruction
register contains the IDCODE instruction. All system logic on the device operates normally.
Run-Test-Idle. Run-Test-Idle is used bet ween sc an operat ions or during specif ic tests . The instr uction reg ister and
all test registers remain idle.
Select-DR-Scan. All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the
controller into the Capture-DR state and initiates a sc an sequence. JTMS high moves the controller to the Select-
IR-SCAN state.
Capture-DR. Data can be parallel-lo aded into the test register selec ted by the curr ent instruction. If the instruction
does not c all for a p aralle l load or t he sel ected t est reg ister does not a llow para llel loads, the r egister rem ains at its
current va lue. On the r ising edge of JTC LK, the contro ller goes to t he Shift -DR state if JTMS is lo w or to the Ex it1-
DR state if JTMS is high.
Shift-DR. The test register selected by the current instruction is connected between JTDI and JTDO and data is
shifted one stage toward the serial output on each rising edge of JTCLK. If a test register selected by the current
instruction is not placed in the serial path, it maintains its previous state.
Exit1-DR. W hile in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state,
which terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Pause-DR
state.
Pause-DR. Shifting of the test registers is halted while in this state. All test registers selected by the current
instruction retain their previous state. The controller remains in this state while JTMS is low. A rising edge on
JTCLK with JTMS high puts the controller in the Exit2-DR state.
Exit2-DR. W hile in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state
and terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Shift-DR
state.
Update-DR. A falling edge on JTCLK while in the Update-DR state latches the data from the shift register path of
the test registers into t he data output latches. T his prevents changes at the par allel outp ut because of cha nges in
the shift regis ter. A rising e dge on JTCLK with JT MS low puts the c ontroller in the Run-Test-Idle stat e. With JTMS
high, the controller enters the Select-DR-Scan state.
Select-IR-Scan. All test r egister s r etai n th eir pr e vious state. The instruc tio n reg is ter r emains unchange d during th is
state. With JTMS low, a rising edge on JTCLK moves the controller into the Capture-IR state and initiates a scan
sequence for the instruction register. JTMS high during a rising edge on JTCLK puts the controller back into the
Test-Logic-Reset state.
Capture-IR. The Cap tur e-I R s tate is us ed to lo ad t he s hif t regis ter in th e instr uc tion r e gis ter w ith a fixed va lu e. This
value is loa ded on the r ising edg e of JT CLK. If JT MS is high on the ris ing edge of JTCLK, the c ontroller ente rs the
Exit1-IR state. If JTMS is low on the rising edge of JTCLK, the controller enters the Shift-IR state.
Shift-IR. In this state, the instruction register’s shift register is connected b etween JTDI and JTDO and shifts data
one stage for every rising edge of JTCLK toward the serial output. The parallel register and the test registers
rem ain at their pr evious st ates. A r ising edg e on JT CLK with JTMS hi gh moves t he contr oller to t he Exit1-IR state.
A rising edge on JTCLK with JTMS low keeps the controller in the Shift-IR state, while moving data one stage
through the instruction shift register.
DS3106
76
Exit1-IR. A rising edge on JTCLK with JTMS low puts the contro ller in the Pause-IR state. If JTMS is high on the
rising edge of JTCLK, the controller enters the Update-IR state and terminates the scanning process.
Pause-IR. Shifting of the instruction register is halted temporarily. With JTMS high, a rising edge on JTCLK puts
the controller in the Exit2-I R state. T he controller rem ains in the Pause-IR state if JT MS is low during a risin g edge
on JTCLK.
Exit2-IR. A rising edge on JTCLK with JTMS high puts the controller in the Update-IR state. The controller loops
back to the Shift-IR state if JTMS is low during a rising edge of JTCLK in this state.
Update-IR. The instruction shifted into the instruction shift register is latched into the parallel output on the falling
edge of JT CLK as the controller e nters this state . Once latched, th is instruction b ecomes the cur rent instruction. A
rising edge on JT CLK with JTMS low puts the controller in the Run-Test-Idle state. With JTMS high, the con troller
enters the Select-DR-Scan state.
Figure 9-2. JTAG TAP Controller State Machine
Test-Logic-Reset
Run-Test/Idle
Select
DR-Scan
1
0
Capture-DR
1
0
Shift-DR
0
1
Exit1- DR
1
0
Pause-DR
1
Exit2-DR
1
Update-DR
0
0
1
Select
IR-Scan
1
0
Capture-IR
0
Shift-IR
0
1
Exit1-IR
1
0
Pause-IR
1
Exit2-IR
1
Update-IR
0
0
1
0
0
1
0
1
0
1
DS3106
77
9.3
JTAG Instruction Register and Instructions
The instr uc tion re gist er c on tains a s h if t r egister as wel l as a latc he d parallel outpu t and is 3 b its in length. When the
TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in
the Shift-IR state, a ris ing edge on J T CLK with JT MS lo w shifts data one s tage to ward the s erial o utput at J TDO. A
rising edge on J T C LK in th e Ex it 1-IR s tat e or th e Ex it2 -IR s tate with J T MS h ig h m oves t he c on trol ler to the U pdat e-
IR state. The falling edge of that same JTCLK latches the data in the instruction shift register to the instruction
parallel output. Table 9-1 shows the instructions supported by the DS3106 and their respective operational binary
codes.
Table 9-1. JTAG Instruction Codes
INSTRUCTIONS
SELECTED REGISTER
INSTRUCTION CODES
SAMPLE/PRELOAD
Boundary Sc an
010
BYPASS
Bypass
111
EXTEST
Boundary Sc an
000
CLAMP
Bypass
011
HIGHZ
Bypass
100
IDCODE
Device Identification
001
SAMPLE/PRELOAD. SAMPLE/RELOAD is a mandatory instruction for the IEEE 1149.1 specification. This
instruction supports two functions. First, the digital I/Os of the device can be sampled at the boundary scan
register, using the Capture-DR state, without interfering with the device’s normal operation. Second, data can be
shifted into the boundary scan register through JTDI using the Shift-DR state.
EXTEST. EX TEST allows tes ting of the interconnec tions to the device. W hen the EX TEST instruction is l atched in
the instruction register, the following actions occur: (1) Once the EXTEST instruction is enabled through the
Update-IR state, the parallel outputs of the digital output pins are driven. (2) The boundary scan register is
connected between JTDI and JTDO. (3) The Capture-DR state samples all digital inputs into the boundary scan
register.
BYPASS. W hen the B YPASS instruc tion is latche d int o the paral lel ins tructio n re gister, J TDI is connected to JTDO
through the 1-b it b ypass r egister. T his allo ws data to p ass from JT DI to JTDO without aff ecting th e device ’s norm al
operation.
IDCODE. When the IDCODE instruction is latched into the parallel instruction register, the device identification
register is selected. The device ID code is loaded into the device identification register on the rising edge of JTCLK,
following entry into the Capture-DR state. Shift-DR can be used to shift the ID code out serially through JTDO.
During Test-Logic-Reset, the ID code is forced into the instruction register’s parallel output.
HIGHZ. A ll digital o utputs a re placed into a high-im pedance state . The bypass register is connec ted betwee n JTDI
and JTDO.
CLAMP. All digital output pins output data from the boundary scan parallel output while connecting the bypass
register between JTDI and JTDO. The outputs do not change during the CLAMP instruction.
DS3106
78
9.4
JTAG Test Registers
IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. An
optional tes t regis ter, the identific ation re gister, h as be en includ ed in the de vice d esign. It is used with the ID CODE
instruction and the Test-Logic-Reset state of the TAP c ontrol ler.
Bypass Register. This is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions to
provide a short path between JTDI and JTDO.
Boundary Scan Register. This register c ontains a shift r egister pat h and a latch ed paralle l output f or contr ol cells
and digital I/O cells. The BSDL file is available on t he DS31 06 page of Microsemi’s website.
Identification Register. This register contains a 32-bit shift register and a 32-bit latched parallel output. It is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. The device
identification code for the DS3106 is shown in Table 9-2.
Table 9-2. JTAG ID Code
DEVICE REVISION DEVICE CODE MANUFACTURER CODE REQUIRED
DS3106 Consult factory 0000000010100100 00010100001 1
DS3106
79
10.
Electrical Char acteristics
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin with Res pect to VSS (except VDD)…….………………………………………..-0.3V to +5.5V
Supply Voltage Range (VDD) with Respect to VSS…….………….………………………………………..-0.3V to +1.98V
Supply Voltage Range (VDDIO) with Respect to VSS…………….………………………………………….-0.3V to +3.63V
Ambient Operating Temperature Range………………………………………………………..…-40°C to +85°C (Note 1)
Junction Operating Temperature Range…………………………………………………………………..-40°C to +125°C
Storage Temperature Range………………………………………………………………………………..-55°C to +125°C
Lead Temperature (soldering, 10s) ................................................................................................................... +300°C
Soldering Temperature (reflow)
Lead(Pb)-free .............................................................................................................................................. +260°C
Containing lead(Pb) ..................................................................................................................................... +240°C
Note 1:
Specifications to -40°C are guaranteed by design and not production tested.
Stresses beyond those listed under “Absol ute Maxi mum Ratings” may cause permanent damage to t he device. These are stress rati ngs only,
and functional operation of the device at these or any other condit i ons beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating condit i ons for extended periods may aff ect device. A mbient operati ng temperature range
when device is mounted on a four-layer JEDEC test board with no airflow.
Note: The typical values listed in the tables of Section 10 are not production tested.
10.1
DC Characteristics
Table 10-1. Recommended DC Operating Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage, Core
VDD
1.62
1.8
1.98
V
Supply Voltage, I/O
VDDIO
3.135
3.3
3.465
V
Ambient Temperature Range
TA
-40
+85
°C
Junction Temperature Range
TJ
-40
+125
°C
Table 10-2. DC Characteristics
(VDD = 1.8V ±10%; VDDIO = 3.3 V ±5%, TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current, Core IDD (Notes 2, 3) 151 185 mA
Supply Current, I/O IDDIO (Notes 2, 3) 37 50 mA
Supply Current from VDD_OC6 When
Output OC6 Enabled
IDDOC6 (Note 4) 16 mA
Input Capacitance CIN 5 pF
Output Capac ita nc e COUT 7 pF
Note 2:
12.800MHz clock appli ed to REFCLK and 19.44MHz clock applied to one CMOS/TTL input clock pin. Output clock pin OC3 at
19.44MHz driving 100pF load; all other inputs at V DDIO or grounded; all other outputs disabled and open.
Note 3:
TYP current measured at V
DD
= 1.8V and V
DDIO
= 3.3V, MAX current measured at V
DD
= 1.98V and V
DDIO
= 3.465V.
Note 4:
19.44MHz output clock frequency, drivi ng t he load shown in Figure 10-1. Enabled means MCR8:OC6SF ≠ 00.
DS3106
80
Table 10-3. CMOS/TTL Pins
(VDD = 1.8V ±10%; VDDIO = 3.3 V ±5%, TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2.0
5.5
V
Input Low Voltage
VIL
-0.3
+0.8
V
Input Leakage IIL (Note 1) -10 +10 µA
Input Leakage, Pins with Internal
Pullup Resistor (50kΩ typ)
IILPU (Note 1) -100 +10 µA
Input Leakage, Pins with Internal
Pulldown Resistor (50kΩ typ)
IILPD (Note 1) -10 +100 µA
Output Leak age (w hen Hig h-Z) ILO (Note 1) -10 +10 µA
Output High Voltage (IO = -4.0mA) VOH 2.4 VDDIO V
(Note 2) 2.0 VDDIOB
Output Low Volta ge (IO = +4.0mA) VOL 0 0.4 V
Note 1:
0V < V
IN
< V
DDIO
for all other digital inputs.
Note 2:
For OC1B to OC5B when V
DDIOB
= 2.5V.
Table 10-4. LVDS Output Pins
(VDD = 1.8V ±10%; VDDIO = 3.3 V ±5%, TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
VOHLVDS
(Note 1)
1.6
V
Output Low Volta ge
VOLLVDS
(Note 1)
0.9
V
Differential Output Voltage
VODLVDS
247
350
454
mV
Output Offset (Common Mode) Voltage
VOSLVDS
25°C (Note 1)
1.125
1.25
1.375
V
Difference in Magnitude of Output
Differential Voltage for Complementary
States
VDOSLVDS 25 mV
Note 1:
With 100Ω load across the differential outputs.
Note 2:
The differential outputs can easil y be interf aced t o LVDS, LVPECL, and CML inputs on neighboring ICs using a few external
passive components. See App Note HFAN-1.0 for det ails.
DS3106
81
Table 10-5. LVPECL Level-Compatible Output Pins
(VDD = 1.8V ±10%; VDDIO = 3.3 V ±5%, TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Output Voltage
VODPECL
595
700
930
mV
Output Offset (Common Mode) Voltage
VOSPECL
25°C (Note 1)
0.8
V
Difference in Magnitude of Output
Differential Voltage for Complementary
States
VDOSPECL 50 mV
Note 1:
With 100Ω load across the differential outputs.
Note 2:
The differential outputs can easil y be interf aced t o LVDS, LVPECL, and CML inputs on neighboring ICs using a few external
passive components. See App Note HFAN-1.0 for details.
Figure 10-1. Recommended Termination for LVDS Output Pins
DS3106
LVDS
OUTPUTS
OC6POS
OC6NEG
50
Ω
50
Ω
100Ω
(5%)
LVDS
RECEIVER
Figure 10-2. Recommended Termination for LVPECL-Compatible Output Pins
DS3106
LVPECL LEVEL-
COMPATIBLE
OUTPUTS
OC6POS
OC6NEG
50Ω
50Ω
82Ω
0.01µF
130Ω
130Ω
GND
3.3V
LVPECL
RECEIVER
82Ω
DS3106
82
10.2
Input Clock Ti mi ng
Table 10-6. Input Clock Timing
(VDD = 1.8V ±10%; VDDIO = 3.3 V ±5%, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Clock Duty Cycle 30 70 %
10.3
Output Clock Timing
Table 10-7. Input Clock to Output Clock Delay
INPUT
FREQUENCY OUTPUT
FREQUENCY
INPUT CLOCK EDGE TO
OUTPUT CLOCK EDGE
DELA Y (ns)
8kHz
8kHz
0 ± 1.5
6.48MHz
6.48MHz
0 ± 1.5
19.44MHz
19.44MHz
0 ± 1.5
25.92MHz
25.92MHz
0 ± 1.5
38.88MHz
38.88MHz
0 ± 1.5
51.84MHz
51.84MHz
0 ± 1.5
77.76MHz
77.76MHz
0 ± 1.5
155.52MHz
155.52MHz
0 ± 1.5
Table 10-8. Output Clock Phase Alignment, Frame-Sync Alignment Mode
OUTPUT
FREQUENCY
MFSYNC FALLING EDGE TO OUTPUT
CLOCK FALLING EDGE DELAY (ns)
8kHz (FSYNC)
0 ± 0.5
2kHz
0 ± 0.5
8kHz
0 ± 0.5
1.544MHz
0 ± 1.25
2.048MHz
0 ± 1.25
44.736MHz
-2.0 ± 1.25
34.368MHz
-2.0 ± 1.25
6.48MHz
-2.0 ± 1.25
19.44MHz
-2.0 ± 1.25
25.92MHz
-2.0 ± 1.25
38.88MHz
-2.0 ± 1.25
51.84MHz
-2.0 ± 1.25
77.76MHz
-2.0 ± 1.25
155.52MHz
-2.0 ± 1.25
311.04MHz
-2.0 ± 1.25
DS3106
83
10.4
SPI Inter f ace Timing
Table 10-9. SPI Interface Timing
(VDD = 1.8V ±10%; VDDIO = 3.3 V ±5%, TA = -40°C to +85°C.) (See Figure 10-3.)
PARAMETER (Note 1)
SYMBOL
MIN
TYP
MAX
UNITS
SCLK Frequency f
BUS
6 MHz
SCLK Cycle Time tCYC 100 ns
CS Setup to First SCLK Edge tSUC 15 ns
CS Hold Time After Last SCLK Edge t
HDC
15 ns
SCLK High Time t
CLKH
50 ns
SCLK Low Time t
CLKL
50 ns
SDI Data Setup Time t
SUI
5 ns
SDI Data Hold Time t
HDI
15 ns
SDO Enable Time (High-Z to Output Active) t
EN
0 ns
SDO Disable Time (Output Active to High-Z) t
DIS
25 ns
SDO Data Valid Time t
DV
50 ns
SDO Data Hold Time After Update SCLK Edge t
HDO
5 ns
Note 1:
All timing is specifi ed with 100pF load on all SPI pins.
DS3106
84
Figure 10-3. SPI Interface Timing Diagram
CS
SCLK,
CPOL=0
SCLK,
CPOL=1
t
SUI
t
HDI
SDI
t
CYC
t
SUC
t
CLKH
t
CLKL
t
CLKL
t
CLKH
t
HDC
SDO t
EN
t
DV
t
HDO
t
DIS
CPHA = 0
CPHA = 1
CS
SCLK,
CPOL=0
SCLK,
CPOL=1
t
CYC
t
SUC
t
CLKH
t
CLKL
t
CLKL
t
HDC
t
SUI
t
HDI
SDI
SDO t
EN
t
DV
t
HDO
t
DIS
t
CLKH
DS3106
85
10.5
JTAG Interface Timing
Table 10-10. JTAG Interface Timing
(VDD = 1.8V ±10%; VDDIO = 3.3 V ±5%, TA = -40°C to +85°C.) (See Figure 10-4.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
JTCLK Clock Period t1 1000 ns
JTCLK Clock High/Low Time (Note 1) t2/t3 50 500 ns
JTCLK to JTDI, JTMS Setup Time t4 50 ns
JTC LK to JTDI, JTMS Hold Time t5 50 ns
JTCLK to JTDO Delay t6 2 50 ns
JTCLK to JTDO High-Z Delay (Note 2) t7 2 50 ns
JTRST Width Low Time t8 100 ns
Note 1:
Clock can be stopped high or low.
Note 2:
Not tested during production t est.
Figure 10-4. JTAG Timing Diagram
t1
JTDO
t4
t5
t2
t3
t7
JTDI, JTMS, JTRST
t6
JTRST
t8
JTCLK
DS3106
86
10.6
Reset Pi n Timing
Table 10-11. Reset Pin Timing
(VDD = 1.8V ±10%; VDDIO = 3.3 V ±5%, TA = -40°C to +85°C.) (See Figure 10-5.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
RST Low Time (Note 1) t1 1000 ns
SONSDH, IPF[2:0], O3F[2:0], O6F[2:0] Setup Time to RST t2
0 ns
SONSDH, IPF[2:0], O3F[2:0], O6F[2:0] Hold Time from RST t3 50 ns
Note 1:
RST should be held low while the REFCLK oscillator stabilizes. It is recommended to force RST low during power-up. The
1000ns minimum time appli es if the RST pulse is applied any time after the device has powered up and the osci llat or has
stabilized.
Figure 10-5. Reset Pin Timing Diagram
RST
SONSDH
OxF[2:0]
IPF[2:0]
VALID
X
X
t2
t3
t1
DS3106
87
11.
Pin Ass ignments
Table 11-1 lists pin assignments sorted in alphabetical order by pin name. Figure 11-1 shows pin assignments
arranged by pin number.
Table 11-1. Pin Assignments Sorted by Signal Name
PIN NAME PIN NUMBER PIN NAME PIN NUMBER
AVDD_DL
59
N.C.
23–26
AVDD_PLL1
4
O3F0
35
AVDD_PLL2
7
MFSYNC
18
AVDD_PLL3
9
O3F1/SRFAIL
38
AVDD_PLL4
11
O3F2/LOCK
36
AVSS_DL
55
O6F0/GPIO1
45
AVSS_PLL1
3
O6F1/GPIO2
46
AVSS_PLL2
8
O6F2/GPIO3
63
AVSS_PLL3
10
OC3
56
AVSS_PLL4
12
OC6NEG
20
CPHA
42
OC6POS
19
CS
44
REFCLK
6
FSYNC
17
RST
48
IC3
29
SCLK
47
IC4
30
SDI
43
IPF0
28
SDO
52
IPF1
33
SONSDH/GPIO4
64
IPF2
34
SRCSW
13
INTREQ/LOS
5
TEST
2
JTCLK
49
VDD
27, 39, 57, 58
JTDI
51
VDDIO
14, 32, 54, 61
JTDO
50
VDD_OC6
22
JTMS 41 VSS
1, 15, 16, 31, 40, 53,
60, 62
JTRST
37
VSS_OC6
21
DS3106
88
Figure 11-1. P in As sign me nt Diagr a m
DS3106
RST
SCLK
O6F1/GPIO2
O6F0/GPIO1
CS
SDI
CPHA
JTMS
VSS
VDD
O3F1/SRFAIL
JTRST
O3F2/LOCK
O3F0
IPF2
IPF1
SONSDH/GPIO4
O6F2/GPIO3
VSS
VDDIO
VSS
AVDD_DL
VDD
VDD
OC3
AVSS_DL
VDDIO
VSS
SDO
JTDI
JTDO
JTCLK
VSS
TEST
AVSS_PLL1
AVDD_PLL1
INTREQ/LOS
REFCLK
AVDD_PLL2
AVSS_PLL2
AVDD_PLL3
AVSS_PLL3
AVDD_PLL4
AVSS_PLL4
SRCSW
VDDIO
VSS
VSS
FSYNC
MFSYNC
OC6POS
OC6NEG
VSS_OC6
VDD_OC6
NC
NC
NC
NC
VDD
IPF0
IC3
IC4
VSS
VDDIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32 49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
DS3106
89
12.
Package Information
For the latest pack age outline information and land patterns, contact Microsem i timing products technical support.
Note that a “+” , “#”, or “ -” in the pack age c ode indicat es RoHS status onl y. Pack age drawings m ay show a diff erent
suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
64 LQFP C64-1 21-0083 90-0141
13.
Thermal I nformation
Table 13-1. LQFP Package Thermal Properties, Natural Convection
PARAMETER
MIN
TYP
MAX
Ambient Temperature (Note 1)
-40°C
+85°C
Junction Temperature
-40°C
+125°C
Theta-JA (θJA) (Note 2)
45.4°C/W
Psi-JB
23.8°C/W
Psi-JT
0.3°C/W
Note 1:
The package is mounted on a four-layer JEDEC standard test board with no airflow and dissipati ng maximum power.
Note 2:
Theta-JA (θ
JA
) is the junction to ambient thermal resistance, when the package is mounted on a four-layer JEDEC standard
test board with no airflow and dissipating maximum power.
Table 13-2. LQFP Theta-JA (
θ
JA) vs. Airflow
FORCED AIR (METERS PER SECOND)
THETA-JA (θJA)
0
45.4°C/W
1
37.3°C/W
2.5
34.5°C/W
DS3106
90
14.
Acronyms and A bbreviati ons
AIS Alarm Indication Signal
AMI Alternate Mark Inversion
APLL Analog Phase-Locked Loop
BITS Building Integrated Timing Supply
BPV Bipolar Violation
DFS Digital Frequency Synthesis
DPLL Digital Phase-Locked Loop
ESF Ext end ed Su perf r am e
EXZ Excessive Zeros
GbE Gigab it Eth er net
I/O Input/Output
LOS Loss of Signal
LVDS Low-Voltage Dif ferential Signal
LVPECL Low-Volt age Positive Em itter -Coup led Lo gic
MTIE Maximum Time Interval Error
OCXO Oven-Controlled Crystal Oscillator
OOF Out of Frame Alignment
PBO Phas e Buil d-Out
PFD Phas e/Fr e qu ency Detector
PLL Phase-Locked Loop
ppb Parts per Billion
ppm Parts per Million
pk-pk Peak-to-Peak
RMS Root-Mean-Square
RAI Remote Alarm Indication
RO Read-Only
R/W Read/Write
SDH Synchronous Digital Hierarchy
SEC SDH Equipment Clock
SETS Synchronous Equipment Timing Source
SF Superframe
SONET Synchronous Optical Network
SSM Synchronization Status Message
SSU Synchronization Supply Unit
STM Synchronous Transport Module
TDEV Time Deviation
TCXO Temperature-Compensated Crystal Oscillator
UI Unit Interva l
UIP-P Unit Interval, Peak -to-Peak
XO Crystal Oscillator
DS3106
91
15.
Data Sheet Rev ision Hi story
REVISION
DATE DESCRIPTION
121407 Initial data sheet release.
100108 In Section 7.7.8, corrected the PLL bandwidth range to have the correct range of 18Hz to 400Hz to match the
register descriptions for T0ABW and T0LBW
030909 Corrected several frequencies in Table 7-16 and Table 7-17 t o match act ual dev ic e operation.
2009-05 In Section 8, added note indicating systems must be able to access entire address range 0-1FFh.
2010-08
In Figure 9-1 corrected pullup resistors values to 50kΩ.
In PHMON.NW bit description, added "(TEST1.D180 = 0)".
In Table 6-3 edited SRFAIL pin description to indicate state is high impedance when MCR10.SRFPIN = 0.
Edited MCR10.SRFPIN decription to say this also.
In Section 7.7.5 delet ed sent e nce that said the hard and soft limits have hysteresis.
Replaced the term "floating" with "unconnected" in several places .
Updated soldering temperature information in Section 10.
2012-04 Reformatted for Microsemi. No content change.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo
CA 92656 USA
Within the USA: +1 (949) 380
-6100
Sales: +1 (949) 380
-6136
Fax
: +1 (949) 215-4996
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
solutions for: aeros pace, defense and security; enterprise and communications; and in dust rial
and alternative energy markets. Products include high
-performance, high-
reliabi lity analog and
RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and
complete subsystems. Microsemi is headquartered in Aliso
Viejo, Calif.
Learn more at
www.microsemi.com
.
© 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of
Microsemi
Cor poratio n. All other t rade mark s and se rvic e m arks are the property o f their respective owners.
