MH16S64AMA-10 - Mitsubishi Electric Semiconductor

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

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MIT-DS-0127-0.0

DESCRIPTION

The MH16S64AMA is 16777216 - word by 64-bit

Synchronous DRAM module. This consists of sixteen

industry standard 16Mx4 Synchronous DRAMs in

TSOP and one industory standard EEPROM in

TSSOP.

The mounting of TSOP on a card edge Dual Inline

package provides any application where high

densities and large quantities of memory are

required.

This is a socket type - memory modules, suitable for

easy interchange or addition of modules.

FEATURES

Clock frequency 125MHz/100MHz/83MHz

single 3.3V±0.3V power supply

Fully synchronous operation referenced to clock rising

edge

Burst length- 1/2/4/8(programmable)

Dual bank operation controlled by BA0,1(Bank Address)

Frequency

-12 83MHz

/CAS latency- 2/3(programmable)

APPLICATION

main memory or graphic memory in computer systems

Auto precharge / All bank precharge controlled by A10

Burst type- sequential / interleave(programmable)

Column access - random

LVTTL Interface

Auto refresh and Self refresh

4096 refresh cycle /64ms

CLK Access Time

8ns(CL=3)

-8 125MHz 6ns(CL=3)

-10 100MHz 8ns(CL=3)

1pin

10pin

11pin

40pin

41pin

84pin

Front side

85pin

94pin

95pin

124pin

125pin

168pin

Back side

Utilizes industry standard 16M x 4 Synchronous DRAMs

TSOP and industry standard EEPROM in TSSOP

168-pin (84-pin dual in-line package)

(Component SDRAM)

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

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MIT-DS-0127-0.0

PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME

1VSS 43 VSS 85 VSS 127 VSS

2 DQ0 44 NC 86 DQ32 128 CKE0

3 DQ1 45 /S2 87 DQ33 129 NC

4 DQ2 46 DQMB2 88 DQ34 130 DQMB6

5 DQ3 47 DQMB3 89 DQ35 131 DQMB7

6 VDD 48 NC 90 VDD 132 NC

7 DQ4 49 VDD 91 DQ36 133 VDD

8 DQ5 50 NC 92 DQ37 134 NC

9 DQ6 51 NC 93 DQ38 135 NC

10 DQ7 52 NC 94 DQ39 136 NC

11 DQ8 53 NC 95 DQ40 137 NC

12 VSS 54 VSS 96 VSS 138 VSS

13 DQ9 55 DQ16 97 DQ41 139 DQ48

14 DQ10 56 DQ17 98 DQ42 140 DQ49

15 DQ11 57 DQ18 99 DQ43 141 DQ50

16 DQ12 58 DQ19 100 DQ44 142 DQ51

17 DQ13 59 VDD 101 DQ45 143 VDD

18 VDD 60 DQ20 102 VDD 144 DQ52

19 DQ14 61 NC 103 DQ46 145 NC

20 DQ15 62 NC 104 DQ47 146 NC

21 NC 63 NC 105 NC 147 NC

22 NC 64 VSS 106 NC 148 VSS

23 VSS 65 DQ21 107 VSS 149 DQ53

24 NC 66 DQ22 108 NC 150 DQ54

25 NC 67 DQ23 109 NC 151 DQ55

26 VDD 68 VSS 110 VDD 152 VSS

27 /WE0 69 DQ24 111 /CAS 153 DQ56

28 DQMB0 70 DQ25 112 DQMB4 154 DQ57

29 DQMB1 71 DQ26 113 DQMB5 155 DQ58

30 /S0 72 DQ27 114 NC 156 DQ59

31 NC 73 VDD 115 /RAS 157 VDD

32 VSS 74 DQ28 116 VSS 158 DQ60

33 A0 75 DQ29 117 A1 159 DQ61

34 A2 76 DQ30 118 A3 160 DQ62

35 A4 77 DQ31 119 A5 161 DQ63

36 A6 78 VSS 120 A7 162 VSS

37 A8 79 CK2 121 A9 163 CK3

38 A10 80 NC 122 BA0 164 NC

39 BA1 81 NC 123 A11 165 SA0

40 VDD 82 SDA 124 VDD 166 SA1

41 VDD 83 SCL 125 CK1 167 SA2

42 CK0 84 VDD 126 NC 168 VDD

NC = No Connection

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

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MIT-DS-0127-0.0

Block Diagram

CK0

SERIAL PD

SCL SDA

SA0 SA1 SA2

A0 A1 A2

Vcc

Vss

D0 - D15

/S0

/S2

DQMB0 DQMB4

DQMB1 DQMB5

DQMB2 DQMB6

DQMB3 DQMB7

I/O 0

I/O 1

I/O 2

I/O 3

DQM /CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

CKE0 D0 - D7

/RAS D0 - D15

/CAS D0 - D15

/WE D0 - D15

BA0,BA1,A<11:0> D0 - D15

CK1

CK,DQ=10Ω

4SDRAMs

I/O 0

I/O 1

I/O 2

I/O 3

DQM /CS

I/O 0

I/O 1

I/O 2

I/O 3

DQM /CS

I/O 0

I/O 1

I/O 2

I/O 3

DQM /CS

CK2

CK3 4SDRAMs

4SDRAMs

I/O 0

I/O 1

I/O 2

I/O 3

DQM /CS

I/O 0

I/O 1

I/O 2

I/O 3

DQM /CS

I/O 0

I/O 1

I/O 2

I/O 3

DQM /CS

I/O 0

I/O 1

I/O 2

I/O 3

DQM /CS

I/O 0

I/O 1

I/O 2

I/O 3

DQM /CS

I/O 0

I/O 1

I/O 2

I/O 3

DQM /CS

I/O 0

I/O 1

I/O 2

I/O 3

DQM /CS

D10

I/O 0

I/O 1

I/O 2

I/O 3

DQM /CS

D11

I/O 0

I/O 1

I/O 2

I/O 3

DQM /CS

I/O 0

I/O 1

I/O 2

I/O 3

DQM /CS

I/O 0

I/O 1

I/O 2

I/O 3

DQM /CS

I/O 0

I/O 1

I/O 2

I/O 3

DQM /CS

I/O 0

I/O 1

I/O 2

I/O 3

DQM /CS

D12

I/O 0

I/O 1

I/O 2

I/O 3

DQM /CS

D13

I/O 0

I/O 1

I/O 2

I/O 3

DQM /CS

D14

I/O 0

I/O 1

I/O 2

I/O 3

DQM /CS

D15

CKE1 D8 - D15

3.3V

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

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MIT-DS-0127-0.0

Serial Presence Detect Table I

Byte Function described SPD enrty data SPD DATA(hex)

0 Defines # bytes written into serial memory at module mfgr 128 80

1 Total # bytes of SPD memory device 256 Bytes 08

2 Fundamental memory type SDRAM 04

3 # Row Addresses on this assembly A0-A11 0C

4 # Column Addresses on this assembly A0-A9 0A

5 # Module Banks on this assembly 1BANK 01

6 Data Width of this assembly... x64 40

7 ... Data Width continuation 0 00

8 Voltage interface standard of this assembly LVTTL 01

9 SDRAM Cycletime at Max. Supported CAS Latency (CL). -8 8ns 80

Cycle time for CL=3 -10 10ns A0

-12 12ns C0

10 SDRAM Access from Clock -8 6ns 60

tAC for CL=3 -10 8ns 80

-12 8ns 80

11 DIMM Configuration type (Non-parity,Parity,ECC) Non-PARITY 00

12 Refresh Rate/Type self refresh(15.625uS) 80

13 SDRAM width,Primary DRAM x4 04

14 Error Checking SDRAM data width N/A 00

15 Minimum Clock Delay,Back to Back Random Column Addresses 1 01

16 Burst Lengths Supported 1/2/4/8 0F

17 # Banks on Each SDRAM device 4bank 04

18 CAS# Latency CL=2/3 06

19 CS# Latency 0 01

20 Write Latency 0 01

21 SDRAM Module Attributes non-buffered,non-registered 00

22 SDRAM Device Attributes:General Precharge All,Auto precharge 06

23 SDRAM Cycle time(2nd highest CAS latency) -8 13ns D0

Cycle time for CL=2 -10 14ns E0

-12 15ns F0

24 SDRAM Access form Clock(2nd highest CAS latency) -8 7ns 70

tAC for CL=2 -10 8ns 80

-12 9ns 90

25 SDRAM Cycle time(3rd highest CAS latency) -8 N/A 00

Cycle time for CL= -10 N/A 00

-12 N/A 00

26 SDRAM Access form Clock(3rd highest CAS latency) -8 N/A 00

tAC for CL= -10 N/A 00

-12 N/A 00

27 Precharge to Active Minimum -8 24ns 18

-10 30ns 1E

-12 30ns 1E

28 Row Active to Row Active Min. -8 16ns 10

-10 20ns 14

-12 24ns 18

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

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MIT-DS-0127-0.0

29 RAS to CAS Delay Min -8 24ns 18

-10 30ns 1E

-12 30ns 1E

30 Active to Precharge Min -8 56ns 38

-10 60ns 3C

-12 70ns 46

31 Density of each bank on module 128MByte 20

32-61 Superset Information (may be used in future) option 00

62 SPD Revision rev 1 01

63 Checksum for bytes 0-62 Check sum for -8 43

Check sum for -10 B7

Check sum for -12 05

64-71 Manufactures Jedec ID code per JEP-108E MITSUBISHI 1CFFFFFFFFFFFFFF

72 Manufacturing location Miyoshi,Japan 01

Tajima,Japan 02

NC,USA 03

Germany 04

73-90 Manufactures Part Number MH16S64AMA-8 4D483136533634414D412D382D38202020202020

MH16S64AMA-10 4D483136533634414D412D313031302020202020

MH16S64AMA-12 4D483136533634414D412D313231322020202020

91-92 Revision Code PCB revision rrrr

93-94 Manufacturing date year/week code yyww

95-98 Assembly Serial Number serial number ssssssss

99-125 Manufacture Specific Data option 00

126 Intetl specification frequency 66MHz 66

127 Intel specification CAS# Latency support CL=3: 04H, CL=2/3: 06H 06

128+ Unused storage locations open 00

Serial Presence Detect Table II

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

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MIT-DS-0127-0.0

PIN FUNCTION

Input Master Clock:All other inputs are referenced to the rising

edge of CK

CKE0 Input

Clock Enable:CKE controls internal clock.When CKE is

low,internal clock for the following cycle is ceased. CKE is

also used to select auto / self refresh. After self refresh

mode is started, CKE E becomes asynchronous input.Self

refresh is maintained as long as CKE is low.

(/S0,/S2) Input Chip Select: When /S is high,any command means

No Operation.

/RAS,/CAS,/WE Input Combination of /RAS,/CAS,/WE defines basic commands.

A0-11 Input

A0-11 specify the Row/Column Address in conjunction with

BA.The Row Address is specified by A0-11.The Column

Address is specified by A0-9.A10 is also used to indicate

precharge option.When A10 is high at a read / write

command, an auto precharge is performed. When A10 is

high at a precharge command, both banks are precharged.

BA0,1 Input Bank Address:BA0,1 is not simply BA.BA specifies the

bank to which a command is applied.BA0,1 must be set

with ACT,PRE,READ,WRITE commands

DQ0-63 Input/Output Data In and Data out are referenced to the rising edge of

DQMB0-7 Input Din Mask/Output Disable:When DQMB is high in burst

write.Din for the current cycle is masked.When DQMB is high

in burst read,Dout is disabled at the next but one cycle.

Vdd,Vss Power Supply Power Supply for the memory mounted module.

SCL

SDA

SA0-3

Input

Output

Input

Serial clock for serial PD

Serial data for serial PD

Address input for serial PD

(CK0 ~ CK3)

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

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MIT-DS-0127-0.0

BASIC FUNCTIONS

/S Chip Select : L=select, H=deselect

/RAS Command

/CAS Command

/WE Command

CKE Refresh Option @refresh

command

A10 Precharge Option @precharge or read/write

command

define basic commands

The MH16S64AMA provides basic functions,bank(row)activate,burst read / write,

bank(row)precharge,and auto / self refresh.

Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In

addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and

precharge option,respectively.

To know the detailed definition of commands please see the command truth table.

Activate(ACT) [/RAS =L, /CAS = /WE =H]

Read(READ) [/RAS =H,/CAS =L, /WE =H]

Write(WRITE) [/RAS =H, /CAS = /WE =L]

Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]

Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]

ACT command activates a row in an idle bank indicated by BA.

READ command starts burst read from the active bank indicated by BA.First output

data appears after /CAS latency. When A10 =H at this command,the bank is

deactivated after the burst read(auto-precharge,READA).

WRITE command starts burst write to the active bank indicated by BA. Total data

length to be written is set by burst length. When A10 =H at this command, the bank is

deactivated after the burst write(auto-precharge,WRITEA).

PRE command deactivates the active bank indicated by BA. This command also

terminates burst read / write operation. When A10 =H at this command, both banks are

deactivated(precharge all, PREA).

PEFA command starts auto-refresh cycle. Refresh address including bank address are

generated internally. After this command, the banks are precharged automatically.

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

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MIT-DS-0127-0.0

COMMAND TRUTH TABLE

COMMAND MNEMONIC CK

n-1 CK

n/S /RAS /CAS /WE BA A10 A0-9

,A11

Deselect DESEL H X H X X X X X X

No Operation NOP H X L H H H X X X

Row Adress Entry &

Bank Activate ACT H X L L H H V V V

Single Bank Precharge PRE H X L L H L V L X

Precharge All Bank PREA H X L L H L V H X

Column Address Entry

& Write WRITE H X L LH H L V L V

Column Address Entry

& Write with Auto-

Precharge WRITEA H X L H L L V H V

Column Address Entry

& Read READ H X L H L H V L V

Column Address Entry

& Read with Auto

Precharge READA H X L H L H V H V

Auto-Refresh REFA H H L HL L H X X X

Self-Refresh Entry REFS H L L L L H X X X

Self-Refresh Exit REFSX L H H LX XXXXX

L H L H H H X X X

Burst Terminate TERM H X L H H L X X X

Mode Register Set MRS H X L L L L L L V*1

H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number

NOTE:

1.A7-9 = 0, A0-6 = Mode Address

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

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MIT-DS-0127-0.0

Current State /S /RAS /CAS /WE Address Command Action

IDLE H X X X X DESEL NOP

L H H H X NOP NOP

L H H L BA TBST ILLEGAL*2

L H L X BA,CA,A10 READ/WRITE ILLEGAL*2

L L H H BA,RA ACT Bank Active,Latch RA

L L H L BA,A10 PRE/PREA NOP*4

L L L H X REFA Auto-Refresh*5

L L L L Op-Code,

Mode-Add MRS Mode Register Set*5

ROW ACTIVE H X X X X DESEL NOP

L H H H X NOP NOP

L H H L BA TBST NOP

L H L H BA,CA,A10 READ/READA Begin Read,Latch CA,

Determine Auto-Precharge

L H L L BA,CA,A10 WRITE/

WRITEA Begin Write,Latch CA,

Determine Auto-Precharge

L L H H BA,RA ACT Bank Active/ILLEGAL*2

L L H L BA,A10 PRE/PREA Precharge/Precharge All

L L L H X REFA ILLEGAL

L L L L Op-Code,

Mode-Add MRS ILLEGAL

READ H X X X X DESEL NOP(Continue Burst to END)

L H H H X NOP NOP(Continue Burst to END)

L H H L BA TBST Terminate Burst

L H L H BA,CA,A10 READ/READA Terminate Burst,Latch CA,

Begin New Read,Determine

Auto-Precharge*3

L H L L BA,CA,A10 WRITE/WRITEA Terminate Burst,Latch CA,

Begin Write,Determine Auto-

Precharge*3

L L H H BA,RA ACT Bank Active/ILLEGAL*2

L L H L BA,A10 PRE/PREA Terminate Burst,Precharge

L L L H X REFA ILLEGAL

L L L L Op-Code,

Mode-Add MRS ILLEGAL

FUNCTION TRUTH TABLE

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

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MIT-DS-0127-0.0

FUNCTION TRUTH TABLE(continued)

Current State /S /RAS /CAS /WE Address Command Action

WRITE H X X X X DESEL NOP(Continue Burst to END)

L H H H X NOP NOP(Continue Burst to END)

L H H L BA TBST Terminate Burst

L H L H BA,CA,A10 READ/READA Terminate Burst,Latch CA,

Begin Read,Determine Auto-

Precharge*3

L H L L BA,CA,A10 WRITE/

WRITEA

Terminate Burst,Latch CA,

Begin Write,Determine Auto-

Precharge*3

L L H H BA,RA ACT Bank Active/ILLEGAL*2

L L H L BA,A10 PRE/PREA Terminate Burst,Precharge

L L L H X REFA ILLEGAL

L L L L Op-Code,

Mode-Add MRS ILLEGAL

READ with H X X X X DESEL NOP(Continue Burst to END)

AUTO L H H H X NOP NOP(Continue Burst to END)

PRECHARGE L H H L BA TBST ILLEGAL

L H L H BA,CA,A10 READ/READA ILLEGAL

L H L L BA,CA,A10 WRITE/

WRITEA ILLEGAL

L L H H BA,RA ACT Bank Active/ILLEGAL*2

L L H L BA,A10 PRE/PREA ILLEGAL*2

L L L H X REFA ILLEGAL

L L L L Op-Code,

Mode-Add MRS ILLEGAL

WRITE with H X X X X DESEL NOP(Continue Burst to END)

AUTO L H H H X NOP NOP(Continue Burst to END)

PRECHARGE L H H L BA TBST ILLEGAL

L H L H BA,CA,A10 READ/READA ILLEGAL

L H L L BA,CA,A10 WRITE/

WRITEA ILLEGAL

L L H H BA,RA ACT Bank Active/ILLEGAL*2

L L H L BA,A10 PRE/PREA ILLEGAL*2

L L L H X REFA ILLEGAL

L L L L Op-Code,

Mode-Add MRS ILLEGAL

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

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MIT-DS-0127-0.0

FUNCTION TRUTH TABLE(continued)

Current State /S /RAS /CAS /WE Address Command Action

PRE - H X X X X DESEL NOP(Idle after tRP)

CHARGING L H H H X NOP NOP(Idle after tRP)

L H H L BA TBST ILLEGAL*2

L H L X BA,CA,A10 READ/WRITE ILLEGAL*2

L L H H BA,RA ACT ILLEGAL*2

L L H L BA,A10 PRE/PREA NOP*4(Idle after tRP)

L L L H X REFA ILLEGAL

L L L L Op-Code,

Mode-Add MRS ILLEGAL

ROW H X X X X DESEL NOP(Row Active after tRCD

ACTIVATING L H H H X NOP NOP(Row Active after tRCD

L H H L BA TBST ILLEGAL*2

L H L X BA,CA,A10 READ/WRITE ILLEGAL*2

L L H H BA,RA ACT ILLEGAL*2

L L H L BA,A10 PRE/PREA ILLEGAL*2

L L L H X REFA ILLEGAL

L L L L Op-Code,

Mode-Add MRS ILLEGAL

WRITE RE- H X X X X DESEL NOP

COVERING L H H H X NOP NOP

L H H L BA TBST ILLEGAL*2

L H L X BA,CA,A10 READ/WRITE ILLEGAL*2

L L H H BA,RA ACT ILLEGAL*2

L L H L BA,A10 PRE/PREA ILLEGAL*2

L L L H X REFA ILLEGAL

L L L L Op-Code,

Mode-Add MRS ILLEGAL

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

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MIT-DS-0127-0.0

FUNCTION TRUTH TABLE(continued)

Current State /S /RAS /CAS /WE Address Command Action

RE- H X X X X DESEL NOP(Idle after tRC)

FRESHING L H H H X NOP NOP(Idle after tRC)

L H H L BA TBST ILLEGAL

L H L X BA,CA,A10 READ/WRITE ILLEGAL

L L H H BA,RA ACT ILLEGAL

L L H L BA,A10 PRE/PREA ILLEGAL

L L L H X REFA ILLEGAL

L L L L Op-Code,

Mode-Add MRS ILLEGAL

MODE H X X X X DESEL NOP(Idle after tRSC)

SETTING L H H L BA TBST ILLEGAL

L H L X BA,CA,A10 READ/WRITE ILLEGAL

L L H H BA,RA ACT ILLEGAL

L L H L BA,A10 PRE/PREA ILLEGAL

L L L H X REFA ILLEGAL

L L L L Op-Code,

Mode-Add MRS ILLEGAL

ABBREVIATIONS:

H = Hige Level, L = Low Level, X = Don't Care

BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation

NOTES:

1. All entries assume that CKE was High during the preceding clock cycle and the current

clock cycle.

2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,

depending on the state of that bank.

3. Must satisfy bus contention, bus turn around, write recovery requirements.

4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.

5. ILLEGAL if any bank is not idle.

ILLEGAL = Device operation and / or date-integrity are not guaranteed.

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

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MIT-DS-0127-0.0

FUNCTION TRUTH TABLE FOR CKE

Current State CK

n-1 CK

n/S /RAS /CAS /WE Add Action

SELF - H X X X X X X INVALID

REFRESH*1 L H H X X X X Exit Self-Refresh(Idle after tRC)

L H L H H H X Exit Self-Refresh(Idle after tRC)

L H L H H L X ILLEGAL

L H L H L X X ILLEGAL

L H L L X X X ILLEGAL

L L X X X X X NOP(Maintain Self-Refresh)

POWER H X X X X X X INVALID

DOWN L H X X X X X Exit Power Down to Idle

L L X X X X X NOP(Maintain Self-Refresh)

ALL BANKS H H X X X X X Refer to Function Truth Table

IDLE*2 H L L L L H X Enter Self-Refresh

H L H X X X X Enter Power Down

H L L H H H X Enter Power Down

H L L H H L X ILLEGAL

H L L H L X X ILLEGAL

H L L L X X X ILLEGAL

L X X X X X X Refer to Current State = Power Down

ANY STATE H H X X X X X Refer to Function Truth Table

other than H L X X X X X Begin CK0 Suspend at Next Cycle*3

listed above L H X X X X X Exit CK0 Suspend at Next Cycle*3

L L X X X X X Maintain CK0 Suspend

ABBREVIATIONS:

H = High Level, L = Low Level, X = Don't Care

NOTES:

1. CKE Low to High transition will re-enable CK and other inputs asynchronously.

A minimum setup time must be satisfied before any command other than EXIT.

2. Power-Down and Self-Refresh can be entered only form the All banks idle State.

3. Must be legal command.

MH16S64AMA -8,-10,-12

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MIT-DS-0127-0.0

SIMPLIFIED STATE DIAGRAM

ROW

ACTIVE

IDLE

PRE

CHARGE

AUTO

REFRESH

SELF

REFRESH

MODE

SET

POWER

DOWN

READ

READA

WRITE

WRITEA

READ

SUSPEND

READA

SUSPEND

WRITE

SUSPEND

WRITEA

SUSPEND

POWER

CLK

SUSPEND

CKEL

CKEH

CKEL

CKEH

CKEL

CKEH

CKEL

CKEH

ACT

REFA

REFS

REFSX

CKEL

CKEH

MRS

CKEL

CKEH

WRITE READ

WRITEA

WRITEA READA

WRITE READ

PRE

READA

WRITEA READA

PRE PRE

PRE

POWER

APPLIED

Automatic Sequence

Command Sequence

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MIT-DS-0127-0.0

POWER ON SEQUENCE

Before starting normal operation, the following power on sequence is necessary to prevent a

SDRAM from damaged or malfunctioning.

1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP

condition at the inputs.

2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 500É s.

3. Issue precharge commands for all banks. (PRE or PREA)

4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

After these sequence, the SDRAM is idle state and ready for normal operation.

MODE REGISTER

R:Reserved for Future Use

/RAS

/CAS

/WE

BA0,1 A11-0

Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode

be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is

ready for new command.

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

BURST

LENGTH

BT= 0 BT= 1

BURST

TYPE SEQUENTIAL

INTERLEAVED

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0

0 0 0 0 0 LTMODE BT BL

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

LATENCY

MODE

/CAS LATENCY

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MIT-DS-0127-0.0

Command

Address

Read

Q0 Q1 Q2 Q3

Write

D0 D1 D2 D3

/CAS Latency Burst Length Burst Length

Burst Type

CL= 3

BL= 4

A2 A1 A0

Initial Address BL

Sequential Interleaved

Column Addressing

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

- 0 0

- 0 1

- 1 0

- 1 1

- - 0

0123456701234567

1234567010325476

2345670123016745

3456701232107654

4567012345670123

5670123454761032

6701234567452301

7 0 1 2

0 1 2 3

1 2 3 0

2 3 0 1

3 0

0 1

7 6 5 4

0 1 2 3

1 0 3 2

2 3 0 1

3 2

0 1

- - 1

1 2

1 0

3 4 5 6 3 2 1 0

1 0

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MIT-DS-0127-0.0

Bank Activation and Precharge All (BL=4, CL=3)

Command

A0-9,11

A10

BA0,1

ACT

READ

Qa0 Qa1 Qa2 Qa3

ACT

PRE

tRRD

tRCD 1

ACT

Precharge all

tRAS tRP

OPERATION DESCRIPTION

BANK ACTIVATE

The SDRAM has two independent banks. Each bank is activated by the ACT command with

the bank address(BA0,1). A row is indicated by the row address A11-0. The minimum

activation interval between one bank and the other bank is tRRD.

PRECHARGE

The PRE command deactivates indicated by BA. When both banks are active, the precharge

all command(PREA,PRE + A10=H) is available to deactivate them at the same time. After tRP

from the precharge, an ACT command can be issued.

READ

After tRCD from the bank activation, a READ command can be issued. 1st output date is

available after the /CAS Latency from the READ, followed by (BL-1) consecutive date when

the Burst Length is BL. The start address is specified by A9-0, and the address sequence of

burst data is defined by the Burst Type. A READ command may be applied to any active bank,

so the row precharge time(tRP) can be hidden behind continuous output data(in case of BL=8)

by interleaving the dual banks. When A10 is high at a READ command, the

auto-precharge(READA) is performed. Any command (READ, WRITE, PRE, ACT) to the

same bank is inhibited till the internal precharge is complete. The internal precharge start

timing depends on /CAD Latency. The next ACT command can be issued after tRP from the

internal precharge timing.

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MIT-DS-0127-0.0

Dual Bank Interleaving READ (BL=4, CL=3)

Command

A0-9,11

A10

BA0,1

ACT

READ

Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2

ACT

PRE

tRCD

/CAS latency Burst Length

READ with Auto-Precharge (BL=4, CL=3)

Command

A10

ACT

READ

Qa0 Qa1 Qa2 Qa3

ACT

Internal precharge begins

tRCD tRP

READ Auto-Precharge Timing (BL=4)

Command ACT READ

Internal Precharge Start Timing

DQ Qa0 Qa1 Qa2 Qa3

CL=3

CL=2

A0-9,11

BA0,1

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MIT-DS-0127-0.0

Dual Bank Interleaving WRITE (BL=4)

Command

A10

ACT

Write

Da0 Da1 Da2 Da3

ACT

PRE

tRCD

Burst Length

Db0 Db1 Db2 Db3

tRCD

tWR

Command

A10

ACT

Write

Da0 Da1 Da2 Da3

ACT

Internal precharge begins

tRCD tRP

tWR

WRITE with Auto-Precharge (BL=4)

WRITE

After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set

at the same cycle as the WRITE. Following(BL-1) data are written into the RAM, when the

Burst Length is BL. The start address is specified by A9-0, and the address sequence of burst

data is defined by the Burst Type. A WRITE command may be applied to any active bank, so

the row precharge time(tRP) can be hidden behind continuous input data (in case of BL=8) by

interleaving the dual banks. From the last input data to the PRE command, the write recovery

time (tWR) is required. When A10 is high at a WRITE command, the auto-precharge(WRITEA)

is performed. Any command(READ, WRITE, PRE, ACT) to the same bank is inhibited till the

internal precharge is complete. The internal precharge begins at tWR after the last input data

cycle. The next ACT command can be issued after tRP from the internal precharge timing.

A0-9,11

BA0,1

A0-9,11

BA0,1

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MIT-DS-0127-0.0

BURST INTERRUPTION

[ Read Interrupted by Read ]

Burst read option can be interrupted by new read of the same or the other bank.

MH16S64AMA allows random column access. READ to READ interval is minimum 1 CK

Read Interrupted by Read (BL=4, CL=3)

Command

A10

READ

Qai0 Qaj1 Qbk0 Qbk1

READ

Qaj0 Qbk2 Qal0

READ

Qal1 Qal2 Qal3

[ Read Interrupted by Write ]

Burst read operation can be interrupted by write of the same or the other bank. Random

column access is allowed. In this case, the DQ should be controlled adequately by using the

DQMB0-7 to prevent the bus contention. The output is disabled automatically 2 cycle after

WRITE assertion.

Read Interrupted by Write (BL=4, CL=3)

Command

A10

READ

Qai0

Write

DDaj0 Daj1 Daj2 Daj3

DQMB0-7

DQM control Write control

A0-9,11

BA0,1

A0-9,11

BA0,1

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MIT-DS-0127-0.0

[ Read Interrupted by Precharge ]

Burst read operation can be interrupted by precharge of the same or the other bank. Read

to PRE interval is minimum 1 CK. A PRE command disables the data output, depending on

the /CAS Latency. The figure below shows examples, when the dataout is terminated.

Read Interrupted by Precharge (BL=4)

Command

READ PRE

Q0 Q1

Command

READ PRE

Q0 Q1

Command

READ PRE

Q0 Q2 Q3Q1

Command

READ PRE

Q0 Q1

Q2 Q3

CL=3

CL=2

Comman

REA

DPRE

Comman

REA

DPR

CL=

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MIT-DS-0127-0.0

[ Read Interrupted by Burst Terminate ]

Similarly to the precharge, burst terminate command can interrupt burst read operation and

disable the data output. READ to TERM interval is minimum 1 CK. The figure below shows

examples, when the dataout is terminated.

Read Interrupted by Burst Terminate (BL=4)

Command

READ TERM

Q0 Q1 Q2 Q3

CL=3

Command

READ TERM

Q0 Q1 Q2

Command

READ TERM

Command

READ TERM

Q0 Q1 Q2 Q3

CL=2

Command

READ TERM

Q0 Q1 Q2

Command

READ TERM

Comman

REA

DTERM

CL=

1Comman

REA

DTERM

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MIT-DS-0127-0.0

[ Write Interrupted by Write ]

Burst write operation can be interrupted by new write of the same or the other bank.

Random column access is allowed. WRITE to WRITE interval is minimum 1 CK.

Write Interrupted by Write (BL=4)

Command

A10

Write

Dai0 Daj0 Daj1 Dbk0

Write

Dbk1 Dbk2

Write

Dal0 Dal1 Dal2 Dal3

[ Write Interrupted by Read ]

Burst write operation can be interrupted by read of the same or the other bank.

Random column access is allowed. WRITE to READ interval is minimum 1 CK. The

input data on DQ at the interrupting READ cycle is "don't care".

Write Interrupted by Read (BL=4, CL=3)

Command

A10

Write

Qaj0

READ

Qaj1Dai0 Dak0 Dak1

DQMB0-7

Write

READ

Qbl0

A0-9,11

BA0,1

A0-9,11

BA0,1

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MIT-DS-0127-0.0

[ Write Interrupted by Precharge ]

Burst write operation can be interrupted by precharge of the same bank. Random

column access is allowed. Because the write recovery time(tWR) is required between

the last input data and the next PRE, 3rd data should be masked with DQMB0-7

shown as below. Write Interrupted by Precharge (BL=4)

Command

A10

Write

PRE

Dai0 Dai1

DQMB0-7

ACT

tWR tRP

This data should be masked to satisfy tWR requirement.

[ Write Interrupted by Burst Terminate ]

Burst terminate command can terminate burst write operation. In this case, the write

recovery time is not required and the bank remains active. The figure below shows

the case 3 words of data are written. Random column access is allowed. WRITE to

TERM interval is minimum 1 CK.

Write Interrupted by Burst Terminate (BL=4)

Command

A10

Write

TERM

Dai0 Dai1

DQMB0-7

Dai2

A0-9,11

BA0,1

A0-9,11

BA0,1

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MIT-DS-0127-0.0

AUTO REFRESH

Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,

/WE=/CKE=H) command. The refresh address is generated internally. 4096 REFA

cycle within 64ms refresh 64Mbit memory cells. The auto-refresh is performed on

4bank alternately(ping-pong refresh). Before performing an auto-refresh, both banks

must be in the idle state. Additional commands must not be supplied to the device

before tRC from the REFA command.

Auto-Refresh

/RAS

/CAS

/WE

CKE

A0-11

BA0,1

Auto Refresh on Bank 0 Auto Refresh on Bank 1

minimum tRC

NOP or DESLECT

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MIT-DS-0127-0.0

SELF REFRESH

Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,

/WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is

kept low.During the self-refresh mode, CKE is asynchronous and the only enabled

input (but asynchronous), all other inputs including CK0 are disabled and ignored, and

power consumption due to synchronous inputs is saved. To exit the self-refresh,

supplying stable CK0 inputs, asserting DESEL or NOP command and then asserting

CKE(REFSX). After tRC from REFSX both banks are in the idle state and a new

command can be issued after tRC, but DESEL or NOP commands must be asserted

till then.

Self-Refresh

/RAS

/CAS

/WE

CKE

A0-11

BA0,1

Self Refresh Entry Self Refresh Exit

minimum tRC

for recovery

Stable CK

NOP

new command

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MIT-DS-0127-0.0

CLK SUSPEND

CKE controls the internal CLK at the following cycle. Figure below shows how CKE

works. By negating CKE, the next internal CLK is suspended. The purpose of CLK

suspend is power down, output suspend or input suspend. CKE is a synchronous

input except during the self-refresh mode. CLK suspend can be performed either

when the banks are active or idle, but a command at the following cycle is ignored.

(ext.CLK)

CKE

int.CLK

Power Down by CKE

Command PRE

CKE

Command

CKE

ACT

NOP NOP NOP NOP NOP NOP

Standby Power Down

Active Power Down

NOP

DQ Suspend by CKE

Command

Write

D0 D1 D2 D3

CKE

READ

Q0 Q1 Q2 Q3

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MIT-DS-0127-0.0

DQM CONTROL

DQMB0-7 is a dual function signal defined as the data mask for writes and the output

disable for reads. During writes, DQMB0-7 masks input data word by word. DQMB0-7

to write mask latency is 0.

During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z

latency is 2.

DQM Function

Command

Write

D0 D2 D3

DQMB0-7

READ

Q0 Q1 Q3

masked by DQM=H disabled by DQM=H

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MIT-DS-0127-0.0

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Condition Ratings Unit

Vdd

Topr

Tstg

Supply Voltage

Input Voltage

Output Voltage

Output Current

Power Dissipation

Operating Temperature

Storage Temperature

with respect to Vss

Ta=25°C

-0.5 ~ 4.6

-0.5 ~ Vdd+0.5

0 ~ 70

-40 ~ 100

°C

RECOMMENDED OPERATING CONDITION

(Ta=0 ~ 70°C, unless otherwise noted)

Symbol

Vdd

Vss

VIH

VIL

Parameter

Supply Voltage

High-Level Input Voltage all inputs

Supply Voltage

Low-Level Input Voltage all inputs

Limits Unit

Min. Typ. Max.

3.0

2.0

-0.3

3.3

03.6

Vdd+0.3

0.8

CAPACITANCE

(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)

Symbol

CI(A)

CI(C)

CI(K)

CI/O

Parameter

Input Capacitance, address pin

Input Capacitance, control pin

Input Capacitance, CK pin

Input Capacitance, I/O pin

Test Condition Limits(max.) Unit

VI = Vss

f=1MHz

Vi=25mVrms

-0.5 ~ Vdd+0.5

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MIT-DS-0127-0.0

AVERAGE SUPPLY CURRENT from Vdd

(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)

Symbol Parameter Test Condition Limits Unit

Min. Max.

VOH(DC) High-Level Output Voltage(DC) IOH=-2mA 2.4 V

VOL(DC) Low-Level Output Voltage(DC) IOL=2mA 0.4 V

VOH(AC

)High-Level Output Voltage(AC) CL=50pF,

IOH=-2mA 2 V

VOL(AC) Low-Level Output Voltage(AC) CL=50pF, IOL=2mA 0.8 V

IOZ Off-stare Output Current Q floating VO=0 Å` Vdd -1

0É A

Ii Input

Current VIH=0 Å` Vdd+0.3V -8

0É

Symbol Parameter Test Condition Limits(max) Unit

-8 -10 -12

Icc1s operating current, single bank tRC=min.tCLK=min, BL=1, CL=3 1520 1360 1200 mA

Icc1d operating current, dual bank tRC=min.tCLK=min, BL=1, CL=3 2080 1840 1680

Icc2h standby current, CKE=H both banks idle, tCLK=min, CKE=H 400 352 320 mA

Icc2l standby current, CKE=L both banks idle, tCLK=min, CKE=L 32 32 32 mA

Icc3 active standby current 800 720 640 mA

Icc4 burst current tCLK=min, BL=4, CL=3, both banks active(discerte) 2080 1840 1680 mA

Icc5 auto-refresh current tRC=min, tCLK=min 2080 1840 1680 mA

Icc6 self-refresh current CKE <0.2V 16 16 16 mA

both banks active, tCLK=min, CKE=H

IOZ Off-stare Output Current Q floating VO=0 ~ Vdd -10 10 uA

Ii Input Current VIH=0 ~ Vdd+0.3V -160 160 uA

(discrete)

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MIT-DS-0127-0.0

Max.

AC TIMING REQUIREMENTS (SDRAM Component)

(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)

Input Pulse Levels: 0.8V to 2.0V

Input Timing Measurement Level: 1.4V

Limits

Symbol Parameter -10 -12 Unit

Min. Max. Min. Max.

tCLK CK cycle time 15 15 ns

12 ns

tCH CK High pulse width 4

10 4 ns

tCL CK Low pilse width 4 4 ns

tT Transition time of CK 1 10 1 10 ns

tIS Input Setup time(all inputs) 3 3 ns

tIH Input Hold time(all inputs) 1 ns

tRC Row cycle time 90 100 ns

tRCD Row to Column Delay 30 30 ns

tRAS Row Active time 60 10000 70 10000 ns

tRP Row Precharge time 30 30 ns

tWR Write Recovery time 10 12 ns

tRRD Act to Act Deley time 20 24 ns

tRSC Mode Register Set Cycle time 20 24 ns

tPDE Power Down Exit time 10 12 ns

tREF Refresh Interval time 64 64 ms

Signal

1.4V

Any AC timing is

referenced to the input

signal crossing through

1.4V.

CL=2

CL=3

Min.-8

1 10

56 10000

864

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MIT-DS-0127-0.0

1.4V

1.4VDQ

tAC tOH tOHZ

SWITCHING CHARACTERISTICS (SDRAM Component)

(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)

Limits

Symbol Parameter -8 -10 -12 Unit

Min. Max. Min. Max. Min. Max.

tAC Access time from CK CL=2 8 9 9.5 ns

CL=3 8 8 8 ns

tOH Output Hold time 2.5 3 3 ns

from CK

tOLZ Delay time, output low

impedance from CK 0 0 0 ns

tOHZ Delay time, output high

impedance from CK 2.5 7 3 8 3 ns

Output Load

Condition

VOUT

50pF

50Ω

VTT=1.4V

Output Timing

Measurement

Reference Point

1.4V

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MIT-DS-0127-0.0

Burst Write (single bank) @BL=4

/CS

/RAS

/CAS

/WE

CKE

BA0,1

0 0

D0 D0 D0 D0

ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

tRCD

tWR

tRP

tRC

tRCD

CLK

Italic parameter indicates minimum case

tRAS

A0-9

A10

DQM

A11

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MIT-DS-0127-0.0

Burst Write (multi bank) @BL=4

/CS

/RAS

/CAS

/WE

CKE

BA0,1

0 1

D0 D0 D0 D0

ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

tRCD

tRAS

tWR

tRP

tRC

tRCD

D1 D1 D1 D1

tRRD

tWR

tRRD

ACT#1 WRITE#1 PRE#1

ACT#2

CLK

Italic parameter indicates minimum case

A0-9

A10

DQM

A11

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

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MITSUBISHI

ELECTRIC 4. Mar.1997

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0127-0.0

Burst Read (single bank) @BL=4 CL=3

/CS

/RAS

/CAS

/WE

CKE

BA0,1

0 0

Q0 Q0 Q0 Q0

Q0 Q0

ACT#0 READ#0 PRE#0 ACT#0 READ#0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

tRCD

tRAS tRP

tRC

tRCD

CL=3

READ to PRE ≥BL allows full data out

DQM read latency =2

CLK

Italic parameter indicates minimum case

A0-9

A10

DQM

A11

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

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MITSUBISHI

ELECTRIC 4. Mar.1997

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0127-0.0

Burst Read (multiple bank) @BL=4 CL=3

/CS

/RAS

/CAS

/WE

CKE

BA0,1

0 0

Q0 Q0 Q0 Q0

ACT#0 READ#0 PRE#0 ACT#0 READ#0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

tRCD

tRAS tRP

tRC

tRCD

CL=3

DQM read latency =2

tRRD

ACT#1

tRRD

Q1 Q1 Q1 Q1

CL=3

READ#1 PRE#1 ACT#2

CLK

Italic parameter indicates minimum case

A0-9

A10

DQM

A11

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

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MITSUBISHI

ELECTRIC 4. Mar.1997

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0127-0.0

Burst Write (multi bank) with Auto-Precharge @BL=4

/CS

/RAS

/CAS

/WE

CKE

BA0,1

0 1

D0 D0 D0 D0

ACT#0 WRITE#0 with

AutoPrecharge ACT#0 WRITE#0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

tRCD

tRC

tRCD

D1 D1 D1 D1

tRRD

Y X

tRRD

ACT#1 WRITE#1 with

AutoPrecharge

BL-1+ tWR + tRP

tRCD

ACT#1 WRITE#1

CLK

BL-1+ tWR + tRP

Italic parameter indicates minimum case

A0-9

A10

DQM

A11

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

( / 52 )

MITSUBISHI

ELECTRIC 4. Mar.1997

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0127-0.0

Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3

/CS

/RAS

/CAS

/WE

CKE

BA0,1

Q0 Q0 Q0 Q0

ACT#0 READ#0 with

Auto-Precharge ACT#0 READ#0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

tRCD

tRC

tRCD

CL=3

DQM read latency =2

tRRD

ACT#1

tRRD

Q1 Q1 Q1 Q1

CL=3

READ#1 with

Auto-Precharge ACT#1

BL+tRP BL+tRP

CLK

CL=3

tRCD

Italic parameter indicates minimum case

A0-9

A10

DQM

A11

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

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MITSUBISHI

ELECTRIC 4. Mar.1997

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0127-0.0

Page Mode Burst Write (multi bank) @BL=4

/CS

/RAS

/CAS

/WE

CKE

BA0,1

0 0

D0 D0 D0 D0

ACT#0 WRITE#0 WRITE#0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

tRCD

D1 D1 D1 D1

Y Y

WRITE#1

CLK

tRRD

D0 D0 D0 D0 D0 D0 D0

ACT#1 WRITE#0

Italic parameter indicates minimum case

A0-9

A10

DQM

A11

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

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MITSUBISHI

ELECTRIC 4. Mar.1997

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0127-0.0

Page Mode Burst Read (multi bank) @BL=4 CL=3

/CS

/RAS

/CAS

/WE

CKE

BA0,1

0 0

Q0 Q0 Q0

ACT#0 READ#0 READ#0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

tRCD

Q1 Q1 Q1 Q1

Y Y

READ#1

CLK

tRRD

Q0 Q0 Q0 Q0

ACT#1 READ#0

CL=3 CL=3 CL=3

DQM read latency=2

Italic parameter indicates minimum case

A0-9

A10

DQM

A11

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

( / 52 )

MITSUBISHI

ELECTRIC 4. Mar.1997

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0127-0.0

Write Interrupted by Write / Read @BL=4

/CS

/RAS

/CAS

/WE

CKE

BA0,1

D0 D0 D0 D0

ACT#0 WRITE#0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

tRCD

WRITE#1

CLK

tRRD

D0 D0 D1 D1 Q0 Q0 Q0

ACT#1 WRITE#0

Y Y

0 0 0

tCCD

CL=3

WRITE#0 READ#0

Burst Write can be interrupted by Write or Read of any active bank.

Italic parameter indicates minimum case

A0-9

A10

DQM

A11

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

( / 52 )

MITSUBISHI

ELECTRIC 4. Mar.1997

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0127-0.0

Read Interrupted by Read / Write @BL=4 CL=3

/CS

/RAS

/CAS

/WE

CKE

BA0,1

0 0

Q0 Q0 Q0

ACT#0 READ#0 WRITE#0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

tRCD

Q0 D0 D0

Y Y

READ#1

CLK

tRRD

Q0 Q0 Q1 Q1

ACT#1 READ#0

DQM read latency=2

Burst Read can be interrupted by Read or Write of any active bank.

READ#0 READ#0

blank to prevent bus contention

Italic parameter indicates minimum case

A0-9

A10

DQM

A11

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

( / 52 )

MITSUBISHI

ELECTRIC 4. Mar.1997

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0127-0.0

Write Interrupted by Precharge @BL=4

/CS

/RAS

/CAS

/WE

CKE

BA0,1

D0 D0 D0 D0

ACT#0 WRITE#0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

tRCD

WRITE#1

CLK

tRRD

D1 D1 D1 D1 D1

ACT#1

1 1

Burst Write is not interrupted by

Precharge of the other bank.

PRE#1

PRE#0 ACT#1 WRITE#1

Burst Write is interrupted by

Precharge of the same bank.

Italic parameter indicates minimum case

A0-9

A10

DQM

A11

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

( / 52 )

MITSUBISHI

ELECTRIC 4. Mar.1997

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0127-0.0

Read Interrupted by Precharge @BL=4 CL=3

/CS

/RAS

/CAS

/WE

CKE

BA0,1

Q0 Q0 Q0

ACT#0 READ#0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

tRCD

PRE#1

CLK

tRRD

Q1 Q1

ACT#1 PRE#0

DQM read latency=2

Burst Read is not interrupted

by Precharge of the other bank.

tRCD

tRP

READ#1 ACT#1 READ#1

Burst Read is interrupted

by Precharge of the same bank.

Italic parameter indicates minimum case

A0-9

A10

DQM

A11

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

( / 52 )

MITSUBISHI

ELECTRIC 4. Mar.1997

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0127-0.0

Mode Register Setting

/CS

/RAS

/CAS

/WE

CKE

BA0,1

Auto-Ref (last of 8 cycles)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

CLK

tRC

Mode

Setting

tRCD

tRSC

ACT#0 WRITE#0

D0 D0 D0

Italic parameter indicates minimum case

A0-9

A10

DQM

A11

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

( / 52 )

MITSUBISHI

ELECTRIC 4. Mar.1997

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0127-0.0

Auto-Refresh @BL=4

/CS

/RAS

/CAS

/WE

CKE

BA0,1

Auto-Refresh

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

CLK

tRC

Before Auto-Refresh,

all banks must be idle state.

tRCD

ACT#0 WRITE#0

D0 D0 D0

After tRC from Auto-Refresh,

all banks are idle state.

Italic parameter indicates minimum case

A0-9

A10

DQM

A11

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

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MITSUBISHI

ELECTRIC 4. Mar.1997

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0127-0.0

Self-Refresh

/CS

/RAS

/CAS

/WE

CKE

BA0,1

Self-Refresh Entry

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

CLK

Before Self-Refresh Entry,

all banks must be idle state.

Self-Refresh Exit ACT#0

After tRC from Self-Refresh Exit,

all banks are idle state.

tRC

tSRX

CLK can be stopped

CKE must be low to maintain Self-Refresh

Italic parameter indicates minimum case

A0-9

A10

DQM

A11

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

( / 52 )

MITSUBISHI

ELECTRIC 4. Mar.1997

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0127-0.0

DQM Write Mask @BL=4

/CS

/RAS

/CAS

/WE

CKE

BA0,1

0 0

D0 D0 D0 D0

D0 D0 D0

ACT#0 WRITE#0 WRITE#0 WRITE#0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

tRCD

CLK

masked masked

Italic parameter indicates minimum case

A0-9

A10

DQM

A11

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

( / 52 )

MITSUBISHI

ELECTRIC 4. Mar.1997

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0127-0.0

DQM Read Mask @BL=4 CL=3

/CS

/RAS

/CAS

/WE

CKE

BA0,1

0 0

Q0 Q0 Q0 Q0

Q0 Q0 Q0

ACT#0 READ#0 READ#0 READ#0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

tRCD

CLK

masked masked

DQM read latency=2

Italic parameter indicates minimum case

A0-9

A10

DQM

A11

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

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MITSUBISHI

ELECTRIC 4. Mar.1997

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0127-0.0

Power Down

/CS

/RAS

/CAS

/WE

CKE

BA0,1

Precharge All ACT#0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

CLK

Standby Power Down Active Power Down

CKE latency=1

Italic parameter indicates minimum case

A0-9

A10

DQM

A11

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

( / 52 )

MITSUBISHI

ELECTRIC 4. Mar.1997

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0127-0.0

CLK Suspend @BL=4 CL=3

/CS

/RAS

/CAS

/WE

CKE

BA0,1

0 0

Q0 Q0 Q0 Q0

ACT#0 WRITE#0 READ#0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

tRCD

CLK

D0 D0 D0D0

CLK suspendedCLK suspended

CKE latency=1 CKE latency=1

Italic parameter indicates minimum case

A0-9

A10

DQM

A11

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

( / 52 )

MITSUBISHI

ELECTRIC 4. Mar.1997

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0127-0.0

1.27±0.1

133.35±0.13 3.9MAX

29.21±0.13

841

127.35±0.13

17.78±0.13

3±0.13

1±0.13

3±0.13

2±0.13

6.35±0.13

24.495±0.13

8.89±0.13 29x1.27=36.83±0.2

42.18±0.13

9x1.27=11.43±0.2 6.35±0.1 43x1.27=54.61±0.2 1.27±0.1

2-ø3±0.1

17.78±0.13

2-R2±0.13

1±0.13

168 85

OUTLINE

Preliminary