2003 Microchip Technology Inc. DS21178D-page 1
24AA00/24LC00/24C00
Device Selection Table
Features
• Low-power CMOS technology
- 500 µA typical active current
- 250 nA typical standby current
• Organized as 16 bytes x 8 bits
• 2-wire serial interface bus, I2C™ compatible
• 100 kHz (1.8V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• 4 ms maximum byte write cycle time
• 1,000,000 erase/write cycles
• ESD protection > 4 kV
• Data retention > 20 0 years
• 8L DIP, SOIC, TSSOP and 5L SOT-23 packages
• Standard or Pb-free finish available
• Temperature ranges available:
Description
The Microchip Technology Inc. 24AA00/24LC00/
24C00 (24XX00*) is a 128-bit Electrically Erasable
PROM me mory orga nized as 16 x 8 with a 2-w ire serial
interface. Low voltage design permits operation down
to 1.8 volts for the 24XX00 version, and every version
maint ains a m aximum s tandby current of only 1 µA and
typical active current of only 500 µA. This device was
designed for where a small amount of EEPROM is
needed for the storage of calibration values, ID
numbers or manufacturing information, etc. The
24XX00 is available in 8-pin PDIP, 8-pin SOIC (150
mil), 8-pin TSSOP and the 5-pin SOT-23 packages.
Package Types
Block Diagram
Pin Function Table
Device VCC Range Temp Range
24AA00 1.8 - 5.5 C,I
24LC00 2.5 - 5.5 C,I
24C00 4.5 - 5.5 C,I,E
- Commercial (C): 0°Cto+70°C
- Industrial (I): -40°Cto+85°C
- Automotive (E): -40°C to +125°C
Name Function
VSS Ground
SDA Serial Data
SCL Serial Clock
VCC +1.8V to 5.5V (24AA00)
+2.5V to 5.5V (24LC00)
+4.5V to 5.5V (24C00)
NC No Internal Connection
24XX00
1
2
3
4
8
7
6
5
15
4
3
24XX00 24XX00
8-PIN PDIP/SOIC
8-PIN TSSOP
5-PIN SOT-23
NC
NC
NC
Vss
VCC
NC
SCL
SDA
NC
NC
NC
VSS
VCC
NC
SCL
SDA
SCL
VSS
SDA
VCC
NC
1
2
3
4
8
7
6
5
2
HV Genera tor
EEPROM
Array
YDEC
XDEC
Sense AMP
R/W Control
Memory
Control
Logic
I/O
Control
Logic
SDA SCL
VCC
VSS
128 Bit I2C™ Bus Serial EEPROM
I2C is a trademark of Philips Corporation.
*24XX00 is used in this document as a generic part number for
the 24AA00/24LC00/24C00 devices.
24AA00/24LC00/24C00
DS21178D-page 2 2003 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-65°C to +125°C
ESD protection on all pins..........................................................................................................................................4 kV
FIGURE 1-1: BUS TIMING DATA
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above th ose indi cated in the opera tional li stings of this sp ecificati on is no t implie d. Exposu re to maxim um rating
conditions for extended periods may affect device reliability.
TABLE 1-1: DC CHARACTERISTICS
All Parameters apply across the
recommended operating ranges unless
otherwise noted
Commercial (C): TA = 0°C to +70°C, VCC = 1.8V to 5.5V
Industrial (I): TA = -40°C to +85°C, VCC = 1.8V to 5.5V
Automotive (E) TA = -40°C to +125°C, VCC = 4.5V to 5.5V
Parameter Symbol Min. Max. Units Conditions
SCL and SDA pins:
High-level input voltage VIH 0.7 VCC V(Note)
Low-level input voltage VIL 0.3 VCC V(Note)
Hysteresis of Schmitt Trigger
inputs VHYS .05 VCC —VVCC ≥ 2.5V (Note)
Low-level output voltage VOL 0.4 V IOL = 3.0 mA, VCC = 4.5V
IOL = 2.1 mA, VCC = 2.5V
Input leakage current ILI —±1µAVIN = VCC or VSS
Output lea kage curre nt ILO —±1µAVOUT = VCC or VSS
Pin capacitance (all inputs/outputs) CIN,
COUT —10pFVCC = 5.0V (Note)
TA = 25°C, f = 1 MHz
Operati ng current ICC Write — 2 mA VCC = 5.5V, SCL = 400 kHz
ICC Read — 1 mA VCC = 5.5V, SCL = 400 kHz
Standby current ICCS —1µAVCC = 5.5V, SDA = SCL = VCC
Note: This parameter is periodically sampled and not 100% tested.
TFTHIGH TR
TSU:STA
TLOW THD:DAT TSU:DAT TSU:STO
TBUF
TAA
TSP
SCL
SDA
IN
SDA
OUT
THD:STA
2003 Microchip Technology Inc. DS21178D-page 3
24AA00/24LC00/24C00
TABLE 1-2: AC CHARACTERISTICS
All Parameters apply across all
recommended operating ranges
unless otherwise noted
Commercial (C): TA = 0°C to +70°C, VCC = 1.8V to 5.5V
Industrial (I): TA = -40°C to +85°C, VCC = 1.8V to 5.5V
Automotive (E): TA = -40°C to +125°C, VCC = 4.5V to 5.5V
Parameter Symbol Min Max Units Conditions
Clock frequency FCLK —
—
—
100
100
400
kHz 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Clock high time THIGH 4000
4000
600
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Clock low time TLOW 4700
4700
1300
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
SDA and SCL rise time
(Note 1) TR—
—
—
1000
1000
300
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
SDA and SCL fall time TF—300ns(Note 1)
Start condition hold time THD:STA 4000
4000
600
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Start condition setup time TSU:STA 4700
4700
600
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Data input hold time THD:DAT 0—ns(Note 2)
Data input setup time TSU:DAT 250
250
100
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Stop condition setup time TSU:STO 4000
4000
600
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Output valid from clock
(Note 2) TAA —
—
—
3500
3500
900
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Bus free time: Time the bus must
be free before a new transmis-
sion can start
TBUF 4700
4700
1300
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Output fall time from VIH
minimum to VIL maximum TOF 20+0.1
CB 250 ns (Note 1), CB ≤ 100 pF
Input filter spike suppression
(SDA and SCL pins) TSP —50ns(Notes 1, 3)
Write cycle time TWC —4ms
Endurance 1M — cycles (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The co mbine d TSP and VHYS specifica tio ns are due to new Schmitt Trigger i np uts which pr ov id e i mp rov ed
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization . For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained on www.microchip.com.
24AA00/24LC00/24C00
DS21178D-page 4 2003 Microchip Technology Inc.
2.0 PIN DESCRIPTIONS
2.1 SDA Serial Data
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For norma l data trans fer SDA is all owed to change only
during SCL low. Changes during SCL high are
reserved for indica ting the Start and Stop conditions.
2.2 SCL Serial Clock
This i nput is u sed t o sy nchron ize the d ata trans fer fro m
and to the device.
2.3 Noise Protection
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
3.0 FUNCTIONAL DESCRIPTION
The 24XX00 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and
generates the Start and Stop conditions, while the
24XX00 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer ma y be initiated only when the bu s
is not busy.
• During data transfer, the data line must remain
stab le whene ver the cl ock lin e is high . Change s in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Fig ure 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A hig h- to - lo w t ran si t i on of t h e SD A l in e whi l e t h e c lo ck
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 S top Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock si gnal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each dat a transf er is initiated w ith a S tart condition an d
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited.
2003 Microchip Technology Inc. DS21178D-page 5
24AA00/24LC00/24C00
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line du ring the Acknow ledge cl ock pulse in s uch a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by no t g ene rati ng an Acknowledge bi t o n th e las t
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the maste r to gen erat e the Stop condition (Fi gur e 4-2).
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 4-2: ACKNOWLEDGE TIMING
Note: The 24XX00 does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress.
(A) (B) (C) (D) (A)(C)
SCL
SDA
START
CONDITION ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
SCL 987654321 123
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line at this point
so the Transm itte r can continue sending data.
Data from transmitter Data from transmitter
SDA
Acknowledge
Bit
24AA00/24LC00/24C00
DS21178D-page 6 2003 Microchip Technology Inc.
5.0 DEVICE ADDRESSING
After generating a Start condition, the bus master
transmits a control byte consisting of a slave address
and a Read/Write bit that indicates what type of
operatio n is to be perfo rmed. The slave add ress for the
24XX00 consists of a 4-bit device code ‘1010’ followed
by three don't care bits.
The last bi t of the control byte determines the operation
to be perfo rme d. When set to a o ne a read operati on is
selected, and when set to a zero a write operation is
selected. (Figure 5-1). The 24XX00 monitors the bus
for its corresponding slave address all the time. It
generate s an Ackn owledge bit if the s lave add ress was
true and it is not in a Programming mode.
FIGURE 5-1: CONTROL BYTE FORMAT
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the Start signal from the master, the device
code (4 b its), the d on't care bit s (3 bits), and the R/W bit
(which is a logic low) are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow after it has genera ted an Acknowl edge bit durin g
the nint h clock cycl e. Therefo re, the next byte transmit-
ted by the master is the word address and will be
written into the address pointer of the 24XX00. Only the
lower four a ddress bit s are us ed by the devic e, and th e
upper four bits are don’t cares. The 24XX00 will
acknowledge the address byte and the master device
will then transmit the data word to be written into the
addressed memory location. The 24XX00 acknowl-
edges again and the master generates a Stop
condition. This initiates the internal write cycle, and
during this time the 24 XX00 will not ge nerate Ack nowl-
edge si gnals (Fi gure 7-2). After a by te Wr ite co mmand,
the internal address counter will not be incremented
and will point to t he same address location that was just
written. If a Stop bit is transmitted to the device at any
point in t he W rite comm and seque nce before the entire
sequence is complete, then the command will abort
and no data will be written. If more than 8 data bits are
transmitted before the Stop bit is sent, then the device
will clear the previously loaded byte and begin loading
the data buffer again. If more than one data byte is
transmitted to the device and a Stop bit is sent before a
full eight data bits have been transmitted, then the
Write command will abort and no data will be written.
The 24XX00 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5V (24AA00 and 24LC00) or 3.8V (24C00)
at nominal conditions.
1010XXXSACKR/W
Device Sele ct
Bits Don’t Care
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
2003 Microchip Technology Inc. DS21178D-page 7
24AA00/24LC00/24C00
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be us ed to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
comma nd has been is sued from the master , the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no AC K is retu rned, then the S t art bit and cont rol byte
must be re-sent. If the cycle is complete, then the
device will return the ACK and the master can then
proceed with the next Read or Write command. See
Figure 7-1 for flow diagram.
FIGURE 7-1: ACKNOWLEDGE
POLLING FLOW
FIGURE 7-2: BYTE WRITE
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
NO
YES
SP
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE WORD
ADDRESS DATA
A
C
K
A
C
K
A
C
K
10 X10 XXX
X = Don’t Care Bit
XXX
0
24AA00/24LC00/24C00
DS21178D-page 8 2003 Microchip Technology Inc.
8.0 READ OPERATIONS
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. Ther e are three ba sic types
of read operation s: curren t address read, ra ndom rea d,
and sequential read.
8.1 Current Address Read
The 24XX00 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n, the next current ad dress read
operatio n wou ld acc ess dat a fr om add ress n + 1. U pon
receipt of the slav e address w ith the R/W b it set to one,
the device issues an acknowledge and transmits the
eight-bit data word. The master will not acknowledge
the tr ansfer bu t does ge nerate a Stop conditi on and th e
device discontinues transmission (Figure 8-1).
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this typ e of re ad ope ration, first the word ad dres s must
be set. This is done b y sending the word address to the
device as part of a write operation.
After the word address is sent, the master generates a
Start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
address pointer is set. Then the master issues the
control b yte again but with the R/W bit set to a on e. The
24XX00 will then issue an acknowledge and transmits
the eight bit data word. The master will not acknowl-
edge the transfer but does generate a Stop condition
and the device discontinues transmission (Figure 8-2).
After this command, the internal address counter will
point to the a ddress loca tion fo llowin g the o ne tha t was
jus t read.
8.3 Sequentia l Read
Sequential reads are initiated in the same way as a
random read except that after the device transmits the
first data byte, the master issues an acknowledge as
opposed to a Stop condition in a random read. This
directs the device to transmit the next sequentially
addressed 8-bit word (Figure 8-3).
To provide sequential reads the 24XX00 contains an
internal address poin ter which is inc remented by o ne at
the completion of each read operation. This address
pointer all ows the entire memor y contents to be seriall y
read during one operation.
FIGURE 8-1: CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
PS
S
T
O
P
CONTROL
BYTE
S
T
A
R
TDATA
A
C
K
N
O
A
C
K
1100XXX1
X = Don’t Care Bit
2003 Microchip Technology Inc. DS21178D-page 9
24AA00/24LC00/24C00
FIGURE 8-2: RANDOM READ
FIGURE 8-3: SEQUENTIAL READ
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
A
C
K
WORD
ADDRESS (n) CONTROL
BYTE
S
T
A
R
TDATA (n)
A
C
K
A
C
K
N
O
A
C
K
XXXX
S1 100XXX0 S1 100XXX1
X = Don’t Care Bit
P
BUS ACTI VITY
MASTER
SDA LINE
BUS ACTI VITY
S
T
O
P
CONTROL
BYTE
A
C
K
N
O
A
C
K
DATA n DAT A n + 1 DAT A n + 2 DAT A n + X
A
C
K
A
C
K
A
C
K
24AA00/24LC00/24C00
DS21178D-page 10 2003 Microchip Technology Inc.
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
XXXXXXXX
T/XXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (150 mil) Example:
XXXXXXXX
T/XXYYWW
NNN
8-Lead TSSOP Example:
24LC00
I/P13F
0327
24LC00
I/SN0327
13F
XXXX
TYWW
NNN
4L00
I327
13F
Legend: XX...X Customer specific information*
T Temperat ure grad e (I,E)
YY Year code (last 2 digits of calendar year)
Y Year code (last di git of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event th e full Mi crochi p pa rt numbe r cannot be ma rked on on e line, it will
be carried ov er to the ne xt li ne thus lim iti ng th e nu mb er of av ai lab le c hara ct ers
for customer specific information.
*Standard QTP marking consists of Microc hip part number, year code, week code, and traceability code.
5-Lead SOT-23 Example:
XXNN M03F
Part
Number
TSSOP Marking
Code
STD Pb-Free
24AA00 4A00 G4A0
24LC00 4L00 G4L0
SOT-23 Mar k ing Code
Part Number C I E
24AA00 A0 B0 —
24LC00 L0 M0 N0
24C00 C0 D0 E0
Note: Pb-free parts are marked same as
standard finish. Pb-free part number using
“G” suffix is marked on carton..
2003 Microchip Technology Inc. DS21178D-page 11
24AA00/24LC00/24C00
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units INCHES* MILLIMETERS
Dime nsion Limits MIN NOM MAX MIN NOM MAX
Number of Pins n88
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α51015 51015
Mold Draft Angle Bottom β51015 51015
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
24AA00/24LC00/24C00
DS21178D-page 12 2003 Microchip Technology Inc.
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Foot A ngle φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Pa ckag e Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004
A1
Standoff § 1.551.421.32.061.056.052A2Molded Packag e Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050
p
Pitch 88
n
Numb er of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
β
c
45°
φ
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
§ Significant Characteristic
2003 Microchip Technology Inc. DS21178D-page 13
24AA00/24LC00/24C00
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
10501050
β
Mold Draft Angle Bottom 10501050
α
Mold Draft Angle Top 0.300.250.19.012.010.007BLead Width 0.200.150.09.008.006.004
c
Lead Thickness
0.700.600.50.028.024.020LFoot Length 3.103.002.90.122.118.114DMolded Package Length 4.504.404.30.177.173.169E1Molded Package Width 6.506.386.25.256.251.246EOverall Width 0.150.100.05.006.004.002
A1
Standoff § 0.950.900.85.037.035.033A2Molded Package Thick ness 1.10.043AOverall Height 0.65.026
p
Pitch 88
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERS*INCHESUnits
α
A2
A
A1
L
c
β
φ
1
2D
n
p
B
E
E1
Foot A ngle φ048048
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
§ Significant Characteristic
24AA00/24LC00/24C00
DS21178D-page 14 2003 Microchip Technology Inc.
5-Lead Plastic Small Outline Transistor (OT) (SOT-23)
10501050
β
Mold Draft Angle Bottom 10501050
α
Mold Draft Angle Top 0.500.430.35.020.017.014BLead Width 0.200.150.09.008.006.004
c
Lead Thickness 10501050
φ
Foot A ngle 0.550.450.35.022.018.014LFoot Length 3.102.952.80.122.116.110DOverall Length 1.751.631.50.069.064.059E1Molded Pa ckag e Width 3.002.802.60.118.110.102EOverall Width 0.150.080.00.006.003.000A1Standoff § 1.301.100.90.051.043.035A2Mol d ed Packag e Thick ness 1.451.180.90.057.046.035AOverall Height 1.90.075
p1
Outside lead pitch (basic) 0.95.038
p
Pitch 55
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
1
p
D
B
n
E
E1
L
c
βφ
α
A2
A
A1
p1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-178
Drawing No. C04-091
§ Significa nt Charact eristic
2003 Microchip Technology Inc. DS21178D-page15
24AA00/24LC00/24C00
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational diff erences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.micr ochip.com)
Please specify which device, revision of silicon and Dat a Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
PART NO.
X/XX
PackageTemperature
Range
Device
Device: 24AA00: = 1.8V, 128 bit I2C™ Serial EEPROM
24AA00 T: = 1.8V, 128 bit I2C Serial EEPROM
(Tape and Reel)
24LC00: = 2.5V, 128 bit I2C Serial EEPROM
24LC00T: = 2.5V, 128 bit I2C Serial EEPROM
(Tape and Reel)
24C00: = 5V, 128 bit I2C™ Serial EEPROM
24C00T: = 5V, 128 bit I2C™ Serial EEPROM
(Tape and Reel)
Temperature
Range: Blank = 0°C to 70°C
I = -40°C to +85°C
E = -40°C to +125°C
Package:
Lead finish
P = Plastic DIP (300 mil body), 8-lead
SN = Plastic SOIC (150 mil body), 8-lead
ST = Plastic TSSOP (4.4 mm), 8-lead
OT = SOT-23, 5-lead (Tape and Reel only)
Blank =Standard 63/37 SnPb
G =Matte T in (pure Sn)
Examples:
a) 24AA00-I/P: Industrial Temperature,1.8V
PDIP package
b) 24AA00-I/SN: Industrial Temperature,
1.8V, SOIC package
c) 24AA00T- I/OT: Industrial Temperature,
1.8V, SOT-23 package, tape and reel
d) 24LC00-I/P: Industrial Temperature,
2.5V, PDIP package
e) 24C00-E/SN: Extended Temperature,
5V, SOIC packag e
f) 24LC00T-I/OT: Industrial Temperature,
2.5V, SOT-23 package, tape and reel
g) 24LC00-I/PG: Industrial Temperature, 2.5V
PDIP p ackage, Pb-free
h) 24LC00T-I/OTG: Industrial Temperature,
2.5V, SOT-23 package, tape and reel,
Pb-free
Lead Finish
X
24AA00/24LC00/24C00
DS21178D-page 16 2003 Microchip Technology Inc.
NOTES:
2003 Microchip Technology Inc. DS21178D-page 17
Information contained in this publication regarding device
applications and the like is intended through sug gestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microc hip Technology Incorporated with respect
to the accuracy or use of such inf orm ation, or inf ringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, MPLAB, PIC, PI Cmicro, PIC START,
PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
AmpLab, FilterLab, microID, MXDEV, M XLAB, PIC MASTER,
SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor , SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• M icrochip products meet the specification contained in their particular Microchip Data Sheet.
• M icrochip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrit y of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code prot ection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such a ct s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and T empe, Arizona in July 1999
and M ountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, micr operipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
DS21178D-page 18 2003 Microchip Technology Inc.
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