24AA00/24LC00/24C00 128 Bit I2CTM Bus Serial EEPROM Device Selection Table Package Types VCC Range Temp Range 24AA00 1.8 - 5.5 C,I 24LC00 2.5 - 5.5 24C00 4.5 - 5.5 8-PIN PDIP/SOIC NC 1 C,I NC 2 C,I,E NC 3 Vss 4 Features The Microchip Technology Inc. 24AA00/24LC00/ 24C00 (24XX00*) is a 128-bit Electrically Erasable PROM memory organized as 16 x 8 with a 2-wire serial interface. Low voltage design permits operation down to 1.8 volts for the 24XX00 version, and every version maintains a maximum standby current of only 1 A and typical active current of only 500 A. This device was designed for where a small amount of EEPROM is needed for the storage of calibration values, ID numbers or manufacturing information, etc. The 24XX00 is available in 8-pin PDIP, 8-pin SOIC (150 mil), 8-pin TSSOP and the 5-pin SOT-23 packages. 1 2 3 4 NC NC NC VSS VCC 7 NC 6 SCL 5 SDA 8 7 6 5 VCC NC SCL SDA 5-PIN SOT-23 SCL 1 VSS 2 SDA 3 24XX00 Description 8 8-PIN TSSOP 24XX00 * Low-power CMOS technology - 500 A typical active current - 250 nA typical standby current * Organized as 16 bytes x 8 bits * 2-wire serial interface bus, I2CTM compatible * 100 kHz (1.8V) and 400 kHz (5V) compatibility * Self-timed write cycle (including auto-erase) * 4 ms maximum byte write cycle time * 1,000,000 erase/write cycles * ESD protection > 4 kV * Data retention > 200 years * 8L DIP, SOIC, TSSOP and 5L SOT-23 packages * Standard or Pb-free finish available * Temperature ranges available: - Commercial (C): 0C to +70C - Industrial (I): -40C to +85C - Automotive (E): -40C to +125C 24XX00 Device 5 VCC 4 NC Block Diagram HV Generator Memory Control Logic I/O Control Logic SDA XDEC EEPROM Array SCL YDEC VCC Sense AMP R/W Control VSS Pin Function Table Name Function VSS Ground SDA Serial Data SCL Serial Clock VCC +1.8V to 5.5V (24AA00) +2.5V to 5.5V (24LC00) I2C is a trademark of Philips Corporation. *24XX00 is used in this document as a generic part number for the 24AA00/24LC00/24C00 devices. 2003 Microchip Technology Inc. +4.5V to 5.5V (24C00) NC No Internal Connection DS21178D-page 1 24AA00/24LC00/24C00 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings() VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65C to +150C Ambient temperature with power applied ................................................................................................-65C to +125C ESD protection on all pins ..........................................................................................................................................4 kV NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS All Parameters apply across the recommended operating ranges unless otherwise noted Parameter Commercial (C): Industrial (I): Automotive (E) Symbol TA = 0C to +70C, TA = -40C to +85C, TA = -40C to +125C, Min. Max. VCC = 1.8V to 5.5V VCC = 1.8V to 5.5V VCC = 4.5V to 5.5V Units Conditions SCL and SDA pins: High-level input voltage VIH 0.7 VCC Low-level input voltage VIL Hysteresis of Schmitt Trigger inputs VHYS Low-level output voltage VOL .05 VCC V (Note) 0.3 VCC V (Note) -- V VCC 2.5V (Note) 0.4 V IOL = 3.0 mA, VCC = 4.5V IOL = 2.1 mA, VCC = 2.5V Input leakage current ILI -- 1 A VIN = VCC or VSS Output leakage current ILO -- 1 A VOUT = VCC or VSS Pin capacitance (all inputs/outputs) CIN, COUT -- 10 pF VCC = 5.0V (Note) TA = 25C, f = 1 MHz Operating current ICC Write -- 2 mA VCC = 5.5V, SCL = 400 kHz ICC Read -- 1 mA VCC = 5.5V, SCL = 400 kHz ICCS -- 1 A VCC = 5.5V, SDA = SCL = VCC Standby current Note: This parameter is periodically sampled and not 100% tested. FIGURE 1-1: BUS TIMING DATA THIGH TF SCL TSU:STA TLOW SDA IN TR TSP TSU:DAT THD:DAT TSU:STO THD:STA TBUF TAA SDA OUT DS21178D-page 2 2003 Microchip Technology Inc. 24AA00/24LC00/24C00 TABLE 1-2: AC CHARACTERISTICS All Parameters apply across all recommended operating ranges unless otherwise noted Parameter Commercial (C): Industrial (I): Automotive (E): Symbol TA = 0C to +70C, VCC = 1.8V to 5.5V TA = -40C to +85C, VCC = 1.8V to 5.5V TA = -40C to +125C, VCC = 4.5V to 5.5V Min Max Units Conditions Clock frequency FCLK -- -- -- 100 100 400 kHz 4.5V Vcc 5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc 5.5V Clock high time THIGH 4000 4000 600 -- -- -- ns 4.5V Vcc 5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc 5.5V Clock low time TLOW 4700 4700 1300 -- -- -- ns 4.5V Vcc 5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc 5.5V SDA and SCL rise time (Note 1) TR -- -- -- 1000 1000 300 ns 4.5V Vcc 5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc 5.5V SDA and SCL fall time TF -- 300 ns (Note 1) Start condition hold time THD:STA 4000 4000 600 -- -- -- ns 4.5V Vcc 5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc 5.5V Start condition setup time TSU:STA 4700 4700 600 -- -- -- ns 4.5V Vcc 5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc 5.5V Data input hold time THD:DAT 0 -- ns (Note 2) Data input setup time TSU:DAT 250 250 100 -- -- -- ns 4.5V Vcc 5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc 5.5V Stop condition setup time TSU:STO 4000 4000 600 -- -- -- ns 4.5V Vcc 5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc 5.5V Output valid from clock (Note 2) TAA -- -- -- 3500 3500 900 ns 4.5V Vcc 5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc 5.5V 4700 4700 1300 -- -- -- ns 4.5V Vcc 5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc 5.5V Bus free time: Time the bus must TBUF be free before a new transmission can start Output fall time from VIH minimum to VIL maximum TOF 20+0.1 CB 250 ns (Note 1), CB 100 pF Input filter spike suppression (SDA and SCL pins) TSP -- 50 ns (Notes 1, 3) Write cycle time TWC -- 4 ms 1M -- cycles Endurance Note 1: 2: 3: 4: (Note 4) Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total EnduranceTM Model which can be obtained on www.microchip.com. 2003 Microchip Technology Inc. DS21178D-page 3 24AA00/24LC00/24C00 2.0 PIN DESCRIPTIONS 2.1 SDA Serial Data 4.0 BUS CHARACTERISTICS The following bus protocol has been defined: This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz). * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. Accordingly, the following bus conditions have been defined (Figure 4-1). 2.2 SCL Serial Clock This input is used to synchronize the data transfer from and to the device. 2.3 Noise Protection The SCL and SDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. 3.0 FUNCTIONAL DESCRIPTION The 24XX00 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the Start and Stop conditions, while the 24XX00 works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. 4.1 Bus Not Busy (A) Both data and clock lines remain high. 4.2 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 4.3 Stop Data Transfer (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. 4.4 Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device and is theoretically unlimited. DS21178D-page 4 2003 Microchip Technology Inc. 24AA00/24LC00/24C00 4.5 Acknowledge The device that acknowledges has to pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the Stop condition (Figure 4-2). Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: The 24XX00 does not generate any Acknowledge bits if an internal programming cycle is in progress. FIGURE 4-1: SCL (A) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (C) (D) START CONDITION ADDRESS OR ACKNOWLEDGE VALID (C) (A) SDA FIGURE 4-2: STOP CONDITION DATA ALLOWED TO CHANGE ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 2 SDA 3 4 5 6 7 Data from transmitter Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. 2003 Microchip Technology Inc. 8 9 1 2 3 Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data. DS21178D-page 5 24AA00/24LC00/24C00 5.0 DEVICE ADDRESSING After generating a Start condition, the bus master transmits a control byte consisting of a slave address and a Read/Write bit that indicates what type of operation is to be performed. The slave address for the 24XX00 consists of a 4-bit device code `1010' followed by three don't care bits. The last bit of the control byte determines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. (Figure 5-1). The 24XX00 monitors the bus for its corresponding slave address all the time. It generates an Acknowledge bit if the slave address was true and it is not in a Programming mode. FIGURE 5-1: CONTROL BYTE FORMAT Read/Write Bit Don't Care Bits Device Select Bits S 1 0 1 0 X X X R/W ACK Slave Address Start Bit DS21178D-page 6 Acknowledge Bit 6.0 WRITE OPERATIONS 6.1 Byte Write Following the Start signal from the master, the device code (4 bits), the don't care bits (3 bits), and the R/W bit (which is a logic low) are placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 24XX00. Only the lower four address bits are used by the device, and the upper four bits are don't cares. The 24XX00 will acknowledge the address byte and the master device will then transmit the data word to be written into the addressed memory location. The 24XX00 acknowledges again and the master generates a Stop condition. This initiates the internal write cycle, and during this time the 24XX00 will not generate Acknowledge signals (Figure 7-2). After a byte Write command, the internal address counter will not be incremented and will point to the same address location that was just written. If a Stop bit is transmitted to the device at any point in the Write command sequence before the entire sequence is complete, then the command will abort and no data will be written. If more than 8 data bits are transmitted before the Stop bit is sent, then the device will clear the previously loaded byte and begin loading the data buffer again. If more than one data byte is transmitted to the device and a Stop bit is sent before a full eight data bits have been transmitted, then the Write command will abort and no data will be written. The 24XX00 employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5V (24AA00 and 24LC00) or 3.8V (24C00) at nominal conditions. 2003 Microchip Technology Inc. 24AA00/24LC00/24C00 7.0 ACKNOWLEDGE POLLING FIGURE 7-1: Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the Start bit and control byte must be re-sent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 7-1 for flow diagram. ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? NO YES Next Operation FIGURE 7-2: BYTE WRITE BUS ACTIVITY MASTER S T A R T SDA LINE S CONTROL BYTE 1 0 1 BUS ACTIVITY 0 X X WORD ADDRESS X X 0 A C K X X S T O P DATA P X A C K A C K X = Don't Care Bit 2003 Microchip Technology Inc. DS21178D-page 7 24AA00/24LC00/24C00 8.0 READ OPERATIONS Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. 8.1 Current Address Read The 24XX00 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to one, the device issues an acknowledge and transmits the eight-bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the device discontinues transmission (Figure 8-1). 8.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the device as part of a write operation. FIGURE 8-1: 8.3 Sequential Read Sequential reads are initiated in the same way as a random read except that after the device transmits the first data byte, the master issues an acknowledge as opposed to a Stop condition in a random read. This directs the device to transmit the next sequentially addressed 8-bit word (Figure 8-3). To provide sequential reads the 24XX00 contains an internal address pointer which is incremented by one at the completion of each read operation. This address pointer allows the entire memory contents to be serially read during one operation. CURRENT ADDRESS READ BUS ACTIVITY MASTER S T A R T SDA LINE S 1 0 1 0 X XX 1 BUS ACTIVITY X = Don't Care Bit DS21178D-page 8 After the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24XX00 will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the device discontinues transmission (Figure 8-2). After this command, the internal address counter will point to the address location following the one that was just read. CONTROL BYTE S T O P DATA P A C K N O A C K 2003 Microchip Technology Inc. 24AA00/24LC00/24C00 FIGURE 8-2: RANDOM READ S T BUS ACTIVITY A MASTER R T CONTROL BYTE WORD ADDRESS (n) X X X X S 1 0 1 0 X X X 0 SDA LINE CONTROL BYTE P A C K BUS ACTIVITY MASTER N O A C K X = Don't Care Bit FIGURE 8-3: S T O P DATA (n) S 1 0 1 0 X X X 1 A C K A C K BUS ACTIVITY S T A R T SEQUENTIAL READ CONTROL BYTE DATA n DATA n + 1 DATA n + 2 S T O P DATA n + X SDA LINE BUS ACTIVITY P A C K 2003 Microchip Technology Inc. A C K A C K A C K N O A C K DS21178D-page 9 24AA00/24LC00/24C00 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) Example: XXXXXXXX T/XXXNNN YYWW 24LC00 I/P13F 0327 8-Lead SOIC (150 mil) Example: XXXXXXXX T/XXYYWW NNN 24LC00 I/SN0327 13F Example: 8-Lead TSSOP XXXX 4L00 TYWW I327 NNN 13F TSSOP Marking Code Part Number STD Pb-Free 24AA00 4A00 G4A0 24LC00 4L00 G4L0 Part Number 24AA00 24LC00 24C00 Note: XXNN Legend: Note: * XX...X T YY Y WW NNN Example: SOT-23 Marking Code 5-Lead SOT-23 C I E A0 B0 -- L0 M0 N0 C0 D0 E0 Pb-free parts are marked same as standard finish. Pb-free part number using "G" suffix is marked on carton.. M03F Customer specific information* Temperature grade (I,E) Year code (last 2 digits of calendar year) Year code (last digit of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard QTP marking consists of Microchip part number, year code, week code, and traceability code. DS21178D-page 10 2003 Microchip Technology Inc. 24AA00/24LC00/24C00 8-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A2 A L c A1 B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D L c B1 B eB MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM MAX 8 .100 .155 .130 .170 .145 .313 .250 .373 .130 .012 .058 .018 .370 10 10 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 2003 Microchip Technology Inc. DS21178D-page 11 24AA00/24LC00/24C00 8-Lead Plastic Small Outline (SN) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A2 A L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21178D-page 12 2003 Microchip Technology Inc. 24AA00/24LC00/24C00 8-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm (TSSOP) E E1 p D 2 1 n B A c A1 A2 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D L c B MIN INCHES NOM MAX 8 .026 .033 .002 .246 .169 .114 .020 0 .004 .007 0 0 .035 .004 .251 .173 .118 .024 4 .006 .010 5 5 .043 .037 .006 .256 .177 .122 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 8 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 2.90 3.00 3.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 MIN Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-086 2003 Microchip Technology Inc. DS21178D-page 13 24AA00/24LC00/24C00 5-Lead Plastic Small Outline Transistor (OT) (SOT-23) E E1 p B p1 n D 1 c A Units Dimension Limits n Number of Pins p Pitch p1 Outside lead pitch (basic) Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic L A A2 A1 E E1 D L c B MIN .035 .035 .000 .102 .059 .110 .014 0 .004 .014 0 0 A2 A1 INCHES* NOM 5 .038 .075 .046 .043 .003 .110 .064 .116 .018 5 .006 .017 5 5 MAX .057 .051 .006 .118 .069 .122 .022 10 .008 .020 10 10 MILLIMETERS NOM 5 0.95 1.90 0.90 1.18 0.90 1.10 0.00 0.08 2.60 2.80 1.50 1.63 2.80 2.95 0.35 0.45 0 5 0.09 0.15 0.35 0.43 0 5 0 5 MIN MAX 1.45 1.30 0.15 3.00 1.75 3.10 0.55 10 0.20 0.50 10 10 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-178 Drawing No. C04-091 DS21178D-page 14 2003 Microchip Technology Inc. 24AA00/24LC00/24C00 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. X PART NO. Device /XX Temperature Package Range X Lead Finish Examples: a) b) Device: 24AA00: 24AA00T: 24LC00: 24LC00T: 24C00: 24C00T: = 1.8V, 128 bit I2CTM Serial EEPROM = 1.8V, 128 bit I2C Serial EEPROM (Tape and Reel) = 2.5V, 128 bit I2C Serial EEPROM = 2.5V, 128 bit I2C Serial EEPROM (Tape and Reel) = 5V, 128 bit I2CTM Serial EEPROM = 5V, 128 bit I2CTM Serial EEPROM (Tape and Reel) Temperature Blank = 0C to 70C Range: I = -40C to +85C E = -40C to +125C Package: P SN ST OT = = = = Lead finish Blank = Standard 63/37 SnPb G = Matte Tin (pure Sn) c) d) e) f) 24AA00-I/P: Industrial Temperature,1.8V PDIP package 24AA00-I/SN: Industrial Temperature, 1.8V, SOIC package 24AA00T-I/OT: Industrial Temperature, 1.8V, SOT-23 package, tape and reel 24LC00-I/P: Industrial Temperature, 2.5V, PDIP package 24C00-E/SN: Extended Temperature, 5V, SOIC package 24LC00T-I/OT: Industrial Temperature, 2.5V, SOT-23 package, tape and reel g) 24LC00-I/PG: Industrial Temperature, 2.5V PDIP package, Pb-free h) 24LC00T-I/OTG: Industrial Temperature, 2.5V, SOT-23 package, tape and reel, Pb-free Plastic DIP (300 mil body), 8-lead Plastic SOIC (150 mil body), 8-lead Plastic TSSOP (4.4 mm), 8-lead SOT-23, 5-lead (Tape and Reel only) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2003 Microchip Technology Inc. DS21178D-page15 24AA00/24LC00/24C00 NOTES: DS21178D-page 16 2003 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. 2003 Microchip Technology Inc. DS21178D-page 17 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Korea Corporate Office Australia 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Atlanta Unit 915 Bei Hai Wan Tai Bldg. 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