DS34LV86T
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SNLS115D –JUNE 2000–REVISED APRIL 2013
DS34LV86T 3V Enhanced CMOS Quad Differential Line Receiver
Check for Samples: DS34LV86T
1FEATURES DESCRIPTION
The DS34LV86T is a high speed quad differential
• Low Power CMOS Design (30 mW Typical) CMOS receiver that meets the requirements of both
• Interoperable With Existing 5V RS-422 TIA/EIA-422-B and ITU-T V.11. The CMOS
Networks DS34LV86T features typical low static ICC of 9 mA
• Industrial Temperature Range which makes it ideal for battery powered and power
conscious applications. The Tri-State enables, EN,
• Meets TIA/EIA-422-B (RS-422) and ITU-T V.11 allow the device to be disabled when not in use to
Recommendation minimize power consumption. The dual enable
• 3.3V Operation scheme allows for flexibility in turning receivers on
• ±7V Common Mode Range @ VID = 3V and off.
• ±10V Common Mode Range @ VID = 0.2V The receiver output (RO) is ensured to be High when
the inputs are left open. The receiver can detect
• Receiver OPEN Input Failsafe Feature signals as low as ±200 mV over the common mode
• Ensured AC Parameter: range of ±10V. The receiver outputs (RO) are
– Maximum Receiver Skew: 4 ns compatible with TTL and LVCMOS levels.
– Transition Time: 10 ns
• Pin Compatible With DS34C86T
• 32 MHz Toggle Frequency
• >6.5k ESD Tolerance (HBM)
• Available in SOIC Packaging
Connection Diagram
Figure 1. SOIC (Top View)
See Package Number D
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2000–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DS34LV86T
SNLS115D –JUNE 2000–REVISED APRIL 2013
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TRUTH TABLE(1)
Enable Inputs Output
EN RI+–RI−RO
L X Z
H VID ≥+0.2V H
H VID ≤ −0.2V L
H Open† H
(1) L = Logic Low
H = Logic High
X = Irrelevant
Z = Tri-State
† = Open, Not Terminated
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Supply Voltage (VCC) +7V
Enable Input Voltage (EN) +7V
Receiver Input Voltage (VID: RI+, RI−) ±14V
Receiver Input Voltage (VCM: RI+, RI−) ±14V
Receiver Output Voltage (RO) −0.5V to VCC + 0.5V
Receiver Output Current (RO) ±25 mA
Maximum Package Power Dissipation @ +25°C D Package 1190 mW
Derate D Package 9.8 mW/°C above +25°C
Storage Temperature Range -65°C to +150°C
Lead Temperature Range Soldering (4 Seconds) +260°C
ESD Ratings (HBM, 1.5k, 100 pF) Receiver Inputs and Enables ≥6.5 kV
Other Pins ≥2 kV
(1) Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that
the devices should be operated at these limits. The table of Electrical Characteristics specifies conditions of device operation.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
RECOMMENDED OPERATING CONDITIONS Min Typ Max Units
Supply Voltage (VCC) 3.0 3.3 3.6 V
Operating Free Air Temperature (TA)−40 +25 +85 °C
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ELECTRICAL CHARACTERISTICS(1)(2)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.
Symbol Parameter Conditions Pin Min Typ Max Units
VTH Differential Input Threshold VOUT = VOH or VOL RI+, −200 ±17.5 +200 mV
−7V < VCM < +7V RI−
VHY Hysteresis VCM = 1.5V 35 mV
VIH Minimum High Level Input Voltage 2.0 V
EN
VIL Minimum Low Level Input Voltage 0.8 V
RIN Input Resistance VIN =−7V, +7V 5.0 8.5 kΩ
(Other Input = GND)
IIN Input Current VIN = +10V 0 1.1 1.8 mA
(Other Input = 0V, RI+,
VIN = +3V 0 0.27 mA
Power On or VCC = 0V) RI−
VIN = 0.5V −0.02 mA
VIN =−3V 0 −0.43 mA
VIN =−10V 0 −1.26 −2.2 mA
IEN VIN = 0V to VCC EN ±1 μA
VOH High Level Output Voltage IOH =−6 mA, VID = +1V 2.4 3 V
IOH =−6 mA, VID = OPEN
VOH High Level Output Voltage IOH =−100 μA, VID = +1V VCC −0.1 V
IOH =−100 μA, VID = OPEN
VOL Low Level Output Voltage IOL = +6 mA, VID =−1V 0.13 0.5 V
RO
IOZ Output Tri-State VIN = VCC or GND ±50 μA
Leakage EN = VIL
Current
ISC Output Short Circuit Current VO= 0V, VID ≥|200 mV| −10 −35 −70 mA
See(3)
ICC Power Supply Current No Load, All RI+, RI−= Open, VCC 9 15 mA
EN = VCC or GND
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VID.
(2) All typicals are given for: VCC = +3.3V, TA= +25°C.
(3) Short one output at a time to ground. Do not exceed package power dissipation ratings.
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SWITCHING CHARACTERISTICS(1)(2)(3)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
tPHL Propagation Delay High to Low CL= 15 pF 6 17.5 35 ns
See (Figure 2 and
tPLH Propagation DeIay Low to High 6 17.8 35 ns
Figure 3 )
trRise Time (20% to 80%) 4.1 10 ns
tfFall Time (80% to 20%) 3.3 10 ns
tPHZ Disable Time CL= 50 pF 40 ns
See (Figure 4 and
tPLZ Disable Time 40 ns
Figure 5)
tPZH Enable Time 40 ns
tPZL Enable Time 40 ns
tSK1 Skew, |tPHL −tPLH| See(4) CL= 15 pF 0.3 4 ns
tSK2 Skew, Pin to Pin See(5) 0.6 4 ns
tSK3 Skew, Part to Part See(6) 7 17 ns
fMAX Maximum Operating Frequency CL= 15 pF 32 MHz
See(7)
(1) All typicals are given for: VCC = +3.3V, TA= +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, Duty Cycle = 50%, ZO= 50Ω, tr≤10 ns, tf≤10 ns.
(3) CLincludes probe and jig capacitance.
(4) tSK1 is the |tPHL −tPLH| of a channel.
(5) tSK2 is the maximum skew between any two channels within a device, on either edge.
(6) tSK3 is the difference in propagation delay times between any channels of any devices. This specification (maximum limit) applies to
devices within VCC ±0.1V of one another,and a Delta TA= ±5°C (between devices) within the operating temperature range. This
parameter is specified by design and characterization.
(7) All channels switching, output duty cycle criteria is 40%/60% measured at 50% Input = 1V to 2V, 50% Duty Cycle, tr/tf≤5 ns. This
parameter is ensured by design and characterization.
PARAMETER MEASUREMENT INFORMATION
Generator waveform for all tests unless otherwise specified: f = 1 MHz, Duty Cycle = 50%, ZO= 50Ω, tr≤10 ns, tf≤
10 ns.
CLincludes probe and jig capacitance.
Figure 2. Receiver Propagation Delay and Transition Time Test Circuit
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SNLS115D –JUNE 2000–REVISED APRIL 2013
PARAMETER MEASUREMENT INFORMATION (continued)
Generator waveform for all tests unless otherwise specified: f = 1 MHz, Duty Cycle = 50%, ZO= 50Ω, tr≤10 ns, tf≤
10 ns.
CLincludes probe and jig capacitance.
Figure 3. Receiver Propagation Delay and Transition Time Waveform
Figure 4. Receiver Tri-State Test Circuit
Generator waveform for all tests unless otherwise specified: f = 1 MHz, Duty Cycle = 50%, ZO= 50Ω, tr≤10 ns, tf≤
10 ns.
CLincludes probe and jig capacitance.
Figure 5. Receiver Tri-State Output Enable and Disable Waveforms
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SNLS115D –JUNE 2000–REVISED APRIL 2013
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TYPICAL APPLICATION INFORMATION
General application guidelines and hints for differential drivers receivers may be found in the following application
notes:
AN-214 (SNLA137), AN-457 (SNLA148), AN-805 (SNOA233), AN-847 (SNLA031), AN-903 (SNLA034), AN-912
(SNLA036), AN-916 (SNLA219)
Power Decoupling Recommendations: Bypass caps must be used on power pins. High frequency ceramic
(surface mount is recommended) 0.1 μF in paraIIel with 0.01 μF at the power supply pin. A 10 μF or greater solid
tantalum or electrolytic should be connected at the power entry point on the printed circuit board.
RTis optional although highly recommended to reduce reflection
Figure 6. Typical Receiver Connections
Figure 7. Typical Receiver Output Waveforms
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SNLS115D –JUNE 2000–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision C (April 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 8
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS34LV86TM/NOPB ACTIVE SOIC D 16 48 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS34LV86
TM
DS34LV86TMX/NOPB ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS34LV86
TM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS34LV86TMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Aug-2018
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS34LV86TMX/NOPB SOIC D 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Aug-2018
Pack Materials-Page 2
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