N-Channel Power MOSFET
ESD
LT2N7002E
01
Rev 0. Nov. 2007
GENERAL DESCRIPTION
The LT2N7002E is the N-Channel logic enhancement mode power
field effect transistors are produced using high cell density , DMOS
trench technology. This high density process is especially tailored to
minimize on-state resistance. These devices are particularly suited
for low voltage application such as cellular phone and notebook
computer power management and other battery powered circuits
where high-side switching , and low in-line power loss are needed in
a very small outline surface mount package.
FEATURES
● Simple Drive Requirement
● Small Package Outline
● ROHS Compliant
● ESD Rating = 2000V HBM
Mechanical data
● High density cell design for low RDS(ON)
● Voltage controlled small signal switching.
● Rugged and reliable.
● High saturation current capability.
● High-speed switching.
● Not thermal runaway.
● The soldering temperature and time shall
not exceed 260℃ for more than 10 seconds.
PIN CONFIGURATION
(SOT-23)
Top View
Absolute Maximum Ratings (TA=25℃ Unless Otherwise Noted)
Parameter Symbol Ratings Unit
Drain-Source Voltage VDS 60 V
Gate-Source Voltage VGS ±20 V
Continuous Drain Current ID 300 mA
Pulsed Drain Current (Note 1) IDM 2000 mA
PD @TA=25°C 0.35
Maximum Power Dissipation
PD @TA=75°C 0.21
W
Operating Junction and Storage Temperature Range TJ, Tstg -55 ~ 150 °C
Junction-to-Ambient Thermal Resistance
(PCB mounted) (Note 2) RθJA 357 °C/W