SPRS073B – AUGUST 1998 – REVISED APRIL 2000
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Best Price/Performance Digital Signal
Processors (DSPs)
Fixed-Point: TMS320C6211
Floating-Point: TMS320C6711
– 10-, 6.7-ns Instruction Cycle Time
– 100-, 150-MHz Clock Rates
– Eight 32-Bit Instructions/Cycle
– 1200 MIPS (’C6211)
– 900 MFLOPS (’C6711)
– ’C6211 and ’C6711 are Pin-Compatible
VelociTI Advanced Very Long Instruction
Word (VLIW) ’C6200 CPU Core (’C6211)
– Eight Highly Independent Functional
Units:
– Six ALUs (32-/40-Bit)
– Two 16-Bit Multipliers (32-Bit Results)
– Load-Store Architecture With 32 32-Bit
General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
VelociTI Advanced Very Long Instruction
Word (VLIW) ’C6700 CPU Core (’C6711)
– Eight Highly Independent Functional
Units:
– Four ALUs (Floating- and Fixed-Point)
– Two ALUs (Fixed-Point)
– Two Multipliers (Floating- and
Fixed-Point)
– Load-Store Architecture With 32 32-Bit
General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
Instruction Set Features
– Hardware Support for IEEE
Single-Precision Instructions (’C6711
Only)
– Hardware Support for IEEE
Double-Precision Instructions (’C6711
Only)
– Byte-Addressable (8-, 16-, 32-Bit Data)
– 8-Bit Overflow Protection
– Saturation
– Bit-Field Extract, Set, Clear
– Bit-Counting
– Normalization
L1/L2 Memory Architecture
– 32K-Bit (4K-Byte) L1P Program Cache
(Direct Mapped)
– 32K-Bit (4K-Byte) L1D Data Cache
(2-Way Set-Associative)
– 512K-Bit (64K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible Data/Program Allocation)
– 1024M-Byte Addressable External
Memory Space
32-Bit External Memory Interface (EMIF)
– Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
– Glueless Interface to Asynchronous
Memories: SRAM and EPROM
Enhanced Direct-Memory-Access (EDMA)
Controller
16-Bit Host-Port Interface (HPI)
– Access to Entire Memory Map
Two Multichannel Buffered Serial Ports
(McBSPs)
– Direct Interface to T1/E1, MVIP, SCSA
Framers
– ST-Bus-Switching Compatible
– Up to 256 Channels Each
– AC97-Compatible
– Serial-Peripheral-Interface (SPI)
Compatible (Motorola)
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked-Loop (PLL) Clock
Generator
IEEE-1149.1 (JTAG†)
Boundary-Scan-Compatible
256-Pin Ball Grid Array (BGA) Package
(GFN Suffix)
0.18-µm/5-Level Metal Process
– CMOS Technology
3.3-V I/Os, 1.8-V Internal
ADVANCE INFORMATION
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
VelociTI is a trademark of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
2POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Table of Contents
electrical characteristics over recommended ranges of
supply voltage and operating case temperature 26.
parameter measurement information 27. . . . . . . . . . . . . . .
input and output clocks 28. . . . . . . . . . . . . . . . . . . . . . . . . . .
asynchronous memory timing 31. . . . . . . . . . . . . . . . . . . . .
synchronous-burst memory timing 34. . . . . . . . . . . . . . . . .
synchronous DRAM timing 36. . . . . . . . . . . . . . . . . . . . . . . .
HOLD/HOLDA timing 42. . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset timing 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
external interrupt timing 45. . . . . . . . . . . . . . . . . . . . . . . . . .
host-port interface timing 46. . . . . . . . . . . . . . . . . . . . . . . . .
multichannel buffered serial port timing 49. . . . . . . . . . . . .
timer timing 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG test-port timing 61. . . . . . . . . . . . . . . . . . . . . . . . . . . .
mechanical data 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GFN BGA package (bottom view) 2. . . . . . . . . . . . . . . . . . . . . .
description 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device characteristics 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device compatibility 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
functional block and CPU diagram 5. . . . . . . . . . . . . . . . . . . . .
CPU description 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
signal groups description 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
signal descriptions 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
development support 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
documentation support 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
clock PLL 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
absolute maximum ratings over operating case
temperature range 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions 26. . . . . . . . . . . . . . . . . . .
GFN BGA package (bottom view)
1915 1713119
Y
V
T
U
P
N
R
W
75
L
J
K
H
F
G
31
D
B
C
A
E
M
2468 201816141210
GFN 256-PIN BALL GRID ARRAY (BGA) PACKAGE
(BOTTOM VIEW)
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
description
The TMS320C62x DSPs (including the TMS320C6211 device) are the fixed-point DSP family in the
TMS320C6000 platform. The TMS320C67x DSPs (including the TMS320C6711 device) are the
floating-point DSP family in the TMS320C6000 platform. The TMS320C6211 (’C6211) and TMS320C6711
(’C6711) devices are based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW)
architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and
multifunction applications.
With performance of up to 1200 million instructions per second (MIPS) at a clock rate of 150 MHz, the ’C6211
device offers cost-effective solutions to high-performance DSP programming challenges. The ’C6211 DSP
possesses the operational flexibility of high-speed controllers and the numerical capability of array processors.
This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional
units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and
two 16-bit multipliers for a 32-bit result. The ’C6211 can produce two multiply-accumulates (MACs) per cycle
for a total of 300 million MACs per second (MMACS).
With performance of up to 900 million floating-point operations per second (MFLOPS) at a clock rate of
150 MHz, the ’C6711 device also offers cost-effective solutions to high-performance DSP programming
challenges. The 100-MHz device is the lowest-cost DSP in the ’C6000 family. The ’C6711 DSP possesses the
operational flexibility of high-speed controllers and the numerical capability of array processors. This processor
has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight
functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point
multipliers. The ’C6711 can produce two MACs per cycle for a total of 300 MMACS.
Both the ’C6211 and ’C6711 DSPs have the same application-specific hardware logic, on-chip memory, and
additional on-chip peripherals.
The ’C6211/’C6711 uses a two-level cache-based architecture and has a powerful and diverse set of
peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache
(L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory
space that is shared between program and data space. L2 memory can be configured as mapped memory,
cache, or combinations of the two.The peripheral set includes two multichannel buf fered serial ports (McBSPs),
two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF)
capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.
The ’C6211/’C6711 has a complete set of development tools which includes: a new C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source
code execution.
ADVANCE INFORMATION
TMS320C62x, TMS320C6000, and TMS320C67x are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
4POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
device characteristics
Table 1 provides an overview of the ’C6211/’C6711 DSP. The table shows significant features of each device,
including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count.
Table 1. Characteristics of the ’C6211/’C6711 Processors
HARDWARE FEATURES ’C6211 (FIXED-POINT DSP) ’C6711 (FLOATING-POINT DSP)
EMIF 1 1
EDMA 1 1
Peripherals HPI 1 1
Peri herals
McBSPs 2 2
32-Bit Timers 2 2
Size (Bytes) 72K 72K
On-Chip Memory Organization 4K-Byte (4KB) L1 Program (L1P) Cache
4KB L1 Data (L1D) Cache
64KB Unified Mapped RAM/Cache (L2)
4K-Byte (4KB) L1 Program (L1P) Cache
4KB L1 Data (L1D) Cache
64KB Unified Mapped RAM/Cache (L2)
Frequency MHz 150 150, 100
Cycle Time ns 6.7 ns (’6211-150) 6.7 ns (’6711-150)
10 ns (’6711-100 [Lowest-Cost Device])
Voltage
Core (V) 1.8 1.8
Voltage I/O (V) 3.3 3.3
PLL Options CLKIN frequency multiplier Bypass (x1), x4 Bypass (x1), x4
BGA Package 27 x 27 mm 256-Pin BGA (GFN) 256-Pin BGA (GFN)
Process Technology µm0.18 µm0.18 µm
Product Status Product Preview (PP)
Advance Information (AI)
Production Data (PD) AI AI
device compatibility
The TMS320C6211 and ’C6711 devices are pin-compatible and have the same peripheral set; thus, making ne w
system designs easier and providing faster time to market. The following list summarizes the device
characteristic differences between the ’C6211 and ’C6711 devices:
The ’C6211 device has a fixed-point ’C62x CPU, while the ’C6711 device has a floating-point ’C67x CPU.
A 100-MHz version of the ’C6711 is available, providing the lowest-cost entry in the TMS320C6000
platform.
For a more detailed discussion on the similarities/differences between the ’C6211 and ’C6711 devices, see the
How to Begin Development Today with the TMS320C6211 DSP
and
How to Begin Development Today with the
TMS320C6711 DSP
application reports (literature number SPRA474 and SPRA522, respectively).
ADVANCE INFORMATION
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5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
functional block and CPU diagram
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Test
’C6000 CPU†
Data Path B
B Register File
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path A
A Register File
Power-Down
Logic
.L1‡.S1‡.M1‡.D1 .D2 .M2‡.S2‡.L2‡
32
SDRAM
ROM/FLASH
SBSRAM
I/O Devices
L1P Cache
Direct Mapped
4K Bytes Total
Control
Registers
Control
Logic
L1D Cache
2-Way Set
Associative
4K Bytes Total
In-Circuit
Emulation
Interrupt
Control
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
’C6211/’C6711 Digital Signal Processors
†The ’C6211 device has a fixed-point ’C62x CPU, while the ’C6711 device has a floating-point ’C67x CPU.
‡For the ’C6711 device only, in addition to fixed-point instructions, these functional units execute floating-point instructions.
Enhanced
DMA
Controller
(16 channel)
16
L2
Memory
4 Banks
64K Bytes
Total
PLL
(x1, x4)
Timer 0
External
Memory
Interface
(EMIF)
Multichannel
Buffered
Serial Port 1
(McBSP1)
Multichannel
Buffered
Serial Port 0
(McBSP0)
Host Port
Interface
(HPI)
SRAM
Timer 1
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
6POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CPU description
The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight
32-bit ins t r u c t i ons to the eight functional units during every clock cycle. The VelociTI VLIW architecture features
controls by w h i c h a l l e i ght units do not have to be supplied with instructions if they are not ready to execute. The
first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the
previous instruction, or whether it should be executed in the following clock as a part of the next execute packet.
Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length
execute packets are a key memory-saving feature, distinguishing the ’C62x and ’C67x CPUs from other VLIW
architectures.
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along
with two register files, compose sides A and B of the CPU (see the functional block and CPU diagram and
Figure 1 for the ’C6211 device; and see the functional block and CPU diagram and Figure 2 for the ’C6711
device). The four functional units on each side of the CPU can freely share the 16 registers belonging to that
side. Additionally, each side features a single data bus connected to all the registers on the other side, by which
the two sets of functional units can access data from the register files on the opposite side. While register access
by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle,
register access using the register file across the CPU supports one read and one write per cycle.
The ’C67x CPU executes all ’C62x instructions. In addition to ’C62x fixed-point instructions, the six out of eight
functional units (.L1, .M1, .D1, .D2, .M2, and .L2) also execute floating-point instructions. The remaining two
functional units (.S1 and .S2) also execute the new LDDW instruction which loads 64 bits per CPU side for a
total of 128 bits per cycle.
Another key feature of the ’C62x/’C67x CPU is the load/store architecture, where all instructions operate on
registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for
all data transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
’C62x/’C67x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing
modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers.
Some registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the
fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of
the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet
can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one
per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store
instructions are byte-, half-word, or word-addressable.
ADVANCE INFORMATION
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7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CPU description (continued)
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2X
1X
.L2
.S2
.M2
.D2
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.M1
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.L1
long src
dst
src
2
src
1
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src
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src
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src
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src
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src
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src
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src
1
8
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8
88
long dst
long dst
dst
dst
dst
dst
dst
dst
dst
src
2
src
2
src
2
src
2
src
2
src
2
src
2
long src
ÁÁ
DA1
DA2
ST1
LD1
LD2
ST2
32
32
Register
File A
(A0–A15)
long src
long dst
long dst
long src
Data Path B
Data Path A
Register
File B
(B0–B15)
Control
Register
File
Figure 1. TMS320C62x CPU Data Paths
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
8POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CPU description (continued)
8
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8
long src
dst
src2
src1
src1
src1
src1
src1
src1
src1
src1
long dst
long dst
dst
dst
dst
dst
dst
dst
dst
src2
src2
src2
src2
src2
src2
src2
long src
long src
long dst
long dst
long src
8
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2X
1X
.L2†
.S2†
.M2†
.D2
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Á
Á
Á
Á
Á
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
.D1
.M1†
Á
Á
Á
Á
Á
Á
Á
ÁÁ
ÁÁ
Á
Á
Á
.S1†
Á
ÁÁ
ÁÁ
Á
Á
.L1†
Á
Á
Á
Á
Á
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
Á
Control
Register File
Á
DA1
DA2
ST1
LD1 32 LSB
LD2 32 LSB
LD2 32 MSB
32
32
Data Path A
Data Path B
Register
File A
(A0–A15)
Register
File B
(B0–B15)
LD1 32 MSB
32
ST2 32
8
8
8
Á
Á
†For the ’C6711 device only, in addition to fixed-point instructions, these functional units execute floating-point instructions.
Figure 2. TMS320C67x CPU Data Paths
ADVANCE INFORMATION
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
signal groups description
HHWIL
HCNTL0
HCNTL1
TRST
EXT_INT7
IEEE Standard
1149.1
(JTAG)
Emulation
Reserved
Data
Register Select
Half-Word
Select
Reset and
Interrupts
Control
HPI
(Host-Port Interface)
16
Control/Status
TDI
TDO
TMS
TCK
EMU0
EMU1
HD[15:0]
NMI
HAS
HR/W
HCS
HDS1
HDS2
HRDY
HINT
EXT_INT6
EXT_INT5
EXT_INT4
RESET
RSV4
RSV3
RSV2
RSV1
RSV0
Clock/PLL
CLKIN
CLKOUT1
CLKMODE0
PLLV
PLLG
PLLF
CLKOUT2
EMU2
EMU3
EMU4
EMU5
RSV5
Figure 3. CPU and Peripheral Signals
ADVANCE INFORMATION
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10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
signal groups description (continued)
CE3
ECLKOUT
ED[31:0]
CE2
CE1
CE0
EA[21:2]
BE3
BE2
BE1
BE0
TOUT1
CLKX1
FSX1
DX1
CLKR1
FSR1
DR1
CLKS1
AOE/SDRAS/SSOE
AWE/SDWE/SSWE
ARDY
TOUT0
CLKX0
FSX0
DX0
CLKR0
FSR0
DR0
CLKS0
Data
Memory Map
Space Select
Address
Byte Enables
32
20
Memory
Control
EMIF
(External Memory Interface)
Timer 1
Receive Receive
Timer 0
Timers
McBSP1 McBSP0
Transmit Transmit
Clock Clock
McBSPs
(Multichannel Buffered Serial Ports)
TINP1 TINP0
ECLKIN
HOLD
HOLDA
BUSREQ
Bus
Arbitration
ARE/SDCAS/SSADS
Figure 4. Peripheral Signals
ADVANCE INFORMATION
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Signal Descriptions
SIGNAL
TYPE†
IPD/
‡
DESCRIPTION
NAME NO. TYPE
†
IPD/
IPU‡
DESCRIPTION
CLOCK/PLL
CLKIN A3 I IPU Clock Input
CLKOUT1 D7 O IPD Clock output at device speed
CLKOUT2 Y12 O IPD Clock output at half of device speed
CLKMODE0 C4 I IPU Clock mode select
•Selects whether the CPU clock frequency = input clock frequency x4 or x1
PLLV§A4 A¶PLL analog VCC connection for the low-pass filter
PLLG§C6 A¶PLL analog GND connection for the low-pass filter
PLLF B5 A¶PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
TMS B7 I IPU JTAG test-port mode select
TDO A8 O/Z IPU JTAG test-port data out
TDI A7 I IPU JTAG test-port data in
TCK A6 I IPU JTAG test-port clock
TRST B6 I IPD JTAG test-port reset
EMU5 B12 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected.
EMU4 C11 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected.
EMU3 B10 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected.
EMU2 D10 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected.
EMU1 B9 I/O/Z IPU Emulation pin 1#
EMU0 D9 I/O/Z IPU Emulation pin 0#
RESETS AND INTERRUPTS
RESET A13 I IPU Device reset
NMI C13 I IPD Nonmaskable interrupt
•Edge-driven (rising edge)
EXT_INT7 E3
EXT_INT6 D2
I
IPU
External interrupts
EXT_INT5 C1 I IPU
External
interru ts
•Edge-driven (rising edge)
EXT_INT4 C2
g(gg)
HOST-PORT INTERFACE (HPI)
HINT J20 O IPU Host interrupt (from DSP to host)
HCNTL1 G19 I IPU Host control – selects between control, address, or data registers
HCNTL0 G18 I IPU Host control – selects between control, address, or data registers
HHWIL H20 I IPU Host half-word select – first or second half-word (not necessarily high or low order)
HR/W G20 I IPU Host read or write select
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = internal pullup. [These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a resistor in the range of 4.7 kΩ to 5.1 kΩ should be used.]
§PLLV and PLLG are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect these
pins.
¶A = Analog Signal (PLL Filter)
#The EMU0 and EMU1 pins are internally pulled up with 30-kΩ resistors; therefore, for emulation and normal operation, no external
pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with an external dedicated
resistor in the range of 4.7 kΩ to 5.1 kΩ.
ADVANCE INFORMATION
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12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Signal Descriptions (Continued)
SIGNAL
TYPE†
IPD/
DESCRIPTION
NAME NO. TYPE
†
IPD/
IPU‡ DESCRIPTION
HOST-PORT INTERFACE (HPI) (CONTINUED)
HD15 B14 IPU
HD14 C14 IPU
HD13 A15 IPU
HD12 C15 IPU
HD11 A16 IPU Host-port data
Udft f fdt dd d tl
HD10 B16 IPU •Used for transfer of data, address, and control
•Also controls initialization of DSP modes at reset via
p
ullu
p
/
p
ulldown resistors
HD9 C16 IPU •
Al
so con
t
ro
l
s
i
n
iti
a
li
za
ti
on o
f
DSP
mo
d
es a
t
rese
t
v
i
a pu
ll
up
/
pu
lld
own res
i
s
t
ors
– Device Endian Mode
HD8 B17
I/O/Z
IPU
Device
Endian
Mode
HD8: 0 – Big Endian
1 Little Endian
HD7 A18 I/O/Z IPU 1 – Little Endian
–
Boot mode
HD6 C17 IPU –
Boot
mode
HD[4:3]: 00 – HPI boot
HD5 B18 IPU
HD[4:3]: 00 HPI
boot
01 – 8-bit ROM boot with default timings
10 16 bit ROM boot with default timings
HD4 C19 IPD 10 – 16-bit ROM boot with default timings
11
–
32
-
bit ROM boot with default timings
HD3 C20 IPU
11
–
32
-
bit
ROM
boot
with
default
timings
HD2 D18 IPU
HD1 D20 IPU
HD0 E20 IPU
HAS E18 I IPU Host address strobe
HCS F20 I IPU Host chip select
HDS1 E19 I IPU Host data strobe 1
HDS2 F18 I IPU Host data strobe 2
HRDY H19 O IPU Host ready (from DSP to host)
EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
CE3 V6 O/Z IPU
CE2 W6 O/Z IPU Memory space enables
•Enabled by bits 28 through 31 of the word address
CE1 W18 O/Z IPU •Enabled by bits 28 through 31 of the word address
•
O
nl
y
o
n
e
asse
rt
ed
du
rin
g
a
n
y
e
xt
e
rn
a
l
da
t
a
access
CE0 V17 O/Z IPU
•Only
one
asserted
during
any
external
data
access
BE3 V5 O/Z IPU
Byte-enable control
BE2 Y4 O/Z IPU
B
yte-ena
bl
e contro
l
•Decoded from the two lowest bits of the internal address
BE1 U19 O/Z IPU
•Decoded
from
the
two
lowest
bits
of
the
internal
address
•Byte-write enables for most types of memory
C b di tl t d t SDRAM d d it k i l (SDQM)
BE0 V20 O/Z IPU
yyy
•Can be directly connected to SDRAM read and write mask signal (SDQM)
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = internal pullup. [These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a resistor in the range of 4.7 kΩ to 5.1 kΩ should be used.]
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
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Signal Descriptions (Continued)
SIGNAL
TYPE†
IPD/
DESCRIPTION
NAME NO. TYPE
†
IPD/
IPU‡DESCRIPTION
EMIF – BUS ARBITRATION
HOLDA J18 O/Z IPU Hold-request-acknowledge to the host
HOLD J17 I IPU Hold request from the host
BUSREQ J19 O/Z IPU Bus request output
EMIF – ASYNCHRONOUS/SYNCHRONOUS DRAM/SYNCHRONOUS BURST SRAM MEMORY CONTROL
ECLKIN Y11 I IPD EMIF input clock
ECLKOUT Y10 O IPD EMIF output clock (based on ECLKIN)
ARE/SDCAS/
SSADS V11 O/Z IPU Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe
AOE/SDRAS/
SSOE W10 O/Z IPU Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable
AWE/SDWE/
SSWE V12 O/Z IPU Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable
ARDY Y5 I IPU Asynchronous memory ready input
EMIF – ADDRESS
EA21 U18
EA20 Y18
EA19 W17
EA18 Y16
EA17 V16
EA16 Y15
EA15 W15
EA14 Y14
EA13 W14
EA12 V14
O/Z
IPU
External address (word address)
EA11 W13 O/Z IPU External address (word address)
EA10 V10
EA9 Y9
EA8 V9
EA7 Y8
EA6 W8
EA5 V8
EA4 W7
EA3 V7
EA2 Y6
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = internal pullup. [These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a resistor in the range of 4.7 kΩ to 5.1 kΩ should be used.]
ADVANCE INFORMATION
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14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Signal Descriptions (Continued)
SIGNAL
TYPE†
IPD/
DESCRIPTION
NAME NO. TYPE
†
IPD/
IPU‡ DESCRIPTION
EMIF – DATA
ED31 N3
ED30 P3
ED29 P2
ED28 P1
ED27 R2
ED26 R3
ED25 T2
ED24 T1
ED23 U3
ED22 U1
ED21 U2
ED20 V1
ED19 V2
ED18 Y3
ED17 W4
ED16 V4
I/O/Z
IPU
External data
ED15 T19 I/O/Z IPU External data
ED14 T20
ED13 T18
ED12 R20
ED11 R19
ED10 P20
ED9 P18
ED8 N20
ED7 N19
ED6 N18
ED5 M20
ED4 M19
ED3 L19
ED2 L18
ED1 K19
ED0 K18
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = internal pullup. [These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a resistor in the range of 4.7 kΩ to 5.1 kΩ should be used.]
ADVANCE INFORMATION
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Signal Descriptions (Continued)
SIGNAL
TYPE†
IPD/
DESCRIPTION
NAME NO. TYPE
†
IPD/
IPU‡ DESCRIPTION
TIMERS
TOUT1 F1 O IPD Timer 1 or general-purpose output
TINP1 F2 I IPD Timer 1 or general-purpose input
TOUT0 G1 O IPD Timer 0 or general-purpose output
TINP0 G2 I IPD Timer 0 or general-purpose input
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1 E1 I IPD External clock source (as opposed to internal)
CLKR1 M1 I/O/Z IPD Receive clock
CLKX1 L3 I/O/Z IPD Transmit clock
DR1 M2 I IPU Receive data
DX1 L2 O/Z IPU Transmit data
FSR1 M3 I/O/Z IPD Receive frame sync
FSX1 L1 I/O/Z IPD Transmit frame sync
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKS0 K3 I IPD External clock source (as opposed to internal)
CLKR0 H3 I/O/Z IPD Receive clock
CLKX0 G3 I/O/Z IPD Transmit clock
DR0 J1 I IPU Receive data
DX0 H2 O/Z IPU Transmit data
FSR0 J3 I/O/Z IPD Receive frame sync
FSX0 H1 I/O/Z IPD Transmit frame sync
RESERVED FOR TEST
RSV0 C12 O IPU Reserved (leave unconnected,
do not
connect to power or ground)
RSV1 D12 O IPU Reserved (leave unconnected,
do not
connect to power or ground)
RSV2 A5 O IPU Reserved (leave unconnected,
do not
connect to power or ground)
RSV3 D3 O Reserved (leave unconnected,
do not
connect to power or ground)
RSV4 N2 O Reserved (leave unconnected,
do not
connect to power or ground)
RSV5 Y20 O Reserved (leave unconnected,
do not
connect to power or ground)
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = internal pullup. [These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a resistor in the range of 4.7 kΩ to 5.1 kΩ should be used.]
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Signal Descriptions (Continued)
SIGNAL
TYPE†
DESCRIPTION
NAME NO. TYPE
†
DESCRIPTION
SUPPLY VOLTAGE PINS
A17
B3
B8
B13
C5
C10
D1
D16
D19
F3
H18
J2
M18
N1
DVDD R1 S3.3-V supply voltage
DVDD
R18
S
3
.
3V
su ly
voltage
T3
U5
U7
U12
U16
V13
V15
V19
W3
W9
W12
Y7
Y17
A9
A10
A12
B2
B19
CV
C3
S
1 8 V supply voltage
CVDD C7 S1.8-V supply voltage
C18
D5
D6
D11
D14
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Signal Descriptions (Continued)
SIGNAL
TYPE†
DESCRIPTION
NAME NO. TYPE
†
DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
D15
F4
F17
K1
K4
K17
L4
L17
L20
CV
R4
S
1 8 V supply voltage
CVDD R17 S1.8-V supply voltage
U6
U10
U11
U14
U15
V3
V18
W2
W19
GROUND PINS
A1
A2
A11
A14
A19
A20
B1
B4
V
B11
GND
Ground pins
VSS B15 GND Ground pins
B20
C8
C9
D4
D8
D13
D17
E2
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Signal Descriptions (Continued)
SIGNAL
TYPE†
DESCRIPTION
NAME NO. TYPE
†
DESCRIPTION
GROUND PINS (CONTINUED)
E4
E17
F19
G4
G17
H4
H17
J4
K2
K20
M4
M17
N4
N17
P4
P17
V
P19
GND
Ground pins
VSS T4 GND Ground pins
T17
U4
U8
U9
U13
U17
U20
W1
W5
W11
W16
W20
Y1
Y2
Y13
Y19
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
development support
TI offers an extensive line of development tools for the TMS320C6000 generation of DSPs, including tools
to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of ’C6000-based applications:
Software Development Tools:
Code Composer Studio Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software
needed to support any DSP application.
Hardware Development Tools:
Extended Development System (XDS) Emulator (supports ’C6000 multiprocessor system debug)
EVM (Evaluation Module)
The
TMS320 DSP Development Support Reference Guide
(SPRU011) contains information about
development-support products for all TMS320 family member devices, including documentation. See this
document for further information on TMS320 documentation or any TMS320 support products from Texas
Instruments. An additional document, the
TMS320 Third-Party Support Reference Guide
(SPRU052), contains
information about TMS320-related products from other companies in the industry. To receive TMS320 literature,
contact the Literature Response Center at 800/477-8924.
See Table 2 for a complete listing of development-support tools for the TMS320C6000 DSP family. For
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
ADVANCE INFORMATION
TMS320C6000, Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments.
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
development support (continued)
Table 2. TMS320C6000 Development-Support Tools
TOOL
PART NUMBER DESCRIPTION DSP/
BIOS
CODE
COMPOSER
STUDIOIDE
CODE
GENERATION
TOOLS
EMULATION
DRIVERS RTDX SIMULATOR TARGET
HARDWARE
TMDX320DAIS-07 TMS320 DSP Algorithm
Standard Developer’s Kit
SOFTWARE TOOLS
6CCSFreeTool
TMS320C6000
Code Composer Studio
Free Evaluation Tools
(FREE 30-Day Trial)†
√ √ √ √ √
TMDX324685C-07
(Windows 95/98
Windows NT)
TMS320C6000 DSP
Code Composer Studio IDE √ √ √ √ √ √
TMDX3246855-07
(Windows 95/98/NT)
TMS320C6000 DSP
Code Composer Studio IDE
Compile Tools √ √ √ √
TMDX3240160-07
(Windows 95/98/NT)
TMS320C6000 DSP
Code Composer Studio IDE
Debug Tools √ √ √ √
HARDWARE TOOLS
TMDX320006211
(DSK)
TMS320C6211 DSP Starter
Kit (DSK)
256KB Code Memory Limit √ √ √ DSK-Specific √C6211 DSP
TMDS3260A6201 TMS320C62x DSP
Evaluation Module (EVM) √ √ EVM-Specific √C6201 DSP
TMDS326006201 TMS320C62x DSP EVM
Bundle √ √ √ EVM-Specific √ √ C6201 DSP
TMDX3260A6701 TMS320C67x DSP EVM √ √ EVM-Specific √C6701 DSP
TMDX326006701 TMS320C67x DSP EVM
Bundle √ √ √ EVM-Specific √ √ C6701 DSP
TMDS00510 XDS510 DSP Emulation
Hardware
Any C6000
DSP via
JTAG
†The TMS320C6000 Code Composer Studio Free Evaluation Tools can be downloaded for a free 30-day trial from the Texas Instruments web
site at http://www.ti.com. A CD-ROM version of the TMS320C6000 Code Composer Studio Free Evaluation Tools (literature number SPRC020)
is also available. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
ADVANCE INFORMATION
Code Composer Studio, TMS320, TMS320C6000, TMS320C62x, TMS320C67x, and XDS510 are trademarks of Texas Instruments.
Windows and Windows NT are registered trademarks of Microsoft Corporation.
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
device and development-support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320
devices and support tools. Each TMS320 member has one of three prefixes: TMX, TMP, or TMS. Texas
Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These
prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX)
through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device’s electrical
specifications
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also i n c l udes a suffix with the device family name. This suffix indicates the package type
(for example, GFN) and the device speed range in megahertz (for example, -150 is 150 MHz). Figure 5 provides
a legend for reading the complete device name for any TMS320 family member.
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
device and development-support tool nomenclature (continued)
PREFIX DEVICE SPEED RANGE
TMS 320 C 6211 GFN 150
TMX= Experimental device
TMP= Prototype device
TMS= Qualified device
SMJ = MIL-STD-883C
SM = High Rel (non-883C)
DEVICE FAMILY
320 = TMS320 family
TECHNOLOGY
PACKAGE TYPE†
N = Plastic DIP
J = Ceramic DIP
JD = Ceramic DIP side-brazed
GB = Ceramic PGA
FZ = Ceramic CC
FN = Plastic leaded CC
FD = Ceramic leadless CC
PJ = 100-pin plastic EIAJ QFP
PQ = 132-pin plastic bumpered QFP
PZ = 100-pin plastic TQFP
PBK = 128-pin plastic TQFP
PGE = 144-pin plastic TQFP
GFN = 256-pin plastic BGA
GGU = 144-pin plastic BGA
GGP = 352-pin plastic BGA
GJC = 352-pin plastic BGA
GJL = 352-pin plastic BGA
GLS = 384-pin plastic BGA
GLW = 340-pin plastic BGA
GHK = 288-pin plastic MicroStar BGA
C = CMOS
E = CMOS EPROM
F = CMOS Flash EEPROM
DEVICE
’1x DSP: 10 16
14 17
15
’2x DSP: 25
26
’2xx DSP:203 206 240
204 209
’3x DSP: 30
31
32
’4x DSP: 40
44
’5x DSP: 50 53
51 56
52 57
’54x DSP:541 545
542 546
543 548
’6x DSP: 6201 6205
6202 6211
6202B 6701
6203 6711
6204
†DIP = Dual-In-Line Package
PGA = Pin Grid Array
CC = Chip Carrier
QFP = Quad Flat Package
TQFP = Thin Quad Flat Package
BGA = Ball Grid Array
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)
( )
Blank = 0°C to 90°C, commercial temperature
A = –40°C to 105°C, extended temperature
100 MHz
120 MHz
150 MHz
167 MHz
200 MHz
233 MHz
250 MHz
300 MHz
Figure 5. TMS320 Device Nomenclature (Including TMS320C6211 and TMS320C6711 devices)
MicroStar BGA is a trademark of Texas Instruments.
ADVANCE INFORMATION
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documentation support
Extensive documentation supports all TMS320 family generations of devices from product announcement
through applications development. The types of documentation available include: data sheets, such as this
document, with design specifications; complete user’s reference guides for all devices and tools; technical
briefs; development-support tools; on-line help; and hardware and software applications. The following is a
brief, descriptive list of support documentation specific to the ’C6x devices:
The
TMS320C6000 CPU and Instruction Set Reference Guide
(literature number SPRU189) describes the
’C6000 CPU architecture, instruction set, pipeline, and associated interrupts.
The
TMS320C6000 Peripherals Reference Guide
(literature number SPRU190) describes the functionality of
the peripherals available on ’C6x devices, such as the external memory interface (EMIF), host-port interface
(HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced
direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and
power-down modes. This guide also includes information on internal data and program memories.
The
TMS320C6000 Technical Brief
(literature number SPRU197) gives an introduction to the ’C62x/C67x
devices, associated development tools, and third-party support.
The tools support documentation is electronically available within the Code Composer Studio Integrated
Development Environment (IDE). For a complete listing of ’C6000 latest documentation, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).
See the Worldwide Web URL for the application reports
How To Begin Development Today with the
TMS320C6211 DSP
(literature number SPRA474) and
How To Begin Development Today with the
TMS320C6711 DSP
(literature number SPRA522) which describe in more detail the similarities/differences
between the ’C6211 and ’C6711 devices.
ADVANCE INFORMATION
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24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
clock PLL
All of the internal ’C62x/’C67x clocks are generated from a single source through the CLKIN pin. This source
clock either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock,
or bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 6
shows the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes. Figure 7 shows the
external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.
To minimize the clock jitter, a single clean power supply should power both the ’C62x/’C67x device and the
external clock oscillator circuit. Noise coupling into PLLF will directly impact PLL clock jitter. The minimum
CLKIN rise and fall times should also be observed. For the input clock timing requirements, see the
input and
output clocks
electricals section.
Available Multiply Factors
CLKMODE0 PLL Multiply
Factors
CPU Clock
Frequency
f(CPUCLOCK)
0 x1(BYPASS) 1 x f(CLKIN)
1 x4 4 x f(CLKIN)
NOTES: A. Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum. In addition,
place all PLL external components (R1, C1, C2, C3, C4, and the EMI Filter) as close to the ’C6000 device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4,
and the EMI Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U.
Figure 6. External PLL Circuitry for Either PLL x4 Mode or x1 (Bypass) Mode
CLKMODE0 PLL
PLLV
CLKIN LOOP FILTER
PLLCLK
PLLMULT
CLKIN
PLLG
Internal to ’C6211/’C6711
CPU
CLOCK
PLLF
1
0
3.3V
NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal.
B. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
Figure 7. External PLL Circuitry for x1 (Bypass) Mode Only
ADVANCE INFORMATION
CLKMODE0 PLL
PLLV
CLKIN LOOP FILTER
PLLCLK
PLLMULT
CLKIN
PLLG
C2
Internal to ’C6211/’C6711
CPU
CLOCK
C1 R1
3.3V
10 F0.1 F
PLLF
EMI Filter
C3 C4
1
0
(For C1, C2, and R1 values, see Table 3.)
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clock PLL (continued)
Table 3. ’C6211/’C6711 PLL Component Selection Table
CLKMODE CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
(CLKOUT1)
RANGE (MHz)
CLKOUT2
RANGE
(MHz)
R1
(Ω)C1
(nF) C2
(pF)
TYPICAL
LOCK TIME
(µs)†
x4 16.3–37.5 65–150 32.5–75 60.4 27 560 75
†Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the
typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
ADVANCE INFORMATION
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26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Supply voltage range, CVDD (see Note 1) – 0.3 V to 2.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage range, DVDD (see Note 1) –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, TC0C to 90C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –55C to 150C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN NOM MAX UNIT
CVDD Supply voltage, Core‡1.71 1.8 1.89 V
DVDD Supply voltage, I/O‡3.14 3.30 3.46 V
VSS Supply ground 0 0 0 V
VIH High-level input voltage 2.0 V
VIL Low-level input voltage 0.8 V
I
High level output current
All signals except CLKOUT1 and CLKOUT2 –4 mA
IOH High-level output current CLKOUT1 and CLKOUT2 –8 mA
I
Low level output current
All signals except CLKOUT1 and CLKOUT2 4 mA
IOL Low-level output current CLKOUT1 and CLKOUT2 8 mA
TCOperating case temperature 0 90 C
‡TI DSP’s do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure
that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. Excessive exposure to
these conditions can adversely affect the long term reliability of the device. System-level concerns such as bus contention may require supply
sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered down after),
the I/O buffers. For additional power supply sequencing information, see the
Power Supply Sequencing Solutions For Dual Supply V oltage DSPs
application report (literature number SLVA073).
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage DVDD = MIN, IOH = MAX 2.4 V
VOL Low-level output voltage DVDD = MIN, IOL = MAX 0.6 V
IIInput current VI = VSS to DVDD ±125 uA
IOZ Off-state output current VO = DVDD or 0 V ±10 uA
I
Supply current CPU CPU memory access§
’C6211, CVDD = NOM, CPU clock = 150 MHz 270 mA
IDD2V Supply current, CPU + CPU memory access
§
’C6711, CVDD = NOM, CPU clock = 150 MHz TBD mA
I
Supply current peripherals§
’C6211, CVDD = NOM, CPU clock = 150 MHz 220 mA
IDD2V Supply current, peripherals
§
’C6711, CVDD = NOM, CPU clock = 150 MHz TBD mA
I
Supply current I/O pins§
’C6211, DVDD = NOM, CPU clock = 150 MHz 60 mA
IDD3V Supply current, I/O pins
§
’C6711, DVDD = NOM, CPU clock = 150 MHz TBD mA
CiInput capacitance 5 pF
CoOutput capacitance 5 pF
§Measured with average activity (50% high/50% low power). For more details on CPU, peripheral, and I/O activity, refer to the
TMS320C6000
Power Consumption Summary
application report (literature number SPRA486).
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PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
Vref
IOL
CT = 30 pF†
IOH
Output
Under
Test
50 Ω
†Typical distributed load circuit capacitance
Figure 8. Test Load Circuit
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
Vref = 1.5 V
Figure 9. Input and Output Voltage Reference Levels for ac Timing Measurements
ADVANCE INFORMATION
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28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN†‡ (see Figure 10)
–100 –150
NO. CLKMODE = x4 CLKMODE = x1 CLKMODE = x4 CLKMODE = x1 UNIT
NO.
MIN MAX MIN MAX MIN MAX MIN MAX
UNIT
1 tc(CLKIN) Cycle time, CLKIN 40 10 26.7 6.7 ns
2 tw(CLKINH) Pulse duration, CLKIN high 0.4C 0.45C 0.4C 0.45C ns
3 tw(CLKINL) Pulse duration, CLKIN low 0.4C 0.45C 0.4C 0.45C ns
4 tt(CLKIN) Transition time, CLKIN 5 0.6 5 0.6 ns
†The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH.
‡C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns.
CLKIN
1
2
3
4
4
Figure 10. CLKIN Timings
switching characteristics for CLKOUT1§¶ (see Figure 11)
NO
PARAMETER
–100
–150
UNIT
NO. PARAMETER CLKMODE = x4 CLKMODE = x1 UNIT
MIN MAX MIN MAX
1 tc(CKO1) Cycle time, CLKOUT1 P – 0.7 P + 0.7 P – 0.7 P + 0.7 ns
2 tw(CKO1H) Pulse duration, CLKOUT1 high (P/2) – 0.5 (P/2 ) + 0.5 PH – 0.5 PH + 0.5 ns
3 tw(CKO1L) Pulse duration, CLKOUT1 low (P/2) – 0.5 (P/2 ) + 0.5 PL – 0.5 PL + 0.5 ns
4 tt(CKO1) Transition time, CLKOUT1 0.6 0.6 ns
§PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
¶P = 1/CPU clock frequency in nanoseconds (ns)
CLKOUT1
1
3
4
4
2
Figure 11. CLKOUT1 Timings
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INPUT AND OUTPUT CLOCKS (CONTINUED)
switching characteristics for CLKOUT2† (see Figure 12)
NO. PARAMETER –100
–150 UNIT
NO
.
PARAMETER
MIN MAX
UNIT
1 tc(CKO2) Cycle time, CLKOUT2 2P – 0.7 2P + 0.7 ns
2 tw(CKO2H) Pulse duration, CLKOUT2 high P – 0.7 P + 0.7 ns
3 tw(CKO2L) Pulse duration, CLKOUT2 low P – 0.7 P + 0.7 ns
4 tt(CKO2) Transition time, CLKOUT2 0.6 ns
†P = 1/CPU clock frequency in ns
CLKOUT2
1
2
3
4
4
Figure 12. CLKOUT2 Timings
timing requirements for ECLKIN‡ (see Figure 13)
NO
–100 –150
UNIT
NO. MIN MAX MIN MAX UNIT
1 tc(EKI) Cycle time, ECLKIN 15 10 ns
2 tw(EKIH) Pulse duration, ECLKIN high 6.8 4.5 ns
3 tw(EKIL) Pulse duration, ECLKIN low 6.8 4.5 ns
4 tt(EKI) Transition time, ECLKIN 3 3 ns
‡The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH.
ECLKIN
1
2
3
4
4
Figure 13. ECLKIN Timings
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30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
INPUT AND OUTPUT CLOCKS (CONTINUED)
switching characteristics for ECLKOUT†‡§ (see Figure 14)
NO. PARAMETER –100
–150 UNIT
NO
.
PARAMETER
MIN MAX
UNIT
1 tc(EKO) Cycle time, ECLKOUT E – 0.7 E + 0.7 ns
2 tw(EKOH) Pulse duration, ECLKOUT high EH – 0.7 EH + 0.7 ns
3 tw(EKOL) Pulse duration, ECLKOUT low EL – 0.7 EL + 0.7 ns
4 tt(EKO) Transition time, ECLKOUT 0.6 ns
5 td(EKIH-EKOH) Delay time, ECLKIN high to ECLKOUT high 1 3 ns
6 td(EKIL-EKOL) Delay time, ECLKIN low to ECLKOUT low 1 3 ns
†The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH.
‡E = ECLKIN period in ns
§EH is the high period of ECLKIN in ns and EL is the low period of ECLKIN in ns.
561
23
ECLKINECLKIN
ECLKOUT
44
Figure 14. ECLKOUT Timings
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ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles†‡§ (see Figure 15–Figure 16)
NO
–100 –150
UNIT
NO. MIN MAX MIN MAX UNIT
3 tsu(EDV-AREH) Setup time, EDx valid before ARE high 6 3 ns
4 th(AREH-EDV) Hold time, EDx valid after ARE high 1 1 ns
6 tsu(ARDY-EKOH) Setup time, ARDY valid before ECLKOUT high 6 2 ns
7 th(EKOH-ARDY) Hold time, ARDY valid after ECLKOUT high 1 1 ns
†To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in
the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide
enough (e.g., pulse width = 2E) to ensure setup and hold time is met.
‡RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the EMIF CE space control registers.
§E = ECLKOUT period in ns
switching characteristics for asynchronous memory cycles‡§¶ (see Figure 15–Figure 16)
NO
PARAMETER
–100 –150
UNIT
NO. PARAMETER MIN MAX MIN MAX UNIT
1 tosu(SELV-AREL) Output setup time, select signals valid to ARE
low RS * E – 2 RS * E – 2 ns
2 toh(AREH-SELIV) Output hold time, ARE high to select signals in-
valid RH * E – 2 RH * E – 2 ns
5 td(EKOH-AREV) Delay time, ECLKOUT high to ARE vaild 211 1.5 6 ns
8 tosu(SELV-AWEL) Output setup time, select signals valid to AWE
low WS * E – 2 WS * E – 2 ns
9 toh(AWEH-SELIV) Output hold time, AWE high to select signals
invalid WH * E – 2 WH * E – 2 ns
10 td(EKOH-AWEV) Delay time, ECLKOUT high to AWE vaild 211 1.5 6 ns
‡RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the EMIF CE space control registers.
§E = ECLKOUT period in ns
¶Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0].
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ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 Strobe = 3 Not Ready Hold = 2
BE
Address
Read Data 21
21
21
21
5
4
3
ARDY
77
66
5
ELCKOUT
CEx
EA[21:2]
ED[31:0]
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
BE[3:0]
AWE/SDWE/SSWE†
†AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE,
respectively, during asynchronous memory accesses.
Figure 15. Asynchronous Memory Read Timing
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ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 Strobe = 3 Not Ready Hold = 2
BE
Address
Write Data
1010
9
8
9
8
9
8
9
8
77 66
ECLKOUT
CEx
EA[21:2]
ED[31:0]
BE[3:0]
ARDY
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
†AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE,
respectively, during asynchronous memory accesses.
Figure 16. Asynchronous Memory Write Timing
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SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles† (see Figure 17)
NO
–100 –150
UNIT
NO. MIN MAX MIN MAX UNIT
6 tsu(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high 6 1.5 ns
7 th(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high 1 1.0 ns
†The ’C6211/’C6711 SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word
bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
switching characteristics for synchronous-burst SRAM cycles†‡ (see Figure 17 and Figure 18)
NO
PARAMETER
–100 –150
UNIT
NO. PARAMETER MIN MAX MIN MAX UNIT
1 td(EKOH-CEV) Delay time, ECLKOUT high to CEx valid 211 1.5 6 ns
2 td(EKOH-BEV) Delay time, ECLKOUT high to BEx valid 11 6 ns
3 td(EKOH-BEIV) Delay time, ECLKOUT high to BEx invalid 2 1.5 ns
4 td(EKOH-EAV) Delay time, ECLKOUT high to EAx valid 11 6 ns
5 td(EKOH-EAIV) Delay time, ECLKOUT high to EAx invalid 2 1.5 ns
8 td(EKOH-ADSV) Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid 211 1.5 6 ns
9 td(EKOH-OEV) Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid 211 1.5 6 ns
10 td(EKOH-EDV) Delay time, ECLKOUT high to EDx valid 11 6 ns
11 td(EKOH-EDIV) Delay time, ECLKOUT high to EDx invalid 2 1.5 ns
12 td(EKOH-WEV) Delay time, ECLKOUT high to AWE/SDWE/SSWE valid 211 1.5 6 ns
†The ’C6211/’C6711 SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word
bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
‡ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.
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SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[21:2]
ED[31:0]
ARE/SDCAS/SSADS†
AOE/SDRAS/SSOE†
AWE/SDWE/SSWE†
BE1 BE2 BE3 BE4
EA
Q1 Q2 Q3 Q4
9
1
45
88
9
67
3
1
2
†ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.
Figure 17. SBSRAM Read Timing
ECLKOUT
CEx
BE[3:0]
EA[21:2]
ED[31:0]
ARE/SDCAS/SSADS†
AOE/SDRAS/SSOE†
AWE/SDWE/SSWE†
BE1 BE2 BE3 BE4
Q1 Q2 Q3 Q4
12
11
3
1
8
12
10
4
2
1
8
5
EA
†ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.
Figure 18. SBSRAM Write Timing
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36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles† (see Figure 19)
NO
–100 –150
UNIT
NO. MIN MAX MIN MAX UNIT
6 tsu(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high 6 1.5 ns
7 th(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high 1 1 ns
†The ’C6211/’C6711 SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word
bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
switching characteristics for synchronous DRAM cycles†‡ (see Figure 19–Figure 25)
NO
PARAMETER
–100 –150
UNIT
NO. PARAMETER MIN MAX MIN MAX UNIT
1 td(EKOH-CEV) Delay time, ECLKOUT high to CEx valid 211 1.5 6 ns
2 td(EKOH-BEV) Delay time, ECLKOUT high to BEx valid 11 6 ns
3 td(EKOH-BEIV) Delay time, ECLKOUT high to BEx invalid 2 1.5 ns
4 td(EKOH-EAV) Delay time, ECLKOUT high to EAx valid 11 6 ns
5 td(EKOH-EAIV) Delay time, ECLKOUT high to EAx invalid 2 1.5 ns
8 td(EKOH-CASV) Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid 211 1.5 6 ns
9 td(EKOH-EDV) Delay time, ECLKOUT high to EDx valid 11 6 ns
10 td(EKOH-EDIV) Delay time, ECLKOUT high to EDx invalid 2 1.5 ns
11 td(EKOH-WEV) Delay time, ECLKOUT high to AWE/SDWE/SSWE valid 211 1.5 6 ns
12 td(EKOH-RAS) Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid 211 1.5 6 ns
†The ’C6211/’C6711 SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word
bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
‡ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
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SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[11:2]
ED[31:0]
EA12
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
EA[21:13]
BE1 BE2 BE3 BE4
Bank
Column
D1 D2 D3 D4
8
7
6
5
5
5
1
3
2
8
4
4
4
1
READ
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 19. SDRAM Read Command (CAS Latency 3)
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38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[11:2]
ED[31:0]
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
EA12
EA[21:13]
BE1 BE2 BE3 BE4
Bank
Column
D1 D2 D3 D4
11
8
9
5
5
5
4
2
11
8
9
4
4
2
1
10
3
4
WRITE
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 20. SDRAM Write Command
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[21:13]
ED[31:0]
EA12
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
Bank Activate
Row Address
Row Address
12
5
5
5
1
EA[11:2]
ACTV
12
4
4
4
1
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 21. SDRAM ACTV Command
ECLKOUT
CEx
BE[3:0]
EA[21:13, 11:2]
ED[31:0]
EA12
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†11
12
5
1
DCAB
11
12
4
1
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 22. SDRAM DCAB Command
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[21:13]
ED[31:0]
EA12
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
EA[11:2]
Bank
11
12
5
5
1
DEAC
11
12
4
4
1
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 23. SDRAM DEAC Command
ECLKOUT
CEx
BE[3:0]
EA[21:2]
ED[31:0]
EA12
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
8
12
1
REFR
8
12
1
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 24. SDRAM REFR Command
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[21:2]
ED[31:0]
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
MRS value
11
8
12
5
1
MRS
11
8
12
4
1
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 25. SDRAM MRS Command
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles† (see Figure 26)
NO. –100
–150 UNIT
NO
.MIN MAX
UNIT
3 toh(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low E ns
†E = ECLKIN period in ns
switching characteristics for the HOLD/HOLDA cycles†‡ (see Figure 26)
NO. PARAMETER –100
–150 UNIT
NO
.
PARAMETER
MIN MAX
UNIT
1 tR(HOLDL-EMHZ) Response time, HOLD low to EMIF Bus high impedance 2E §ns
2 td(EMHZ-HOLDAL) Delay time, EMIF Bus high impedance to HOLDA low 0 2E ns
4 tR(HOLDH-EMLZ) Response time, HOLD high to EMIF Bus low impedance 2E 7E ns
5 td(EMLZ-HOLDAH) Delay time, EMIF Bus low impedance to HOLDA high 0 2E ns
†E = ECLKIN period in ns
‡EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.
§All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
HOLD
HOLDA
EMIF Bus†
DSP Owns Bus External Requestor
Owns Bus DSP Owns Bus
C6211/C6711 C6211/C6711
1
3
25
4
†EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.
Figure 26. HOLD/HOLDA Timing
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
RESET TIMING
timing requirements for reset† (see Figure 27)
NO. –100
–150 UNIT
NO
.MIN MAX
UNIT
1
t
Width of the RESET pulse (PLL stable)‡10P ns
1 tw(RST) Width of the RESET pulse (PLL needs to sync up)§250 µs
14 tsu(HD) Setup time, HD boot configuration bits valid before RESET high¶2P ns
15 th(HD) Hold time, HD boot configuration bits valid after RESET high¶2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4 when CLKIN and PLL are stable.
§This parameter applies to CLKMODE x4 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock PLL
circuit. The PLL, however, may need up to 250 µs to stabilize following device power up or after PLL configuration has been changed. During
that time, RESET must be asserted to ensure proper device operation. See the
clock PLL
section for PLL lock times.
¶HD[4:3] are the boot configuration pins during device reset.
switching characteristics during reset†#|| (see Figure 27)
NO. PARAMETER –100
–150 UNIT
NO
.
PARAMETER
MIN MAX
UNIT
2 tR(RSTL-ECKI) Response time, RESET low to ECLKIN synchronized 2P + 3E 3P + 4E ns
3 tR(RSTH-ECKI) Response time, RESET high to ECLKIN synchronized 2P + 3E 3P + 4E ns
4 td(RSTL-EMIFZHZ) Delay time, RESET low to EMIF Z group high impedance 2P + 3E ns
5 td(RSTH-EMIFZV) Delay time, RESET high to EMIF Z group valid 3P + 4E ns
6 td(RSTL-EMIFHIV) Delay time, RESET low to EMIF high group invalid 2P + 3E ns
7 td(RSTH-EMIFHV) Delay time, RESET high to EMIF high group valid 3P + 4E ns
8 td(RSTL-EMIFLIV) Delay time, RESET low to EMIF low group invalid 2P + 3E ns
9 td(RSTH-EMIFLV) Delay time, RESET high to EMIF low group valid 3P + 4E ns
10 td(RSTL-HIGHIV) Delay time, RESET low to high group invalid 2P ns
11 td(RSTH-HIGHV) Delay time, RESET high to high group valid 4P ns
12 td(RSTL-ZHZ) Delay time, RESET low to Z group high impedance 2P ns
13 td(RSTH-ZV) Delay time, RESET high to Z group valid 2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
#E = ECLKIN period in ns
|| EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE
EMIF high group consists of: HOLDA
EMIF low group consists of: BUSREQ
High group consists of: HRDY and HINT
Z group consists of: HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, TOUT0, and TOUT1.
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
RESET TIMING (CONTINUED)
1312
1110
98
76
54
32
15
14
1
CLKOUT1
CLKOUT2
RESET
ECLKIN
EMIF Z Group†
EMIF High Group†
EMIF Low Group†
High Group†
Z Group†
HD[4:3]‡
†EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE
EMIF high group consists of: HOLDA
EMIF low group consists of: BUSREQ
High group consists of: HRDY and HINT
Z group consists of: HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, TOUT0, and TOUT1.
‡HD[4:3] are the boot configuration pins during device reset.
Figure 27. Reset Timing
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
EXTERNAL INTERRUPT TIMING
timing requirements for external interrupts† (see Figure 28)
NO. –100
–150 UNIT
NO
.MIN MAX
UNIT
1 tw(ILOW) Width of the interrupt pulse low 2E ns
2 tw(IHIGH) Width of the interrupt pulse high 2E ns
†E = ECLKIN period in ns
2
1
EXT_INT, NMI
Figure 28. External/NMI Interrupt Timing
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
HOST-PORT INTERFACE TIMING
timing requirements for host-port interface cycles†‡ (see Figure 29, Figure 30, Figure 31, and
Figure 32)
NO. –100
–150 UNIT
NO
.MIN MAX
UNIT
1 tsu(SELV-HSTBL) Setup time, select signals§ valid before HSTROBE low 5 ns
2 th(HSTBL-SELV) Hold time, select signals§ valid after HSTROBE low 2 ns
3 tw(HSTBL) Pulse duration, HSTROBE low 4P ns
4 tw(HSTBH) Pulse duration, HSTROBE high between consecutive accesses 4P ns
10 tsu(SELV-HASL) Setup time, select signals§ valid before HAS low 5 ns
11 th(HASL-SELV) Hold time, select signals§ valid after HAS low 2 ns
12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high 5 ns
13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 2 ns
14 th(HRDYL-HSTBL)
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not complete
properly. 2 ns
18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low 2 ns
19 th(HSTBL-HASL) Hold time, HAS low after HSTROBE low 2 ns
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
‡P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
§Select signals include: HCNTL[1:0], HR/W, and HHWIL.
switching characteristics during host-port interface cycles†‡ (see Figure 29, Figure 30, Figure 31,
and Figure 32)
NO. PARAMETER –100
–150 UNIT
NO
.
PARAMETER
MIN MAX
UNIT
5 td(HCS-HRDY) Delay time, HCS to HRDY¶1 7 ns
6 td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high#3 12 ns
7 td(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an HPI read 2 ns
8 td(HDV-HRDYL) Delay time, HD valid to HRDY low 2P – 4 2P ns
9 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 3 12 ns
15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance 3 12 ns
16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid 3 12 ns
17 td(HSTBH-HRDYH) Delay time, HSTROBE high to HRDY high|| 3 12 ns
20 td(HASL-HRDYH) Delay time, HAS low to HRDY high 3 12 ns
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
‡P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
¶HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy
completing a previous HPID write or READ with autoincrement.
#This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the
request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads
the requested data into HPID.
|| This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write
or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
47
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
HOST-PORT INTERFACE TIMING (CONTINUED)
1st halfword 2nd halfword
5
17
86
5
17
85
15
916
15
97
4
3
2
1
2
1
2
1
2
1
2
1
2
1
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE†
HCS
HD[15:0] (output)
HRDY (case 1)
HRDY (case 2)
3
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 29. HPI Read Timing (HAS Not Used, Tied High)
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE†
HCS
HD[15:0] (output)
HRDY (case 1)
HRDY (case 2)
1st half-word 2nd half-word
517820
51785
15
916
15
97
4
3
11
10
11
10
11
10
11
10
11
1011
10 19 19
18
18
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 30. HPI Read Timing (HAS Used)
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
HOST-PORT INTERFACE TIMING (CONTINUED)
1st halfword 2nd halfword 5
17
5
13
12
13
12
4
14
3
2
1
2
1
2
1
2
1
2
1
2
1
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE†
HCS
HD[15:0] (input)
HRDY
3
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 31. HPI Write Timing (HAS Not Used, Tied High)
1st half-word 2nd half-word 5
17
5
13
12
13
12
4
14
3
11
10
11
10
11
10
11
10
11
10
11
10
13
12
13
12
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE†
HCS
HD[15:0] (input)
HRDY
HBE[1:0]
19
19
18 18
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 32. HPI Write Timing (HAS Used)
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
49
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP†‡ (see Figure 33)
NO. –100
–150 UNIT
NO
.MIN MAX
UNIT
2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P§ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P – 1¶ns
5
t
Setup time external FSR high before CLKR low
CLKR int 9
ns
5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR ext 1ns
6
t
Hold time external FSR high after CLKR low
CLKR int 6
ns
6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR ext 3ns
7
t
Setup time DR valid before CLKR low
CLKR int 8
ns
7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR ext 0ns
8
t
Hold time DR valid after CLKR low
CLKR int 3
ns
8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR ext 3ns
10
t
Setup time external FSX high before CLKX low
CLKX int 9
ns
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX ext 1ns
11
t
Hold time external FSX high after CLKX low
CLKX int 6
ns
11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX ext 3ns
†CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡P = 1/CPU clock frequency in ns.
§The maximum McBSP bit rate is 50 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 20 ns (50 MHz),
whichever value is larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 20 ns as the minimum CLKR/X clock cycle (by setting
the appropriate CLKGDV ratio or external clock source). When running parts at 80 MHz (P = 12.5 ns), use 2P = 25 ns (40 MHz) as the minimum
CLKR/X clock cycle. The maximum McBSP bit rate applies to the following hardware configuration: the serial port is a master of the clock and
frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode
(R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.
¶The minimum CLKR/X pulse duration is either (P–1) or 9 ns, whichever is larger. For example, when running parts at 150 MHz (P = 6.7 ns), use
9 ns as the minimum CLKR/X pulse duration. When running parts at 80 MHz (P = 12.5 ns), use (P–1) = 11.5 ns as the minimum CLKR/X pulse
duration.
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics for McBSP†‡ (see Figure 33)
NO. PARAMETER –100
–150 UNIT
NO
.
PARAMETER
MIN MAX
UNIT
1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input 4 10 ns
2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P§¶ ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C – 1#C + 1#ns
4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int –2 3 ns
9
t
Delay time CLKX high to internal FSX valid
CLKX int –2 3
ns
9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX ext 3 9 ns
12
t
Disable time, DX hi
g
h impedance followin
g
last data bit CLKX int –1 4
ns
12 tdis(CKXH-DXHZ)
Disable
time
,
DX
high
im edance
following
last
data
bit
from CLKX high CLKX ext 3 9 ns
13
t
Delay time CLKX high to DX valid
CLKX int –1 + D|| 4 + D||
ns
13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX ext 3 + D|| 9 + D|| ns
14
t
Delay time, FSX high to DX valid FSX int –1 3
ns
14 td(FXH-DXV) ONLY applies when in data
delay 0 (XDATDLY = 00b) mode FSX ext 3 9 ns
†CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡Minimum delay times also represent minimum output hold times.
§P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
¶The maximum McBSP bit rate is 50 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 20 ns (50 MHz),
whichever value is larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 20 ns as the minimum CLKR/X clock cycle (by setting
the appropriate CLKGDV ratio or external clock source). When running parts at 80 MHz (P = 12.5 ns), use 2P = 25 ns (40 MHz) as the minimum
CLKR/X clock cycle. The maximum McBSP bit rate applies to the following hardware configuration: the serial port is a master of the clock and
frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode
(R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.
#C = H or L
S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 50 MHz limit.
|| Extra delay from CLKX high to DX valid applies
only
to the first data bit of a device, if and only if DXENA = 1 in SPCR.
D = extra delay from CLKX high to DX vaild = 0 if DXENA = 0
= extra delay from CLKX high to DX vaild = 2P if DXENA = 1
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
51
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit(n-1) (n-2) (n-3)
Bit 0 Bit(n-1) (n-2) (n-3)
14
1312
11
10
9
3
32
8
7
6
5
4
4
3
1
32
CLKS
CLKR
FSR (int)
FSR (ext)
DR
CLKX
FSX (int)
FSX (ext)
FSX (XDATDLY=00b)
DX
13
Figure 33. McBSP Timings
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 34)
NO. –100
–150 UNIT
NO
.MIN MAX
UNIT
1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high 4 ns
2 th(CKSH-FRH) Hold time, FSR high after CLKS high 4 ns
2
1
CLKS
FSR external
CLKR/X (no need to resync)
CLKR/X(needs resync)
Figure 34. FSR Timing When GSYNC = 1
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
53
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 35)
NO
–100
–150
UNIT
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 12 2 – 6P ns
5 th(CKXL-DRV) Hold time, DR valid after CLKX low 45 + 12P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡
(see Figure 35)
NO
PARAMETER
–100
–150
UNIT
NO. PARAMETER MASTER§SLAVE UNIT
MIN MAX MIN MAX
1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶T – 2 T + 3 ns
2 td(FXL-CKXH) Delay time, FSX low to CLKX high#L – 2 L + 3 ns
3 td(CKXH-DXV) Delay time, CLKX high to DX valid –2 4 6P + 4 10P + 17 ns
6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from
CLKX low L – 2 L + 3 ns
7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from
FSX high 2P + 3 6P + 17 ns
8 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 2 8P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
3
87
6
21
CLKX
FSX
DX
DR
Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 36)
NO
–100
–150
UNIT
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 – 6P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 45 + 12P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡
(see Figure 36)
NO
PARAMETER
–100
–150
UNIT
NO. PARAMETER MASTER§SLAVE UNIT
MIN MAX MIN MAX
1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶L – 2 L + 3 ns
2 td(FXL-CKXH) Delay time, FSX low to CLKX high#T – 2 T + 3 ns
3 td(CKXL-DXV) Delay time, CLKX low to DX valid –2 4 6P + 4 10P + 17 ns
6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from
CLKX low –2 4 6P + 3 10P + 17 ns
7 td(FXL-DXV) Delay time, FSX low to DX valid H – 2 H + 4 4P + 2 8P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
4
376
21
CLKX
FSX
DX
DR 5
Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 37)
NO
–100
–150
UNIT
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 – 6P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 45 + 12P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡
(see Figure 37)
NO
PARAMETER
–100
–150
UNIT
NO. PARAMETER MASTER§SLAVE UNIT
MIN MAX MIN MAX
1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶T – 2 T + 3 ns
2 td(FXL-CKXL) Delay time, FSX low to CLKX low#H – 2 H + 3 ns
3 td(CKXL-DXV) Delay time, CLKX low to DX valid –2 4 6P + 4 10P + 17 ns
6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from
CLKX high H – 2 H + 3 ns
7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from
FSX high 2P + 3 6P + 17 ns
8 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 2 8P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
57
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
38
7
6
21
CLKX
FSX
DX
DR
Figure 37. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 38)
NO
–100
–150
UNIT
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 – 6P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 45 + 12P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡
(see Figure 38)
NO
PARAMETER
–100
–150
UNIT
NO. PARAMETER MASTER§SLAVE UNIT
MIN MAX MIN MAX
1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶H – 2 H + 3 ns
2 td(FXL-CKXL) Delay time, FSX low to CLKX low#T – 2 T + 1 ns
3 td(CKXH-DXV) Delay time, CLKX high to DX valid –2 4 6P + 4 10P + 17 ns
6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from
CLKX high –2 4 6P + 3 10P + 17 ns
7 td(FXL-DXV) Delay time, FSX low to DX valid L – 2 L + 4 4P + 2 8P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
59
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
3
7
6
21
CLKX
FSX
DX
DR
Figure 38. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TIMER TIMING
timing requirements for timer inputs† (see Figure 39)
NO. –100
–150 UNIT
NO
.MIN MAX
UNIT
1 tw(TINPH) Pulse duration, TINP high 2P ns
2 tw(TINPL) Pulse duration, TINP low 2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
switching characteristics for timer outputs† (see Figure 39)
NO. PARAMETER –100
–150 UNIT
NO
.
PARAMETER
MIN MAX
UNIT
3 tw(TOUTH) Pulse duration, TOUT high 4P–3 ns
4 tw(TOUTL) Pulse duration, TOUT low 4P–3 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
TINPx
TOUTx
4
3
2
1
Figure 39. Timer Timing
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
61
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 40)
NO. –100
–150 UNIT
NO
.MIN MAX
UNIT
1 tc(TCK) Cycle time, TCK 35 ns
3 tsu(TDIV-TCKH) Setup time, TDI/TMS/TRST valid before TCK high 10 ns
4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 9 ns
switching characteristics for JTAG test port (see Figure 40)
NO. PARAMETER –100
–150 UNIT
NO
.
PARAMETER
MIN MAX
UNIT
2 td(TCKL-TDOV) Delay time, TCK low to TDO valid –3 12 ns
TCK
TDO
TDI/TMS/TRST
1
2
34
2
Figure 40. JTAG Test-Port Timing
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MECHANICAL DATA
GFN (S-PBGA-N256) PLASTIC BALL GRID ARRAY
0,635
1915 1713119
Y
V
T
U
P
N
R
W
75
L
J
K
H
F
G
31
D
B
C
A
E
M
24,13 TYP
Seating Plane
4040185-2/B 11/97
10 12 14 16 18 208642
27,20
23,95
24,70 SQ
SQ
26,80
0,90
0,60 0,50
0,70
0,635 1,27
0,15
1,27
M
0,15
2,32 MAX
0,40
0,30
1,17 NOM
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
thermal resistance characteristics (S-PBGA package)
NO °C/W Air Flow LFPM†
1 RΘJC Junction-to-case 6.4 N/A
2 RΘJA Junction-to-free air 25.2 0
3 RΘJA Junction-to-free air 23.1 100
4 RΘJA Junction-to-free air 21.9 250
5 RΘJA Junction-to-free air 20.6 500
†LFPM = Linear Feet Per Minute
ADVANCE INFORMATION
IMPORTANT NOTICE
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