HCPL-063A#500E - AVAGO TECHNOLOGIES

Features

• HCMOS/LSTTL/TTL performance compatible

• 1000 V/µs minimum Common Mode Rejection (CMR)

at VCM = 50 V (HCPL-261A family) and 15 kV/µs

minimum CMR at VCM = 1000 V (HCPL-261N family)

• High speed: 10 MBd typical

• AC and DC performance specied over industrial

temperature range -40°C to +85°C

• Available in 8 pin DIP, SOIC-8 packages

• Safety approval:

– UL recognized per UL1577 3750 V rms for 1 minute

and 5000 V rms for 1 minute (Option 020)

– CSA Approved

– IEC/EN/DIN EN 60747-5-5 approved

Applications

• Low input current (3.0 mA) HCMOS compatible

version of 6N137 optocoupler

• Isolated line receiver

• Simplex/multiplex data transmission

• Computer-peripheral interface

• Digital isolation for A/D, D/A conversion

• Switching power supplies

• Instrumentation input/output isolation

• Ground loop elimination

• Pulse transformer replacement

HCPL-261A, HCPL-061A, HCPL-263A, HCPL-063A

HCPL-261N, HCPL-061N, HCPL-263N, HCPL-063N

HCMOS Compatible, High CMR, 10 MBd Optocouplers

Data Sheet

The connection of a 0.1 µF bypass capacitor between pins 5 and 8 is

required.

Description

The HCPL-261A family of optically coupled gates shown

on this data sheet provide all the benets of the in-

dustry standard 6N137 family with the added benet

of HCMOS compatible input cur rent. This allows direct

interface to all common circuit topologies without

additional LED buer or drive components. The Al-

GaAs LED used allows lower drive currents and reduc-

es degradation by using the latest LED tech nol ogy. On

the single channel parts, an enable output allows the de-

tector to be strobed. The output of the detector IC is an

open collector schottky-clamped transistor. The internal

shield provides a mini mum common mode transient im-

munity of 1000 V/µs for the HCPL-261A family and 15000

V/µs for the HCPL-261N family.

Functional Diagram

CAUTION: It is advised that normal static precautions be taken in handling and assembly

of this component to prevent damage and/or degradation which may be induced by ESD.

Lead (Pb) Free

RoHS 6 fully

compliant

RoHS 6 fully compliant options available;

-xxxE denotes a lead-free product

CATHODE

ANODE

GND

VCC

ANODE 2

CATHODE 2

CATHODE 1

ANODE 1

GND

VCC

VEVO1

HCPL-261A/261N

HCPL-061A/061N

HCPL-263A/263N

HCPL-063A/063N

NC SHIELD SHIELD

LED

OFF

ENABLE

OUTPUT

TRUTH TABLE

(POSITIVE LOGIC)

LED

OFF

OUTPUT

TRUTH TABLE

(POSITIVE LOGIC)

Selection Guide

Widebody

Minimum CMR 8-Pin DIP (300 Mil) Small-Outline SO-8 (400 Mil) Hermetic

On- Single Dual Single Dual Single Single and

dV/dt VCM Current Output Channel Channel Channel Channel Channel Dual Channel

(V/µs) (V) (mA) Enable Package Package Package Package Package Packages

NA NA 5 YES 6N137[1] HCPL-0600[1] HCNW137[1]

NO HCPL-2630[1] HCPL-0630[1]

5,000 50 YES HCPL-2601[1] HCPL-0601[1] HCNW2601[1]

NO HCPL-2631[1] HCPL-0631[1]

10,000 1,000 YES HCPL-2611[1] HCPL-0611[1] HCNW2611[1]

NO HCPL-4661[1] HCPL-0661[1]

1,000 50 YES HCPL-2602[1]

3,500 300 YES HCPL-2612[1]

1,000 50 3 YES HCPL-261A HCPL-061A

NO HCPL-263A HCPL-063A

1,000[2] 1,000 YES HCPL-261N HCPL-061N

NO HCPL-263N HCPL-063N

1,000 50 12.5 [3] HCPL-193x[1]

HCPL-56xx[1]

HCPL-66xx[1]

Notes:

1. Technical data are on separate Avago publications.

2. 15 kV/µs with VCM = 1 kV can be achieved using Avago application circuit.

3. Enable is available for single channel products only, except for HCPL-193x devices.

Input

Schematic

SHIELD

USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED

BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 16).

–

IFICC VCC

GND

IE7

HCPL-261A/261N

HCPL-061A/061N

SHIELD

VF1

–

IF1

ICC VCC

VO1

IO1

SHIELD

–

VF2

IF2

VO2

GND

IO2

HCPL-263A/263N

HCPL-063A/063N

Ordering Information

HCPL-xxxx is UL Recognized with 3750 Vrms for 1 minute per UL1577.

Part number

Option

Package

Surface

Mount

Gull

Wing

Tape

& Reel

UL 5000

Vrms/1

Minute rating

IEC/EN/DIN EN

60747-5-5 Quantity

RoHS

Compliant

Non RoHS

Compliant

HCPL-261A

-000E No option

300mil

DIP-8

50 per tube

-300E #300 X X 50 per tube

-500E #500 X X X 1000 per reel

-020E #020 X 50 per tube

-320E -320 X X X 50 per tube

-520E -520 X X X X 1000 per reel

-060E #060 X 50 per tube

-560E #560 X X X X 1000 per reel

HCPL-

261N

-000E No option

300mil

DIP-8

50 per tube

-300E #300 X X 50 per tube

-500E #500 X X X 1000 per reel

-020E #020 X 50 per tube

-320E #320 X X X 50 per tube

-520E -520 X X X X 1000 per reel

-060E #060 X 50 per tube

-360E #360 X X X 50 per tube

-560E - X X X X 1000 per reel

HCPL-263A

-000E No option

300mil

DIP-8

50 per tube

-300E #300 X X 50 per tube

-500E #500 X X X 1000 per reel

-020E #020 X 50 per tube

-320E #320 X X X 50 per tube

-520E -520 X X X X 1000 per reel

HCPL-

263N

-000E No option

300mil

DIP-8

50 per tube

-300E #300 X X 50 per tube

-500E #500 X X X 1000 per reel

-020E #020 X 50 per tube

-320E #320 X X X 50 per tube

-520E #520 X X X X 1000 per reel

HCPL-061A

HCPL-

061N

-000E No option

SO-8

X 100 per tube

-500E #500 X X 1500 per reel

-060E #060 X X 100 per tube

-560E #560 X X X 1500 per reel

HCPL-063A

HCPL-

063N

-000E No option

SO-8

X 100 per tube

-500E #500 X X 1500 per reel

To order, choose a part number from the part number column and combine with the desired option from the option

column to form an order entry. Combination of Option 020 and Option 060 is not available.

Example 1:

HCPL-261A-560E to order product of 300mil DIP Gull Wing Surface Mount package in Tape and Reel packaging

with IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant.

Example 2:

HCPL-263N to order product of 300mil DIP package in tube packaging and non RoHS compliant.

Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and

RoHS compliant option will use ‘-XXXE‘.

HCPL-261A/261N/263A/263N Outline Drawing

Pin Location (for reference only)

Figure 2. Gull wing surface mount option #300.

Figure 1. 8-Pin dual in-line package device outline drawing.

9.40 (0.370)

9.90 (0.390)

PIN ONE

1.78 (0.070) MAX.

A XXXXZ

YYWW

OPTION CODE*

DATE CODE

0.76 (0.030)

1.40 (0.056)

2.28 (0.090)

2.80 (0.110)

0.51 (0.020) MIN.

0.65 (0.025) MAX.

4.70 (0.185) MAX.

2.92 (0.115) MIN.

6.10 (0.240)

6.60 (0.260)

0.20 (0.008)

0.33 (0.013)

5 TYP.

7.36 (0.290)

7.88 (0.310)

DIMENSIONS IN MILLIMETERS AND (INCHES).

5678

4321

1.19 (0.047) MAX.

TYPE NUMBER

* MARKING CODE LETTER FOR OPTION NUMBERS.

"L" = OPTION 020

"V" = OPTION 060

OPTION NUMBERS 300 AND 500 NOT MARKED.

NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.

3.56 ± 0.13

(0.140 ± 0.005)

0.635 ± 0.25

(0.025 ± 0.010) 12 NOM.

9.65 ± 0.25

(0.380 ± 0.010)

0.635 ± 0.130

(0.025 ± 0.005)

7.62 ± 0.25

(0.300 ± 0.010)

9.65 ± 0.25

(0.380 ± 0.010)

6.350 ± 0.25

(0.250 ± 0.010)

1.02 (0.040)

1.27 (0.050)

10.9 (0.430)

2.0 (0.080)

LAND PATTERN RECOMMENDATION

1.080 ± 0.320

(0.043 ± 0.013)

3.56 ± 0.13

(0.140 ± 0.005)

1.780

(0.070)

MAX.

1.19

(0.047)

MAX.

2.540

(0.100)

BSC

DIMENSIONS IN MILLIMETERS (INCHES).

TOLERANCES (UNLESS OTHERWISE SPECIFIED):

LEAD COPLANARITY

MAXIMUM: 0.102 (0.004)

NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.

xx.xx = 0.01

xx.xxx = 0.005

0.20 (0.008)

0.33 (0.013)

HCPL-061A/061N/063A/063N Outline Drawing

Figure 3. 8-Pin Small Outline Package Device Drawing.

Solder Reow Prole

Recommended reow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.

Regulatory Information

The HCPL-261A and HCPL-261N families have been approved by the following organizations:

Recognized under UL 1577, Component Recognition Program, File E55361.

CSA

Approved under CSA Component Acceptance Notice #5, File CA 88324.

IEC/EN/DIN EN 60747-5-5

XXX

YWW

8765

4321

5.994 ± 0.203

(0.236 ± 0.008)

3.937 ± 0.127

(0.155 ± 0.005)

0.406 ± 0.076

(0.016 ± 0.003) 1.270

(0.050)BSC

* 5.080 ± 0.127

(0.200 ± 0.005)

3.175 ± 0.127

(0.125 ± 0.005) 1.524

(0.060)

45 X 0.432

(0.017)

0.228 ± 0.025

(0.009 ± 0.001)

TYPE NUMBER

(LAST 3 DIGITS)

DATE CODE

0.305

(0.012)MIN.

* TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)

5.207 ± 0.254 (0.205 ± 0.010)

DIMENSIONS IN MILLIMETERS (INCHES).

LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.

0.203 ± 0.102

(0.008 ± 0.004)

NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.

7.49 (0.295)

1.9 (0.075)

0.64 (0.025)

LAND PATTERN RECOMMENDATION

Insulation and Safety Related Specications

8-Pin DIP

(300 Mil) SO-8

Parameter Symbol Value Value Units Conditions

Minimum External Air L(101) 7.1 4.9 mm Measured from input terminals to

Gap (External output terminals, shortest distance

Clearance) through air.

Minimum External L(102) 7.4 4.8 mm Measured from input terminals to

Tracking (External output terminals, shortest distance

Creepage) path along body.

Minimum Internal Plastic 0.08 0.08 mm Through insulation distance, conductor

Gap (Internal Clearance) to conductor, usually the direct

distance between the photoemitter and

photodetector inside the optocoupler

cavity.

Tracking Resistance CTI 200 200 Volts DIN IEC 112/ VDE 0303 Part 1

(Comparative Tracking

Index)

Isolation Group IIIa IIIa Material Group (DIN VDE 0110, 1/89,

Table 1)

Option 300 – surface mount classication is Class A in accordance with CECC 00802.

IEC/EN/DIN EN 60747-5-5 Insulation Characteristics*

Description Symbol PDIP Option 060 SO-8 Option 060 Unit

Installation classication per DIN VDE 0110, Table 1

for rated mains voltage ≤ 150 Vrms

for rated mains voltage ≤ 300 Vrms

for rated mains voltage ≤ 600 Vrms

I – IV

I – III

I – IV

I – III

Climatic Classication 40/85/21 40/85/21

Pollution Degree (DIN VDE 0110/39) 2 2

Maximum Working Insulation Voltage VIORM 630 567 Vpeak

Input to Output Test Voltage, Method b*

VIORM x 1.875 = VPR, 100% Production Test with tm=1 sec,

Partial discharge < 5 pC

VPR 1181 1063 Vpeak

Input to Output Test Voltage, Method a*

VIORM x 1.6 = VPR, Type and Sample Test, tm=10 sec,

Partial discharge < 5 pC

VPR 1008 907 Vpeak

Highest Allowable Overvoltage

(Transient Overvoltage tini = 60 sec)

VIOTM 6000 6000 Vpeak

Safety-limiting values – maximum values allowed in the event of a failure

Case Temperature TS175 150 °C

Input Current IS, INPUT 230 150 mA

Output Power PS, OUTPUT 600 600 mW

Insulation Resistance at TS, VIO = 500 V RS≥109≥109W

* Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-5, for a

detailed description.

Absolute Maximum Ratings

Parameter Symbol Min. Max. Units Note

Storage Temperature TS -55 125 °C

Operating Temperature TA -40 +85 °C

Average Input Current IF(AVG)

10 mA 1

Reverse Input Voltage VR

3 Volts

Supply Voltage VCC -0.5 7 Volts 2

Enable Input Voltage VE -0.5 5.5 Volts

Output Collector Current (Each Channel) IO

50 mA

Output Power Dissipation (Each Channel) PO

60 mW 3

Output Voltage (Each channel) VO -0.5 7 Volts

Lead Solder Temperature

260°C for 10 s, 1.6 mm Below Seating Plane

(Through Hole Parts Only)

Solder Reow Temperature Prole See Package Outline Drawings section

(Surface Mount Parts Only)

Recommended Operating Conditions

Parameter Symbol Min. Max. Units

Input Voltage, Low Level VFL -3 0.8 V

Input Current, High Level IFH 3.0 10 mA

Power Supply Voltage VCC 4.5 5.5 Volts

High Level Enable Voltage VEH 2.0 VCC Volts

Low Level Enable Voltage VEL 0 0.8 Volts

Fan Out (at RL = 1 kΩ) N

5 TTL Loads

Output Pull-up Resistor RL 330 4k Ω

Operating Temperature TA -40 85 °C

Electrical Specications

Over recommended operating temperature (TA = -40°C to +85°C) unless otherwise specied.

Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note

High Level Output IOH

3.1 100 µA VCC = 5.5 V, VO = 5.5 V, 4 18

Current VF = 0.8 V, VE = 2.0 V

Low Level Output VOL

0.4 0.6 V VCC = 5.5 V, IOL = 13 mA 5, 8 4, 18

Voltage (sinking), IF = 3.0 mA,

VE = 2.0 V

High Level Supply ICCH

7 10 mA VE = 0.5 V** VCC = 5.5 V

9 15 Dual Channel

Products***

Low Level Supply ICCL

8 13 mA VE = 0.5 V** VCC = 5.5 V

12 21

Dual Channel

Products***

High Level Enable IEH

-0.6 -1.6 mA VCC = 5.5 V, VE = 2.0 V

Current**

Low Level Enable IEL

-0.9 -1.6 mA VCC = 5.5 V, VE = 0.5 V

Current**

Input Forward VF 1.0 1.3 1.6 V IF = 4 mA 6 4

Voltage

Temperature Co- ∆VF/∆TA

-1.25

mV/°C IF = 4 mA 4

ecient of Forward

Voltage

Input Reverse BVR 3 5 V IR = 100 µA 4

Breakdown Voltage

Input Capacitance CIN

60 pF f = 1 MHz, VF = 0 V

*All typical values at TA = 25°C, VCC = 5 V

**Single Channel Products only (HCPL-261A/261N/061A/061N)

***Dual Channel Products only (HCPL-263A/263N/063A/063N)

IF = 0 mA

IF = 3.0 mA

Current

Switching Specications

Over recommended operating temperature (TA = -40°C to +85°C) unless otherwise specied.

Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note

Input Current Threshold ITHL

1.5 3.0 mA VCC = 5.5 V, VO = 0.6 V, 7, 10 18

High to Low IO >13 mA (Sinking)

Propagation Delay tPLH

52 100 ns IF = 3.5 mA 9, 11, 4, 9,

Time to High Output VCC = 5.0 V, 12 18

Level VE = Open,

Propagation Delay tPHL

53 100 ns 9, 11, 4, 10,

Time to Low Output 12 18

Level

Pulse Width Distortion PWD

11 45 ns 9, 13 17, 18

|tPHL - tPLH|

Propagation Delay Skew tPSK

60 ns 24 11, 18

Output Rise Time tR

42 ns 9, 14 4, 18

Output Fall Time tF

12 ns 9, 14 4, 18

Propagation Delay tEHL

19 ns IF = 3.5 mA 15, 12

Time of Enable VCC = 5.0 V, 16

from VEH to VEL VEL = 0 V, VEH = 3 V,

Propagation Delay tELH

30 ns 15, 12

Time of Enable 16

from VEL to VEH

*All typical values at TA = 25°C, VCC = 5 V.

CL = 15 pF,

RL = 350 Ω

CL = 15 pF,

RL = 350 Ω

Common Mode Transient Immunity Specications, All values at TA = 25°C

Parameter Device Symbol Min. Typ. Max. Units Test Conditions Fig. Note

Output High HCPL-261A |CMH| 1 5 kV/µs VCM = 50 V VCC = 5.0 V, 17 4, 13,

Level Common HCPL-061A RL = 350 Ω, 15, 18

Mode Transient HCPL-263A IF = 0 mA,

Immunity HCPL-063A TA = 25°C

HCPL-261N 1 5 kV/µs VCM = 1000 V

HCPL-061N

HCPL-263N 15 25 kV/µs Using Avago 20 4, 13,

HCPL-063N App Circuit 15

Output Low HCPL-261A |CML| 1 5 kV/µs VCM = 50 V VCC = 5.0 V, 17 4, 14,

Level Common HCPL-061A RL = 350 Ω, 15, 18

Mode Transient HCPL-263A IF = 3.5 mA,

Immunity HCPL-063A VO(MAX) = 0.8 V

HCPL-261N 1 5 kV/µs VCM = 1000 V

HCPL-061N

HCPL-263N 15 25 kV/µs Using Avago 20 4, 14,

HCPL-063N App Circuit 15

VO(MIN) = 2 V

TA = 25°C

Package Characteristics

All Typicals at TA = 25°C

Parameter Sym. Package* Min. Typ. Max. Units Test Conditions Fig. Note

Input-Output VISO 3750 V rms RH ≤ 50%, 5, 6

Momentary With- t = 1 min.,

stand Voltage** TA = 25°C

Input-Output RI-O 1012 Ω VI-O = 500 Vdc 4, 8

Resistance

Input-Output CI-O 0.6 pF f = 1 MHz, 4, 8

Capacitance TA = 25°C

Input-Input II-I Dual Channel 0.005 µA RH ≤ 45%, 19

Insulation t = 5 s,

Leakage Current VI-I = 500 V

Resistance RI-I Dual Channel 1011 Ω 19

(Input-Input)

Capacitance CI-I Dual 8-pin DIP 0.03 pF f = 1 MHz 19

Dual SO-8 0.25

*Ratings apply to all devices except otherwise noted in the Package column.

**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous

voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table (if applicable), your equip-

ment level safety specication or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”

†For 8-pin DIP package devices (HCPL-261A/261N/263A/263N) only.

(Input-Input)

OPT 020† 5000 5, 7

Notes:

1. Peaking circuits may be used which produce transient input currents up to 30 mA, 50 ns maximum pulse width, provided the average cur-

rent does not exceed 10 mA.

2. 1 minute maximum.

3. Derate linearly above 80 °C free-air temperature at a rate of 2.7 mW/°C for the SOIC-8 package.

4. Each channel.

5. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.

6. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 VRMS for 1 second (leakage detec-

tion current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (method b) shown in the IEC/EN/

DIN EN 60747-5-5 Insulation Characteristics Table, if applicable.

7. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 VRMS for 1 second (leakage detec-

tion current limit, II-O ≤ 5 µA).

8. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together.

9. The tPLH propagation delay is measured from the 1.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of

the output pulse.

10. The tPHL propagation delay is measured from the 1.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of

the output pulse.

11. Propagation delay skew (tPSK) is equal to the worst case dierence in tPLH and/or tPHL that will be seen between any two units under the same

test conditions and operating temperature.

12. Single channel products only (HCPL-261A/261N/061A/061N).

13. Common mode transient immunity in a Logic High level is the maximum tolerable |dVCM/dt| of the common mode pulse, VCM, to assure that

the output will remain in a Logic High state (i.e., Vo > 2.0 V).

14. Common mode transient immunity in a Logic Low level is the maximum tolerable |dVCM/dt| of the common mode pulse, VCM, to assure that

the output will remain in a Logic Low state (i.e., VO < 0.8 V).

15. For sinusoidal voltages

(|dVCM/dt|)max = πfCM VCM(P-P).

16. Bypassing of the power supply line is required with a 0.1 µF ceramic disc capacitor adjacent to each optocoup ler as shown in Figure 19. Total

lead length between both ends of the capacitor and the isolator pins should not exceed 10 mm.

17. Pulse Width Distortion (PWD) is dened as the dierence between tPLH and tPHL for any given device.

18. No external pull up is required for a high logic state on the enable input of a single channel product. If the VE pin is not used, tying VE to VCC

will result in improved CMR performance.

19. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel parts only.

IOH – HIGH LEVEL OUTPUT CURRENT – µA

-60

TA – TEMPERATURE – C

100

-20

VCC = 5.5 V

VO = 5.5 V

VE = 2 V

VF = 0.8 V

-40 0 40 80

IOL – LOW LEVEL OUTPUT CURRENT – mA

-60

TA – TEMPERATURE – C

100

-20

VCC = 5 V

VE = 2 V

VOL = 0.6 V

IF = 3.5 mA

60-40 0 40 80

IF – INPUT FORWARD CURRENT – mA

1.0

0.01

VF – FORWARD VOLTAGE – V

1.5

10.0

100.0

1.2

0.1

1.41.1 1.3

1.0

TA = 85 C TA = 40 C

TA = 25 C

–

VO – OUTPUT VOLTAGE – V

IF – FORWARD INPUT CURRENT – mA

2.0

4.0

5.0

1.0

2.0

0.5 1.5

3.0

1.0

RL = 4 kW

RL = 350 Ω

RL = 1 kΩ

VOL – LOW LEVEL OUTPUT VOLTAGE – V

-60

0.2

TA – TEMPERATURE – C

100

0.5

0.6

-20

0.3

20 60-40 0 40 80

0.4

VCC = 5.5 V

VE = 2 V

IF = 3.0 mA

IO = 16 mA

IO = 12.8 mA

IO = 9.6 mA

IO = 6.4 mA

Figure 9. Test circuit for tPHL and tPLH.

Figure 4. Typical high level output current vs.

temperature.

Figure 6. Typical diode input forward current

characteristic.

Figure 5. Low level output current vs. temper-

ature.

Figure 7. Typical output voltage vs. forward

input current.

Figure 8. Typical low level output voltage vs.

temperature.

OUTPUT V

MONITORING

NODE

1.5 V

tPHL tPLH

INPUT

OUTPUT

I = 3.5 mA

I = 1.75 mA

+5 V

PULSE GEN.

Z = 50 Ω

t = t = 5 ns

0.1 µF

BYPASS

*CL

*C IS APPROXIMATELY 15 pF WHICH INCLUDES

PROBE AND STRAY WIRING CAPACITANCE.

GND

INPUT

MONITORING

NODE

HCPL-261A/261N

90% 90%

10% 10%

trise tfall

VOH

VOL

ITH – INPUT THRESHOLD CURRENT – mA

-60

TA – TEMPERATURE – C

100

1.5

2.0

-20

0.5

20 60-40 0 40 80

1.0

VCC = 5 V

VO = 0.6 V

RL = 350 Ω

RL = 1 kΩ

RL = 4 kΩ

tp – PROPAGATION DELAY – ns

-60

TA – TEMPERATURE – C

100

120

-20

20 60-40 0 40 80

TPLH

RL = 4 kΩ

TPLH

RL = 1 kΩ

TPLH

RL = 350 kΩ

TPHL

RL = 350 Ω, 1 kΩ, 4 kΩ

VCC = 5 V

IF = 3.5 mA

tp – PROPAGATION DELAY – ns

IF – PULSE INPUT CURRENT – mA

100

120

6 84 10

TPLH

RL = 4 kΩ

VCC = 5 V

TA = 25 C

TPLH

RL = 1 kΩ

TPHL

RL = 350 Ω, 1 kΩ, 4 kΩ

TPLH

RL = 350 Ω

tr, tf – RISE, FALL TIME – ns

-60

TA – TEMPERATURE – C

100

140

160

-20

20 60-40 0 40 80

120

VCC = 5 V

IF = 3.5 mA

RL = 4 kΩ

RL = 1 kΩ

RL = 350 Ω, 1 kΩ, 4 kΩ

trise

tfall

RL = 350 Ω

PWD – ns

-60

TA – TEMPERATURE – C

100

-20

20 60-40 0 40 80

RL = 1 kΩ

RL = 350 Ω

VCC = 5 V

IF = 3.5 mA

RL = 4 kΩ

Figure 10. Typical input threshold current vs.

temperature.

Figure 13. Typical pulse width distortion vs.

temperature.

Figure 11. Typical propagation delay vs. tem-

perature.

Figure 12. Typical propagation delay vs. pulse

input current.

Figure 14. Typical rise and fall time vs. temperature.

OUTPUT V

MONITORING

NODE

1.5 V

tEHL tELH

INPUT

OUTPUT

3.0 V

1.5 V

+5 V

PULSE GEN.

Z = 50 Ω

t = t = 5 ns

0.1 µF

BYPASS

*CL

*C IS APPROXIMATELY 15 pF WHICH INCLUDES

PROBE AND STRAY WIRING CAPACITANCE.

GND

3.5 mA

INPUT VE

MONITORING NODE

HCPL-261A/261N

tE – ENABLE PROPAGATION DELAY – ns

-60

TA – TEMPERATURE – C

100

120

-20

20 60-40 0 40 80

VCC = 5 V

VEH = 3 V

VEL = 0 V

IF = 3.5 mA

tELH, RL = 4 kΩ

tELH, RL = 1 kΩ

tEHL, RL = 350 Ω, 1k Ω, 4 kΩ

tELH, RL = 350 Ω

VO0.5 V

V (min.)

5 V

0 V SWITCH AT A: I = 0 mA

SWITCH AT B: I = 3.5 mA

CM L

V (max.)

V (PEAK)

+5 V

1CC

0.1 µF

BYPASS

GND

OUTPUT V

MONITORING

NODE

PULSE GEN.

Z = 50 Ω

350 Ω

VFF

HCPL-261A/261N

OUTPUT POWER – PS, INPUT CURRENT – IS

TS – CASE TEMPERATURE – C

20050

400

12525 75 100 150

600

800

200

100

300

500

700

PS (mW)

IS (mA)

HCPL-261A/261N OPTION 060 ONLY

175

Figure 15. Test circuit for tEHL and tELH.

Figure 17. Test circuit for common mode transient immunity and typical waveforms.

Figure 16. Typical enable propaga tion delay vs. temperature.

HCPL-261A/-261N/-061A/-061N Only.

Figure 18. Thermal derating curve, dependence of safety limiting

value with case temperature per IEC/EN/DIN EN 60747-5-5.

Figure 20. Recommended drive circuit for HCPL-261A/-261N families for high-CMR

(similar for HCPL-263A/-263N).

Application Information

Common-Mode Rejection for HCPL-

261A/HCPL-261N Families:

Figure 20 shows the recom mended

drive circuit for the HCPL-261N/-

261A for optimal common-mode

rejection performance. Two main

points to note are:

1. The enable pin is tied to VCC rather

than oating (this applies to

single-channel parts only).

2. Two LED-current setting resistors

are used instead of one. This is

to balance ILED variation during

common-mode transients.

If the enable pin is left oating, it is

possible for common-mode tran-

sients to couple to the enable pin,

resulting in common-mode failure.

This failure mechanism only occurs

when the LED is on and the output

is in the Low State. It is identied as

occurring when the transient output

voltage rises above 0.8 V. Therefore,

the enable pin should be connected

to either VCC or logic-level high for

best common-mode performance

with the output low (CMRL). This

failure mechanism is only present

in single-channel parts (HCPL-261N,

-261A, -061N, -061A) which have the

enable function.

Also, common-mode transients can

capacitively couple from the LED an-

ode (or cathode) to the output-side

ground causing current to be shunt-

ed away from the LED (which can be

bad if the LED is on) or conversely

cause current to be injected into the

LED (bad if the LED is meant to be

o). Figure 21 shows the parasitic

capacitances which exists between

LED anode/cathode and output

ground (CLA and CLC). Also shown in

Figure 21 on the input side is an AC-

equivalent circuit.

*Higher CMR may be obtainable by connecting pins 1, 4 to input ground (Gnd1).

SINGLE CHANNEL PRODUCTS

Figure 19. Recommended printed circuit board layout.

DUAL CHANNEL PRODUCTS

ENABLE

(IF USED)

GND BUS (BACK)

V BUS (FRONT)

N.C.

OUTPUT 1

OUTPUT 2

ENABLE

(IF USED)

0.1µF

10 mm MAX. (SEE NOTE 16)

GND BUS (BACK)

V BUS (FRONT)

OUTPUT 1

OUTPUT 2

0.1µF

10 mm MAX. (SEE NOTE 16)

0.01 µF

350 Ω

74LS04

OR ANY TOTEM-POLE

OUTPUT LOGIC GATE

VCC+

SHIELD 5

HCPL-261A/261N

GND

GND2

357 Ω

(MAX.)

VCC

357 Ω

(MAX.)

* HIGHER CMR MAY BE OBTAINABLE BY CONNECTING PINS 1, 4 TO INPUT GROUND (GND1).

GND1

Figure 22. TTL interface circuit for the HCPL-261A/-261N families.

Table 1 indicates the directions of ILP and ILN ow depend-

ing on the direction of the common-mode transient.

For transients occurring when the LED is on, common-

mode rejec tion (CMRL, since the output is in the “low”

state) depends upon the amount of LED current drive (IF).

For conditions where IF is close to the switching thresh-

old (ITH), CMRL also depends on the extent which ILP and ILN

balance each other. In other words, any condition where

common-mode transients cause a momentary decrease

in IF (i.e. when dVCM/dt>0 and |IFP| > |IFN|, referring to Table

1) will cause common-mode failure for transients which

are fast enough.

Likewise for common-mode transients which occur

when the LED is o (i.e. CMRH, since the output is “high”),

if an imbalance between ILP and ILN results in a transient

IF equal to or greater than the switching threshold of the

optocoupler, the transient “signal” may cause the output

to spike below 2 V (which consti tutes a CMRH failure).

By using the recommended circuit in Figure 20, good

CMR can be achieved. (In the case of the -261N families,

a minimum CMR of 15 kV/µs is guaranteed using this cir-

cuit.) The balanced ILED-setting resistors help equalize ILP

and ILN to reduce the amount by which ILED is modulated

from transient coupling through CLA and CLC.

CMR with Other Drive Circuits

CMR performance with drive circuits other than that

shown in Figure 20 may be enhanced by following these

guidelines:

1. Use of drive circuits where current is shunted from

the LED in the LED “o” state (as shown in Figures 22

and 23). This is benecial for good CMRH.

2. Use of IFH > 3.5 mA. This is good for high CMRL.

Using any one of the drive circuits in Figures 22-24 with

IF = 10 mA will result in a typical CMR of 8 kV/µs for the

HCPL-261N family, as long as the PC board layout prac-

tices are followed. Figure 22 shows a circuit which can

be used with any totem-pole-output TTL/LSTTL/HCMOS

logic gate. The buer PNP transistor allows the circuit to

be used with logic devices which have low current-sink-

ing capability. It also helps maintain the driving-gate

power-supply current at a constant level to minimize

ground shifting for other devices connected to the in-

put-supply ground.

When using an open-collector TTL or open-drain CMOS

logic gate, the circuit in Figure 23 may be used. When

using a CMOS gate to drive the optocoupler, the circuit

shown in Figure 24 may be used. The diode in parallel

with the RLED speeds the turn-o of the optocoupler

LED.

Figure 21. AC equivalent circuit for HCPL-261X.

350 Ω

1/2 RLED

VCC+

15 pF

VCM

SHIELD 5

CLA VO

GND

0.01 µF

1/2 RLED

CLC

ILN

ILP

–

420 Ω

(MAX)

2N3906

(ANY PNP)

VCC

74L504

(ANY

TTL/CMOS

GATE)

HCPL-261X

LED

Figure 24. CMOS gate drive circuit for HCPL-261A/-261N families.

Figure 23. TTL open-collector/open drain gate drive circuit for

HCPL-261A/-261N families.

coup lers, dierences in propaga tion delays will cause

the data to arrive at the outputs of the opto couplers at

dierent times. If this dierence in propagation delay

is large enough it will determine the maximum rate at

which parallel data can be sent through the optocou-

plers.

Propagation delay skew is dened as the dierence be-

tween the minimum and maximum propaga tion delays,

either tPLH or tPHL, for any given group of optocouplers

which are operating under the same conditions (i.e., the

same drive current, supply voltage, output load, and op-

erating temperature). As illustrated in Figure 25, if the in-

puts of a group of optocouplers are switched either ON

or OFF at the same time, tPSK is the dier ence between

the shortest propagation delay, either tPLH or tPHL, and the

longest propagation delay, either tPLH or tPHL.

As mentioned earlier, tPSK can determine the maximum

parallel data transmission rate. Figure 26 is the timing

diagram of a typical parallel data application with both

the clock and the data lines being sent through opto-

couplers.

Table 1. Eects of Common Mode Pulse Direction on Transient ILED

If |ILP| < |ILN|, If |ILP| > |ILN|,

LED IF Current LED IF Current

If dVCM/dt Is: then ILP Flows: and ILN Flows: Is Momentarily: Is Momentarily:

positive (>0) away from LED away from LED increased decreased

anode through CLA cathode through CLC

negative (<0) toward LED toward LED decreased increased

anode through CLA cathode through CLC

Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew

Propagation delay is a gure of merit which describes

how quickly a logic signal propagates through a sys-

tem. The propaga tion delay from low to high (tPLH) is the

amount of time required for an input signal to propa-

gate to the output, causing the output to change from

low to high. Similarly, the propagation delay from high

to low (tPHL) is the amount of time required for the input

signal to propagate to the output, causing the output to

change from high to low (see Figure 9).

Pulse-width distortion (PWD) results when tPLH and tPHL

dier in value. PWD is dened as the dierence between

tPLH and tPHL and often determines the maximum data

rate capability of a transmission system. PWD can be ex-

pressed in percent by dividing the PWD (in ns) by the

minimum pulse width (in ns) being transmitted. Typical-

ly, PWD on the order of 20-30% of the minimum pulse

width is tolerable; the exact gure depends on the par-

ticular appli cation (RS232, RS422, T-1, etc.).

Propagation delay skew, tPSK, is an important parameter

to con sider in parallel data applications where synchro-

nization of signals on parallel data lines is a con cern. If

the parallel data is being sent through a group of opto-

820 Ω1

VCC

74HC00

(OR ANY

OPEN-COLLECTOR/

OPEN-DRAIN

LOGIC GATE)

HCPL-261X

LED

750 Ω

VCC

74HC04

(OR ANY

TOTEM-POLE

OUTPUT LOGIC

GATE)

HCPL-261A/261N

1N4148

LED

50%

1.5 V

50%I F

tPSK

1.5 V

TPHL

TPLH

DATA

tPSK

INPUTS

CLOCK

DATA

OUTPUTS

CLOCK

tPSK

Figure 25. Illustration of propagation delay skew – tPSK.

Figure 26. Parallel data transmission example.

The gure shows data and clock signals at the inputs and

outputs of the optocouplers. To obtain the maximum

data transmission rate, both edges of the clock signal are

being used to clock the data; if only one edge were used,

the clock signal would need to be twice as fast.

Propagation delay skew repre sents the uncertainty of

where an edge might be after being sent through an op-

tocoupler. Figure 26 shows that there will be uncertainty

in both the data and the clock lines. It is important that

these two areas of uncer tainty not overlap, otherwise

the clock signal might arrive before all of the data out-

puts have settled, or some of the data outputs may start

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AV02-0391EN - April 30, 2013

to change before the clock signal has arrived. From these

considera tions, the absolute minimum pulse width that

can be sent through optocouplers in a parallel applica-

tion is twice tPSK. A cautious design should use a slightly

longer pulse width to ensure that any additional uncer-

tainty in the rest of the circuit does not cause a prob-

lem.

The tPSK specied optocouplers oer the advantages of

guaran teed specications for propaga tion delays, pulse-

width distortion, and propagation delay skew over the

recommended temperature, input current, and power

supply ranges.