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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC084S085
SNAS363F –MAY 2006–REVISED MARCH 2016
DAC084S085 8-Bit Micropower QUAD Digital-to-Analog Converter With Rail-to-Rail Output
1
1 Features
1• Ensured Monotonicity
• Low-Power Operation
• Rail-to-Rail Voltage Output
• Power-On Reset to 0 V
• Simultaneous Output Updating
• Wide Power Supply Range (2.7 V to 5.5 V)
• Industry's Smallest Package
• Power Down Modes
• Key Specifications
– Resolution: 8 Bits
– INL: ±0.5 LSB (Maximum)
– DNL: +0.18 / −0.13 LSB (Maximum)
– Setting Time: 4.5 µs (Maximum)
– Zero Code Error: +15 mV (Maximum)
– Full-Scale Error: −0.75 %FS (Maximum)
– Supply Power:
– Normal: 1.1 mW (3 V) / 2.5 mW (5 V)
Typical
– Power Down: 0.3 µW (3 V) / 0.8 µW (5 V)
Typical
2 Applications
• Battery-Powered Instruments
• Digital Gain and Offset Adjustment
• Programmable Voltage and Current Sources
• Programmable Attenuators
3 Description
The DAC084S085 is a full-featured, general-purpose
QUAD 8-bit voltage-output digital-to-analog converter
(DAC) that can operate from a single 2.7-V to 5.5-V
supply and consumes 1.1 mW at 3 V and 2.5 mW at
5 V. The DAC084S085 is packaged in 10-pin SON
and VSSOP packages. The 10-pin SON package
makes the DAC084S085 the smallest QUAD DAC in
its class. The on-chip output amplifier allows rail-to-
rail output swing and the three wire serial interface
operates at clock rates up to 40 MHz over the entire
supply voltage range. Competitive devices are limited
to 25-MHz clock rates at supply voltages in the 2.7-V
to 3.6-V range. The serial interface is compatible with
standard SPI, QSPI, MICROWIRE, and DSP
interfaces.
The reference for the DAC084S085 serves all four
channels and can vary in voltage between 1 V and
VA, providing the widest possible output dynamic
range. The DAC084S085 has a 16-bit input shift
register that controls the outputs to be updated, the
mode of operation, the power-down condition, and
the binary input data. All four outputs can be updated
simultaneously or individually depending on the
setting of the two mode of operation bits.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
DAC084S085 VSSOP (10) 3.00 mm × 3.00 mm
WSON (10) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
DNL vs Code at VA=3V
2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Description............................................................. 3
6 Pin Configuration and Functions......................... 3
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements................................................ 7
7.7 Typical Characteristics.............................................. 9
8 Detailed Description............................................ 14
8.1 Overview................................................................. 14
8.2 Functional Block Diagram....................................... 14
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 16
8.5 Programming........................................................... 16
9 Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Application ................................................. 20
10 Power Supply Recommendations ..................... 21
10.1 Using References as Power Supplies................... 21
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 Device and Documentation Support................. 25
12.1 Device Support .................................................... 25
12.2 Community Resources.......................................... 26
12.3 Trademarks........................................................... 26
12.4 Electrostatic Discharge Caution............................ 26
12.5 Glossary................................................................ 26
13 Mechanical, Packaging, and Orderable
Information........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2013) to Revision F Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.................................................................................................. 1
Changes from Revision D (March 2013) to Revision E Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 24
VA
VOUTA
VOUTB
VOUTD
VOUTC
SCLK
DIN
VREFIN
GND
VSSOP
1
2
3
4
5
10
9
8
7
6
SYNC
VA
VOUTA
VOUTB
VOUTD
VOUTC
SCLK
DIN
VREFIN
GND
SON
1
2
3
4
5
10
9
8
7
6
SYNC
3
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5 Description
A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a
valid write to the device. A power-down feature reduces power consumption to less than a microWatt with three
different termination options.
The low-power consumption and small packages of the DAC084S085 make it an excellent choice for use in
battery-operated equipment.
The DAC084S085 is one of a family of pin-compatible DACs, including the 10-bit DAC104S085 and the 12-bit
DAC124S085. The DAC084S085 operates over the extended industrial temperature range of −40°C to +105°C.
6 Pin Configuration and Functions
DSC Package
10-Pin WSON
Top View DGS Package
10-Pin VSSOP
Top View
Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
1 VASupply Power supply input. Must be decoupled to GND.
2 VOUTA Analog Output Channel A Analog Output Voltage.
3 VOUTB Analog Output Channel B Analog Output Voltage.
4 VOUTC Analog Output Channel C Analog Output Voltage.
5 VOUTD Analog Output Channel D Analog Output Voltage.
6 GND Ground Ground reference for all on-chip circuitry.
7 VREFIN Analog Input Unbuffered reference voltage shared by all channels. Must be decoupled
to GND.
8 DIN Digital Input Serial Data Input. Data is clocked into the 16-bit shift register on the
falling edges of SCLK after the fall of SYNC.
9 SYNC Digital Input
Frame synchronization input for the data input. When this pin goes low, it
enables the input shift register and data is transferred on the falling edges
of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is
brought high before the 16th clock, in which case the rising edge of
SYNC acts as an interrupt and the write sequence is ignored by the DAC.
10 SCLK Digital Input Serial Clock Input. Data is clocked into the input shift register on the
falling edges of this pin.
11 PAD
(WSON only) Ground Exposed die attach pad can be connected to ground or left floating.
Soldering the pad to the PCB offers optimal thermal performance and
enhances package self-alignment during reflow.
I/O
GND
TO INTERNAL
CIRCUITRY
4
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are measured with respect to GND = 0 V, unless otherwise specified.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Semiconductor Sales Office/Distributors for
availability and specifications.
(4) When the input voltage at any pin exceeds 5.5 V or is less than GND, the current at that pin must be limited to 10 mA. The 20 mA
maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of
10 mA to two.
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax −TA) / θJA. The values for maximum power dissipation is reached only when the device is operated in a severe fault
condition (that is, when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).
7 Specifications
7.1 Absolute Maximum Ratings(1)(2)(3)
MIN MAX UNIT
Supply voltage, VA6.5 V
Voltage on any input pin −0.3 6.5 V
Input current at any pin(4) 10 mA
Package input current(4) 20 mA
Power consumption at TA= 25°C See(5)
Junction temperature 150 °C
Storage temperature, Tstg −65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Human body model is 100-pF capacitor discharged through a 1.5-kΩresistor. Machine model is 220 pF discharged through 0 Ω.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(3) ±250
(1) All voltages are measured with respect to GND = 0 V, unless otherwise specified.
(2) The inputs are protected as shown below. Input voltage magnitudes up to 5.5 V, regardless of VA, does not cause errors in the
conversion result. For example, if VAis 3 V, the digital input pins can be driven with a 5-V logic device.
7.3 Recommended Operating Conditions
See (1)
MIN MAX UNIT
Operating temperature −40 105 °C
Supply voltage, VA2.7 5.5 V
Reference voltage, VREFIN 1 VAV
Digital input voltage (2) 0 5.5 V
Output load 0 1500 pF
SCLK frequency 40 MHz
5
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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Reflow temperature profiles are different for lead-free packages..
7.4 Thermal Information
THERMAL METRIC(1)(2) DAC084S085
UNITDGS (VSSOP) DSC (WSON)
10 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 240 250 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 53.3 40.7 °C/W
RθJB Junction-to-board thermal resistance 78.9 23.7 °C/W
ψJT Junction-to-top characterization parameter 4.8 0.4 °C/W
ψJB Junction-to-board characterization parameter 77.6 23.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 4.7 °C/W
(1) Typical figures are at TJ= 25°C, and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing
Quality Level).
(2) This parameter is specified by design and/or characterization and is not tested in production.
7.5 Electrical Characteristics
The following specifications apply for VA= 2.7 V to 5.5 V, VREFIN = VA, CL= 200 pF to GND, fSCLK = 30 MHz, input code range
3 to 252. All limits are at TA= 25°C, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN(1) TYP(1) MAX(1) UNIT
STATIC PERFORMANCE
Resolution TMIN ≤TA≤TMAX 8 Bits
Monotonicity TMIN ≤TA≤TMAX 8 Bits
INL Integral non-linearity TA= 25°C ±0.14 LSB
TMIN ≤TA≤TMAX ±0.5
DNL Differential non-linearity VA= 2.7 V to 5.5 V TA= 25°C −0.02 +0.04 LSB
TMIN ≤TA≤TMAX −0.13 +0.18
ZE Zero code error IOUT = 0 mA TA= 25°C +4 mV
TMIN ≤TA≤TMAX +15
FSE Full-scale error IOUT = 0 mA TA= 25°C −0.1 %FSR
TMIN ≤TA≤TMAX −0.75
GE Gain error All ones Loaded to
DAC register TA= 25°C −0.2 %FSR
TMIN ≤TA≤TMAX −1
ZCED Zero code error drift −20 µV/°C
TC GE Gain error tempco VA= 3 V −0.7 ppm/°C
VA= 5 V −1
OUTPUT CHARACTERISTICS
Output voltage range See (2), TMIN ≤TA≤TMAX 0 VREFIN V
IOZ High-impedance output
leakage current(2) TMIN ≤TA≤TMAX ±1 µA
ZCO Zero code output
VA= 3 V, IOUT = 200 µA 1.3
mV
VA= 3 V, IOUT = 1 mA 6
VA= 5 V, IOUT = 200 µA 7
VA= 5 V, IOUT = 1 mA 10
FSO Full scale output
VA= 3 V, IOUT = 200 µA 2.984
V
VA= 3 V, IOUT = 1 mA 2.934
VA= 5 V, IOUT = 200 µA 4.989
VA= 5 V, IOUT = 1 mA 4.958
IOS Output short-circuit current
(source)
VA= 3 V, VOUT = 0 V,
Input Code = FFh –56 mA
VA= 5 V, VOUT = 0 V,
Input Code = FFh –69
6
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Electrical Characteristics (continued)
The following specifications apply for VA= 2.7 V to 5.5 V, VREFIN = VA, CL= 200 pF to GND, fSCLK = 30 MHz, input code range
3 to 252. All limits are at TA= 25°C, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN(1) TYP(1) MAX(1) UNIT
IOS Output short-circuit current
(sink)
VA= 3 V, VOUT = 3 V,
Input Code = 00h 52 mA
VA= 5 V, VOUT = 5 V,
Input Code = 00h 75
IOContinuous output
current(2) Avaliable on each DAC output, TMIN ≤TA≤TMAX 11 mA
CLMaximum load capacitance RL=∞1500 pF
RL= 2 kΩ1500
ZOUT DC output impedance 7.5 Ω
REFERENCE INPUT CHARACTERISTICS
VREFIN
Input range minimum 0.2 V
TMIN ≤TA≤TMAX 1
Input range maximum TMIN ≤TA≤TMAX VAV
Input impedance 30 kΩ
LOGIC INPUT CHARACTERISTICS
IIN Input current(2) TMIN ≤TA≤TMAX ±1 µA
VIL Input low voltage(2) VA= 3 V TA= 25°C 0.9 V
TMIN ≤TA≤TMAX 0.6
VA= 5 V TA= 25°C 1.5 V
TMIN ≤TA≤TMAX 0.8
VIH Input high voltage(2) VA= 3 V TA= 25°C 1.4 V
TMIN ≤TA≤TMAX 2.1
VA= 5 V TA= 25°C 2.1 V
TMIN ≤TA≤TMAX 2.4
CIN Input capacitance(2) TMIN ≤TA≤TMAX 3 pF
POWER REQUIREMENTS
VASupply voltage minimum TMIN ≤TA≤TMAX 2.7 V
Supply voltage maximum TMIN ≤TA≤TMAX 5.5 V
INNormal supply current (output
unloaded)
fSCLK = 30 MHz
VA= 2.7 V
to 3.6 V TA= 25°C 370 µA
TMIN ≤TA≤TMAX 485
VA= 4.5 V
to 5.5 V TA= 25°C 500 µA
TMIN ≤TA≤TMAX 650
fSCLK = 0 MHz
VA= 2.7 V
to 3.6 V 350 µA
VA= 4.5 V
to 5.5 V 460 µA
IPD Power-down supply current
(output unloaded, SYNC = DIN
= 0 V after PD mode loaded) All PD Modes(2)
VA= 2.7 V
to 3.6 V TA= 25°C 0.1 µA
TMIN ≤TA≤TMAX 1
VA= 4.5 V
to 5.5 V TA= 25°C 0.15 µA
TMIN ≤TA≤TMAX 1
PNNormal supply power (output
unloaded)
fSCLK = 30 MHz
VA= 2.7 V
to 3.6 V TA= 25°C 1.1 mW
TMIN ≤TA≤TMAX 1.7
VA= 4.5 V
to 5.5 V TA= 25°C 2.5 mW
TMIN ≤TA≤TMAX 3.6
fSCLK = 0 MHz
VA= 2.7 V
to 3.6 V 1.1 mW
VA= 4.5 V
to 5.5 V 2.3 mW
7
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Electrical Characteristics (continued)
The following specifications apply for VA= 2.7 V to 5.5 V, VREFIN = VA, CL= 200 pF to GND, fSCLK = 30 MHz, input code range
3 to 252. All limits are at TA= 25°C, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN(1) TYP(1) MAX(1) UNIT
PPD Power-down supply power
(output unloaded, SYNC = DIN
= 0 V after PD mode loaded) All PD Modes(2)
VA= 2.7 V
to 3.6 V TA= 25°C 0.3 µW
TMIN ≤TA≤TMAX 3.6
VA= 4.5 V
to 5.5 V TA= 25°C 0.8 µW
TMIN ≤TA≤TMAX 5.5
(1) Typical figures are at TJ= 25°C, and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing
Quality Level).
(2) This parameter is specified by design and/or characterization and is not tested in production.
7.6 Timing Requirements
Values shown in this table are design targets and are subject to change before product release.
The following specifications apply for VA= 2.7 V to 5.5 V, VREFIN = VA, CL= 200 pF to GND, fSCLK = 30 MHz, input code range
3 to 252. All limits are at TA= 25°C, unless otherwise specified. MIN(1) TYP(1) MAX(1) UNIT
fSCLK SCLK frequency TA= 25°C 40 MHz
TMIN ≤TA≤TMAX 30
tsOutput voltage settling time(2) 40h to C0h code change
RL= 2 kΩ, CL= 200 pF TA= 25°C 3 µs
TMIN ≤TA≤TMAX 4.5
SR Output slew rate 1 V/µs
Glitch impulse Code change from 80h to 7Fh 12 nV-sec
Digital feedthrough 0.5 nV-sec
Digital crosstalk 1 nV-sec
DAC-to-DAC crosstalk 3 nV-sec
Multiplying bandwidth VREFIN = 2.5 V ± 0.1 Vpp 160 kHz
Total harmonic distortion VREFIN = 2.5 V ± 0.1 Vpp
input frequency = 10 kHz 70 dB
tWU Wake-up time VA= 3 V 6 µsec
VA= 5 V 39 µsec
1/fSCLK SCLK cycle time TA= 25°C 25 ns
TMIN ≤TA≤TMAX 33
tCH SCLK high time TA= 25°C 7 ns
TMIN ≤TA≤TMAX 10
tCL SCLK low Time TA= 25°C 7 ns
TMIN ≤TA≤TMAX 10
tSS SYNC set-up time prior to SCLK
falling edge TA= 25°C 4 ns
TMIN ≤TA≤TMAX 10
tDS Data set-up time prior to SCLK falling
edge TA= 25°C 1.5 ns
TMIN ≤TA≤TMAX 3.5
tDH Data hold time after SCLK falling
edge TA= 25°C 1.5 ns
TMIN ≤TA≤TMAX 3.5
tCFSR SCLK fall prior to rise of SYNC TA= 25°C 0 ns
TMIN ≤TA≤TMAX 3
tSYNC SYNC high time TA= 25°C 6 ns
TMIN ≤TA≤TMAX 10
OUTPUT
VOLTAGE
DIGITAL INPUT CODE
00 255
ZE
FSE
GE = FSE - ZE
FSE = GE + ZE
255 x VREFIN
256
DB15 DB0
SCLK
DIN
SYNC
tSYNC
tDS
tDH
tCL tCH
1 / fSCLK
tCFSR
|
|
||
1 2 13 14 15 16
tSS
8
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Figure 1. Serial Timing Diagram
Figure 2. Input / Output Transfer Characteristic
9
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7.7 Typical Characteristics
VREF = VA, fSCLK = 30 MHz, TA= 25°C, Input Code Range 3 to 252, unless otherwise stated
Figure 3. INL at VA= 3 V Figure 4. INL at VA= 5 V
Figure 5. DNL at VA= 3 V Figure 6. DNL at VA= 5 V
Figure 7. INL/DNL vs VREFIN at VA= 3 V Figure 8. INL/DNL vs VREFIN at VA= 5 V
10
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Typical Characteristics (continued)
VREF = VA, fSCLK = 30 MHz, TA= 25°C, Input Code Range 3 to 252, unless otherwise stated
Figure 9. INL/DNL vs fSCLK at VA= 2.7 V Figure 10. INL/DNL vs VA
Figure 11. INL/DNL vs Clock Duty Cycle at VA= 3 V Figure 12. INL/DNL vs Clock Duty Cycle at VA= 5 V
Figure 13. INL/DNL vs Temperature at VA= 3 V Figure 14. INL/DNL vs Temperature at VA= 5 V
11
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Typical Characteristics (continued)
VREF = VA, fSCLK = 30 MHz, TA= 25°C, Input Code Range 3 to 252, unless otherwise stated
Figure 15. Zero Code Error vs VAFigure 16. Zero Code Error vs VREFIN
Figure 17. Zero Code Error vs fSCLK Figure 18. Zero Code Error vs Clock Duty Cycle
Figure 19. Zero Code Error vs Temperature Figure 20. Full-Scale Error vs VA
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Typical Characteristics (continued)
VREF = VA, fSCLK = 30 MHz, TA= 25°C, Input Code Range 3 to 252, unless otherwise stated
Figure 21. Full-Scale Error vs VREFIN Figure 22. Full-Scale Error vs fSCLK
Figure 23. Full-Scale Error vs Clock Duty Cycle Figure 24. Full-Scale Error vs Temperature
Figure 25. Supply Current vs VAFigure 26. Supply Current vs Temperature
13
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Typical Characteristics (continued)
VREF = VA, fSCLK = 30 MHz, TA= 25°C, Input Code Range 3 to 252, unless otherwise stated
Figure 27. 5V Glitch Response Figure 28. Power-On Reset
POWER-ON
RESET
DAC
REGISTER
INPUT
CONTROL
LOGIC
8
POWER-DOWN
CONTROL
LOGIC
VREFIN
DAC084S085
VOUTA
8 BIT DAC
REF
8
SCLK DIN
SYNC
8
8
8
VOUTB
VOUTC
VOUTD
2.5k 100k
2.5k 100k
2.5k 100k
2.5k 100k
8 BIT DAC
REF
8 BIT DAC
REF
8 BIT DAC
REF
BUFFER
BUFFER
BUFFER
BUFFER
14
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8 Detailed Description
8.1 Overview
The DAC084S085 is a full-featured, general-purpose QUAD 8-bit voltage-output digital-to-analog converter
(DAC) that can operate from a single 2.7-V to 5.5-V supply and consumes 1.1 mW at 3 V and 2.5 mW at 5 V.
The on-chip output amplifier allows rail-to-rail output swing and the three wire serial interface operates at clock
rates up to 40 MHz over the entire supply voltage range. The serial interface is compatible with standard SPI,
QSPI, MICROWIRE, and DSP interfaces.
The reference for the DAC084S085 serves all four channels and can vary in voltage between 1 V and VA,
providing the widest possible output dynamic range. The DAC084S085 has a 16-bit input shift register that
controls the outputs to be updated, the mode of operation, the power-down condition, and the binary input data.
All four outputs can be updated simultaneously or individually depending on the setting of the two mode of
operation bits.
A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a
valid write to the device. A power-down feature reduces power consumption to less than a microWatt with three
different termination options.
8.2 Functional Block Diagram
VA
R
R
R
R
To Output Amplifier
R
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8.3 Feature Description
8.3.1 DAC Section
The DAC084S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor
strings that are followed by an output buffer. The reference voltage is externally applied at VREFIN and is shared
by all four DACs.
For simplicity, a single resistor string is shown in Figure 29. This string consists of 256 equal valued resistors
with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register
determines which switch is closed, connecting the proper node to the amplifier. The input coding is straight
binary with an ideal output voltage of:
VOUTA,B,C,D = VREFIN x (D / 256)
where
•Dis the decimal equivalent of the binary code that is loaded into the DAC register. D can take on any value
between 0 and 255. This configuration ensures that the DAC is monotonic. (1)
Figure 29. DAC Resistor String
8.3.2 Output Amplifiers
The output amplifiers are rail-to-rail, providing an output voltage range of 0 V to VAwhen the reference is VA. All
amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0 V and VA,
in this case). For this reason, linearity is specified over less than the full output range of the DAC. However, if the
reference is less than VA, there is only a loss in linearity in the lowest codes. The output capabilities of the
amplifier are described in Electrical Characteristics.
The output amplifiers are capable of driving a load of 2 kΩin parallel with 1500 pF to ground or to VA. The zero-
code and full-scale outputs for given load currents are available in Electrical Characteristics.
8.3.3 Reference Voltage
The DAC084S085 uses a single external reference that is shared by all four channels. The reference pin, VREFIN,
is not buffered and has an input impedance of 30 kΩ. TI recommends that VREFIN be driven by a voltage source
with low output impedance. The reference voltage range is 1 V to VA, providing the widest possible output
dynamic range.
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Feature Description (continued)
8.3.4 Power-On Reset
The power-on reset circuit controls the output voltages of the four DACs during power-up. Upon application of
power, the DAC registers are filled with zeros and the output voltages are 0 V. The outputs remain at 0 V until a
valid write sequence is made to the DAC.
8.4 Device Functional Modes
8.4.1 Power-Down Modes
The DAC084S085 has four power-down modes, two of which are identical. In power-down mode, the supply
current drops to 20 µA at 3 V and 30 µA at 5 V. The DAC084S085 is set in power-down mode by setting OP1
and OP0 to 11. Since this mode powers down all four DACs, the address bits, A1 and A0, are used to select
different output terminations for the DAC outputs. Setting A1 and A0 to 00 or 11 causes the outputs to be tri-
stated (a high impedance state). While setting A1 and A0 to 01 or 10 causes the outputs to be terminated by
2.5 kΩor 100 kΩto ground respectively (see Table 1).
Table 1. Power-Down Modes
A1 A0 OP1 OP0 OPERATING MODE
0 0 1 1 High-Z outputs
0 1 1 1 2.5 kΩto GND
1 0 1 1 100 kΩto GND
1 1 1 1 High-Z outputs
The bias generator, output amplifiers, resistor strings, and other linear circuitry are all shut down in any of the
power-down modes. However, the contents of the DAC registers are unaffected when in power-down. Each DAC
register maintains its value prior to the DAC084S085 being powered down unless it is changed during the write
sequence which instructed it to recover from power down. Minimum power consumption is achieved in the
power-down mode with SYNC and DIN idled low and SCLK disabled. The time to exit power-down (Wake-Up
Time) is typically tWU µs as stated in Timing Requirements.
8.5 Programming
8.5.1 Serial Interface
The three-wire interface is compatible with SPI™, QSPI, and MICROWIRE, as well as most DSPs and operates
at clock rates up to 40 MHz. See Figure 1 for information on a write sequence.
A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked
into the 16-bit serial input register on the falling edges of SCLK. To avoid misclocking data into the shift register,
it is critical that SYNC not be brought low simultaneously with a falling edge of SCLK (see Figure 1). On the 16th
falling clock edge, the last data bit is clocked in and the programmed function (a change in the DAC channel
address, mode of operation, and/or register contents) is executed. At this point the SYNC line may be kept low or
brought high. Any data and clock pulses after the 16th falling clock edge is ignored. In either case, SYNC must
be brought high for the minimum specified time before the next write sequence is initiated with a falling edge of
SYNC.
Because the SYNC and DIN buffers draw more current when they are high, they must be idled low between write
sequences to minimize power consumption.
ADSP-2101/
ADSP2103 DAC084S085
TFS
DT
SCLK
DIN
SCLK
SYNC
MSB
A1 A0 OP1 OP0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
DATA BITS
0 0 Write to specified register but do not update outputs.
0 1 Write to specified register and update outputs.
1 0 Write to all registers and update outputs.
1 1 Power-down outputs.
LSB
0 0 DAC A
0 1 DAC B
1 0 DAC C
1 1 DAC D
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Programming (continued)
8.5.2 Input Shift Register
The input shift register, Figure 30, has 16 bits. The first two bits are address bits. They determine whether the
register data is for DAC A, DAC B, DAC C, or DAC D. The address bits are followed by two bits that determine
the mode of operation (writing to a DAC register without updating the outputs of all four DACs, writing to a DAC
register and updating the outputs of all four DACs, writing to the register of all four DACs and updating their
outputs, or powering down all four outputs). The final twelve bits of the shift register are the data bits. The data
format is straight binary (MSB first, LSB last), with all 0s corresponding to an output of 0 V and all 1s
corresponding to a full-scale output of VREFIN – 1 LSB. The contents of the serial input register are transferred to
the DAC register on the sixteenth falling edge of SCLK. See Figure 1.
Figure 30. Input Register Contents
Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th
SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the data transfer to the shift
register is aborted and the write sequence is invalid. Under this condition, the DAC register is not updated and
there is no change in the mode of operation or in the DAC output voltages.
8.5.3 DSP and Microprocessor Interfacing
Interfacing the DAC084S085 to microprocessors and DSPs is quite simple.
8.5.3.1 ADSP-2101 and ADSP2103 Interfacing
Figure 31 shows a serial interface between the DAC084S085 and the ADSP-2101 or ADSP2103. The DSP must
be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control
register and must be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length.
Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.
Figure 31. ADSP-2101 and 2103 Interface
8.5.3.2 80C51 and 80L51 Interface
Figure 32 shows a serial interface between the DAC084S085 and the 80C51 or 80L51 microcontroller. The
SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line
P3.3. This line is taken low when data is transmitted to the DAC084S085. Because the 80C51 and 80L51
transmits 8-bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the
P3.3 line must be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the
second byte of data, after which port line P3.3 is brought high. The 80C51 and 80L51 transmit routine must
recognize that the 80C51 and 80L51 transmits data with the LSB first while the DAC084S085 requires data with
the MSB first.
MICROWIRE
DEVICE DAC084S085
CS
SK
SO
SCLK
DIN
SYNC
68HC11 DAC084S085
PC7
SCK
MOSI
SCLK
DIN
SYNC
80C51/80L51 DAC084S085
P3.3
TXD
RXD
SCLK
DIN
SYNC
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Programming (continued)
Figure 32. 80C51 and 80L51 Interface
8.5.3.3 68HC11 Interface
Figure 33 shows a serial interface between the DAC084S085 and the 68HC11 microcontroller. The SYNC line of
the DAC084S085 is driven from a port line (PC7 in the figure), similar to the 80C51 and 80L51.
The 68HC11 must be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration
causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the
DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB
first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the
second byte of data to the DAC, after which PC7 must be raised to end the write sequence.
Figure 33. 68HC11 Interface
8.5.3.4 Microwire Interface
Figure 34 shows an interface between a Microwire compatible device and the DAC084S085. Data is clocked out
on the rising edges of the SK signal. As a result, the SK of the Microwire device must be inverted before driving
the SCLK of the DAC084S085.
Figure 34. Microwire Interface
DAC084S085
DIN
SCLK
SYNC VOUT
0.1 PF
+
10 PF+
-
+5V
R1
R2
-5V
+5V
±5V
10 pF
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Bipolar Operation
The DAC084S085 is designed for single-supply operation and thus has a unipolar output. However, a bipolar
output may be obtained with the circuit in Figure 35. This circuit provides an output voltage range of ±5 V. A rail-
to-rail amplifier must be used if the amplifier supplies are limited to ±5 V.
Figure 35. Bipolar Operation
The output voltage of this circuit for any code is found to be:
VO= (VA× (D / 256) × ((R1 + R2) / R1) – VA× R2 / R1)
where
• D is the input code in decimal form. (2)
With VA= 5 V and R1 = R2,
VO= (10 × D / 256) – 5 V (3)
A list of rail-to-rail amplifiers suitable for this application are indicated in Table 2.
Table 2. Some Rail-to-Rail Amplifiers
AMP PKGS Typ VOS Typ ISUPPLY
LMC7111 DIP-8
SOT23-5 0.9 mV 25 µA
LM7301 SO-8
SOT23-5 0.03 mV 620 µA
LM8261 SOT23-5 0.7 mV 1 mA
+
-
+
-
ADC121S705
REF
Controller
LMP7702
RI
RF
RF
Bridge
Sensor
+5V
CSB
SCLK
DOUT
SYNCB
SCLK
DIN
REF
REF
DAC084S085
+5V
Channel B
Channel A
Av = 1 + 2 RF
RI
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9.2 Typical Application
Figure 36. Driving an ADC Reference
9.2.1 Design Requirements
Figure 36 shows Channel A of the DAC084S085 providing the drive or supply voltage for a bridge sensor. By
having the sensor supply voltage adjustable, the output of the sensor can be optimized to the input level of the
ADC monitoring it.
9.2.2 Detailed Design Procedure
The output of the sensor is amplified by a fixed gain amplifier stage with a differential gain of 1 + 2 × (RF/ RI).
The advantage of this amplifier configuration is the high input impedance seen by the output of the bridge
sensor. The disadvantage is the poor common-mode rejection ratio (CMRR). The common-mode voltage (VCM)
of the bridge sensor is half of DAC output of Channel A. The VCM is amplified by a gain of 1 V/V by the amplifier
stage and thus becomes the bias voltage for the input of the ADC121S705. Channel B of the DAC084S085 is
providing the reference voltage to the ADC121S705. The reference for the ADC121S705 may be set to any
voltage from 1 V to 5 V, providing the widest dynamic range possible.
The reference voltage for Channel A and B is powered by an external 5-V power supply. Because the 5-V supply
is common to the sensor supply voltage and the reference voltage of the ADC, fluctuations in the value of the
5-V supply has a minimal effect on the digital output code of the ADC. This type of configuration is often referred
to as a ratiometric design. For example, an increase of 5% to the 5-V supply causes the sensor supply voltage to
increase by 5%. This causes the gain or sensitivity of the sensor to increase by 5%. The gain of the amplifier
stage is unaffected by the change in supply voltage. The ADC121S705 on the other hand, also experiences a
5% increase to its reference voltage. This causes the size of the ADC's least significant bit (LSB) to increase by
5%. As a result of the gain of the sensor increasing by 5% and the LSB size of the ADC increasing by the same
5%, there is no net effect on the circuit's performance. It is assumed that the amplifier gain is set low enough to
allow for a 5% increase in the sensor output. Otherwise, the increase in the sensor output level may cause the
output of the amplifiers to clip.
LM4132-4.1
DAC084S085
DIN
SCLK
SYNC VOUT = 0V to 4.092V
C1
0.1 PFC2
2.2 PF
Input
Voltage
VA VREFIN
C3
0.1 PF
OUTPUT
VOLTAGE
DIGITAL INPUT CODE
00 255
ZE
FSE
GE = FSE - ZE
FSE = GE + ZE
255 x VREFIN
256
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Typical Application (continued)
9.2.3 Application Curve
Figure 37. Input / Output Transfer Characteristic
10 Power Supply Recommendations
10.1 Using References as Power Supplies
While the simplicity of the DAC084S085 implies ease of use, it is important to recognize that the path from the
reference input (VREFIN) to the VOUTs has essentially zero power supply rejection ratio (PSRR). Therefore, it is
necessary to provide a noise-free supply voltage to VREFIN. To use the full dynamic range of the DAC084S085,
the supply pin (VA) and VREFIN can be connected together and share the same supply voltage. Because the
DAC084S085 consumes very little power, a reference source may be used as the reference input and/or the
supply voltage. The advantages of using a reference source over a voltage regulator are accuracy and stability.
Some low noise regulators can also be used. Listed below are a few reference and power supply options for the
DAC084S085.
10.1.1 LM4130
The LM4130, with its 0.05% accuracy over temperature, is a good choice as a reference source for the
DAC084S085. The 4.096-V version is useful if a 0-V to 4.095-V output range is desirable or acceptable.
Bypassing the LM4130 VIN pin with a 0.1-µF capacitor and the VOUT pin with a 2.2-µF capacitor improves
stability and reduces output noise. The LM4130 comes in a space-saving 5-pin SOT-23.
Figure 38. LM4130 as a Power Supply
LP3985
1 PF0.1 PF
Input
Voltage
0.01 PF
VOUT = 0V to 5V
DAC084S085
DIN
SCLK
SYNC
VA VREFIN
0.1 PF
LM4050-4.1
or
LM4050-5.0 VOUT = 0V to 5V
0.47 PF
Input
Voltage
RVZ
DAC084S085
DIN
SCLK
SYNC
VA VREFIN
0.1 PF
IZ
IDAC
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Using References as Power Supplies (continued)
10.1.2 LM4050
Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a reference for the
DAC084S085. It is available in 4.096-V and 5-V versions, and comes in a space-saving 3-pin SOT-23.
Figure 39. LM4050 as a Power Supply
The minimum resistor value in the circuit of Figure 39 must be chosen such that the maximum current through
the LM4050 does not exceed its 15-mA rating. The conditions for maximum current include the input voltage at
its maximum, the LM4050 voltage at its minimum, and the DAC084S085 drawing zero current. The maximum
resistor value must allow the LM4050 to draw more than its minimum current for regulation plus the maximum
DAC084S085 current in full operation. The conditions for minimum current include the input voltage at its
minimum, the LM4050 voltage at its maximum, the resistor value at its maximum due to tolerance, and the
DAC084S085 draws its maximum current. These conditions can be summarized as:
R(min) = ( VIN(max) −VZ(min) ) /IZ(max) (4)
and R(max) = ( VIN(min) −VZ(max) ) / ( (IDAC(max) + IZ(min) )
where
• VZ(min) and VZ(max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over
temperature,
• IZ(max) is the maximum allowable current through the LM4050,
• IZ(min) is the minimum current required by the LM4050 for proper regulation,
• and IDAC(max) is the maximum DAC084S085 supply current. (5)
10.1.3 LP3985
The LP3985 is a low-noise, ultra-low dropout voltage regulator with a 3% accuracy over temperature. It is a good
choice for applications that do not require a precision reference for the DAC084S085. It comes in 3-V, 3.3-V, and
5-V versions, among others, and sports a low 30-µV noise specification at low frequencies. Because low
frequency noise is relatively difficult to filter, this specification could be important for some applications. The
LP3985 comes in a space-saving 5-pin SOT-23 and 5-bump DSBGA packages.
Figure 40. Using the LP3985 Regulator
LP2980
1 PF
Input
Voltage
ON /OFF
VIN VOUT
VOUT = 0V to 5V
DAC084S085
DIN
SCLK
SYNC
VA VREFIN
0.1 PF
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Using References as Power Supplies (continued)
An input capacitance of 1 µF without any ESR requirement is required at the LP3985 input, while a 1-µF ceramic
capacitor with an ESR requirement of 5 mΩto 500 mΩis required at the output. Careful interpretation and
understanding of the capacitor specification is required to ensure correct device operation.
10.1.4 LP2980
The LP2980 is an ultra-low dropout regulator with a 0.5% or 1% accuracy over temperature, depending upon
grade. It is available in 3-V, 3.3-V, and 5-V versions, among others.
Figure 41. Using the LP2980 Regulator
Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor
must be at least 1 µF over temperature, but values of 2.2 µF or more provides even better performance. The
ESR of this capacitor must be within the range specified in the LP2980 data sheet. Surface-mount solid tantalum
capacitors offer a good combination of small size and ESR. Ceramic capacitors are attractive due to their small
size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic capacitors
are typically not a good choice due to their large size and have ESR values that may be too high at low
temperatures.
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11 Layout
11.1 Layout Guidelines
For best accuracy and minimum noise, the printed-circuit board containing the DAC084S085 must have separate
analog and digital areas. The areas are defined by the locations of the analog and digital power planes. Both of
these planes must be located in the same board layer. There must be a single ground plane. A single ground
plane is preferred if digital return current does not flow through the analog ground area. Frequently a single
ground plane design uses a fencing technique to prevent the mixing of analog and digital ground current.
Separate ground planes must only be used when the fencing technique is inadequate. The separate ground
planes must be connected in one place, preferably near the DAC084S085. Special care is required to ensure
that digital signals with fast edge rates do not pass over split ground planes. They must always have a
continuous return path below their traces.
The DAC084S085 power supply must be bypassed with a 10-µF and a 0.1-µF capacitor as close as possible to
the device with the 0.1 µF right at the device supply pin. The 10-µF capacitor must be a tantalum type and the
0.1-µF capacitor must be a low ESL, low ESR type. The power supply for the DAC084S085 must only be used
for analog circuits.
Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the
board. The clock and data lines must have controlled impedances.
11.2 Layout Example
Figure 42. Typical Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
12.1.1.1 Specification Definitions
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of
1 LSB, which is VREF / 256 = VA/ 256.
DAC-to-DAC CROSSTALK is the glitch impulse transferred to a DAC output in response to a full-scale change
in the output of another DAC.
DIGITAL CROSSTALK is the glitch impulse transferred to a DAC output at mid-scale in response to a full-scale
change in the input register of another DAC.
DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital
inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data bus.
FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFh) loaded
into the DAC and the value of VAx 255 / 256.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and
Full-Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error.
GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register
changes. It is specified as the area of the glitch in nanovolt-seconds.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line
through the input to output transfer function. The deviation of any given code from this straight line is measured
from the center of that code value. The end point method is used. INL for this product is specified over a limited
range, per Electrical Characteristics.
LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is
LSB = VREF / 2n
where
• VREF is the supply voltage for this product,
• and "n" is the DAC resolution in bits, which is 8 for the DAC084S085. (6)
MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output
stability maintained.
MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when
the input code increases.
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is
1/2 of VA.
MULTIPLYING BANDWIDTH is the frequency at which the output amplitude falls 3dB below the input sine wave
on VREFIN with a full-scale code loaded into the DAC.
POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from
the power supply. The difference between the supply and output currents is the power consumed by the device
without a load.
SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is
updated.
TOTAL HARMONIC DISTORTION (THD) is the measure of the harmonics present at the output of the DACs
with an ideal sine wave applied to VREFIN. THD is measured in dB.
WAKE-UP TIME is the time for the output to exit power-down mode. This is the time from the falling edge of the
16th SCLK pulse to when the output voltage deviates from the power-down voltage of 0 V.
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Device Support (continued)
ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 00h has been
entered.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
SPI is a trademark of Motorola, Inc..
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DAC084S085CIMM NRND VSSOP DGS 10 1000 Non-RoHS
& Green Call TI Call TI -40 to 105 X70C
DAC084S085CIMM/NOPB ACTIVE VSSOP DGS 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 X70C
DAC084S085CIMMX/NOPB ACTIVE VSSOP DGS 10 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 X70C
DAC084S085CISD/NOPB ACTIVE WSON DSC 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 X71C
DAC084S085CISDX/NOPB ACTIVE WSON DSC 10 4500 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 X71C
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC084S085CIMM VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
DAC084S085CIMM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
DAC084S085CIMMX/NOP
BVSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
DAC084S085CISD/NOPB WSON DSC 10 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
DAC084S085CISDX/NOP
BWSON DSC 10 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC084S085CIMM VSSOP DGS 10 1000 210.0 185.0 35.0
DAC084S085CIMM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0
DAC084S085CIMMX/NOP
BVSSOP DGS 10 3500 367.0 367.0 35.0
DAC084S085CISD/NOPB WSON DSC 10 1000 210.0 185.0 35.0
DAC084S085CISDX/NOP
BWSON DSC 10 4500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP
5.05
4.75
1.1 MAX
8X 0.5
10X 0.27
0.17
2X
2
0.15
0.05
TYP
0.23
0.13
0 - 8
0.25
GAGE PLANE
0.7
0.4
A
NOTE 3
3.1
2.9
B
NOTE 4
3.1
2.9
4221984/A 05/2015
VSSOP - 1.1 mm max heightDGS0010A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
110
0.1 C A B
6
5
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 3.200
www.ti.com
EXAMPLE BOARD LAYOUT
(4.4)
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
10X (1.45)
10X (0.3)
8X (0.5)
(R )
TYP
0.05
4221984/A 05/2015
VSSOP - 1.1 mm max heightDGS0010A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:10X
1
56
10
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(4.4)
8X (0.5)
10X (0.3)
10X (1.45)
(R ) TYP0.05
4221984/A 05/2015
VSSOP - 1.1 mm max heightDGS0010A
SMALL OUTLINE PACKAGE
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
56
10
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
MECHANICAL DATA
DSC0010A
www.ti.com
SDA10A (Rev A)
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