FQB12P20 / FQI12P20 May 2000 QFET TM FQB12P20 / FQI12P20 200V P-Channel MOSFET General Description Features These P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switching DC/DC converters. * * * * * * -11.5A, -200V, RDS(on) = 0.47 @VGS = -10 V Low gate charge ( typical 31 nC) Low Crss ( typical 30 pF) Fast switching 100% avalanche tested Improved dv/dt capability S D ! G! G S D2-PAK G D S FQB Series I2-PAK FQI Series ! D Absolute Maximum Ratings Symbol VDSS ID TC = 25C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25C) Drain Current FQB12P20 / FQI12P20 -200 Units V -11.5 A -7.27 A - Continuous (TC = 100C) IDM Drain Current VGSS Gate-Source Voltage EAS Single Pulsed Avalanche Energy IAR Avalanche Current EAR Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TA = 25C) * dv/dt PD TJ, TSTG TL - Pulsed -46 A 30 V (Note 2) 810 mJ (Note 1) -11.5 A (Note 1) 12 -5.5 3.13 mJ V/ns W 120 0.96 -55 to +150 W W/C C 300 C (Note 1) (Note 3) Power Dissipation (TC = 25C) - Derate above 25C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds Thermal Characteristics Symbol RJC Parameter Thermal Resistance, Junction-to-Case Typ -- Max 1.04 Units C/W RJA Thermal Resistance, Junction-to-Ambient * -- 40 C/W RJA Thermal Resistance, Junction-to-Ambient -- 62.5 C/W * When mounted on the minimum pad size recommended (PCB Mount) (c)2000 Fairchild Semiconductor International Rev. A, May 2000 Symbol TC = 25C unless otherwise noted Parameter Test Conditions Min Typ Max Units -200 -- -- V -- - -- V/C Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 A BVDSS / TJ Breakdown Voltage Temperature Coefficient ID = -250 A, Referenced to 25C IDSS IGSSF IGSSR VDS = -200 V, VGS = 0 V -- -- -1 A VDS = -160 V, TC = 125C -- -- -10 A Gate-Body Leakage Current, Forward VGS = -30 V, VDS = 0 V -- -- -100 nA Gate-Body Leakage Current, Reverse VGS = 30 V, VDS = 0 V -- -- 100 nA Zero Gate Voltage Drain Current On Characteristics VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 A -3.0 -- -5.0 V RDS(on) Static Drain-Source On-Resistance VGS = -10 V, ID = -5.75 A -- 0.36 0.47 gFS Forward Transconductance VDS = -40 V, ID = -5.75 A -- 6.4 -- S -- 920 1200 pF -- 190 250 pF -- 30 40 pF ns (Note 4) Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance VDS = -25 V, VGS = 0 V, f = 1.0 MHz Switching Characteristics td(on) Turn-On Delay Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = -100 V, ID = -11.5 A, RG = 25 (Note 4, 5) VDS = -160 V, ID = -11.5 A, VGS = -10 V (Note 4, 5) -- 20 50 -- 195 400 ns -- 40 90 ns -- 60 130 ns -- 31 40 nC -- 8.1 -- nC -- 16 -- nC A Drain-Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain-Source Diode Forward Current -- -- -11.5 ISM -- -- -46 A VSD Maximum Pulsed Drain-Source Diode Forward Current VGS = 0 V, IS = -11.5 A Drain-Source Diode Forward Voltage -- -- -5.0 V trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = -11.5 A, dIF / dt = 100 A/s (Note 4) -- 180 -- ns -- 1.44 -- C Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 9.2mH, IAS = -11.5A, VDD = -50V, RG = 25 , Starting TJ = 25C 3. ISD -11.5A, di/dt 300A/s, VDD BVDSS, Starting TJ = 25C 4. Pulse Test : Pulse width 300s, Duty cycle 2% 5. Essentially independent of operating temperature (c)2000 Fairchild Semiconductor International Rev. A, May 2000 FQB12P20 / FQI12P20 Elerical Characteristics VGS -15.0 V -10.0 V -8.0 V -7.0 V -6.5 V -6.0 V Bottom : -5.5 V Top : -I D, Drain Current [A] 1 10 -I D , Drain Current [A] 1 10 0 10 Notes : 1. 250s Pulse Test 2. TC = 25 150 0 10 25 Notes : 1. VDS = -40V 2. 250s Pulse Test -55 -1 -1 10 -1 0 10 10 1 10 2 10 4 6 8 10 -VGS , Gate-Source Voltage [V] -VDS, Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 1.5 1 10 -I DR , Reverse Drain Current [A] RDS(on) [ ], Drain-Source On-Resistance 2.0 VGS = - 10V VGS = - 20V 1.0 0.5 Note : TJ = 25 0 10 150 Notes : 1. VGS = 0V 2. 250s Pulse Test 25 -1 0.0 0 10 20 30 40 10 0.0 0.5 -ID , Drain Current [A] 1.0 1.5 2.0 2.5 3.0 -VSD , Source-Drain Voltage [V] Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature 12 2400 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd 1600 Notes : 1. VGS = 0 V 2. f = 1 MHz Ciss Coss 1200 800 Crss 400 0 -1 10 VDS = -40V 10 -V GS , Gate-Source Voltage [V] 2000 Capacitance [pF] FQB12P20 / FQI12P20 Typical Characteristics VDS = -100V VDS = -160V 8 6 4 2 Note : ID = -11.5 A 0 0 10 1 10 -VDS, Drain-Source Voltage [V] Figure 5. Capacitance Characteristics (c)2000 Fairchild Semiconductor International 0 5 10 15 20 25 30 35 QG, Total Gate Charge [nC] Figure 6. Gate Charge Characteristics Rev. A, May 2000 (Continued) 2.5 1.2 2.0 1.1 RDS(ON) , (Normalized) Drain-Source On-Resistance -BV DSS , (Normalized) Drain-Source Breakdown Voltage FQB12P20 / FQI12P20 Typical Characteristics 1.0 Notes : 1. VGS = 0 V 2. ID = -250 A 0.9 0.8 -100 -50 0 50 100 150 1.5 1.0 Notes : 1. VGS = -10 V 2. ID = -5.75 A 0.5 0.0 -100 200 -50 0 o 50 100 150 200 o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 12 Operation in This Area is Limited by R DS(on) 2 10 10 1 ms -I D, Drain Current [A] -I D, Drain Current [A] 100 s 1 10 10 ms DC 0 10 Notes : o 1. TC = 25 C 8 6 4 2 o 2. TJ = 150 C 3. Single Pulse -1 10 0 1 10 0 25 2 10 10 50 100 125 150 Figure 10. Maximum Drain Current vs. Case Temperature 0 D = 0 .5 N o te s : 1 . Z J C ( t ) = 1 . 0 4 /W M a x . 2 . D u ty F a c t o r , D = t 1 /t 2 3 . T J M - T C = P D M * Z J C( t ) 0 .2 10 0 .1 -1 0 .0 5 PDM 0 .0 2 0 .0 1 JC ( t) , T h e r m a l R e s p o n s e Figure 9. Maximum Safe Operating Area 10 75 TC, Case Temperature [] -VDS, Drain-Source Voltage [V] t1 Z s in g le p u ls e 10 t2 -2 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ] Figure 11. Transient Thermal Response Curve (c)2000 Fairchild Semiconductor International Rev. A, May 2000 FQB12P20 / FQI12P20 Gate Charge Test Circuit & Waveform VGS Same Type as DUT 50K Qg 200nF 12V -10V 300nF VDS VGS Qgs Qgd DUT -3mA Charge Resistive Switching Test Circuit & Waveforms VDS RL t on VDD VGS RG td(on) VGS t off tr td(off) tf 10% DUT -10V VDS 90% Unclamped Inductive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L VDS tp ID RG VDD DUT -10V tp (c)2000 Fairchild Semiconductor International VDD Time VDS (t) ID (t) IAS BVDSS Rev. A, May 2000 FQB12P20 / FQI12P20 Peak Diode Recovery dv/dt Test Circuit & Waveforms + VDS DUT _ I SD L Driver RG VGS VGS ( Driver ) I SD ( DUT ) Compliment of DUT (N-Channel) VDD * dv/dt controlled by RG * ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V Body Diode Reverse Current IRM di/dt IFM , Body Diode Forward Current VDS ( DUT ) VSD Body Diode Forward Voltage Drop VDD Body Diode Recovery dv/dt (c)2000 Fairchild Semiconductor International Rev. A, May 2000 4.50 0.20 9.90 0.20 +0.10 2.00 0.10 2.54 TYP (0.75) ~3 0 0.80 0.10 1.27 0.10 2.54 0.30 15.30 0.30 0.10 0.15 2.40 0.20 4.90 0.20 9.20 0.20 1.30 -0.05 1.20 0.20 (0.40) D2PAK 1.40 0.20 +0.10 0.50 -0.05 2.54 TYP 4.90 0.20 (2XR0.45) 9.20 0.20 10.00 0.20 (7.20) (1.75) 10.00 0.20 (8.00) (4.40) 15.30 0.30 FQB12P20 / FQI12P20 Package Dimensions 0.80 0.10 (c)2000 Fairchild Semiconductor International Rev. A, May 2000 FQB12P20 / FQI12P20 Package Dimensions (Continued) I2PAK 4.50 0.20 (0.40) 9.90 0.20 +0.10 MAX13.40 9.20 0.20 (1.46) 1.20 0.20 1.30 -0.05 0.80 0.10 2.54 TYP 2.54 TYP 10.08 0.20 1.47 0.10 MAX 3.00 (0.94) 13.08 0.20 ) 5 (4 1.27 0.10 +0.10 0.50 -0.05 2.40 0.20 10.00 0.20 (c)2000 Fairchild Semiconductor International Rev. A, May 2000 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM E2CMOSTM FACTTM FACT Quiet SeriesTM FAST(R) FASTrTM GTOTM HiSeCTM ISOPLANARTM MICROWIRETM POPTM PowerTrench(R) QFETTM QSTM Quiet SeriesTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM UHCTM VCXTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. (c)2000 Fairchild Semiconductor International Rev. A, January 2000 Product Folder - Fairchild P/N FQB12P20 - 200V P-Channel QFET Page 1 of 2 Careers | Sitema Go DATASHEETS, SAMPLES, BUY TECHNICAL INFORMATION APPLICATIONS DESIGN CENTER SUPPORT COMPANY INVESTORS MY FA Home >> Find products >> Related Links FQB12P20 200V P-Channel QFET Request samples Contents *General description *Features *Product status/pricing/packaging *Order Samples How to order products *Qualification Support Product Change Notices (PCNs) Datasheet Download this datasheet Support Sales support General description These P-Channel enhancement mode power field effect transistors are e-mail this datasheet produced using Fairchild's proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are This page well suited for low voltage applications such as high efficiency switching Print version DC/DC converters, and DC motor control. Quality and reliability Design center back to top Features z z z z z z -11.5A, -200V, RDS(on)= 0.47 @VGS= -10V Low gate charge ( typical 31 nC) Low Crss (typical 30 pF) Fast switching 100% avalanche tested Improved dv/dt capability back to top Product status/pricing/packaging Product Product status Pb-free Status Pricing* Package type Leads Packing method Package Marking Convention** Line 1: $Y (Fairchild logo) mhtml:file://C:\TEMP\FQB12P20TM_SB82075.mht 17-Aug-2007 Product Folder - Fairchild P/N FQB12P20 - 200V P-Channel QFET FQB12P20TM FQB12P20TM_SB82075 Full Production Full Production $1.26 TO-263(D2PAK) N/A TO-263(D2PAK) Page 2 of 2 2 2 TAPE REEL TAPE REEL &Z (Asm. Plant Code) &4 (4-Digit Date Code) Line 2: FQB Line 3: 12P20 Line 1: $Y (Fairchild logo) &Z (Asm. Plant Code) &4 (4-Digit Date Code) Line 2: FQB Line 3: 12P20 * Fairchild 1,000 piece Budgetary Pricing ** A sample button will appear if the part is available through Fairchild's on-line samples program. If there is no sample button, please contact a Fairchild distributor to obtain samples Indicates product with Pb-free second-level interconnect. For more information click here. Package marking information for product FQB12P20 is available. Click here for more information . back to top Qualification Support Click on a product for detailed qualification data Product FQB12P20TM FQB12P20TM_SB82075 back to top (c) 2007 Fairchild Semiconductor Products | Design Center | Support | Company News | Investors | My Fairchild | Contact Us | Site Index | Privacy Policy | Site Terms & Conditions | Standard Terms & Conditions o mhtml:file://C:\TEMP\FQB12P20TM_SB82075.mht 17-Aug-2007