www.fairchildsemi.com AN-6860 Low-Cost, Green-Mode PWM Controller for Flyback Converters Description This highly integrated PWM controller provides several special enhancements designed to meet the low standbypower needs of low-power SMPS. To minimize standby power consumption, the proprietary green-mode function provides off-time modulation to linearly decrease the switching frequency under light-load conditions. This green-mode function enables the power supply to meet strict power conservation requirements. The BiCMOS fabrication process enables reducing the startup current to 9A and the operating current to 3mA. To further improve power conservation, a large start-up resistance can be used. Built-in synchronized slope compensation ensures the stability of peak current mode control. Proprietary internal compensation provides a constant output power limit over a universal line input range (90VAC to 264VAC). Pulse-by-pulse current limiting ensures safe operation even during short-circuit conditions. To protect the external power MOSFET from being damaged by excessive supply voltage, the output driver is clamped at 17V. SG6860 controllers can be used to improve the performance and reduce the production cost of power supplies. The SG6860 can replace linear and RCCmode power adapters and is available in 8-pin DIP and 6-pin SOT-26 packages. Start-up Circuitry When the power is turned on, the input rectified voltage, VDC, charges the hold-up capacitor C1 via a start-up resistor RIN. As the voltage of VDD pin reaches the start threshold voltage, VDD-ON; SG6860 activates the entire power supply. Figure 1. Flyback Converter Circuit (c) 2008 Fairchild Semiconductor Corporation Rev. 1.0.0 * 2/22/08 www.fairchildsemi.com AN-6860 APPLICATION NOTE VDD-ON VDD-ON VDC R IN t D_ON VDD VD IDD SG6860 -ST D1 C1 Figure 3. Feedback Circuit GND GN Oscillator & Green-Mode Operation Figure 2. Circuit Providing Power to SG6860 One external resistor, RI, connected between the RI and GND pins, is used to program the PWM frequency of the SG6860. The approximated formula is: The maximum power-on delay time is determined as: VDD -ON = (Vdc - IDD - ST R IN )(1 - e - tD_ON RIN C1 ) (1) fOSC (KHz ) = where 6650 RI (K) (3) The recommended fOSC is from 50 to 80KHz. IDD-ST is the start-up current of SG6860; VDD-ON is the power-on delay time of the power supply. Due to the low start-up current, a large RIN, such as 1.5, can be used. With a hold-up capacitor of 10F/50V, the power-on delay tD_ON is less than 2.8s for 90VAC input. FB Input The FB pin is designed for feedback control and to activate the green-mode function. Figure 3 is a typical feedback circuit, mainly consisting of a shunt regulator and an photocoupler. R1 and R2 form a voltage divider for the output voltage regulation. R3 and C1 are adjusted for control-loop compensation. A small-value RC filter (e.g. RFB= 47, CFB= 1nF) placed from the FB pin to GND can increase stability. The maximum source current on the FB pin is 1.5mA. The phototransistor must be capable of sinking this current to pull the FB level down at no load. Thus, the value of the biasing resistor Rb is determined as follows: Vo - VD - VZ K 1.5mA Rb Figure 4. Setting PWM Frequency The patented green-mode function provides off-time modulation to reduce the PWM frequency at light-load and no-load conditions. The feedback voltage of the FB pin is taken as a reference. When the feedback voltage is lower than ~2.85V, the PWM frequency decreases. Because most losses in a switching-mode power supply are proportional to the PWM frequency, the off-time modulation reduces the power consumption of the power supply at light-load and no-load conditions. For a typical case of RI = 95K, the PWM frequency is 70KHz at nominal load, and decreases to 20KHz at light load, about two-fifths (2/5) of the nominal PWM frequency. The power supply enters "Adaptive off-time modulation" in zero-load conditions. (2) where VD is the drop voltage of a photodiode, about 1.2V; VZ is the minimum operating voltage of the shunt regulator (typical value = 2.5V); K is the current transfer rate (CTR) of the photo-coupler. For an output voltage Vo=5V with CTR=100%, the maximum value of Rb is 860ohm. (c) 2008 Fairchild Semiconductor Corporation Rev. 1.0.0 * 2/22/08 www.fairchildsemi.com 2 AN-6860 APPLICATION NOTE 50%. Adding slope compensation (reducing the currentloop gain) is an effective way to prevent this oscillation. The SG6860 introduces a synchronized positive-going ramp (VSLOPE) in every switching cycle to stabilize the current loop. The sensed voltage, together with this slope compensation signal (VSLOPE), is fed into the non-inverting input of the PWM comparator. The resulting voltage is compared with the FB signal to adjust the PWM duty cycle, such that the output voltage is regulated. The SG6860 helps design cost-effective, highly efficient, and compact-sized flyback power supplies operating in CCM without adding external components. Figure 5. PWM Frequency vs. FB Voltage (RI=95K) A frequency-hopping function is built-in to improve the system level of EMI performance. The PWM switching frequency hops between 70KHz +/-4.9KHz. The hopping period is around 4.4ms. The positive ramp added is: VSLOPE = VSL * D (4) where VSL = 0.33V; D = Duty cycle. Built-in Slope Compensation Constant Output Power Limit A flyback converter can be operated in either discontinuous current mode (DCM) or continuous current mode (CCM). There are many advantages to operating the converter in CCM. With the same output power, a converter in CCM exhibits smaller peak inductor currents than in DCM, allowing a small-sized transformer and a low-rated MOSFET to be applied. On the secondary side of the transformer, the RMS output current of DCM can be up to twice that of CCM. Larger wire gauge and output capacitors with larger ripple current ratings are required. DCM operation also results in higher output voltage spikes. A large LC filter must also be added. Therefore, a flyback converter in CCM achieves better performance with lower component cost. The maximum output power of a flyback converter can generally be determined from the current-sense resistor RS. When the load increases, the peak inductor current increases accordingly. Once the output current arrives at the protection value, the OCP comparator dominates the current control loop. OCP occurs when the current-sense voltage reaches the threshold value. The output GATE driver is turned off after a small propagation delay, tPD. The delay time results in unequal power-limit level under universal input. In the SG6860, a sawtooth power-limiter (saw limiter) is designed to solve the unequal power-limit problem. As shown in Figure 7, the saw limiter is designed as a positive ramp (Vlimit_ramp) signal and is fed to the inverting input of the OCP comparator. This results in a lower current limit at high-line inputs than at low-line inputs. However, with fixed propagation delay, tPD, the peak primary current would be the same for various line input voltages. Therefore, the maximum output power can practically be limited to a constant value within a wide input voltage range without adding external circuitry. SG6860 Figure 6. Synchronized Slope Compensation Despite the advantages of operating in CCM, there is one concern - stability. Operating in CCM, the output power is proportional to the average inductor current, while the peak current is controlled. This causes a well-known subharmonic oscillation when the PWM duty cycle exceeds (c) 2008 Fairchild Semiconductor Corporation Rev. 1.0.0 * 2/22/08 Figure 7. Constant Power Limit Compensation www.fairchildsemi.com 3 AN-6860 APPLICATION NOTE VDD Over-voltage Protection VDD over-voltage protection is built-in to prevent the controller from over-voltage damage. The voltage on VDD rises when an open-loop failure occurs. Once the VDD voltage exceeds 24.5V for ~120s, the power supply is latched off. Short-Circuit Protection When the output of a flyback power supply is shorted, the primary VDD decreases due to the coupling polarity between the aux winding and the secondary winding of a transformer. When VDD drops below UVLO level of the SG6860, the power supply enters "hiccup" operation mode and limits the output power. However, it is possible that the VDD voltage remains higher than the UVLO level even if the output is shorted. This happens when the coupling between the aux and the primary winding is too good. Therefore, the construction of the transformer becomes a dominant factor. The recommended construction layout is to increase the insulation thickness for the aux winding and place the primary aux winding in one side of the bobbin. For lowoutput voltage applications, using a low-dropout voltage diode and a larger secondary winding improves protection. Figure 9. Turn-on Spike Open-Loop Protection When an open-loop failure occurs, the voltage on the FB pin rises rapidly, owing to the internal pull-high circuitry. Once the FB voltage level goes beyond 4.7V for ~54ms, the SG6860 stops PWM output pulses. As the PWM output is turned off, VDD begins decreasing. After VDD goes below the turn-off threshold (e.g. 9.5V), the SG6860 is totally shut down and FB voltage drops to zero. Then VDD is charged up to the start-up threshold voltage of 16.5V through the startup resistor until PWM output is restarted. This "hiccup" mode protection occurs repeatedly as long as the opencircuit failure persists. Gate Drive The output stage is a fast totem-pole driver that can drive a MOSFET gate directly. It is also equipped with a voltageclamping Zener diode to protect the MOSFET from damage caused by undesirable over-drive voltage. The output voltage is clamped at 17V. An internal pull-down resistor is used to avoid a floating state of the gate before startup. A gate drive resistor of 47--100 is recommended, which limits the peak gate drive current and provides damping to prevent oscillations at the MOSFET gate terminal. Figure 8. Transformer Construction Leading-Edge Blanking A voltage signal proportional to the MOSFET current develops on the current-sensing resistor, RS. Each time the MOSFET is turned on, a spike is induced by the diode reverse recovery and by the output capacitances of the MOSFET and diode, appears on the sensed signal. A leading-edge blanking time of ~300ns is introduced to avoid premature termination of the MOSFET by the spike. Therefore, only a small-value RC filter (100 + 470pF) is required between the SENSE pin and RS. Still, a noninductive resistor for the RS is recommended. SG6860 VDD 17V Gate ON/OFF Driver Figure 10. (c) 2008 Fairchild Semiconductor Corporation Rev. 1.0.0 * 2/22/08 Gate Driver www.fairchildsemi.com 4 AN-6860 APPLICATION NOTE Lab Note This device is sensitive to ESD discharge. To improve the production yield, the production line should be ESD protected in accordance to ANSI ESD S1.1, ESD S1.4, ESD S7.1, ESD STM 12.1, and EOS/ESD S6.1. Before reworking or soldering/de-soldering on the power supply, it is suggested to discharge the primary capacitors by an external bleeding resistor: Otherwise, the PWM IC may be destroyed by external high-voltage during soldering or de-soldering. Printed Circuit Board (PCB) Layout High-frequency switching current / voltage make PCB layout a very important design issue. Good PCB layout minimizes excessive EMI and helps the power supply survive during surge / ESD tests. Two suggestions for ground connections, with different pro and cons, are offered: Guidelines: GND3214: This should be better for ESD tests, where the earth ground is not available on the power supply. Regarding the ESD discharge path, the charges go from secondary through the transformer's stray capacitance to GND2 first. Then the charges go from GND2 to GND1 and back to the mains. It should be noted that control circuits should not be placed in the discharge path. Point discharges for common choke can decrease the high-frequency impedance and help increase ESD immunity. GND3241: This should avoid common impedance interference for the sense signal. To get better EMI performance and reduce line frequency ripples, the output of the bridge rectifier should be connected to capacitor C1, then to the switching circuits. The high frequency current loop is in C1 - Transformer - MOSFET - RS - C1. The area enclosed by this current loop should be as small as possible. Keep the traces (especially 41) short, direct, and wide. High-voltage traces related to the drain of the MOSFET and the RCD snubber should be kept far way from control circuits to prevent unnecessary interference. If a heat sink is used for the MOSFET, connect this heat sink to ground. Should a Y-cap between primary and secondary be required, connect this Y-cap to the positive terminal of C1 (VDC). If this Y-cap is connected to primary GND, it should be connected to the negative terminal of C1 (GND1) directly. The point discharge of this Y-cap also helps with ESD; however, the distance between these two points should be at least 5mm according to safety requirements. As indicated by line 3 in Figure 11, the ground of control circuits should be connected first before any other circuitry. As indicated by line 2 in Figure 11, the area enclosed by the transformer aux winding, D1, and C2 should also be kept small. Place C2 close to the SG6860 for good decoupling. R IN VDC D1 C1 Common mode C2 1 choke VDD 2 Rg RI RI SG6860 SG6848 Gate Rf Sense FB Cf RFB CFB RS GND 4 3 Y-cap 5 Figure 11. (c) 2008 Fairchild Semiconductor Corporation Rev. 1.0.0 * 2/22/08 Layout Considerations www.fairchildsemi.com 5 AN-6860 APPLICATION NOTE DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. 2. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. (c) 2008 Fairchild Semiconductor Corporation Rev. 1.0.0 * 2/22/08 www.fairchildsemi.com 6