PIC16(L)F1526/27 Data Sheet 64-Pin Flash Microcontrollers with nanoWatt XLP Technology 2011 Microchip Technology Inc. Preliminary DS41458B Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-133-9 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS41458B-page 2 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 64-Pin Flash Microcontrollers with nanoWatt Technology High-Performance RISC CPU: Extreme Low-Power Management PIC16LF1526/27 with nanoWatt XLP: * C Compiler Optimized Architecture * Only 49 Instructions * Up to 28 Kbytes Linear Program Memory Addressing * Up to 1536 Bytes Linear Data Memory Addressing * Operating Speed: - DC - 20 MHz clock input @ 2.5V - DC - 16 MHz clock input @ 1.8V - DC - 200 ns instruction cycle * Interrupt Capability with Automatic Context Saving * 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset * Direct, Indirect and Relative Addressing modes: - Two full 16-bit File Select Registers (FSRs) - FSRs can read program and data memory * Sleep mode: 20 nA @ 1.8V, typical * Watchdog Timer: 300 nA @ 1.8V, typical * Secondary Oscillator: 600 nA @ 32 kHz, 1.8V, typical Analog Features: * Analog-to-Digital Converter (ADC): - 10-bit resolution - 30 external channels - Two internal channels - Fixed Voltage Reference (FVR) channel - Temperature Indicator channel - Auto acquisition capability - Conversion available during Sleep - Dedicated ADC RC oscillator - Fixed Voltage Reference (FVR) as ADC positive reference * Voltage Reference module: - Fixed Voltage Reference (FVR) with 1.024V, 2.048V and 4.096V output levels - Low-Power Sleep mode - Low-Power BOR (LPBOR) Flexible Oscillator Structure: * 16 MHz Internal Oscillator Block: - Software selectable frequency range from 16 MHz to 31 kHz * 31 kHz Low-Power Internal Oscillator * External Oscillator Block with: - Four crystal/resonator modes up to 20 MHz - Three external clock modes up to 20 MHz * Fail-Safe Clock Monitor - Allows for safe shutdown if peripheral clock stops * Two-Speed Oscillator Start-up * Oscillator Start-up Timer (OST) Peripheral Features: Special Microcontroller Features: * Operating Voltage Range: - 1.8V to 3.6V (PIC16LF1526/27) - 2.3V to 5.5V (PIC16F1526/27) * Self-Programmable under Software Control * Power-on Reset (POR) * Power-up Timer (PWRT) * Programmable Low-Power Brown-Out Reset (LPBOR) * Extended Watch-Dog Timer (WDT): - Programmable period from 1ms to 256s * Programmable Code Protection * In-Circuit Serial ProgrammingTM (ICSPTM) via two pins * In-Circuit Debug (ICD) via Two Pins * Enhanced Low-Voltage Programming (LVP) * Power-Saving Sleep mode 2011 Microchip Technology Inc. * 53 I/O Pins and 1 Input-only Pin: - High current sink/source 25 mA/25 mA - Individually programmable weak pull-ups - Individually programmable interrupt-on-change (IOC) pins * Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler * Enhanced Timer1, 3, 5: - 16-bit timer/counter with prescaler - External Gate Input mode - Low-power 32 kHz secondary oscillator driver * Timer2, 4, 6, 8, 10: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler * Ten Capture/Compare/PWM (CCP) modules: - 16-bit Capture, 200 ns (max. resolution) - 16-bit Compare, 200 ns (max. resolution) - 10-bit PWM, 20 kHz @ 10 bits (max. frequency) * Two Master Synchronous Serial Ports (MSSPs) with SPI and I2 CTM with: - 7-bit address masking - SMBus/PMBusTM compatibility - Auto-wake-up on start * Two Enhanced Universal Synchronous Asynchronous Receiver Transmitters (EUSART): - RS-232, RS-485 and LIN compatible - Auto-Baud Detect Preliminary DS41458B-page 3 PIC16(L)F1526/27 TABLE 1: PIC16(L)F1526/27 FAMILY TYPES Device PIC16F1526 PIC16LF1526 PIC16F1527 PIC16LF1527 FIGURE 1: Program Memory Flash (words) SRAM (bytes) I/Os 10-bit A/D (ch) Timers 8/16-bit EUSART MSSP (I2CTM/SPI) CCP 8192 768 54 30 6/3 2 2 10 16384 1536 54 30 6/3 2 2 10 64-PIN TQFP (10MM X 10MM) PACKAGE DIAGRAM FOR PIC16(L)F1526/27 RD0 VDD VSS RD1 RD2 RD3 RD4 RD5 RD6 RD7 RE2 RE3 RE4 RE5 RE6 RE7 TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1 RE0 RG0 RG1 RG2 RG3 VPP/MCLR/RG5 RG4 VSS VDD RF7 RF6 RF5 RF4 RF3 RF2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC16(L)F1526 PIC16(L)F1527 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RB0 RB1 RB2 RB3 RB4 RB5 RB6 VSS RA6 RA7 VDD RB7 RC5 RC4 RC3 RC2 RF1 RF0 AVDD AVSS RA3 RA2 RA1 RA0 VSS VDD RA5 RA4 RC1 RC0 RC6 RC7 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Note 1: DS41458B-page 4 See TABLE 1-2: "PIC16(L)F1526 Pinout Description" for list of pin peripheral function. Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 2: 64-PIN QFN (9MM X 9MM) PACKAGE DIAGRAM FOR PIC16(L)F1526/27 RD0 VDD VSS RD1 RD2 RD3 RD4 RD5 RD6 RD7 RE2 RE3 RE4 RE5 RE6 RE7 QFN 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1 RE0 RG0 RG1 RG2 RG3 VPP/MCLR/RG5 RG4 VSS VDD RF7 RF6 RF5 RF4 RF3 RF2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC16(L)F1526 PIC16(L)F1527 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RB0 RB1 RB2 RB3 RB4 RB5 RB6 VSS RA6 RA7 VDD RB7 RC5 RC4 RC3 RC2 RF1 RF0 AVDD AVSS RA3 RA2 RA1 RA0 VSS VDD RA5 RA4 RC1 RC0 RC6 RC7 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Note 1: See TABLE 1-2: "PIC16(L)F1526 Pinout Description" for list of pin peripheral function. 2011 Microchip Technology Inc. Preliminary DS41458B-page 5 PIC16(L)F1526/27 47 46 45 44 43 42 37 30 29 33 34 35 36 31 32 58 55 54 53 52 51 50 AN18 AN19 AN20 AN21 AN22 -- -- -- -- -- -- -- -- -- -- AN23 AN24 AN25 AN26 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TX1/CK1 RX1/DT1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SCK1/SCL1 SDI1/SDA1 SDO1 -- -- -- -- -- -- SDO2 SDI2, SDA2 SCK2, SCL2 -- -- -- -- -- -- T3CKI(2) -- T1G/T3CKI(1) -- -- -- -- -- SOSCO/T1CKI -- SOSCI CCP2(1) -- CCP1 -- -- -- -- -- -- -- -- -- -- -- -- T5CKI -- -- -- -- -- -- -- -- -- -- -- Basic RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RD0 RD1 RD2 RD3 RD4 RD5 RD6 -- -- -- -- -- -- -- -- -- Pull-up -- -- -- -- T0CKI T3G -- -- -- Interrupt AN0 AN1 AN2 AN3 -- AN4 -- -- AN17 SSP Timers 24 23 22 21 28 27 40 39 48 USART A/D RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RB0 CCP 64-Pin TQFP, QFN 64-PIN DEVICE ALLOCATION TABLE (PIC16(L)F1526/27) I/O TABLE 1: -- -- -- -- -- -- -- -- INT/ IOC IOC IOC IOC IOC IOC IOC IOC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Y -- -- -- VREF+ -- -- OSC2/CLKOUT OSC1/CLKIN -- Y Y Y Y Y Y Y -- -- -- -- -- -- -- -- Y Y Y Y Y Y Y -- -- -- -- -- ICSPCLK/ICDCLK ICSPDAT/ICDDAT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RD7 49 -- -- -- -- SS2 -- Y -- RE0 2 AN27 -- -- -- -- Y -- RE1 1 AN28 -- -- -- -- -- Y -- RE2 64 AN29 -- CCP10 -- -- -- Y -- RE3 63 -- -- CCP9 -- -- -- Y -- RE4 62 -- -- CCP8 -- -- -- Y -- RE5 61 -- -- CCP7 -- -- -- Y -- RE6 60 -- -- CCP6 -- -- -- Y -- Note 1: Peripheral pin location selected using APFCON register. Default Location. 2: Peripheral pin location selected using APFCON register. Alternate Location. 3: Weak pull-up is always enabled when MCLR is enabled, otherwise the pull-up is under user control. DS41458B-page 6 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 64-Pin TQFP, QFN A/D Timers CCP USART SSP Interrupt Pull-up Basic 64-PIN DEVICE ALLOCATION TABLE (PIC16(L)F1526/27) (CONTINUED) I/O TABLE 1: RE7 RF0 RF1 RF2 RF3 RF4 RF5 RF6 59 18 17 16 15 14 13 12 -- AN16 AN6 AN7 AN8 AN9 AN10 AN11 -- -- -- -- -- -- -- -- CCP2(2) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Y -- -- -- -- -- -- -- -- VCAP -- -- -- -- -- -- RF7 RG0 RG1 RG2 RG3 RG4 11 3 4 5 6 8 AN5 -- AN15 AN14 AN13 AN12 -- -- -- -- -- T5G -- CCP3 -- -- CCP4 CCP5 -- -- TX2/CK2 RX2/DT2 -- -- SS1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RG5 VDD VSS AVDD AVSS Note 1: 2: 3: 7 -- -- -- -- -- -- Y(3) MCLR/VPP 10, 26, -- -- -- -- -- -- -- VDD 38, 57 9, 25, -- -- -- -- -- -- -- VSS 41, 56 19 -- -- -- -- -- -- -- AVDD 20 -- -- -- -- -- -- -- AVSS Peripheral pin location selected using APFCON register. Default Location. Peripheral pin location selected using APFCON register. Alternate Location. Weak pull-up is always enabled when MCLR is enabled, otherwise the pull-up is under user control. 2011 Microchip Technology Inc. Preliminary DS41458B-page 7 PIC16(L)F1526/27 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 17 3.0 Memory Organization ................................................................................................................................................................. 19 4.0 Device Configuration .................................................................................................................................................................. 45 5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 51 6.0 Resets ........................................................................................................................................................................................ 67 7.0 Interrupts .................................................................................................................................................................................... 75 8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 91 9.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 95 10.0 Watchdog Timer (WDT) ............................................................................................................................................................. 97 11.0 Flash Program Memory Control ............................................................................................................................................... 101 12.0 I/O Ports ................................................................................................................................................................................... 113 13.0 Interrupt-on-Change ................................................................................................................................................................. 139 14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 143 15.0 Temperature Indicator .............................................................................................................................................................. 145 16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 147 17.0 Timer0 Module ......................................................................................................................................................................... 161 18.0 Timer1/3/5 Modules.................................................................................................................................................................. 165 19.0 Timer2/4/6/8/10 Modules.......................................................................................................................................................... 177 20.0 Capture/Compare/PWM Module .............................................................................................................................................. 181 21.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 199 22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 253 23.0 In-Circuit Serial ProgrammingTM (ICSPTM) ................................................................................................................................ 283 24.0 Instruction Set Summary .......................................................................................................................................................... 287 25.0 Electrical Specifications............................................................................................................................................................ 301 26.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 331 27.0 Development Support............................................................................................................................................................... 333 28.0 Packaging Information.............................................................................................................................................................. 335 Appendix A: Revision History............................................................................................................................................................. 343 Index .................................................................................................................................................................................................. 345 The Microchip Web Site ..................................................................................................................................................................... 351 Customer Change Notification Service .............................................................................................................................................. 351 Customer Support .............................................................................................................................................................................. 351 Reader Response .............................................................................................................................................................................. 352 Product Identification System............................................................................................................................................................. 353 DS41458B-page 8 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2011 Microchip Technology Inc. Preliminary DS41458B-page 9 PIC16(L)F1526/27 NOTES: DS41458B-page 10 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 1.0 DEVICE OVERVIEW The PIC16(L)F1526/27 are described within this data sheet. They are available in 64-pin packages. Figure 1-1 shows a block diagram of the PIC16(L)F1526/27 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device. PIC16F1527 PIC16LF1527 DEVICE PERIPHERAL SUMMARY PIC16F1526 PIC16LF1526 TABLE 1-1: ADC EUSART Fixed Voltage Reference (FVR) Temperature Indicator CCP1 CCP2 CCP3 CCP4 CCP5 CCP6 CCP7 CCP8 CCP9 CCP10 EUSART1 EUSART2 MSSP1 MSSP2 Peripheral Capture/Compare/PWM Modules EUSARTs Master Synchronous Serial Ports Timers Timer0 Timer1/3/5 Timer2/4/6 /8/10 2011 Microchip Technology Inc. Preliminary DS41458B-page 11 PIC16(L)F1526/27 FIGURE 1-1: PIC16(L)F1526/27 BLOCK DIAGRAM PORTA Program Flash Memory RAM PORTB OSC2/CLKOUT Timing Generation OSC1/CLKIN PORTC CPU INTRC Oscillator PORTD (Figure 2-1) MCLR PORTE PORTF Timer0 Timer1/3/5 Timer2/4/6/8/10 EUSARTs PORTG CCP1-10 Note 1: 2: DS41458B-page 12 MSSPs Temp. Indicator ADC 10-Bit FVR See applicable chapters for more information on peripherals. See Table 1-1 for peripherals available on specific devices. Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 TABLE 1-2: PIC16(L)F1526 PINOUT DESCRIPTION Name RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF+ RA4/T0CKI RA5/AN4/T3G RA6/OSC2/CLKOUT RA7/OSC1/CLKIN RB0/AN17/INT RB1/AN18 RB2/AN19 RB3/AN20 RB4/AN21/T3CKI(2) RB5/AN22/T1G/T3CKI(1)/ RB6/ICSPCLK/ICDCLK Function Input Type Output Type RA0 TTL AN0 AN RA1 TTL AN1 AN RA2 TTL AN2 AN RA3 TTL AN3 AN -- A/D Channel 3 input. VREF+ AN -- A/D Positive Voltage Reference input. RA4 TTL Description CMOS General purpose I/O. -- A/D Channel 0 input. CMOS General purpose I/O. -- A/D Channel 1 input. CMOS General purpose I/O. -- A/D Channel 2 input. CMOS General purpose I/O. CMOS General purpose I/O. T0CKI ST RA5 TTL AN4 AN -- A/D Channel 4 input. T3G ST -- Timer3 gate input. RA6 TTL OSC2 -- CLKOUT -- RA7 TTL -- Timer0 clock input. CMOS General purpose I/O. CMOS General purpose I/O. XTAL Crystal/Resonator (LP, XT, HS modes). CMOS FOSC/4 output. CMOS General purpose I/O. OSC1 XTAL -- Crystal/Resonator (LP, XT, HS modes). CLKIN ST -- External clock input (EC mode). RB0 TTL AN17 AN INT ST RB1 TTL AN18 AN RB2 TTL AN19 AN RB3 TTL AN20 AN RB4 TTL CMOS General purpose I/O with IOC and WPU. -- A/D Channel 17 input. -- External interrupt. CMOS General purpose I/O with IOC and WPU. -- A/D Channel 18 input. CMOS General purpose I/O with IOC and WPU. -- A/D Channel 19 input. CMOS General purpose I/O with IOC and WPU. -- A/D Channel 20 input. CMOS General purpose I/O with IOC and WPU. AN21 AN -- A/D Channel 21 input. T3CKI ST -- Timer3 clock input. RB5 TTL AN22 AN CMOS General purpose I/O with IOC and WPU. -- A/D Channel 22 input. T1G ST -- Timer1 gate input. T3CKI ST -- Timer3 clock input. RB6 TTL ICSPCLK ST CMOS General purpose I/O with IOC and WPU. -- Serial Programming Clock. ICDCLK ST -- In-Circuit Debug Clock. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Peripheral pin location selected using APFCON register. Default location. 2: Peripheral pin location selected using APFCON register. Alternate location. 3: RC3, RC4, RD5 and RD6 read the I2C ST input when I2C mode is enabled. 2011 Microchip Technology Inc. Preliminary DS41458B-page 13 PIC16(L)F1526/27 TABLE 1-2: PIC16(L)F1526 PINOUT DESCRIPTION (CONTINUED) Name RB7/ICSPDAT/ICDDAT RC0/SOSCO/T1CKI RC1/SOSCI/CCP2(1) RC2/CCP1 RC3/SCK1/SCL1(3) RC4/SDI1/SDA1 (3) RC5/SDO1 RC6/TX1/CK1 RC7/RX1/DT1 RDO/AN23 RD1/AN24/T5CKI RD2/AN25 RD3/AN26 RD4/SDO2 RD5/SDI2/SDA2(3) Function Input Type RB7 TTL Output Type Description CMOS General purpose I/O with IOC and WPU. ICSPDAT ST CMOS ICSPTM Data I/O. ICDDAT ST CMOS In-Circuit Data I/O. RC0 ST CMOS General purpose I/O. SOSCO XTAL XTAL -- Timer1/3/5 oscillator connection. T1CKI ST RC1 ST Timer1/3/5 clock input. SOSCI XTAL CCP2 ST CMOS Capture/Compare/PWM2. CMOS General purpose I/O. XTAL Timer1/3/5 oscillator connection. RC2 ST CMOS General purpose I/O. CCP1 ST CMOS Capture/Compare/PWM1. RC3 ST CMOS General purpose I/O. SCK1 ST CMOS SPI clock. 2 SCL1 I CTM OD I2CTM clock. RC4 ST SDI1 ST CMOS General purpose I/O. -- SPI data input. SDA1 I2CTM OD I2CTM data input/output. RC5 ST SDO1 -- CMOS General purpose I/O. CMOS SPI data output. RC6 ST CMOS General purpose I/O. TX1 -- CMOS USART1 asynchronous transmit. CK1 ST CMOS USART1 synchronous clock. RC7 ST CMOS General purpose I/O. RX1 ST DT1 ST CMOS USART1 synchronous data. CMOS General purpose I/O with WPU. RD0 ST AN23 AN RD1 ST AN24 AN T5CKI ST RD2 ST AN25 AN RD3 ST AN26 AN RD4 ST -- -- USART1 asynchronous input. A/D Channel 23 input. CMOS General purpose I/O with WPU. -- A/D Channel 24 input. -- Timer5 clock input. CMOS General purpose I/O with WPU. -- A/D Channel 25 input. CMOS General purpose I/O with WPU. -- A/D Channel 26 input. CMOS General purpose I/O with WPU. SDO2 -- CMOS SPI data output. RD5 ST CMOS General purpose I/O with WPU. SDI2 ST -- SPI data input. SDA2 I2C OD I2CTM data input/output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Peripheral pin location selected using APFCON register. Default location. 2: Peripheral pin location selected using APFCON register. Alternate location. 3: RC3, RC4, RD5 and RD6 read the I2C ST input when I2C mode is enabled. DS41458B-page 14 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 TABLE 1-2: PIC16(L)F1526 PINOUT DESCRIPTION (CONTINUED) Name RD6/SCK2/SCL2(3) RD7/SS2 RE0/AN27 RE1/AN28 RE2/AN29/CCP10 RE3/CCP9 RE4/CCP8 RE5/CCP7 RE6/CCP6 RE7/CCP2(2) RF0/AN16/VCAP RF1/AN6 RF2/AN7 RF3/AN8 RF4/AN9 RF5/AN10 RF6/AN11 RF7/AN5/SS1 Function Input Type RD6 ST CMOS General purpose I/O with WPU. SCK2 ST CMOS SPI clock. SCL2 I2C RD7 ST SS2 ST RE0 ST AN27 AN RE1 ST AN28 AN Output Type OD Description I2CTM clock. CMOS General purpose I/O with WPU. -- Slave Select input. CMOS General purpose I/O with WPU. -- A/D Channel 27 input. CMOS General purpose I/O with WPU. -- A/D Channel 28 input. RE2 ST AN29 AN CCP10 ST CMOS Capture/Compare/PWM10. RE3 ST CMOS General purpose I/O with WPU. CCP9 ST CMOS Capture/Compare/PWM9. RE4 ST CMOS General purpose I/O with WPU. CCP8 ST CMOS Capture/Compare/PWM8. RE5 ST CMOS General purpose I/O with WPU. CCP7 ST CMOS Capture/Compare/PWM7. RE6 ST CMOS General purpose I/O with WPU. CCP6 ST CMOS Capture/Compare/PWM6. RE7 ST CMOS General purpose I/O with WPU. CCP2 ST CMOS Capture/Compare/PWM2. RF0 ST CMOS General purpose I/O. AN16 AN -- VCAP Power Power RF1 ST AN6 AN RF2 ST AN7 AN RF3 ST AN8 AN RF4 ST AN9 AN RF5 ST AN10 AN RF6 ST AN11 AN CMOS General purpose I/O with WPU. -- A/D Channel 29 input. A/D Channel 16 input. Filter capacitor for Voltage Regulator. CMOS General purpose I/O. -- A/D Channel 6 input. CMOS General purpose I/O. -- A/D Channel 7 input. CMOS General purpose I/O. -- A/D Channel 8 input. CMOS General purpose I/O. -- A/D Channel 9 input. CMOS General purpose I/O. -- A/D Channel 10 input. CMOS General purpose I/O. -- A/D Channel 11 input. RF7 ST AN5 AN CMOS General purpose I/O. -- A/D Channel 5 input. SS1 ST -- Slave Select input. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Peripheral pin location selected using APFCON register. Default location. 2: Peripheral pin location selected using APFCON register. Alternate location. 3: RC3, RC4, RD5 and RD6 read the I2C ST input when I2C mode is enabled. 2011 Microchip Technology Inc. Preliminary DS41458B-page 15 PIC16(L)F1526/27 TABLE 1-2: PIC16(L)F1526 PINOUT DESCRIPTION (CONTINUED) Name RG0/CCP3 RG1/AN15/TX2/CK2 RG2/AN14/RX2/DT2 RG3/AN13/CCP4 RG4/AN12/T5G/CCP5 Function Input Type Output Type RG0 ST CMOS General purpose I/O. CCP3 ST CMOS Capture/Compare/PWM3. RG1 ST CMOS General purpose I/O. AN15 AN TX2 -- -- Description A/D Channel 15 input. CMOS USART2 asynchronous transmit. CK2 ST CMOS USART2 synchronous clock. RG2 ST CMOS General purpose I/O. AN14 AN -- A/D Channel 14 input. RX2 ST -- USART2 asynchronous input. DT2 ST CMOS USART2 synchronous data. RG3 ST CMOS General purpose I/O. AN13 AN CCP4 ST -- A/D Channel 13 input. CMOS Capture/Compare/PWM4. RG4 ST -- AN12 AN -- General purpose input. A/D Channel 12 input. T5G ST -- Timer5 gate input. CCP5 ST CMOS Capture/Compare/PWM5. RG5 ST -- MCLR ST -- Master Clear with internal pull-up. VPP HV -- Programming voltage. AVDD AVDD Power -- Analog positive supply. AVSS AVSS Power -- Analog ground reference. VDD VDD Power -- Positive supply. VSS VSS Power -- Ground reference. RG5/MCLR/VPP General purpose input with WPU. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Peripheral pin location selected using APFCON register. Default location. 2: Peripheral pin location selected using APFCON register. Alternate location. 3: RC3, RC4, RD5 and RD6 read the I2C ST input when I2C mode is enabled. DS41458B-page 16 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 2.0 ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. * * * * Automatic Interrupt Context Saving 16-level Stack with Overflow and Underflow File Select Registers Instruction Set 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 7.5 "Automatic Context Saving", for more information. 2.2 16-level Stack with Overflow and Underflow These devices have an external stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled will cause a software Reset. See Section 3.4 "Stack" for more details. 2.3 File Select Registers There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See Section 3.5 "Indirect Addressing" for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 24.0 "Instruction Set Summary" for more details. 2011 Microchip Technology Inc. Preliminary DS41458B-page 17 PIC16(L)F1526/27 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration 15 MUX Flash Program Memory Program Bus 16-Level 8 Level Stack Stack (13-bit) (15-bit) 14 Instruction Instruction Reg reg 8 Data Bus Program Counter RAM Program Memory Read (PMR) 12 RAM Addr Addr MUX Indirect Addr 12 12 Direct Addr 7 5 BSR FSR Reg reg 15 FSR0reg Reg FSR FSR1 Reg FSR reg 15 STATUS Reg reg STATUS 8 3 Power-up Timer CLKIN CLKOUT Instruction Decodeand & Decode Control Timing Generation Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset MUX ALU 8 W Reg Internal Oscillator Block VDD DS41458B-page 18 VSS Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 3.0 MEMORY ORGANIZATION 3.1 These devices contain the following types of memory: * Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory * Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented for the PIC16(L)F1526/27 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 3-1 and Figure 3-2). The following features are associated with access and control of program memory and data memory: * PCL and PCLATH * Stack * Indirect Addressing TABLE 3-1: DEVICE SIZES AND ADDRESSES Device Program Memory Space (Words) Last Program Memory Address PIC16F1526 PIC16LF1526 8,192 1FFFh PIC16F1527 PIC16LF1527 16,384 3FFFh 2011 Microchip Technology Inc. Preliminary DS41458A-page 19 PIC16(L)F1526/27 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1526 FIGURE 3-2: PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE PC<14:0> 15 Stack Level 0 Stack Level 1 CALL, CALLW 15 RETURN, RETLW Interrupt, RETFIE Stack Level 0 Stack Level 1 Stack Level 15 Stack Level 15 Reset Vector 0000h Reset Vector 0000h Interrupt Vector 0004h 0005h Interrupt Vector 0004h 0005h Page 0 Page 0 07FFh 0800h On-chip Program Memory PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1527 07FFh 0800h Page 1 Page 1 0FFFh 1000h Page 2 Page 3 Rollover to Page 0 17FFh 1800h 0FFFh 1000h On-chip Program Memory Page 2 Page 3 1FFFh 2000h Page 4 Page 7 Rollover to Page 0 Rollover to Page 3 DS41458A-page 20 7FFFh Preliminary Rollover to Page 7 17FFh 1800h 1FFFh 2000h 3FFFh 4000h 7FFFh 2011 Microchip Technology Inc. PIC16(L)F1526/27 3.1.1 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.1.1.1 RETLW Instruction The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1. EXAMPLE 3-1: constants BRW RETLW RETLW RETLW RETLW DATA0 DATA1 DATA2 DATA3 RETLW INSTRUCTION EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR constants RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3 my_function ;... LOTS OF CODE... MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1] ;THE PROGRAM MEMORY IS IN W ;Add Index in W to ;program counter to ;select data ;Index0 data ;Index1 data my_function ;... LOTS OF CODE... MOVLW DATA_INDEX CALL constants ;... THE CONSTANT IS IN W The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 3.1.1.2 Indirect Read with FSR The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower 8 bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR. The HIGH directive will set bit<7> if a label points to a location in program memory. 2011 Microchip Technology Inc. Preliminary DS41458A-page 21 PIC16(L)F1526/27 3.2 3.2.1 Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3): * * * * 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh). These registers are listed below in Table 3-2. For detailed information, see Table 3-4. TABLE 3-2: The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as `0'. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 3.5 "Indirect Addressing" for more information. Data memory uses a 12-bit address. The upper 7-bit of the address define the Bank address and the lower 5-bits select the registers/RAM in that bank. DS41458A-page 22 CORE REGISTERS Preliminary CORE REGISTERS Addresses BANKx x00h or x80h x01h or x81h x02h or x82h x03h or x83h x04h or x84h x05h or x85h x06h or x86h x07h or x87h x08h or x88h x09h or x89h x0Ah or x8Ah x0Bh or x8Bh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON 2011 Microchip Technology Inc. PIC16(L)F1526/27 3.2.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: * the arithmetic status of the ALU * the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. REGISTER 3-1: U-0 It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 24.0 "Instruction Set Summary"). Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. STATUS: STATUS REGISTER U-0 -- For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as `000u u1uu' (where u = unchanged). -- U-0 R-1/q -- TO R-1/q R/W-0/u R/W-0/u R/W-0/u Z DC(1) C(1) PD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as `0' bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. 2011 Microchip Technology Inc. Preliminary DS41458A-page 23 PIC16(L)F1526/27 3.2.2 SPECIAL FUNCTION REGISTER FIGURE 3-3: The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.2.3 7-bit Bank Offset 0Bh 0Ch GENERAL PURPOSE RAM Core Registers (12 bytes) Special Function Registers (20 bytes maximum) 1Fh 20h Linear Access to GPR The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 3.5.2 "Linear Data Memory" for more information. 3.2.4 Memory Region 00h There are up to 80 bytes of GPR in each data memory bank. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). 3.2.3.1 BANKED MEMORY PARTITIONING General Purpose RAM (80 bytes maximum) COMMON RAM There are 16 bytes of common RAM accessible from all banks. 6Fh 70h Common RAM (16 bytes) 7Fh 3.2.5 DEVICE MEMORY MAPS The memory maps for PIC16(L)F1526/27 is shown in Table 3-3. DS41458A-page 24 Preliminary 2011 Microchip Technology Inc. 2011 Microchip Technology Inc. TABLE 3-3: PIC16(L)F1526/27 MEMORY MAP BANK 0 000h BANK 1 080h Core Registers (Table 3-2) Preliminary 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h PORTA PORTB PORTC PORTD PORTE PIR1 PIR2 PIR3 PIR4 TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON -- -- -- Core Registers (Table 3-2) 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h Legend: Note 1: -- Core Registers (Table 3-2) 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h 0EFh 0F0h 0FFh Common RAM (Accesses 70h - 7Fh) LATA LATB LATC LATD LATE -- -- -- -- -- BORCON FVRCON -- -- -- -- -- APFCON -- -- 16Fh 170h 17Fh Common RAM (Accesses 70h - 7Fh) = Unimplemented data memory locations, read as `0'. PIC16F1526/27 only. BANK 4 200h Core Registers (Table 3-2) 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h General Purpose Register 80 Bytes General Purpose Register 80 Bytes Common RAM 07Fh TRISA TRISB TRISC TRISD TRISE PIE1 PIE2 PIE3 PIE4 OPTION_REG PCON WDTCON -- OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 BANK 3 180h ANSELA ANSELB -- ANSELD ANSELE PMADRL PMADRH PMDATL PMDATH PMCON1 PMCON2 VREGCON(1) -- RC1REG TX1REG SP1BRG SP1BRGH RC1STA TX1STA BAUD1CON Core Registers (Table 3-2) 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh 220h General Purpose Register 80 Bytes 1EFh 1F0h 1FFh Common RAM (Accesses 70h - 7Fh) BANK 5 280h -- WPUB -- WPUD WPUE SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON1 SSP1CON2 SSP1CON3 -- SSP2BUF SSP2ADD SSP2MSK SSP2STAT SSP2CON1 SSP2CON2 SSP2CON3 Core Registers (Table 3-2) 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh 2A0h General Purpose Register 80 Bytes 26Fh 270h 27Fh Common RAM (Accesses 70h - 7Fh) BANK 6 300h PORTF PORTG -- -- -- CCPR1L CCPR1H CCP1CON -- -- -- -- CCPR2L CCPR2H CCP2CON -- -- CCPTMRS0 CCPTMRS1 CCPTMRS2 Core Registers (Table 3-2) 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh 320h General Purpose Register 80 Bytes 2EFh 2F0h 2FFh Common RAM (Accesses 70h - 7Fh) BANK 7 380h TRISF TRISG -- -- -- CCPR3L CCPR3H CCP3CON -- -- -- -- CCPR4L CCPR4H CCP4CON -- CCPR5L CCPR5H CCP5CON -- Core Registers (Table 3-2) 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh 3A0h General Purpose Register 80 Bytes 36Fh 370h 37Fh Common RAM (Accesses 70h - 7Fh) LATF LATG -- -- -- -- -- -- IOCBP IOCBN IOCBF -- -- -- -- -- -- -- -- -- General Purpose Register 80 Bytes 3EFh 3F0h 3FFh Common RAM (Accesses 70h - 7Fh) DS41458A-page 25 PIC16(L)F1526/27 General Purpose Register 80 Bytes 06Fh 070h BANK 2 100h PIC16(L)F1526/27 MEMORY MAP (CONTINUED) BANK 8 400h BANK 9 480h Core Registers (Table 3-2) 40Bh Preliminary ANSELF ANSELG -- -- -- TMR3L TMR3H T3CON T3GCON TMR4 PR4 T4CON TMR5L TMR5H T5CON T5GCON TMR6 PR6 T6CON -- 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h General Purpose Register 80 Bytes 46Fh 470h 2011 Microchip Technology Inc. Common RAM (Accesses 70h - 7Fh) 47Fh Legend: Note 1: BANK 10 500h Core Registers (Table 3-2) 48Bh -- 48Ch WPUG 48Dh -- 48Eh -- 48Fh -- 490h RC2REG 491h TX2REG 492h SP2BRG 493h SP2BRGH 494h RC2STA 495h TX2STA 496h BAUD2CON 497h -- 498h -- 499h -- 49Ah -- 49Bh -- 49Ch -- 49Dh -- 49Eh -- 49Fh 4A0h General Purpose Register 32 Bytes 4BFh Core Registers (Table 3-2) 50Bh 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h Unimplemented Read as `0' 51Fh 520h General Purpose Register 80 Bytes(1) Common RAM (Accesses 70h - 7Fh) = Unimplemented data memory locations, read as `0'. BANK 12 600h Core Registers (Table 3-2) 50Ch 4C0h General Purpose Register 48 Bytes(1) 4EFh 56Fh 4F0h 570h Common RAM (Accesses 70h - 7Fh) 4FFh 57Fh PIC16(L)F1527 only. BANK 11 580h Core Registers (Table 3-2) 60Bh -- -- -- -- -- -- -- -- -- TMR8 PR8 T8CON -- -- -- -- TMR10 PR10 T10CON -- 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h 615h 616h 617h 618h 619h 61Ah 61Bh 61Ch 61Dh 61Eh 61Fh 620h General Purpose Register 80 Bytes(1) 5EFh 5F0h 5FFh Common RAM (Accesses 70h - 7Fh) BANK 13 680h -- -- -- -- -- CCPR6L CCPR6H CCP6CON CCPR7L CCPR7H CCP7CON CCPR8L CCPR8H CCP8CON CCPR9L CCPR9H CCP9CON CCPR10L CCPR10H CCP10CON Core Registers (Table 3-2) 67Fh Common RAM (Accesses 70h - 7Fh) BANK 15 780h Core Registers (Table 3-2) Core Registers (Table 3-2) 68Bh 70Bh 78Bh 68Ch 70Ch 78Ch Unimplemented Unimplemented Unimplemented Read as `0' Read as `0' Read as `0' 69Fh 6A0h General Purpose Register 80 Bytes(1) 66Fh 670h BANK 14 700h 71Fh 720h General Purpose Register 80 Bytes(1) 6EFh 6F0h 6FFh Common RAM (Accesses 70h - 7Fh) 79Fh 7A0h General Purpose Register 80 Bytes(1) 76Fh 770h 77Fh Common RAM (Accesses 70h - 7Fh) General Purpose Register 80 Bytes(1) 7EFh 7F0h 7FFh Common RAM (Accesses 70h - 7Fh) PIC16(L)F1526/27 DS41458A-page 26 TABLE 3-3: 2011 Microchip Technology Inc. TABLE 3-3: PIC16(L)F1526/27 MEMORY MAP (CONTINUED) BANK 16 800h BANK 17 880h Core Registers (Table 3-2) 80Bh 80Ch Core Registers (Table 3-2) 88Bh 88Ch Unimplemented Read as `0' 81Fh 820h 86Fh 870h 87Fh General Purpose Register 80 Bytes(1) Common RAM (Accesses 70h - 7Fh) 89Fh 8A0h 8EFh 8F0h 8FFh Preliminary C0Bh C0Ch Legend: Note 1: 96Fh 970h 97Fh Core Registers (Table 3-2) A0Bh A0Ch Common RAM (Accesses 70h - 7Fh) Unimplemented Read as `0' 9EFh 9F0h 9FFh BANK 26 BANK 22 B00h Core Registers (Table 3-2) A8Bh A8Ch D7Fh = Unimplemented data memory locations, read as `0'. PIC16(L)F1527 only. A6Fh A70h A7Fh BANK 23 B80h Core Registers (Table 3-2) B0Bh B0Ch AFFh Core Registers (Table 3-2) B8Bh B8Ch E7Fh B7Fh EFFh BEFh BF0h BFFh Common RAM (Accesses 70h - 7Fh) BANK 30 Core Registers (Table 3-2) F0Bh F0Ch Unimplemented Read as `0' EEFh EF0h Common RAM (Accesses 70h - 7Fh) Unimplemented Read as `0' F00h E8Bh E8Ch Common RAM (Accesses 70h - 7Fh) B6Fh B70h Core Registers (Table 3-2) Unimplemented Read as `0' E6Fh E70h Common RAM (Accesses 70h - 7Fh) Unimplemented Read as `0' BANK 29 Core Registers (Table 3-2) Unimplemented Read as `0' DFFh AEFh AF0h E80h E0Bh E0Ch Common RAM (Accesses 70h - 7Fh) Unimplemented Read as `0' BANK 28 Core Registers (Table 3-2) DEFh DF0h Common RAM (Accesses 70h - 7Fh) E00h D8Bh D8Ch Common RAM (Accesses 70h - 7Fh) Unimplemented Read as `0' BANK 27 Unimplemented Read as `0' D6Fh D70h Common RAM (Accesses 70h - 7Fh) D80h Core Registers (Table 3-2) Unimplemented Read as `0' CFFh General Purpose Register 80 Bytes(1) D0Bh D0Ch Common RAM (Accesses 70h - 7Fh) BANK 21 A80h Common RAM (Accesses 70h - 7Fh) Unimplemented Read as `0' F6Fh F70h F7Fh Common RAM (Accesses 70h - 7Fh) DS41458A-page 27 PIC16(L)F1526/27 Common RAM (Accesses 70h - 7Fh) 91Fh 920h Core Registers (Table 3-2) CEFh CF0h Core Registers (Table 3-2) 98Bh 98Ch D00h C8Bh C8Ch BANK 20 A00h Unimplemented Read as `0' BANK 25 Unimplemented Read as `0' C7Fh Common RAM (Accesses 70h - 7Fh) C80h Core Registers (Table 3-2) C6Fh C70h 90Bh 90Ch General Purpose Register 80 Bytes(1) BANK 19 980h Core Registers (Table 3-2) Unimplemented Read as `0' BANK 24 C00h BANK 18 900h PIC16(L)F1526 MEMORY MAP (CONTINUED) Bank 31 F80h Core Registers (Table 3-2) F8Bh F8Ch Unimplemented Read as `0' Preliminary FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh FF0h FFFh Legend: STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD -- STKPTR TOSL TOSH Common RAM (Accesses 70h - 7Fh) = Unimplemented data memory locations, read as `0'. PIC16(L)F1526/27 DS41458A-page 28 TABLE 3-3: 2011 Microchip Technology Inc. PIC16(L)F1526/27 3.2.6 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-4 can be addressed from any Bank. TABLE 3-4: Addr Name CORE FUNCTION REGISTERS SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0-31 x00h or INDF0 x80h Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx uuuu uuuu x01h or INDF1 x81h Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx uuuu uuuu x02h or PCL x82h Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 ---1 1000 ---q quuu x03h or STATUS x83h -- -- -- TO PD Z DC C x04h or FSR0L x84h Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x05h or FSR0H x85h Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x06h or FSR1L x86h Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x07h or FSR1H x87h Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 0000 0000 0000 x08h or BSR x88h -- x09h or WREG x89h -- BSR4 BSR3 BSR2 BSR1 BSR0 Working Register x0Ah or PCLATH x8Ah -- x0Bh or INTCON x8Bh GIE Legend: -- Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. 2011 Microchip Technology Inc. Preliminary DS41458A-page 29 PIC16(L)F1526/27 TABLE 3-2: Addr Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0 00Ch PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu 00Dh PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 00Eh PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 00Fh PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu 010h PORTE PORTE Data Latch when written: PORTE pins when read 011h TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 OSFIF TMR5GIF TMR3GIF -- BCL1IF TMR10IF TMR8IF CCP2IF 000- 0000 000- 0000 013h PIR3 CCP6IF CCP5IF CCP4IF CCP3IF TMR6IF TMR5IF TMR4IF TMR3IF 0000 0000 0000 0000 014h PIR4 CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF 0000 0000 0000 0000 PIR1 012h PIR2 xxxx xxxx uuuu uuuu 015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 018h T1CON 019h T1GCON TMR1CS<1:0> TMR1GE T1CKPS<1:0> T1GPOL T1GTM 01Ah TMR2 Timer 2 Module Register 01Bh PR2 Timer 2 Period Register 01Ch T2CON T1GSPM xxxx xxxx uuuu uuuu SOSCEN T1SYNC -- T1GGO/ DONE T1GVAL T1GSS<1:0> TMR1ON 0000 00-0 uuuu uu-u 0000 0x00 uuuu uxuu 0000 0000 0000 0000 1111 1111 1111 1111 -- T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000 01Dh -- Unimplemented -- -- 01Eh -- Unimplemented -- -- 01Fh -- Unimplemented -- -- Bank 1 08Ch TRISA PORTA Data Direction Register 1111 1111 1111 1111 08Dh TRISB PORTB Data Direction Register 1111 1111 1111 1111 08Eh TRISC PORTC Data Direction Register 1111 1111 1111 1111 08Fh TRISD PORTD Data Direction Register 1111 1111 1111 1111 090h TRISE PORTE Data Direction Register 091h PIE1 TMR1GIE 092h PIE2 OSFIE ADIE RC1IE TMR5GIE TMR3GIE 1111 1111 1111 1111 TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 -- BCL1IE TMR10IE TMR8IE CCP2IE 000- 0000 000- 0000 0000 0000 0000 0000 093h PIE3 CCP6IE CCP5IE CCP4IE CCP3IE TMR6IE TMR5IE TMR4IE TMR3IE 094h PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA 096h PCON STKOVF STKUNF -- RWDT -- -- 097h WDTCON 098h -- 09Ah OSCSTAT SOSCR IRCF<3:0> -- OSTS A/D Result Register Low 09Ch ADRESH A/D Result Register High 09Dh ADCON0 -- 09Eh ADCON1 ADFM 09Fh -- 1: 2: POR BOR 00-1 11qq qq-q qquu SWDTEN --01 0110 --01 0110 -- -- 09Bh ADRESL Note RI WDTPS<4:0> 0000 0000 0000 0000 1111 1111 1111 1111 Unimplemented 099h OSCCON Legend: RMCLR PS<2:0> HFIOFR -- -- -- LFIOFR HFIOFS -- -011 1-00 -011 1-00 0-q0 --00 q-qq --0q xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CHS<4:0> ADCS<2:0> SCS<1:0> GO/DONE -- -- ADON ADPREF<1:0> Unimplemented -000 0000 -000 0000 0000 --00 0000 --00 -- -- x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F1526/7 only. Unimplemented, read as `1'. DS41458A-page 30 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 TABLE 3-2: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu 10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu 10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu 10Fh LATD PORTD Data Latch xxxx xxxx uuuu uuuu 110h PORTE Data Latch xxxx xxxx uuuu uuuu LATE 111h to -- 115h Unimplemented -- 116h BORCON SBOREN BORFS -- -- -- -- -- 117h FVRCON FVREN FVRRDY TSEN TSRNG -- -- ADFVR<1:0> 118h to -- 11Ch BORRDY 10-- ---q uu-- ---u Unimplemented 11Dh APFCON -- 0q00 0000 0q00 0000 -- -- -- -- -- -- -- -- T3CKISEL CCP2SEL ---- --00 ---- --00 11Eh -- Unimplemented -- -- 11Fh Unimplemented -- -- -- Bank 3 18Ch ANSELA -- -- ANSA5 -- ANSA3 ANSA2 ANSA1 ANSA0 --1- 1111 --1- 1111 18Dh ANSELB -- -- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111 -- -- -- -- ANSD3 ANSD2 ANSD1 ANSD0 ---- 1111 ---- 1111 -- -- -- -- -- ANSE2 ANSE1 ANSE0 ---- -111 ---- -111 18Eh ANSELC 18Fh ANSELD 190h ANSELE 191h PMADRL 192h PMADRH 193h PMDATL Unimplemented -- Program Memory Address Register Low Byte -- -- 195h PMCON1 -- CFGS 197h VREGCON(1) 1000 0000 1000 0000 Program Memory Data Register Low Byte -- 196h PMCON2 0000 0000 0000 0000 Program Memory Address Register High Byte 194h PMDATH xxxx xxxx uuuu uuuu Program Memory Data Register High Byte LWLO --xx xxxx --uu uuuu FREE WRERR WREN WR -- -- -- VREGPM RD Program Memory control register 2 -- -- -- 198h -- Unimplemented 199h RC1REG USART Receive Data Register 19Ah TX1REG USART Transmit Data Register -- -000 x000 -000 q000 0000 0000 0000 0000 Reserved ---- --01 ---- --01 -- -- 0000 0000 0000 0000 0000 0000 0000 0000 19Bh SP1BRG BRG<7:0> 19Ch SP1BRGH BRG<15:8> 0000 0000 0000 0000 0000 0000 0000 0000 19Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 19Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 01-0 0-00 01-0 0-00 19Fh BAUD1CON Legend: Note 1: 2: 0000 000x 0000 000x x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F1526/7 only. Unimplemented, read as `1'. 2011 Microchip Technology Inc. Preliminary DS41458A-page 31 PIC16(L)F1526/27 TABLE 3-2: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Value on POR, BOR Value on all other Resets -- -- Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111 Bank 4 20Ch -- Unimplemented 20Dh WPUB 20Eh -- WPUB6 Unimplemented 20Fh WPUD 210h WPUE 211h WPUB7 SSP1BUF -- -- WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 1111 1111 1111 1111 WPUE7 WPUE6 WPUE5 WPUE4 WPUE3 WPUE2 WPUE1 WPUE0 1111 1111 1111 1111 Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 212h SSP1ADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 213h SSP1MSK Synchronous Serial Port (I2C mode) Address Mask Register 1111 1111 1111 1111 214h SSP1STAT SMP CKE D/A P 215h SSP1CON1 WCOL SSPOV SSPEN CKP 216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 S R/W UA BF SSPM<3:0> 0000 0000 0000 0000 0000 0000 0000 0000 218h -- Unimplemented 219h SSP2BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 21Ah SSP2ADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 21Bh SSP2MSK Synchronous Serial Port (I2C mode) Address Mask Register -- -- 1111 1111 1111 1111 21Ch SSP2STAT SMP CKE D/A P 21Dh SSP2CON1 WCOL SSPOV SSPEN CKP 21Eh SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 21Fh SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 28Ch PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 xxxx xxxx uuuu uuuu 28Dh PORTG -- -- RG5 RG4 RG3 RG2 RG1 RG0 --xx xxxx --uu uuuu S R/W UA BF SSPM<3:0> 0000 0000 0000 0000 0000 0000 0000 0000 Bank 5 28Eh -- Unimplemented -- -- 28Fh -- Unimplemented -- -- 290h -- Unimplemented -- -- 291h CCPR1L Capture/Compare/PWM Register 1 (LSB) 292h CCPR1H Capture/Compare/PWM Register 1 (MSB) 293h CCP1CON -- -- xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu DC1B<1:0> CCP1M<3:0> --00 0000 --00 0000 294h -- Unimplemented -- -- 295h -- Unimplemented -- -- 296h -- Unimplemented -- -- 297h -- Unimplemented -- -- 298h CCPR2L Capture/Compare/PWM Register 2 (LSB) 299h CCPR2H Capture/Compare/PWM Register 2 (MSB) 29Ah CCP2CON -- -- xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu DC2B<1:0> CCP2M<3:0> --00 0000 --00 0000 29Bh -- Unimplemented -- -- 29Ch -- Unimplemented -- -- 29Dh CCPTMRS0 C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 0000 0000 0000 0000 29Eh CCPTMRS1 C8TSEL<1:0> C7TSEL<1:0> C6TSEL<1:0> C5TSEL<1:0> 0000 0000 0000 0000 29Fh CCPTMRS2 -- -- C10TSEL<1:0> C9TSEL<1:0> ---- 0000 ---- 0000 Legend: Note 1: 2: -- -- x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F1526/7 only. Unimplemented, read as `1'. DS41458A-page 32 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 TABLE 3-2: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bit 7 Bit 6 Bit 5 30Ch TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111 30Dh TRISG -- -- --(2) TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 --11 1111 --11 1111 Bank 6 30Eh -- Unimplemented -- -- 30Fh -- Unimplemented -- -- 310h -- Unimplemented -- -- 311h CCPR3L Capture/Compare/PWM Register 3 (LSB) 312h CCPR3H Capture/Compare/PWM Register 3 (MSB) 313h CCP3CON -- -- xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu DC3B<1:0> CCP3M<3:0> --00 0000 --00 0000 314h -- Unimplemented -- -- 315h -- Unimplemented -- -- 316h -- Unimplemented -- -- 317h -- Unimplemented -- -- 318h CCPR4L Capture/Compare/PWM Register 4 (LSB) 319h CCPR4H Capture/Compare/PWM Register 4 (MSB) 31Ah CCP4CON -- -- Unimplemented 31Ch CCPR5L Capture/Compare/PWM Register 5 (LSB) 31Dh CCPR5H Capture/Compare/PWM Register 5 (MSB) 31Fh -- -- xxxx xxxx uuuu uuuu DC4B<1:0> 31Bh -- 31Eh CCP5CON xxxx xxxx uuuu uuuu CCP4M<3:0> --00 0000 --00 0000 -- -- -- xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu DC5B<1:0> CCP5M<3:0> --00 0000 --00 0000 Unimplemented -- -- Bank 7 38Ch LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx xxxx uuuu uuuu 38Dh LATG -- -- -- LATG4 LATG3 LATG2 LATG1 LATG0 ---x xxxx ---u uuuu 38Eh to -- 393h Unimplemented -- -- 394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0000 0000 0000 0000 395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0000 0000 0000 0000 396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000 0000 0000 397h to -- 39Fh Legend: Note 1: 2: Unimplemented -- -- x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F1526/7 only. Unimplemented, read as `1'. 2011 Microchip Technology Inc. Preliminary DS41458A-page 33 PIC16(L)F1526/27 TABLE 3-2: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 40Ch ANSELF ANSF7 ANSF6 ANSF5 ANSF4 ANSF3 40Dh ANSELG -- -- -- ANSG4 ANSG3 Bit 2 Value on POR, BOR Value on all other Resets Bit 1 Bit 0 ANSF2 ANSF1 ANSF0 1111 1111 1111 1111 ANSG2 ANSG1 -- ---1 111- ---1 111- Bank 8 40Eh -- Unimplemented -- -- 40Fh -- Unimplemented -- -- 410h -- Unimplemented -- -- 411h TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register 412h TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register 413h T3CON 414h T3GCON TMR3CS<1:0> TMR3GE T3GPOL 415h TMR4 Timer 4 Module Register 416h PR4 Timer 4 Period Register 417h T4CON -- T3CKPS<1:0> T3GTM T3GSPM T3SYNC -- T3GGO/ DONE T3GVAL T3GSS<1:0> 419h TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register TMR5GE T5GPOL 41Ch TMR6 Timer 6 Module Register 41Dh PR6 Timer 6 Period Register 41Eh T6CON 41Fh -- -- 0000 0x00 uuuu uxuu 1111 1111 1111 1111 TMR4ON Holding Register for the Least Significant Byte of the 16-bit TMR5 Register 41Bh T5GCON TMR3ON 0000 00-0 uuuu uu-u 0000 0000 0000 0000 T4OUTPS<3:0> TMR5CS<1:0> xxxx xxxx uuuu uuuu SOSCEN 418h TMR5L 41Ah T5CON xxxx xxxx uuuu uuuu T5CKPS<1:0> T5GTM T5GSPM T4CKPS<1:0> -000 0000 -000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu SOSCEN T5SYNC -- T5GGO/ DONE T5GVAL T5GSS<1:0> TMR5ON 0000 00-0 uuuu uu-u 0000 0x00 uuuu uxuu 0000 0000 0000 0000 1111 1111 1111 1111 T6OUTPS<3:0> TMR6ON T6CKPS<1:0> Unimplemented -000 0000 -000 0000 -- -- -- -- Bank 9 48Ch -- Unimplemented 48Dh WPUG -- -- WPUG5 48Dh to -- 490h Unimplemented 491h RC2REG USART Receive Data Register 492h TX2REG USART Transmit Data Register -- -- -- -- -- --1- ---- --1- ----- -- 0000 0000 0000 0000 0000 0000 0000 0000 493h SP2BRG BRG<7:0> 494h SP2BRGH BRG<15:8> 0000 0000 0000 0000 0000 0000 0000 0000 495h RC2STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 496h TX2STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 01-0 0-00 01-0 0-00 497h BAUD2CON 498h to -- 49Fh Legend: Note 1: 2: Unimplemented 0000 000x 0000 000x -- -- x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F1526/7 only. Unimplemented, read as `1'. DS41458A-page 34 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 TABLE 3-2: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on POR, BOR Value on all other Resets Unimplemented -- -- Unimplemented -- -- Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 10 50Ch -- -- 51Fh Bank 11 58Ch -- -- 594h 595h TMR8 Timer 8 Module Register 596h PR8 Timer 8 Period Register 597h T8CON -- Unimplemented 59Ch TMR10 Timer 10 Module Register 59Dh PR10 Timer 10 Period Register 59Fh -- 1111 1111 1111 1111 T8OUTPS<3:0> 598h -- -- 59Bh 59Eh T10CON 0000 0000 0000 0000 TMR8ON T8CKPS<1:0> -000 0000 -000 0000 -- 0000 0000 0000 0000 1111 1111 1111 1111 T10OUTPS<3:0> -- -- TMR10ON T10CKPS<1:0> -000 0000 -000 0000 Unimplemented -- -- 60Ch -- -- 610h Unimplemented -- -- 611h CCPR6L Capture/Compare/PWM Register 6 (LSB) 612h CCPR6H Capture/Compare/PWM Register 6 (MSB) Bank 12 613h CCP6CON -- -- DC6B<1:0> 614h CCPR7L Capture/Compare/PWM Register 7 (LSB) 615h CCPR7H Capture/Compare/PWM Register 7 (MSB) 616h CCP7CON -- -- DC7B<1:0> 617h CCPR8L Capture/Compare/PWM Register 8 (LSB) 618h CCPR8H Capture/Compare/PWM Register 8 (MSB) 619h CCP8CON -- -- DC8B<1:0> 61Ah CCPR9L Capture/Compare/PWM Register 9 (LSB) 61Bh CCPR9H Capture/Compare/PWM Register 9 (MSB) 61Ch CCP9CON -- -- DC9B<1:0> 61Dh CCPR10L Capture/Compare/PWM Register 10 (LSB) 61Eh CCPR10H Capture/Compare/PWM Register 10 (MSB) 61Fh CCP10CON -- -- DC10B<1:0> xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP6M<3:0> --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP7M<3:0> --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP8M<3:0> --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP9M<3:0> --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP10M<3:0> --00 0000 --00 0000 Bank 13-30 x0Ch or x8Ch to -- x1Fh or x9Fh Legend: Note 1: 2: Unimplemented -- -- x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F1526/7 only. Unimplemented, read as `1'. 2011 Microchip Technology Inc. Preliminary DS41458A-page 35 PIC16(L)F1526/27 TABLE 3-2: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- Bank 31 F8Ch -- -- FE3h Unimplemented FE4h STATUS_SHAD FE5h WREG_SHAD -- -- -- -- -- Z_SHAD DC_SHAD C_SHAD Working Register Normal (Non-ICD) Shadow FE6h BSR_SHAD -- FE7h PCLATH_SHAD -- -- -- ---- -xxx ---- -uuu xxxx xxxx uuuu uuuu Bank Select Register Normal (Non-ICD) Shadow Program Counter Latch High Register Normal (Non-ICD) Shadow ---x xxxx ---u uuuu -xxx xxxx uuuu uuuu FE8h FSR0L_SHAD Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu FE9h FSR0H_SHAD Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu FEAh FSR1L_SHAD Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu FEBh FSR1H_SHAD Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu FECh -- Unimplemented FEDh STKPTR FEEh TOSL Note 1: 2: -- -- -- Current Stack Pointer -- -- ---1 1111 ---1 1111 Top of Stack Low byte FEFh TOSH Legend: -- xxxx xxxx uuuu uuuu Top of Stack High byte -xxx xxxx -uuu uuuu x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F1526/7 only. Unimplemented, read as `1'. DS41458A-page 36 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 3.3 3.3.3 PCL and PCLATH COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-4 shows the five situations for the loading of the PC. A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). FIGURE 3-4: If using the CALL instruction, the PCH<2:0> and PCL registers are loaded with the operand of the CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>. PC LOADING OF PC IN DIFFERENT SITUATIONS 14 PCH 6 7 14 PCH PCL 0 PCLATH PC 8 ALU Result PCL 0 4 0 14 11 PCL 0 CALLW 6 PCLATH PCH 14 7 0 PCH 8 W PCL BRW PCH BRANCHING If using BRA, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the BRA instruction. 15 14 3.3.4 If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address PC + 1 + W. 0 PC + W PC The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH. The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed. OPCODE <10:0> PC PC Instruction with PCL as Destination GOTO, CALL 6 PCLATH 0 PCL 0 BRA 15 PC + OPCODE <8:0> 3.3.1 MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 7 bits to the PCLATH register. When the lower 8 bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. 3.3.2 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, "Implementing a Table Read" (DS00556). 2011 Microchip Technology Inc. Preliminary DS41458A-page 37 PIC16(L)F1526/27 3.4 3.4.1 Stack The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is 5 bits to allow detection of overflow and underflow. All devices have a 16-level x 15-bit wide hardware stack (refer to Figures 3-5 through 3-8). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer if the STVREN bit is programmed to `0' (Configuration Word 2). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled. Note: Care should be taken when modifying the STKPTR while interrupts are enabled. During normal program operation, CALL, CALLW and Interrupts will increment STKPTR while RETLW, RETURN, and RETFIE will decrement STKPTR. At any time STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will increment the STKPTR and then write the PC, and a return will unload the PC and then decrement STKPTR. Note 1: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-5: ACCESSING THE STACK Reference Figures 3-5 through 3-8 for examples of accessing the stack. ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL 0x0F STKPTR = 0x1F Stack Reset Disabled (STVREN = 0) 0x0E 0x0D 0x0C 0x0B 0x0A Initial Stack Configuration: 0x09 After Reset, the stack is empty. The empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack Overflow/Underflow Reset is enabled, the TOSH/TOSL registers will return `0'. If the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F. 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 TOSH:TOSL DS41458A-page 38 0x1F 0x0000 Preliminary STKPTR = 0x1F Stack Reset Enabled (STVREN = 1) 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F). 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL FIGURE 3-7: 0x00 Return Address STKPTR = 0x00 ACCESSING THE STACK EXAMPLE 3 0x0F 0x0E 0x0D 0x0C After seven CALLs or six CALLs and an interrupt, the stack looks like the figure on the left. A series of RETURN instructions will repeatedly place the return addresses into the Program Counter and pop the stack. 0x0B 0x0A 0x09 0x08 0x07 TOSH:TOSL 2011 Microchip Technology Inc. 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address Preliminary STKPTR = 0x06 DS41458A-page 39 PIC16(L)F1526/27 FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.4.2 0x0F Return Address 0x0E Return Address 0x0D Return Address 0x0C Return Address 0x0B Return Address 0x0A Return Address 0x09 Return Address 0x08 Return Address 0x07 Return Address 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address When the stack is full, the next CALL or an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will not be overwritten. STKPTR = 0x10 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Word 2 is programmed to `1', the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. 3.5 Indirect Addressing The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return `0' and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: * Traditional Data Memory * Linear Data Memory * Program Flash Memory DS41458A-page 40 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 3-9: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. 2011 Microchip Technology Inc. Preliminary DS41458A-page 41 PIC16(L)F1526/27 3.5.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Direct Addressing 4 BSR 0 6 Indirect Addressing From Opcode 0 7 0 Bank Select Location Select FSRxH 0 0 0 7 FSRxL 0 0 Bank Select 00000 00001 00010 11111 Bank 0 Bank 1 Bank 2 Bank 31 Location Select 0x00 0x7F DS41458A-page 42 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 3.5.2 3.5.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank. The 16 bytes of common memory are not included in the linear data memory region. FIGURE 3-11: 7 FSRnH 0 0 1 LINEAR DATA MEMORY MAP 0 7 FSRnL To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower 8 bits of each memory location is accessible via INDF. Writing to the program Flash memory cannot be accomplished via the FSR/INDF interface. All instructions that access program Flash memory via the FSR/INDF interface will require one additional instruction cycle to complete. FIGURE 3-12: 7 1 0 PROGRAM FLASH MEMORY FSRnH PROGRAM FLASH MEMORY MAP 0 Location Select Location Select 0x2000 7 FSRnL 0x8000 0 0x0000 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Program Flash Memory (low 8 bits) Bank 2 0x16F 0xF20 Bank 30 0x29AF 2011 Microchip Technology Inc. 0xF6F Preliminary 0xFFFF 0x7FFF DS41458A-page 43 PIC16(L)F1526/27 NOTES: DS41458A-page 44 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 4.0 DEVICE CONFIGURATION Device Configuration consists of Configuration Word 1 and Configuration Word 2, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Word 2 is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. 2011 Microchip Technology Inc. Preliminary DS41458B-page 45 PIC16(L)F1526/27 REGISTER 4-1: CONFIGURATION WORD 1 R/P-1 R/P-1 R/P-1 FCMEN IESO CLKOUTEN R/P-1 R/P-1 U-1 BOREN<1:0> -- bit 13 R/P-1 R/P-1 R/P-1 CP MCLRE PWRTE bit 8 R/P-1 R/P-1 R/P-1 WDTE<1:0> R/P-1 R/P-1 FOSC<2:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `1' `0' = Bit is cleared `1' = Bit is set -n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 12 IESO: Internal External Switchover bit 1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled bit 11 CLKOUTEN: Clock Out Enable bit If FOSC configuration bits are set to LP, XT, HS modes: This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin. All other FOSC modes: 1 = CLKOUT function is disabled. I/O function on the CLKOUT pin. 0 = CLKOUT function is enabled on the CLKOUT pin bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the BORCON register 00 = BOR disabled bit 8 Unimplemented: Read as `1' bit 7 CP: Code Protection bit 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 6 MCLRE: MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3 bit. bit 5 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit 11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled DS41458B-page 46 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 REGISTER 4-1: bit 2-0 CONFIGURATION WORD 1 (CONTINUED) FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin 100 = INTOSC oscillator: I/O function on CLKIN pin 011 = EXTRC oscillator: External RC circuit connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins 001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins 000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins 2011 Microchip Technology Inc. Preliminary DS41458B-page 47 PIC16(L)F1526/27 REGISTER 4-2: CONFIGURATION WORD 2 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 LVP DEBUG LPBOR BORV STVREN -- bit 13 U-1 U-1 -- bit 8 U-1 -- -- R/P-1 (1) VCAPEN U-1 U-1 -- -- R/P-1 R/P-1 WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `1' `0' = Bit is cleared `1' = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit 1 = Low-voltage programming enabled 0 = High-voltage on MCLR must be used for programming bit 12 DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger bit 11 LPBOR: Low-Power BOR bit 1 = Low-Power BOR is disabled 0 = Low-Power BOR is enabled bit 10 BORV: Brown-out Reset Voltage Selection bit 1 = Brown-out Reset voltage set to 1.9V (typical) 0 = Brown-out Reset voltage set to 2.5V (typical) bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset bit 8-5 Unimplemented: Read as `1' bit 4 VCAPEN: Voltage Regulator Capacitor Enable bits(1) If PIC16LF1526/27 (regulator disabled): These bits are ignored. All VCAP pin functions are disabled. If PIC16F1526/27 (regulator enabled): 0 = VCAP functionality is enabled on RF0. 1 = All VCAP pin functions are disabled bit 3-2 Unimplemented: Read as `1' bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits 8 kW Flash memory (PIC16(L)F1526 only): 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to 1FFFh may be modified by PMCON control 01 = 000h to FFFh write-protected, 1000h to 1FFFh may be modified by PMCON control 00 = 000h to 1FFFh write-protected, no addresses may be modified by PMCON control 16 kW Flash memory (PIC16(L)F1527 only): 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to 3FFFh may be modified by PMCON control 01 = 000h to 1FFFh write-protected, 2000h to 3FFFh may be modified by PMCON control 00 = 000h to 3FFFh write-protected, no addresses may be modified by PMCON control Note 1: PIC16F1526/27 only. DS41458B-page 48 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 4.2 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection is controlled independently. Internal access to the program memory is unaffected by any code protection setting. 4.2.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Word 1. When CP = 0, external reads and writes of program memory are inhibited and a read will return all `0's. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section 4.3 "Write Protection" for more information. 4.3 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified. The WRT<1:0> bits in Configuration Word 2 define the size of the program memory block that is protected. 4.4 User ID Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section 11.5 "User ID, Device ID and Configuration Word Access" for more information on accessing these memory locations. For more information on checksum calculation, see the "PIC16F/LF151X/152X Memory Programming Specification" (DS41422). 2011 Microchip Technology Inc. Preliminary DS41458B-page 49 PIC16(L)F1526/27 4.5 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 11.5 "User ID, Device ID and Configuration Word Access" for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. REGISTER 4-3: DEVICEID: DEVICE ID REGISTER R R R R R R DEV<8:3> bit 13 R R bit 8 R R R DEV<2:0> R R R REV<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `1' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared P = Programmable bit bit 13-5 DEV<8:0>: Device ID bits DEVICEID<13:0> Values Device bit 4-0 DEV<8:0> REV<4:0> PIC16F1526 01 0101 100 x xxxx PIC16F1527 01 0101 101 x xxxx PIC16LF1526 01 0101 110 x xxxx PIC16LF1527 01 0101 111 x xxxx REV<4:0>: Revision ID bits These bits are used to identify the revision (see Table under DEV<8:0> above). DS41458B-page 50 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 5.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 5.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be supplied from one of two internal oscillators, with a choice of speeds selectable via software. Additional clock features include: * Selectable system clock source between external or internal sources via software. * Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution. * Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator. * Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources * Fast start-up oscillator allows internal circuits to power up and stabilize before switching to the 16 MHz HFINTOSC 2011 Microchip Technology Inc. The oscillator module can be configured in one of eight clock modes. 1. 2. 3. 4. 5. 6. 7. 8. ECL - External Clock Low Power mode (0 MHz to 0.5 MHz) ECM - External Clock Medium Power mode (0.5 MHz to 4 MHz) ECH - External Clock High Power mode (4 MHz to 20 MHz) LP - 32 kHz Low-Power Crystal mode. XT - Medium Gain Crystal or Ceramic Resonator Oscillator mode (up to 4 MHz) HS - High Gain Crystal or Ceramic Resonator mode (4 MHz to 20 MHz) RC - External Resistor-Capacitor (RC). INTOSC - Internal oscillator (31 kHz to 16 MHz). Clock Source modes are selected by the FOSC<2:0> bits in the Configuration Word 1. The FOSC bits determine the type of oscillator that will be used when the device is first powered. The EC Clock mode relies on an external logic level signal as the device clock source. The LP, XT and HS clock modes require an external crystal or resonator to be connected to the device. Each mode is optimized for a different frequency range. The RC Clock mode requires an external resistor and capacitor to set the oscillator frequency. The INTOSC internal oscillator block produces a low and high frequency clock source, designated LFINTOSC and HFINTOSC. (see Internal Oscillator Block, Figure 5-1). A wide selection of device clock frequencies may be derived from these two clock sources. Preliminary DS41458B-page 51 PIC16(L)F1526/27 SIMPLIFIED PIC(R) MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 5-1: Low Power Mode Event Switch (SCS<1:0>) Primary Oscillator OSC2 Primary Oscillator (OSC) 2 OSC1 Primary Clock 00 SOSCO/ T1CKI SOSCI Secondary Oscillator (SOSC) Secondary Clock INTOSC 01 1x Clock Switch MUX Secondary Oscillator Internal Oscillator IRCF<3:0> 4 Start-Up Osc LF-INTOSC (31.25 kHz) DS41458B-page 52 INTOSC Divide Circuit 16 MHz Primary Osc /1 /2 /4 /8 /16 HF-16 MHz /32 HF-500 kHz /64 HF-250 kHz HF-8 MHz HF-4 MHz HF-2 MHz HF-1 MHz /128 HF-125 kHz /256 HF-62.5 kHz /512 HF-31.25 kHz LF-31 kHz 1111 1110 1101 1100 1011 1010/ 0111 1001/ 0110 1000/ 0101 0100 0011 0010 0001 0000 Internal Oscillator MUX Start-up Control Logic 4 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 5.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. Internal clock sources are contained internally within the oscillator module. The internal oscillator block has two internal oscillators that are used to generate the internal system clock sources: the 16 MHz High-Frequency Internal Oscillator and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC). The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC(R) MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. FIGURE 5-2: 5.2.1 An external clock source can be used as the device system clock by performing one of the following actions: * Program the FOSC<2:0> bits in the Configuration Word 1 to select an external clock source that will be used as the default system clock upon a device Reset. * Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to: - Secondary oscillator during run-time, or - An external clock source determined by the value of the FOSC bits. See Section 5.3 "Clock Switching"for more information. 5.2.1.1 EC Mode The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure 5-2 shows the pin connections for EC mode. EC mode has three power modes to select from through Configuration Word 1: PIC(R) MCU FOSC/4 or I/O(1) Note 1: EXTERNAL CLOCK SOURCES OSC1/CLKIN Clock from Ext. System The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bits in the OSCCON register. See Section 5.3 "Clock Switching" for additional information. 5.2.1.2 EXTERNAL CLOCK (EC) MODE OPERATION OSC2/CLKOUT Output depends upon CLKOUTEN bit of the Configuration Word 1. LP, XT, HS Modes The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 5-3). The three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals). XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. Figure 5-3 and Figure 5-4 show typical circuits for quartz crystal and ceramic resonators, respectively. * High power, 4-20 MHz (FOSC = 111) * Medium power, 0.5-4 MHz (FOSC = 110) * Low power, 0-0.5 MHz (FOSC = 101) 2011 Microchip Technology Inc. Preliminary DS41458B-page 53 PIC16(L)F1526/27 FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) FIGURE 5-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) PIC(R) MCU PIC(R) MCU OSC1/CLKIN C1 Note 1: 2: C1 To Internal Logic Quartz Crystal C2 OSC1/CLKIN RS(1) RF(2) Sleep RP(3) OSC2/CLKOUT Note 1: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Applications Notes: DS41458B-page 54 RF(2) C2 Ceramic RS(1) Resonator A series resistor (RS) may be required for quartz crystals with low drive level. * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPIC(R) and PIC(R) Devices" (DS00826) * AN849, "Basic PIC(R) Oscillator Design" (DS00849) * AN943, "Practical PIC(R) Oscillator Analysis and Design" (DS00943) * AN949, "Making Your Oscillator Work" (DS00949) To Internal Logic Sleep OSC2/CLKOUT A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation. 5.2.1.3 Oscillator Start-up Timer (OST) If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 5.4 "Two-Speed Clock Start-up Mode"). Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 5.2.1.4 5.2.1.5 Secondary Oscillator External RC Mode The secondary oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins. The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. The secondary oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching. Refer to Section 5.3 "Clock Switching" for more information. The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the state of the CLKOUTEN bit in Configuration Word 1. FIGURE 5-5: Figure 5-6 shows the external RC mode connections. QUARTZ CRYSTAL OPERATION (SECONDARY OSCILLATOR) FIGURE 5-6: VDD OSC1/CLKIN SOSCI VSS FOSC/4 or I/O(1) SOSCO OSC2/CLKOUT Recommended values: 10 k REXT 100 k, <3V 3 k REXT 100 k, 3-5V CEXT > 20 pF, 2-5V Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Applications Notes: * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPIC(R) and PIC(R) Devices" (DS00826) * AN849, "Basic PIC(R) Oscillator Design" (DS00849) * AN943, "Practical PIC(R) Oscillator Analysis and Design" (DS00943) * AN949, "Making Your Oscillator Work" (DS00949) * TB097, "Interfacing a Micro Crystal MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS" (DS91097) * AN1288, "Design Practices for Low-Power External Oscillators" (DS01288) 2011 Microchip Technology Inc. Internal Clock CEXT To Internal Logic 32.768 kHz Quartz Crystal C2 PIC(R) MCU REXT PIC(R) MCU C1 EXTERNAL RC MODES Note 1: Output depends upon CLKOUTEN bit of the Configuration Word 1. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: * threshold voltage variation * component tolerances * packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used. Preliminary DS41458B-page 55 PIC16(L)F1526/27 5.2.2 INTERNAL CLOCK SOURCES 5.2.2.2 The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: * Program the FOSC<2:0> bits in Configuration Word 1 to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. * Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 5.3 "Clock Switching"for more information. In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the state of the CLKOUTEN bit in Configuration Word 1. LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). Select 31 kHz, via software, using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.4 "Internal Oscillator Clock Switch Timing" for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF<3:0> bits of the OSCCON register = 000) as the system clock source (SCS bits of the OSCCON register = 1x), or when any of the following are enabled: The internal oscillator block has two independent oscillators that provides the internal system clock source. * Configure the IRCF<3:0> bits of the OSCCON register for the desired LF frequency, and * FOSC<2:0> = 100, or * Set the System Clock Source (SCS) bits of the OSCCON register to `1x' 1. Peripherals that use the LFINTOSC are: 2. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 16 MHz. The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at 31 kHz. 5.2.2.1 HFINTOSC * Power-up Timer (PWRT) * Watchdog Timer (WDT) * Fail-Safe Clock Monitor (FSCM) The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized. The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source. The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). The frequency derived from the HFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.4 "Internal Oscillator Clock Switch Timing" for more information. The HFINTOSC is enabled by: * Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and * FOSC<2:0> = 100, or * Set the System Clock Source (SCS) bits of the OSCCON register to `1x'. The High-Frequency Internal Oscillator Ready bit (HFIOFR) of the OSCSTAT register indicates when the HFINTOSC is running and can be utilized. The High-Frequency Internal Oscillator Status Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value. DS41458B-page 56 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 5.2.2.3 Internal Oscillator Frequency Selection 5.2.2.4 The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register. The output of the 16 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). The Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators. One of the following frequencies can be selected via software: * * * * * * * * * * * Note: 2. 3. 4. 5. 6. 7. Following any Reset, the IRCF<3:0> bits of the OSCCON register are set to `0111' and the frequency selection is set to 500 kHz. The user can modify the IRCF bits to select a different frequency. The IRCF<3:0> bits of the OSCCON register allow duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes that use the same oscillator source. 2011 Microchip Technology Inc. When switching between the HFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 5-7). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows: 1. 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz (Default after Reset) 250 kHz 125 kHz 62.5 kHz 31.25 kHz 31 kHz (LFINTOSC) Internal Oscillator Clock Switch Timing IRCF<3:0> bits of the OSCCON register are modified. If the new clock is shut down, a clock start-up delay is started. Clock switch circuitry waits for a falling edge of the current clock. The current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. The new clock is now active. The OSCSTAT register is updated as required. Clock switch is complete. See Figure 5-7 for more details. If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 5-1. Start-up delay specifications are located in the oscillator tables of Section 25.0 "Electrical Specifications" Preliminary DS41458B-page 57 PIC16(L)F1526/27 FIGURE 5-7: HFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (FSCM and WDT disabled) HFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC 2-cycle Sync Running LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC HFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC IRCF <3:0> =0 0 System Clock DS41458B-page 58 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 5.3 5.3.3 Clock Switching SECONDARY OSCILLATOR The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins. * Default system oscillator determined by FOSC bits in Configuration Word 1 * Secondary oscillator 32 kHz crystal * Internal Oscillator Block (INTOSC) The secondary oscillator is enabled using the SOSCEN control bit in the TxCON register. See Section 18.0 "Timer1 Module with Gate Control" for more information about the Timer1 peripheral. 5.3.1 5.3.4 SYSTEM CLOCK SELECT (SCS) BITS The System Clock Select (SCS) bits of the OSCCON register selects the system clock source that is used for the CPU and peripherals. * When the SCS bits of the OSCCON register = 00, the system clock source is determined by value of the FOSC<2:0> bits in the Configuration Word 1. * When the SCS bits of the OSCCON register = 01, the system clock source is the secondary oscillator. * When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared. Note: SECONDARY OSCILLATOR READY (SOSCR) BIT The user must ensure that the secondary oscillator is ready to be used before it is selected as a system clock source. The Secondary Oscillator Ready (SOSCR) bit of the OSCSTAT register indicates whether the secondary oscillator is ready to be used. After the SOSCR bit is set, the SCS bits can be configured to select the secondary oscillator. Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 5-1. 5.3.2 OSCILLATOR START-UP TIME-OUT STATUS (OSTS) BIT The Oscillator Start-up Time-out Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word 1, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the secondary oscillator. 2011 Microchip Technology Inc. Preliminary DS41458B-page 59 PIC16(L)F1526/27 5.4 5.4.1 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC internal oscillator block as the clock source and go back to Sleep without waiting for the external oscillator to become stable. Two-Speed Start-up provides benefits when the oscillator module is configured for LP, XT or HS modes. The Oscillator Start-up Timer (OST) is enabled for these modes and must count 1024 oscillations before the oscillator can be used as the system clock source. TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: * IESO (of the Configuration Word 1) = 1; Internal/External Switchover bit (Two-Speed Start-up mode enabled). * SCS (of the OSCCON register) = 00. * FOSC<2:0> bits in the Configuration Word 1 configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after: * Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or * Wake-up from Sleep. If the oscillator module is configured for any mode other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep. If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT register is set and program execution switches to the external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear. TABLE 5-1: OSCILLATOR SWITCHING DELAYS Switch From Switch To Frequency Oscillator Delay Sleep/POR LFINTOSC HFINTOSC 31 kHz 31.25 kHz-16 MHz Oscillator Warm-up Delay (TWARM) Sleep/POR EC, RC DC - 20 MHz 2 cycles LFINTOSC EC, RC DC - 20 MHz 1 cycle of each Sleep/POR Secondary Oscillator, 32 kHz-20 MHz LP, XT, HS 1024 Clock Cycles (OST) Any clock source HFINTOSC 31.25 kHz-16 MHz 2 s (approx.) Any clock source LFINTOSC 31 kHz 1 cycle of each Any clock source Secondary Oscillator 32 kHz DS41458B-page 60 Preliminary 1024 Clock Cycles (OST) 2011 Microchip Technology Inc. PIC16(L)F1526/27 5.4.2 1. 2. 3. 4. 5. 6. 7. TWO-SPEED START-UP SEQUENCE 5.4.3 Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source. FIGURE 5-8: CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word 1, or the internal oscillator. TWO-SPEED START-UP INTOSC TOST OSC1 0 1 1022 1023 OSC2 Program Counter PC - N PC + 1 PC System Clock 2011 Microchip Technology Inc. Preliminary DS41458B-page 61 PIC16(L)F1526/27 5.5 5.5.3 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word 1. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, RC and secondary oscillator). FIGURE 5-9: FSCM BLOCK DIAGRAM External Clock LFINTOSC Oscillator / 64 31 kHz (~32 s) 488 Hz (~2 ms) S Q R Q Sample Clock 5.5.1 The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register. When the SCS bits are changed, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared and the device will be operating from the external clock source. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared. 5.5.4 Clock Monitor Latch RESET OR WAKE-UP FROM SLEEP The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating. Clock Failure Detected Note: FAIL-SAFE DETECTION The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 5-9. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. 5.5.2 FAIL-SAFE CONDITION CLEARING Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed. FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. DS41458B-page 62 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 2011 Microchip Technology Inc. Preliminary DS41458B-page 63 PIC16(L)F1526/27 5.6 Oscillator Control Registers REGISTER 5-1: U-0 OSCCON: OSCILLATOR CONTROL REGISTER R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 IRCF<3:0> -- U-0 R/W-0/0 R/W-0/0 SCS<1:0> -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits 000x = 31 kHz LF 001x = 31.25 kHz 0100 = 62.5 kHz 0101 = 125 kHz 0110 = 250 kHz 0111 = 500 kHz (default upon Reset) 1000 = 125 kHz(1) 1001 = 250 kHz(1) 1010 = 500 kHz(1) 1011 = 1 MHz 1100 = 2 MHz 1101 = 4 MHz 1110 = 8 MHz 1111 = 16 MHz bit 2 Unimplemented: Read as `0' bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Secondary oscillator 00 = Clock determined by FOSC<2:0> in Configuration Word 1. Note 1: Duplicate frequency derived from HFINTOSC. DS41458B-page 64 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q U-0 R-q/q R-0/q U-0 U-0 R-0/0 R-0/q SOSCR -- OSTS HFIOFR -- -- LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Conditional bit 7 SOSCR: Secondary Oscillator Ready bit If SOSCEN = 1: 1 = Secondary oscillator is ready 0 = Secondary oscillator is not ready If SOSCEN = 0: 1 = Timer1 clock source is always ready bit 6 Unimplemented: Read as `0' bit 5 OSTS: Oscillator Start-up Time-out Status bit 1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Word 1 0 = Running from an internal oscillator (FOSC<2:0> = 100) bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit 1 = HFINTOSC is ready 0 = HFINTOSC is not ready bit 3-2 Unimplemented: Read as `0' bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit 1 = HFINTOSC 16 MHz Oscillator is stable and is driving the INTOSC 0 = HFINTOSC 16 MHz is not stable, the 12 MHz Start-up Oscillator is driving INTOSC TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page OSCCON -- OSCSTAT SOSCR -- OSTS HFIOFR -- -- LFIOFR HFIOFS 65 PIE2 OSFIE TMR5GIE TMR3GIE -- BCL1IE TMR10IE TMR8IE CCP2IE 83 PIR2 OSFIF TMR5GIF TMR3GIF -- BCL1IF TMR10IF TMR8IF CCP2IF 85 SOSCEN T1SYNC -- TMR1ON 165 TMR1CS<1:0> T1CON Legend: CONFIG1 Legend: -- T1CKPS<1:0> SCS<1:0> 64 -- = unimplemented location, read as `0'. Shaded cells are not used by clock sources. TABLE 5-3: Name IRCF<3:0> Bits SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Bit -/7 Bit 13/5 Bit 12/4 Bit 11/3 FCMEN IESO CLKOUTEN MCLRE PWRTE -- 13:8 7:0 Bit -/6 CP Bit 10/2 Bit 9/1 BOREN<1:0> WDTE<1:0> FOSC<2:0> Bit 8/0 -- Register on Page 46 -- = unimplemented location, read as `0'. Shaded cells are not used by clock sources. 2011 Microchip Technology Inc. Preliminary DS41458B-page 65 PIC16(L)F1526/27 NOTES: DS41458B-page 66 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 6.0 A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 6-1. RESETS There are multiple ways to reset this device: * * * * * * * * * Power-on Reset (POR) Brown-out Reset (BOR) Low-Power Brown-out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event. FIGURE 6-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Stack Overflow/Underflow Reset Pointer External Reset MCLRE MCLR Sleep WDT Time-out Device Reset Power-on Reset VDD Brown-out Reset LPBOR Reset BOR Enable PWRT Zero LFINTOSC 64 ms PWRTEN 2011 Microchip Technology Inc. Preliminary DS41458B-page 67 PIC16(L)F1526/27 6.1 Power-on Reset (POR) 6.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. 6.1.1 * * * * POWER-UP TIMER (PWRT) The Power-up Timer provides a nominal 64 ms time-out on POR or Brown-out Reset. The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration Word 1. The Power-up Timer starts after the release of the POR and BOR. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting" (DS00607). TABLE 6-1: The Brown-out Reset module has four operating modes controlled by the BOREN<1:0> bits in Configuration Word 1. The four operating modes are: BOR is always on BOR is off when in Sleep BOR is controlled by software BOR is always off Refer to Table 6-1 for more information. The Brown-out Reset voltage level is selectable by configuring the BORV bit in Configuration Word 2. A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a duration greater than parameter TBORDC, the device will reset. See Figure 6-2 for more information. BOR OPERATING MODES BOREN<1:0> SBOREN Device Mode BOR Mode Device Operation Device Operation upon wake- up from upon release of POR Sleep 11 X X Active Waits for BOR ready(1) Awake Active 10 X Sleep Disabled 1 01 X 0 00 X X Waits for BOR ready Active Begins immediately Disabled Begins immediately Disabled Begins immediately Note 1: Even though this case specifically waits for the BOR, the BOR is already operating, so there is no delay in start-up. 6.2.1 BOR IS ALWAYS ON 6.2.3 BOR CONTROLLED BY SOFTWARE When the BOREN bits of Configuration Word 1 are set to `11', the BOR is always on. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. When the BOREN bits of Configuration Word 1 are set to `01', the BOR is controlled by the SBOREN bit of the BORCON register. The device start-up is not delayed by the BOR ready condition or the VDD level. BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep. BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register. 6.2.2 BOR IS OFF IN SLEEP When the BOREN bits of Configuration Word 1 are set to `10', the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is unchanged by Sleep. BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready. DS41458B-page 68 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 6-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: TPWRT(1) TPWRT delay only if PWRTE bit is programmed to `0'. REGISTER 6-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u SBOREN BORFS -- -- -- -- -- BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit(1) If BOREN <1:0> 01: SBOREN is read/write, but has no effect on the BOR. If BOREN <1:0> = 01: 1 = BOR Enabled 0 = BOR Disabled bit 6 BORFS: Brown-out Reset Fast Start bit(1) If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off) BORFS is Read/Write, but has no effect. If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control): 1 = Band gap is forced on always (covers sleep/wake-up/operating cases) 0 = Band gap operates normally, and may turn off bit 5-1 Unimplemented: Read as `0' bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive Note 1: BOREN<1:0> bits are located in Configuration Word 1. 2011 Microchip Technology Inc. Preliminary DS41458B-page 69 PIC16(L)F1526/27 6.3 Low-Power Brown-out Reset (LPBOR) 6.5 The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to Figure 6-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 6-2. 6.3.1 ENABLING LPBOR The LPBOR is controlled by the LPBOR bit of Configuration Word 2. When the device is erased, the LPBOR module defaults to disabled. 6.3.1.1 LPBOR Module Output The output of the LPBOR module is a signal indicating whether or not a Reset is to be asserted. This signal is to be OR'd together with the Reset signal of the BOR module to provide the generic BOR signal which goes to the PCON register and to the power control block. 6.4 MCLR Watchdog Timer (WDT) Reset The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO and PD bits in the STATUS register are changed to indicate the WDT Reset. See Section 10.0 "Watchdog Timer" for more information. 6.6 RESET Instruction A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to `0'. See Table 6-4 for default conditions after a RESET instruction has occurred. 6.7 Stack Overflow/Underflow Reset The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Word 2. See Section 3.4.2 "Overflow/Underflow Reset" for more information. 6.8 Programming Mode Exit Upon exit of Programming mode, the device will behave as if a POR had just occurred. The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Word 1 and the LVP bit of Configuration Word 2 (Register 4-2). 6.9 TABLE 6-2: The Power-up Timer is controlled by the PWRTE bit of Configuration Word 1. MCLR CONFIGURATION MCLRE LVP MCLR 0 0 Disabled 1 0 Enabled x 1 Enabled 6.4.1 MCLR ENABLED A Reset does not drive the MCLR pin low. MCLR DISABLED When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See Section 12.6 "PORTE Registers" for more information. DS41458B-page 70 Start-up Sequence Upon the release of a POR or BOR, the following must occur before the device will begin executing: The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. 6.4.2 The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to allow VDD to stabilize before allowing the device to start running. 6.10 When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up. Note: Power-Up Timer 1. 2. 3. Power-up Timer runs to completion (if enabled). Oscillator start-up timer runs to completion (if required for oscillator source). MCLR must be released (if enabled). The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See Section 5.0 "Oscillator Module (With Fail-Safe Clock Monitor)" for more information. The Power-up Timer and oscillator start-up timer run independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer and oscillator start-up timer will expire. Upon bringing MCLR high, the device will begin execution immediately (see Figure 6-3). This is useful for testing purposes or to synchronize more than one device operating in parallel. Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 6-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-Up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC 2011 Microchip Technology Inc. Preliminary DS41458B-page 71 PIC16(L)F1526/27 6.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers. TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition 0 0 1 1 1 0 x 1 1 Power-on Reset 0 0 1 1 1 0 x 0 x Illegal, TO is set on POR 0 0 1 1 1 0 x x 0 Illegal, PD is set on POR 0 0 u 1 1 u 0 1 1 Brown-out Reset u u 0 u u u u 0 u WDT Reset u u u u u u u 0 0 WDT Wake-up from Sleep u u u u u u u 1 0 Interrupt Wake-up from Sleep u u u 0 u u u u u MCLR Reset during normal operation u u u 0 u u u 1 0 MCLR Reset during Sleep u u u u 0 u u u u RESET Instruction Executed 1 u u u u u u u u Stack Overflow Reset (STVREN = 1) u 1 u u u u u u u Stack Underflow Reset (STVREN = 1) TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS(2) Program Counter STATUS Register PCON Register Power-on Reset 0000h ---1 1000 00-1 110x MCLR Reset during normal operation 0000h ---u uuuu uu-u 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-u 0uuu WDT Reset 0000h ---0 uuuu uu-0 uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-u uuuu Brown-out Reset 0000h ---1 1uuu 00-1 11u0 ---1 0uuu uu-u uuuu ---u uuuu uu-u u0uu Condition Interrupt Wake-up from Sleep RESET Instruction Executed PC + 1 (1) 0000h Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-u uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-u uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 2: If a Status bit is not implemented, that bit will be read as `0'. DS41458B-page 72 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 6.12 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: * * * * * * * Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) The PCON register bits are shown in Register 6-2. REGISTER 6-2: PCON: POWER CONTROL REGISTER R/W/HS-0/q R/W/HS-0/q U-0 STKOVF STKUNF -- R/W/HC-1/q R/W/HC-1/q RWDT RMCLR R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u RI POR BOR bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or set to `0' by firmware bit 6 STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or set to `0' by firmware bit 5 Unimplemented: Read as `0' bit 4 RWDT: Watchdog Timer Reset Flag bit 1 = A Watchdog Timer Reset has not occurred or set to `1' by firmware 0 = A Watchdog Timer Reset has occurred (set to `0' in hardware when a Watchdog Timer Reset) bit 3 RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set to `1' by firmware 0 = A MCLR Reset has occurred (set to `0' in hardware when a MCLR Reset occurs) bit 2 RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set to `1' by firmware 0 = A RESET instruction has been executed (set to `0' in hardware upon executing a RESET instruction) bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2011 Microchip Technology Inc. Preliminary DS41458B-page 73 PIC16(L)F1526/27 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN BORFS -- -- -- -- -- BORRDY 69 PCON STKOVF STKUNF -- RWDT RMCLR RI POR BOR 73 STATUS -- -- -- TO PD Z DC C 23 WDTCON -- -- SWDTEN 99 WDTPS<4:0> Legend: -- = unimplemented bit, reads as `0'. Shaded cells are not used by Resets. DS41458B-page 74 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 7.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: * * * * * Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce Interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure 7-1. FIGURE 7-1: INTERRUPT LOGIC TMR0IF TMR0IE Peripheral Interrupts (TMR1IF) PIR1<0> (TMR1IF) PIR1<0> Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE Interrupt to CPU PEIE PIRn<7> PIEn<7> 2011 Microchip Technology Inc. GIE Preliminary DS41458B-page 75 PIC16(L)F1526/27 7.1 Operation 7.2 Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: * GIE bit of the INTCON register * Interrupt Enable bit(s) for the specific interrupt event(s) * PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIEx register) Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is 3 or 4 instruction cycles. For asynchronous interrupts, the latency is 3 to 5 instruction cycles, depending on when the interrupt occurs. See Figure 7-2 and Figure 7-3 for more details. The INTCON and PIRx registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: * Current prefetched instruction is flushed * GIE bit is cleared * Current Program Counter (PC) is pushed onto the stack * Critical registers are automatically saved to the shadow registers (See Section 7.5 "Automatic Context Saving") * PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. For additional information on a specific interrupt's operation, refer to its peripheral chapter. Note 1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. DS41458B-page 76 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 7-2: INTERRUPT LATENCY OSC1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKOUT Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NOP Inst(0004h) Interrupt GIE PC Execute PC-1 PC 2 Cycle Instruction at PC Interrupt GIE PC Execute PC-1 PC 3 Cycle Instruction at PC Interrupt GIE PC Execute PC-1 PC 3 Cycle Instruction at PC 2011 Microchip Technology Inc. Preliminary PC+2 NOP NOP DS41458B-page 77 PIC16(L)F1526/27 FIGURE 7-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF Interrupt Latency (2) (5) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC - 1) PC + 1 Inst (PC + 1) PC + 1 -- Dummy Cycle Inst (PC) 0004h 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT not available in all oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 25.0 "Electrical Specifications". 5: INTF is enabled to be set any time during the Q4-Q1 cycles. DS41458B-page 78 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 7.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to the Section 8.0 "Power-Down Mode (Sleep)" for more details. 7.4 INT Pin The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. 7.5 Automatic Context Saving Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the Shadow registers: * * * * * W register STATUS register (except for TO and PD) BSR register FSR registers PCLATH register Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user's application, other registers may also need to be saved. 2011 Microchip Technology Inc. Preliminary DS41458B-page 79 PIC16(L)F1526/27 7.6 Interrupt Control Registers Note: 7.6.1 INTCON REGISTER The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, interrupt-on-change and external INT pin interrupts. REGISTER 7-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 GIE: Global Interrupt Enable bit 1 = Enables all active interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 3 IOCIE: Interrupt-on-Change Interrupt Enable bit 1 = Enables the interrupt-on-change interrupt 0 = Disables the interrupt-on-change interrupt bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed 0 = TMR0 register did not overflow bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(1) 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state Note 1: The IOCIF flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCBF register have been cleared by software. DS41458B-page 80 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 7.6.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as shown in Register 7-2. REGISTER 7-2: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 Gate Acquisition interrupt 0 = Disables the Timer1 Gate Acquisition interrupt bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RC1IE: USART1 Receive Interrupt Enable bit 1 = Enables the USART1 receive interrupt 0 = Disables the USART1 receive interrupt bit 4 TX1IE: USART1 Transmit Interrupt Enable bit 1 = Enables the USART1 transmit interrupt 0 = Disables the USART1 transmit interrupt bit 3 SSP1IE: Synchronous Serial Port (MSSP1) Interrupt Enable bit 1 = Enables the MSSP1 interrupt 0 = Disables the MSSP1 interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt 2011 Microchip Technology Inc. Preliminary DS41458B-page 81 PIC16(L)F1526/27 7.6.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as shown in Register 7-3. REGISTER 7-3: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OSFIE TMR5GIE TMR3GIE -- BCL1IE TMR10IE TMR8IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt bit 6 TMR5GIE: Timer5 Gate Interrupt Enable bit 1 = Enables the Timer5 Gate Acquisition interrupt 0 = Disables the Timer5 Gate Acquisition interrupt bit 5 TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enables the Timer3 Gate Acquisition interrupt 0 = Disables the Timer3 Gate Acquisition interrupt bit 4 Unimplemented: Read as `0' bit 3 BCL1IE: MSSP1 Bus Collision Interrupt Enable bit 1 = Enables the MSSP1 Bus Collision Interrupt 0 = Disables the MSSP1 Bus Collision Interrupt bit 2 TMR10IE: TMR10 to PR10 Match Interrupt Enable bit 1 = Enables the Timer10 to PR10 match interrupt 0 = Disables the Timer10 to PR10 match interrupt bit 1 TMR8IE: TMR8 to PR8 Match Interrupt Enable bit 1 = Enables the Timer8 to PR8 match interrupt 0 = Disables the Timer8 to PR8 match interrupt bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt DS41458B-page 82 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 7.6.4 PIE3 REGISTER The PIE3 register contains the interrupt enable bits, as shown in Register 7-4. REGISTER 7-4: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CCP6IE CCP5IE CCP4IE CCP3IE TMR6IE TMR5IE TMR4IE TMR3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 CCP6IE: CCP6 Interrupt Enable bit 1 = Enables the CCP6 interrupt 0 = Disables the CCP6 interrupt bit 6 CCP5IE: CCP5 Interrupt Enable bit 1 = Enables the CCP5 interrupt 0 = Disables the CCP5 interrupt bit 5 CCP4IE: CCP4 Interrupt Enable bit 1 = Enables the CCP4 interrupt 0 = Disables the CCP4 interrupt bit 4 CCP3IE: CCP3 Interrupt Enable bit 1 = Enables the CCP3 interrupt 0 = Disables the CCP3 interrupt bit 3 TMR6IE: TMR6 to PR6 Match Interrupt Enable bit 1 = Enables the TMR6 to PR6 Match interrupt 0 = Disables the TMR6 to PR6 Match interrupt bit 2 TMR5IE: Timer5 Overflow Interrupt Enable bit 1 = Enables the Timer5 overflow interrupt 0 = Disables the Timer5 overflow interrupt bit 1 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enables the TMR4 to PR4 Match interrupt 0 = Disables the TMR4 to PR4 Match interrupt bit 0 TMR3IE: Timer3 Overflow Interrupt Enable bit 1 = Enables the Timer3 overflow interrupt 0 = Disables the Timer3 overflow interrupt 2011 Microchip Technology Inc. Preliminary DS41458B-page 83 PIC16(L)F1526/27 7.6.5 PIE4 REGISTER The PIE4 register contains the interrupt enable bits, as shown in Register 7-5. REGISTER 7-5: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 CCP10IE: CCP10 Interrupt Enable bit 1 = Enables the CCP10 interrupt 0 = Disables the CCP10 interrupt bit 6 CCP9IE: CCP9 Interrupt Enable bit 1 = Enables the CCP9 interrupt 0 = Disables the CCP9 interrupt bit 5 RC2IE: USART2 Receive Interrupt Enable bit 1 = Enables the USART2 receive interrupt 0 = Disables the USART2 receive interrupt bit 4 TX2IE: USART2 Transmit Interrupt Enable bit 1 = Enables the USART2 transmit interrupt 0 = Disables the USART2 transmit interrupt bit 3 CCP8IE: CCP8 Interrupt Enable bit 1 = Enables the CCP8 interrupt 0 = Disables the CCP8 interrupt bit 2 CCP7IE: CCP7 Interrupt Enable bit 1 = Enables the CCP7 interrupt 0 = Disables the CCP7 interrupt bit 1 BCL2IE: MSSP2 Bus Collision Interrupt Enable bit 1 = Enables the MSSP2 Bus Collision Interrupt 0 = Disables the MSSP2 Bus Collision Interrupt bit 0 SSP2IE: Synchronous Serial Port (MSSP2) Interrupt Enable bit 1 = Enables the MSSP2 interrupt 0 = Disables the MSSP2 interrupt DS41458B-page 84 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 7.6.6 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as shown in Register 7-6. REGISTER 7-6: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 RC1IF: USART1 Receive Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 TX1IF: USART1 Transmit Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 SSP1IF: Synchronous Serial Port (MSSP1) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 CCP1IF: CCP1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending 2011 Microchip Technology Inc. Preliminary DS41458B-page 85 PIC16(L)F1526/27 7.6.7 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as shown in Register 7-7. REGISTER 7-7: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OSFIF TMR5GIF TMR3GIF -- BCL1IF TMR10IF TMR8IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 TMR5GIF: Timer5 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 TMR3GIF: Timer3 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 Unimplemented: Read as `0' bit 3 BCL1IF: MSSP1 Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 TMR10IF: Timer10 to PR10 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR8IF: Timer8 to PR8 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 CCP2IF: CCP2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending DS41458B-page 86 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 7.6.8 PIR3 REGISTER The PIR3 register contains the interrupt flag bits, as shown in Register 7-8. REGISTER 7-8: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CCP6IF CCP5IF CCP4IF CCP3IF TMR6IF TMR5IF TMR4IF TMR3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 CCP6IF: CCP6 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 CCP5IF: CCP5 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 CCP4IF: CCP4 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 CCP3IF: CCP3 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 TMR6IF: TMR6 to PR6 Match Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 TMR5IF: Timer5 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 TMR3IF: Timer3 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending 2011 Microchip Technology Inc. Preliminary DS41458B-page 87 PIC16(L)F1526/27 7.6.9 PIR4 REGISTER The PIR4 register contains the interrupt flag bits, as shown in Register 7-9. REGISTER 7-9: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 CCP10IF: CCP10 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 CCP9IF: CCP9 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 RC2IF: USART2 Receive Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 TX2IF: USART2 Transmit Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 CCP8IF: CCP8 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 CCP7IF: CCP7 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 BCL2IF: MSSP2 Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 SSP2IF: Synchronous Serial Port (MSSP2) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending DS41458B-page 88 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 TABLE 7-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 INTCON Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 80 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 143 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 143 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 143 WPUEN INTEDG TMR0CS TMR0SE PSA PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 81 PIE2 OSFIE TMR5GIE TMR3GIE -- BCLIE TMR10IE TMR8IE CCP2IE 82 PIE3 CCP6IE CCP5IE CCP4IE CCP3IE TMR6IE TMR5IE TMR4IE TMR3IE 83 PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 84 PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 85 PIR2 OSFIF TMR5GIF TMR3GIF -- BCL1IF TMR10IF TMR8IF CCP2IF 86 PIR3 CCP6IF CCP5IF CCP4IF CCP3IF TMR6IF TMR5IF TMR4IF TMR3IF 87 PIR4 CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF 88 OPTION_REG Legend: PS<2:0> 165 -- = unimplemented locations read as `0'. Shaded cells are not used by Interrupts. 2011 Microchip Technology Inc. Preliminary DS41458B-page 89 PIC16(L)F1526/27 NOTES: DS41458B-page 90 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 8.0 POWER-DOWN MODE (SLEEP) 8.1 Wake-up from Sleep The Power-Down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 1. 2. 3. 4. 5. 6. 7. 8. 9. WDT will be cleared but keeps running, if enabled for operation during Sleep. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. CPU clock is disabled. 31 kHz LFINTOSC is unaffected and peripherals that operate from it may continue operation in Sleep. Secondary oscillator is unaffected and peripherals that operate from it may continue operation in Sleep. ADC is unaffected, if the dedicated FRC clock is selected. I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance). Resets other than WDT are not affected by Sleep mode. Refer to individual chapters for more details on peripheral operation during Sleep. To minimize current consumption, the following conditions should be considered: * * * * * * I/O pins should not be floating External circuitry sinking current from I/O pins Internal circuitry sourcing current from I/O pins Current draw from pins with internal weak pull-ups Modules using 31 kHz LFINTOSC Modules using Secondary oscillator External Reset input on MCLR pin, if enabled BOR Reset, if enabled POR Reset Watchdog Timer, if enabled Any external interrupt Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information) The first three events will cause a device Reset. The last three events are considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to Section 6.11 "Determining the Cause of a Reset". When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction, the device will call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs. Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules. See Section 8.0 "Digital-to-Analog Converter (DAC) Module" and Section 14.0 "Fixed Voltage Reference (FVR)" for more information on these modules. 2011 Microchip Technology Inc. Preliminary DS41458B-page 91 PIC16(L)F1526/27 8.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP. - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction FIGURE 8-1: - SLEEP instruction will be completely executed - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared - TO bit of the STATUS register will be set - PD bit of the STATUS register will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1(1) TOST(3) CLKOUT(2) Interrupt flag Interrupt Latency (4) GIE bit (INTCON reg.) Processor in Sleep Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: PC Inst(PC) = Sleep Inst(PC - 1) PC + 1 PC + 2 PC + 2 Inst(PC + 1) Inst(PC + 2) Sleep Inst(PC + 1) PC + 2 Dummy Cycle 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) XT, HS or LP Oscillator mode assumed. CLKOUT is not available in XT, HS or LP Oscillator modes, but shown here for timing reference. TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes. DS41458B-page 92 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 8.2 8.2.2 Low-Power Sleep Mode The PIC16F1526 device contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode. The PIC16F1526 allows the user to optimize the operating current in Sleep, depending on the application requirements. A Low-Power Sleep mode can be selected by setting the VREGPM bit of the VREGCON register. With this bit set, the LDO and reference circuitry are placed in a low-power state when the device is in Sleep. 8.2.1 Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected. The LDO will remain in the normal power mode when those peripherals are enabled. The Low-Power Sleep mode is intended for use with these peripherals: * * * * * Brown-Out Reset (BOR) Watchdog Timer (WDT) External interrupt pin/Interrupt-on-change pins Timer1 (with external clock source) CCP (Capture mode) Note: SLEEP CURRENT VS. WAKE-UP TIME PERIPHERAL USAGE IN SLEEP In the Default Operating mode, the LDO and reference circuitry remain in the normal configuration while in Sleep. The device is able to exit Sleep mode quickly since all circuits remain active. In Low-Power Sleep mode, when waking up from Sleep, an extra delay time is required for these circuits to return to the normal configuration and stabilize. The PIC16LF1526/27 does not have a configurable Low-Power Sleep mode. PIC16LF1526/27 is an unregulated device and is always in the lowest power state when in Sleep, with no wake-up time penalty. This device has a lower maximum VDD and I/O voltage than the PIC16LF1526/27. See Section 25.0 "Electrical Specifications" for more information. The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time. The normal mode is beneficial for applications that need to wake from Sleep quickly and frequently. 2011 Microchip Technology Inc. Preliminary DS41458B-page 93 PIC16(L)F1526/27 8.3 Power Control Registers VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1) REGISTER 8-1: U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1 -- -- -- -- -- -- VREGPM Reserved bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-2 Unimplemented: Read as `0' bit 1 VREGPM: Voltage Regulator Power Mode Selection bit 1 = Low-Power Sleep mode enabled in Sleep(2) Draws lowest current in Sleep, slower wake-up 0 = Normal Power mode enabled in Sleep(2) Draws higher current in Sleep, faster wake-up bit 0 Reserved: Read as `1'. Maintain this bit set. Note 1: 2: PIC16F1526/27 only. See Section 25.0 "Electrical Specifications". TABLE 8-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Bit 7 INTCON Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 80 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 143 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 143 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 143 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 81 PIE2 OSFIE TMR5GIE TMR3GIE -- BCLIE TMR10IE TMR8IE CCP2IE 82 PIE3 CCP6IE CCP5IE CCP4IE CCP3IE TMR6IE TMR5IE TMR4IE TMR3IE 83 PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 84 PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 85 PIE1 PIR2 OSFIF TMR5GIF TMR3GIF -- BCL1IF TMR10IF TMR8IF CCP2IF 86 PIR3 CCP6IF CCP5IF CCP4IF CCP3IF TMR6IF TMR5IF TMR4IF TMR3IF 87 PIR4 CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF 88 STATUS -- -- -- TO PD Z DC C 23 VREGCON(1) -- -- -- -- -- -- VREGPM Reserved 94 WDTCON -- -- SWDTEN 99 Legend: Note 1: WDTPS<4:0> -- = unimplemented, read as `0'. Shaded cells are not used in Power-down mode. PIC16F1526/27 only. DS41458B-page 94 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 9.0 LOW DROPOUT (LDO) VOLTAGE REGULATOR The PIC16F1526/27 has an internal Low Dropout Regulator (LDO) which provides operation above 3.6V. The LDO regulates a voltage for the internal device logic while permitting the VDD and I/O pins to operate at a higher voltage. There is no user enable/disable control available for the LDO, it is always active. The PIC16LF1526/27 operates at a maximum VDD of 3.6V and does not incorporate an LDO. On power-up, the external capacitor will load the LDO voltage regulator. To prevent erroneous operation, the device is held in Reset while a constant current source charges the external capacitor. After the cap is fully charged, the device is released from Reset. For more information on recommended capacitor values and the constant current rate, refer to the LDO Regulator Characteristics Table in Section 25.0 "Electrical Specifications". A device I/O pin may be configured as the LDO voltage output, identified as the VCAP pin. Although not required, an external low-ESR capacitor may be connected to the VCAP pin for additional regulator stability. The VCAPEN bit of Configuration Word 2 enables the VCAP pin. Refer to Table 9-1. TABLE 9-1: VCAPEN SELECT BIT Pin VCAPEN 0 RF0 1 No Vcap TABLE 9-2: Name CONFIG2 Legend: Note 1: SUMMARY OF CONFIGURATION WORD WITH LDO Bits Bit -/7 13:8 7:0 Bit -/6 -- -- -- Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 LVP DEBUG LPBOR BORV STVREN -- -- VCAPEN(1) -- -- WRT<1:0> Register on Page 48 -- = unimplemented locations read as `0'. Shaded cells are not used by LDO. PIC16F1526/27 only. 2011 Microchip Technology Inc. Preliminary DS41458B-page 95 PIC16(L)F1526/27 NOTES: DS41458B-page 96 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 10.0 WATCHDOG TIMER The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events. The WDT has the following features: * Independent clock source * Multiple operating modes - WDT is always on - WDT is off when in Sleep - WDT is controlled by software - WDT is always off * Configurable time-out period is from 1 ms to 256 seconds (typical) * Multiple Reset conditions * Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> = 01 SWDTEN WDTE<1:0> = 11 LFINTOSC 23-bit Programmable Prescaler WDT WDT Time-out WDTE<1:0> = 10 Sleep 2011 Microchip Technology Inc. WDTPS<4:0> Preliminary DS41458B-page 97 PIC16(L)F1526/27 10.1 Independent Clock Source 10.3 The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1ms. See Section 25.0 "Electrical Specifications" for the LFINTOSC tolerances. 10.2 WDT IS ALWAYS ON When the WDTE bits of Configuration Word 1 are set to `11', the WDT is always on. WDT protection is active during Sleep. 10.2.2 WDT protection is not active during Sleep. WDT CONTROLLED BY SOFTWARE When the WDTE bits of Configuration Word 1 are set to `01', the WDT is controlled by the SWDTEN bit of the WDTCON register. WDT protection is unchanged Table 10-1 for more details. TABLE 10-1: by Sleep. See WDT OPERATING MODES WDTE<1:0> SWDTEN Device Mode WDT Mode 11 X X Active Awake Active 10 X Sleep Disabled 1 X 01 0 00 TABLE 10-2: X X 10.4 Clearing the WDT * * * * * * * Any Reset CLRWDT instruction is executed Device enters Sleep Device wakes up from Sleep Oscillator fail event WDT is disabled OST is running See Table 10-2 for more information. WDT IS OFF IN SLEEP When the WDTE bits of Configuration Word 1 are set to `10', the WDT is on, except in Sleep. 10.2.3 The WDTPS bits of the WDTCON register set the time-out period from 1ms to 256 seconds (nominal). After a Reset, the default time-out period is 2 seconds. The WDT is cleared when any of the following conditions occur: WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Word 1. See Table 10-1. 10.2.1 Time-Out Period 10.5 Operation During Sleep When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes counting. When the device exits Sleep, the WDT is cleared again. The WDT remains clear until the OST, if enabled, completes. See Section 5.0 "Oscillator Module (With Fail-Safe Clock Monitor)" for more information on the OST. When a WDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits in the STATUS register are changed to indicate the event. See Section 3.0 "Memory Organization" and The STATUS register (Register 3-1) for more information. Active Disabled Disabled WDT CLEARING CONDITIONS Conditions WDT WDTE<1:0> = 00 WDTE<1:0> = 01 and SWDTEN = 0 WDTE<1:0> = 10 and enter Sleep Cleared CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = SOSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Change INTOSC divider (IRCF bits) DS41458B-page 98 Unaffected Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 10.6 Watchdog Control Register REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 -- -- R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 WDTPS<4:0> bit 7 R/W-0/0 SWDTEN bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits(1) Bit Value = Prescale Rate 00000 = 1:32 (Interval 1 ms nominal) 00001 = 1:64 (Interval 2 ms nominal) 00010 = 1:128 (Interval 4 ms nominal) 00011 = 1:256 (Interval 8 ms nominal) 00100 = 1:512 (Interval 16 ms nominal) 00101 = 1:1024 (Interval 32 ms nominal) 00110 = 1:2048 (Interval 64 ms nominal) 00111 = 1:4096 (Interval 128 ms nominal) 01000 = 1:8192 (Interval 256 ms nominal) 01001 = 1:16384 (Interval 512 ms nominal) 01010 = 1:32768 (Interval 1s nominal) 01011 = 1:65536 (Interval 2s nominal) (Reset value) 01100 = 1:131072 (217) (Interval 4s nominal) 01101 = 1:262144 (218) (Interval 8s nominal) 01110 = 1:524288 (219) (Interval 16s nominal) 01111 = 1:1048576 (220) (Interval 32s nominal) 10000 = 1:2097152 (221) (Interval 64s nominal) 10001 = 1:4194304 (222) (Interval 128s nominal) 10010 = 1:8388608 (223) (Interval 256s nominal) 10011 = Reserved. Results in minimum interval (1:32) * * * 11111 =Reserved. Results in minimum interval (1:32) bit 0 Note 1: SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. Times are approximate. WDT time is based on 31 kHz LFINTOSC. 2011 Microchip Technology Inc. Preliminary DS41458B-page 99 PIC16(L)F1526/27 TABLE 10-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Bit 7 Bit 6 Bit 5 -- OSCCON -- STATUS -- -- WDTCON -- -- Legend: CONFIG1 Legend: Bit 3 IRCF<3:0> Bit 2 -- TO PD Bit 1 Bit 0 SCS<1:0> Z DC WDTPS<4:0> Register on Page 64 C 23 SWDTEN 99 x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by Watchdog Timer. TABLE 10-4: Name Bit 4 SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER Bits Bit -/7 13:8 7:0 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 FCMEN IESO CLKOUTEN MCLRE PWRTE -- CP Bit 10/2 Bit 9/1 BOREN<1:0> WDTE<1:0> FOSC<2:0> Bit 8/0 -- Register on Page 46 -- = unimplemented location, read as `0'. Shaded cells are not used by Watchdog Timer. DS41458B-page 100 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 11.0 11.1.1 FLASH PROGRAM MEMORY CONTROL The Flash program memory is readable and writable during normal operation over the full VDD range. Program memory is indirectly addressed using Special Function Registers (SFRs). The SFRs used to access program memory are: * * * * * * PMCON1 PMCON2 PMDATL PMDATH PMADRL PMADRH When accessing the program memory, the PMDATH:PMDATL register pair forms a 2-byte word that holds the 14-bit data for read/write, and the PMDATH:PMDATL register pair forms a 2-byte word that holds the 15-bit address of the program memory location being read. The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the operating voltage range of the device. The Flash program memory can be protected in two ways; by code protection (CP bit in Configuration Word 1) and write protection (WRT<1:0> bits in Configuration Word 2). Code protection (CP = 0)(1), disables access, reading and writing, to the Flash program memory via external device programmers. Code protection does not affect the self-write and erase functionality. Code protection can only be reset by a device programmer performing a bulk erase to the device, clearing all Flash program memory, Configuration bits and User IDs. Write protection prohibits self-write and erase to a portion or all of the Flash program memory as defined by the bits WRT<1:0>. Write protection does not affect a device programmers ability to read, write or erase the device. PMCON1 is the control register for Flash program memory accesses. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared by hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation to occur. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and execute the appropriate error handling routine. The PMCON2 register is a write-only register. Attempting to read the PMCON2 register will return all `0's. To enable writes to the program memory, a specific pattern (the unlock sequence), must be written to the PMCON2 register. The required unlock sequence prevents inadvertent writes to the program memory write latches and Flash program memory. 11.2 After a row has been erased, the user can reprogram all or a portion of this row. Data to be written into the program memory row is written to 14-bit wide data write latches. These write latches are not directly accessible to the user, but may be loaded via sequential writes to the PMDATH:PMDATL register pair. Note: PMADRL and PMADRH Registers The PMADRH:PMADRL register pair can address up to a maximum of 32K words of program memory. When selecting a program address value, the MSB of the address is written to the PMADRH register and the LSB is written to the PMADRL register. 2011 Microchip Technology Inc. Flash Program Memory Overview It is important to understand the Flash program memory structure for erase and programming operations. Flash program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum size that can be erased by user software. Note 1: Code protection of the entire Flash program memory array is enabled by clearing the CP bit of Configuration Word 1. 11.1 PMCON1 AND PMCON2 REGISTERS If the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in RAM prior to the erase. Then, new data and retained data can be written into the write latches to reprogram the row of Flash program memory. However, any unprogrammed locations can be written without first erasing the row. In this case, it is not necessary to save and rewrite the other previously programmed locations. See Table 11-1 for Erase Row size and the number of write latches for Flash program memory. Preliminary DS41458B-page 101 PIC16(L)F1526/27 TABLE 11-1: FLASH MEMORY ORGANIZATION BY DEVICE Device PIC16(L)F1526 PIC16(L)F1527 11.2.1 Row Erase (words) Write Latches (words) 32 32 FIGURE 11-1: READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must: 1. 2. 3. Write the desired address to the PMADRH:PMADRL register pair. Clear the CFGS bit of the PMCON1 register. Then, set control bit RD of the PMCON1 register. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the "BSF PMCON1,RD" instruction to be ignored. The data is available in the very next cycle, in the PMDATH:PMDATL register pair; therefore, it can be read as two bytes in the following instructions. PMDATH:PMDATL register pair will hold this value until another read or until it is written to by the user. Note: The two instructions following a program memory read are required to be NOPs. This prevents the user from executing a two-cycle instruction on the next instruction after the RD bit is set. FLASH PROGRAM MEMORY READ FLOWCHART Start Read Operation Select Program or Configuration Memory (CFGS) Select Word Address (PMADRH:PMADRL) Initiate Read Operation (RD = 1) Instruction Fetched ignored NOP execution forced Instruction Fetched ignored NOP execution forced Data read now in PMDATH:PMDATL End Read Operation DS41458B-page 102 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 11-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here PC +3 PC+3 PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD executed here PMDATH,PMDATL INSTR(PC + 1) instruction ignored Forced NOP executed here PC + 4 INSTR (PC + 3) INSTR(PC + 2) instruction ignored Forced NOP executed here PC + 5 INSTR (PC + 4) INSTR(PC + 3) executed here INSTR(PC + 4) executed here RD bit PMDATH PMDATL Register EXAMPLE 11-1: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWL PMADRL PROG_ADDR_LO PMADRL PROG_ADDR_HI PMADRH ; Select Bank for PMCON registers ; ; Store LSB of address ; ; Store MSB of address BCF BSF NOP NOP PMCON1,CFGS PMCON1,RD ; ; ; ; Do not select Configuration Space Initiate read Ignored (Figure 11-2) Ignored (Figure 11-2) MOVF MOVWF MOVF MOVWF PMDATL,W PROG_DATA_LO PMDATH,W PROG_DATA_HI ; ; ; ; Get LSB of word Store in user location Get MSB of word Store in user location 2011 Microchip Technology Inc. Preliminary DS41458B-page 103 PIC16(L)F1526/27 11.2.2 FLASH MEMORY UNLOCK SEQUENCE FIGURE 11-3: The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing. The sequence must be executed and completed without interruption to successfully complete any of the following operations: * Row Erase * Load program memory write latches * Write of program memory write latches to program memory * Write of program memory write latches to User IDs FLASH PROGRAM MEMORY UNLOCK SEQUENCE FLOWCHART Start Unlock Sequence Write 055h to PMCON2 The unlock sequence consists of the following steps: Write 0AAh to PMCON2 1. Write 55h to PMCON2 Initiate Write or Erase Operation (WR = 1) 2. Write AAh to PMCON2 3. Set the WR bit in PMCON1 4. NOP instruction 5. NOP instruction Once the WR bit is set, the processor will always force two NOP instructions. When an Erase Row or Program Row operation is being performed, the processor will stall internal operations (typical 2 ms), until the operation is complete and then resume with the next instruction. When the operation is loading the program memory write latches, the processor will always force the two NOP instructions and continue uninterrupted with the next instruction. Instruction Fetched ignored NOP execution forced Instruction Fetched ignored NOP execution forced End Unlock Sequence Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. DS41458B-page 104 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 11.2.3 ERASING FLASH PROGRAM MEMORY FIGURE 11-4: While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. Load the PMADRH:PMADRL register pair with any address within the row to be erased. Clear the CFGS bit of the PMCON1 register. Set the FREE and WREN bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). Set control bit WR of the PMCON1 register to begin the erase operation. See Example 11-2. After the "BSF PMCON1,WR" instruction, the processor requires two cycles to set up the erase operation. The user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms erase time. This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the PMCON1 WRITE instruction. FLASH PROGRAM MEMORY ERASE FLOWCHART Start Erase Operation Disable Interrupts (GIE = 0) Select Program or Configuration Memory (CFGS) Select Row Address (PMADRH:PMADRL) Select Erase Operation (FREE = 1) Enable Write/Erase Operation (WREN = 1) Unlock Sequence Figure 11-3 (FIGURE x-x) CPU stalls while Erase operation completes (2ms typical) Disable Write/Erase Operation (WREN = 0) Re-enable Interrupts (GIE = 1) End Erase Operation 2011 Microchip Technology Inc. Preliminary DS41458B-page 105 ERASING ONE ROW OF PROGRAM MEMORY Preliminary Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF BANKSEL MOVF MOVWF MOVF MOVWF BCF BSF BSF INTCON,GIE PMADRL ADDRL,W PMADRL ADDRH,W PMADRH PMCON1,CFGS PMCON1,FREE PMCON1,WREN MOVLW MOVWF MOVLW MOVWF BSF NOP NOP 55h PMCON2 0AAh PMCON2 PMCON1,WR BCF BSF PMCON1,WREN INTCON,GIE ; Disable ints so required sequences will execute properly ; Load lower 8 bits of erase address boundary ; Load upper 6 bits of erase address boundary ; Not configuration space ; Specify an erase operation ; Enable writes ; ; ; ; ; ; ; ; ; ; Start of required sequence to initiate erase Write 55h Write AAh Set WR bit to begin erase NOP instructions are forced as processor starts row erase of program memory. The processor stalls until the erase process is complete after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts PIC16(L)F1526/27 DS41458B-page 106 EXAMPLE 11-2: 2011 Microchip Technology Inc. PIC16(L)F1526/27 11.2.4 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the address in PMADRH:PMADRL of the row to be programmed. Load each write latch with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written. The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts. First, each write latch is loaded with data from the PMDATH:PMDATL using the unlock sequence with LWLO = 1. When the last word to be loaded into the write latch is ready, the LWLO bit is cleared and the unlock sequence executed. This initiates the programming operation, writing all the latches into Flash program memory. Note: Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write. Program memory can be written one or more words at a time. The maximum number of words written at one time is equal to the number of write latches. See Figure 11-5 (row writes to program memory with 32 write latches) for more details. The write latches are aligned to the Flash row address boundary defined by the upper 10-bits of PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>) with the lower 5-bits of PMADRL, (PMADRL<4:0>) determining the write latch being loaded. Write operations do not cross these boundaries. At the completion of a program memory write operation, the data in the write latches is reset to contain 0x3FFF. The special unlock sequence is required to load a write latch with data or initiate a Flash programming operation. If the unlock sequence is interrupted, writing to the latches or program memory will not be initiated. 1. 2. 3. Set the WREN bit of the PMCON1 register. Clear the CFGS bit of the PMCON1 register. Set the LWLO bit of the PMCON1 register. When the LWLO bit of the PMCON1 register is `1', the write sequence will only load the write latches and will not initiate the write to Flash program memory. 4. Load the PMADRH:PMADRL register pair with the address of the location to be written. 5. Load the PMDATH:PMDATL register pair with the program memory data to be written. 6. Execute the unlock sequence (Section 11.2.2 "Flash Memory Unlock Sequence"). The write latch is now loaded. 7. Increment the PMADRH:PMADRL register pair to point to the next location. 8. Repeat steps 5 through 7 until all but the last write latch has been loaded. 9. Clear the LWLO bit of the PMCON1 register. When the LWLO bit of the PMCON1 register is `0', the write sequence will initiate the write to Flash program memory. 10. Load the PMDATH:PMDATL register pair with the program memory data to be written. 11. Execute the unlock sequence (Section 11.2.2 "Flash Memory Unlock Sequence"). The entire program memory latch content is now written to Flash program memory. Note: The program memory write latches are reset to the blank state (0x3FFF) at the completion of every write or erase operation. As a result, it is not necessary to load all the program memory write latches. Unloaded latches will remain in the blank state. An example of the complete write sequence is shown in Example 11-3. The initial address is loaded into the PMADRH:PMADRL register pair; the data is loaded using indirect addressing. 2011 Microchip Technology Inc. Preliminary DS41458B-page 107 PIC16(L)F1526/27 FIGURE 11-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES 7 6 0 7 PMADRH - 54 7 0 PMADRL 5 - 0 7 PMDATH 6 - r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 c4 c3 c2 c1 c0 0 PMDATL 8 14 10 Program Memory Write Latches 5 14 PMADRL<4:0> Write Latch #0 00h 14 Write Latch #1 01h 14 CFGS = 0 PMADRH<6:0> :PMADRL<7:5> Row Address Decode 14 14 Write Latch #30 Write Latch #31 1Eh 1Fh 14 14 14 Row Addr Addr Addr Addr 000h 0000h 0001h 001Eh 001Fh 001h 0020h 0021h 003Eh 003Fh 002h 0040h 0041h 005Eh 005Fh 3FEh 7FC0h 7FC1h 7FDEh 7FDFh 3FFh 7FE0h 7FE1h 7FFEh 7FFFh Flash Program Memory 400h CFGS = 1 8000h - 8003h USER ID 0 - 3 8004h - 8005h 8006h 8007h - 8008h 8009h - 801Fh reserved DEVICEID REVID Configuration Words reserved Configuration Memory DS41458B-page 108 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 11-6: FLASH PROGRAM MEMORY WRITE FLOWCHART Start Write Operation Determine number of words to be written into Program or Configuration Memory. The number of words cannot exceed the number of words per row. (word_cnt) Disable Interrupts (GIE = 0) Select Program or Config. Memory (CFGS) Select Row Address (PMADRH:PMADRL) Enable Write/Erase Operation (WREN = 1) Load the value to write (PMDATH:PMDATL) Update the word counter (word_cnt--) Last word to write ? Yes No Unlock Sequence (Figure11-3 x-x) Figure Select Write Operation (FREE = 0) No delay when writing to Program Memory Latches Load Write Latches Only (LWLO = 1) Increment Address (PMADRH:PMADRL++) Write Latches to Flash (LWLO = 0) Unlock Sequence (Figure11-3 x-x) Figure CPU stalls while Write operation completes (2ms typical) Disable Write/Erase Operation (WREN = 0) Re-enable Interrupts (GIE = 1) End Erase Operation 2011 Microchip Technology Inc. Preliminary DS41458B-page 109 PIC16(L)F1526/27 EXAMPLE 11-3: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF BANKSEL MOVF MOVWF MOVF MOVWF MOVLW MOVWF MOVLW MOVWF BCF BSF BSF INTCON,GIE PMADRH ADDRH,W PMADRH ADDRL,W PMADRL LOW DATA_ADDR FSR0L HIGH DATA_ADDR FSR0H PMCON1,CFGS PMCON1,WREN PMCON1,LWLO ; ; ; ; ; ; ; ; ; ; ; ; ; Disable ints so required sequences will execute properly Bank 3 Load initial address MOVIW MOVWF MOVIW MOVWF FSR0++ PMDATL FSR0++ PMDATH ; Load first data byte into lower ; ; Load second data byte into upper ; MOVF XORLW ANDLW BTFSC GOTO PMADRL,W 0x1F 0x1F STATUS,Z START_WRITE ; Check if lower bits of address are '00000' ; Check if we're on the last of 32 addresses ; ; Exit if last of 32 words, ; MOVLW MOVWF MOVLW MOVWF BSF NOP 55h PMCON2 0AAh PMCON2 PMCON1,WR ; ; ; ; ; ; ; ; PMADRL,F LOOP ; Still loading latches Increment address ; Write next latches PMCON1,LWLO ; No more loading latches - Actually start Flash program ; memory write 55h PMCON2 0AAh PMCON2 PMCON1,WR ; ; ; ; ; ; ; ; ; ; ; ; ; Load initial data address Load initial data address Not configuration space Enable writes Only Load Write Latches Required Sequence LOOP NOP INCF GOTO Required Sequence START_WRITE BCF MOVLW MOVWF MOVLW MOVWF BSF NOP NOP BCF BSF DS41458B-page 110 PMCON1,WREN INTCON,GIE Start of required write sequence: Write 55h Write AAh Set WR bit to begin write NOP instructions are forced as processor loads program memory write latches Start of required write sequence: Write 55h Write AAh Set WR bit to begin write NOP instructions are forced as processor writes all the program memory write latches simultaneously to program memory. After NOPs, the processor stalls until the self-write process in complete after write processor continues with 3rd instruction Disable writes Enable interrupts Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 11.3 Modifying Flash Program Memory FIGURE 11-7: When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory. Load the starting address of the row to be rewritten. Erase the program memory row. Load the write latches with data from the RAM image. Initiate a programming operation. FLASH PROGRAM MEMORY MODIFY FLOWCHART Start Modify Operation Read Operation (Figure11-2 x.x) Figure An image of the entire row read must be stored in RAM Modify Image The words to be modified are changed in the RAM image Erase Operation (Figure11-4 x.x) Figure Write Operation use RAM image (Figure11-5 x.x) Figure End Modify Operation 2011 Microchip Technology Inc. Preliminary DS41458B-page 111 PIC16(L)F1526/27 11.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the User ID's, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 11-2. When read access is initiated on an address outside the parameters listed in Table 11-2, the PMDATH:PMDATL register pair is cleared, reading back `0's. TABLE 11-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1) Address Function Read Access Write Access 8000h-8003h 8006h 8007h-8008h User IDs Device ID/Revision ID Configuration Words 1 and 2 Yes Yes Yes Yes No No EXAMPLE 11-4: CONFIGURATION WORD AND DEVICE ID ACCESS * This code block will read 1 word of program memory at the memory address: * PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF CLRF PMADRL PROG_ADDR_LO PMADRL PMADRH ; Select correct Bank ; ; Store LSB of address ; Clear MSB of address BSF BCF BSF NOP NOP BSF PMCON1,CFGS INTCON,GIE PMCON1,RD INTCON,GIE ; ; ; ; ; ; Select Configuration Space Disable interrupts Initiate read Executed (See Figure 11-2) Ignored (See Figure 11-2) Restore interrupts MOVF MOVWF MOVF MOVWF PMDATL,W PROG_DATA_LO PMDATH,W PROG_DATA_HI ; ; ; ; Get LSB of word Store in user location Get MSB of word Store in user location DS41458B-page 112 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 11.5 Write Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 11-8: FLASH PROGRAM MEMORY VERIFY FLOWCHART Start Verify Operation This routine assumes that the last row of data written was from an image saved in RAM. This image will be used to verify the data currently stored in Flash Program Memory. Read Operation (Figure x.x) Figure 11-2 PMDAT = RAM image ? Yes No No Fail Verify Operation Last Word ? Yes End Verify Operation 2011 Microchip Technology Inc. Preliminary DS41458B-page 113 PIC16(L)F1526/27 11.6 Flash Program Memory Control Registers REGISTER 11-1: R/W-x/u PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PMDAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 PMDAT<7:0>: Read/write value for Least Significant bits of program memory REGISTER 11-2: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER U-0 U-0 -- -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PMDAT<13:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 PMDAT<13:8>: Read/write value for Most Significant bits of program memory REGISTER 11-3: R/W-0/0 PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PMADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 PMADR<7:0>: Specifies the Least Significant bits for program memory address REGISTER 11-4: U-1 PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER R/W-0/0 R/W-0/0 -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PMADR<14:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `1' bit 6-0 PMADR<14:8>: Specifies the Most Significant bits for program memory address DS41458B-page 114 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 REGISTER 11-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER U-1(1) R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 -- CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Bit is cleared by hardware bit 7 Unimplemented: Read as `1' bit 6 CFGS: Configuration Select bit 1 = Access Configuration, User ID and Device ID Registers 0 = Access Flash program memory bit 5 LWLO: Load Write Latches Only bit(3) 1 = Only the addressed program memory write latch is loaded/updated on the next WR command 0 = The addressed program memory write latch is loaded/updated and a write of all program memory write latches will be initiated on the next WR command bit 4 FREE: Program Flash Erase Enable bit 1 = Performs an erase operation on the next WR command (hardware cleared upon completion) 0 = Performs an write operation on the next WR command bit 3 WRERR: Program/Erase Error Flag bit 1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write `1') of the WR bit). 0 = The program or erase operation completed normally. bit 2 WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash bit 1 WR: Write Control bit 1 = Initiates a program Flash program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash is complete and inactive. bit 0 RD: Read Control bit 1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a program Flash read. Note 1: 2: 3: Unimplemented bit, read as `1'. The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1). The LWLO bit is ignored during a program memory erase operation (FREE = 1). 2011 Microchip Technology Inc. Preliminary DS41458B-page 115 PIC16(L)F1526/27 REGISTER 11-6: W-0/0 PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 Program Memory Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the PMCON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes. TABLE 11-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- CFGS LWLO FREE WRERR WREN WR RD 115 PMCON1 PMCON2 Program Memory Control Register 2 116 PMADRL PMADRL<7:0> 114 -- PMADRH PMADRH<6:0> PMDATL PMDATH -- -- INTCON GIE PEIE Legend: CONFIG1 CONFIG2 Legend: 114 PMDATH<5:0> TMR0IE INTE IOCIE 114 TMR0IF INTF IOCIF 80 -- = unimplemented location, read as `0'. Shaded cells are not used by Flash program memory module. TABLE 11-4: Name 114 PMDATL<7:0> SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 13:8 -- -- FCMEN IESO CLKOUTEN 7:0 CP MCLRE PWRTE 13:8 7:0 -- -- Bit 10/2 Bit 9/1 Bit 8/0 BOREN<1:0> WDTE<1:0> -- FOSC<2:0> LVP DEBUG LPBOR BORV -- VCAPEN(1) -- -- STVREN WRT<1:0> -- Register on Page 46 48 -- = unimplemented location, read as `0'. Shaded cells are not used by Flash program memory. DS41458B-page 116 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 12.0 I/O PORTS FIGURE 12-1: GENERIC I/O PORT OPERATION In general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output. However, the pin can still be read. Each port has three standard registers for its operation. These registers are: * TRISx registers (data direction) * PORTx registers (reads the levels on the pins of the device) * LATx registers (output latch) D Write LATx Write PORTx Some ports may have one or more of the following additional registers. These registers are: TRISx Q CK VDD Data Register Data Bus I/O pin * ANSELx (analog select) * WPUx (weak pull-up) Read PORTx To peripherals ANSELx Device PORTB PORTC PORTD PORTE PORTF PORTG PORT AVAILABILITY PER DEVICE PORTA TABLE 12-1: Read LATx PIC16(L)F1526 PIC16(L)F1527 The Data Latch (LATA register) is useful for read-modify-write operations on the value that the I/O pins are driving. A write operation to the LATA register has the same affect as a write to the corresponding PORTA register. A read of the LATA register reads of the values held in the I/O PORT latches, while a read of the PORTA register reads the actual I/O pin value. EXAMPLE 12-1: ; ; ; ; VSS INITIALIZING PORTA This code example illustrates initializing the PORTA register. The other ports are initialized in the same manner. BANKSEL CLRF BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF PORTA PORTA LATA LATA ANSELA ANSELA TRISA B'00111000' TRISA ; ;Init PORTA ;Data Latch ; ; ;digital I/O ; ;Set RA<5:3> as inputs ;and set RA<2:0> as ;outputs The port has analog functions and has an ANSELA register which can disable the digital input and save power. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 12-1. 2011 Microchip Technology Inc. Preliminary DS41458B-page 117 PIC16(L)F1526/27 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) registers are used to steer specific peripheral input and output functions between different pins. The APFCON registers are shown in Register 12-1. For this device family, the following functions can be moved between different pins. * Timer3 * CCP2 These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected. REGISTER 12-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 -- -- -- -- -- -- T3CKISEL CCP2SEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-2 Unimplemented: Read as `0' bit 1 T3CKISEL: Timer3 Input Selection bit 0 = T3CKI function is on RB5 1 = T3CKI function is on RB4 bit 0 CCP2SEL: Pin Selection bit 0 = CCP2 function is on RC1 1 = CCP2 function is on RE7 DS41458B-page 118 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 12.2 12.2.2 PORTA Registers PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 12-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). Example 12-1 shows how to initialize an I/O port. Reading the PORTA register (Register 12-2) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATA). PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 12-2. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input functions, such as ADC, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown in Table 12-2. TABLE 12-2: Pin Name PORTA OUTPUT PRIORITY Function Priority(1) The TRISA register (Register 12-3) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. RA0 RA0 RA1 RA1 RA2 RA2 RA3 RA3 RA4 RA4 12.2.1 RA5 RA5 RA6 CLKOUT OSC2 RA6 RA7 RA7 ANSELA REGISTER The ANSELA register (Register 12-5) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. Note 1: Priority listed from highest to lowest. The state of the ANSELA bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELA bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. 2011 Microchip Technology Inc. Preliminary DS41458B-page 119 PIC16(L)F1526/27 REGISTER 12-2: PORTA: PORTA REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared RA<7:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 12-3: TRISA: PORTA TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared TRISA<7:0>: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output bit 7-0 REGISTER 12-4: LATA: PORTA DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: LATA<7:0>: RA<7:0> Output Latch Value bits(1) Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. DS41458B-page 120 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 REGISTER 12-5: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 -- -- ANSA5 -- ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5 ANSA5: Analog Select between Analog or Digital Function on pins RA5, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. bit 4 Unimplemented: Read as `0' bit 3-0 ANSA<3:0>: Analog Select between Analog or Digital Function on pins RA<3:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA -- -- ANSA5 -- ANSA3 ANSA2 ANSA1 ANSA0 121 APFCON -- -- -- -- -- -- LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 WPUEN INTEDG TMR0CS TMR0SE PSA PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 120 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 120 Name LATA OPTION_REG Legend: CONFIG1 Legend: LATA1 118 LATA0 120 PS<2:0> 165 x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTA. TABLE 12-4: Name T3CKISEL CCP2SEL Bits SUMMARY OF CONFIGURATION WORD WITH PORTA Bit -/7 13:8 7:0 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 FCMEN IESO CLKOUTEN MCLRE PWRTE -- CP Bit 10/2 WDTE<1:0> Bit 9/1 BOREN<1:0> FOSC<2:0> Bit 8/0 -- Register on Page 48 -- = unimplemented location, read as `0'. Shaded cells are not used by PORTA. 2011 Microchip Technology Inc. Preliminary DS41458B-page 121 PIC16(L)F1526/27 12.3 12.3.2 PORTB Registers PORTB is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 12-7). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 12-1 shows how to initialize an I/O port. Reading the PORTB register (Register 12-6) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATB). Each PORTB pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 12-5. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output. Certain digital input functions override other port functions and are included in Table 12-5. TABLE 12-5: Pin Name The TRISB register (Register 12-7) controls the PORTB pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISB register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. 12.3.1 ANSELB REGISTER The ANSELB register (Register 12-9) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELB bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELB bits has no effect on digital output functions. A pin with TRIS clear and ANSELB set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: PORTB FUNCTIONS AND OUTPUT PRIORITIES Note 1: PORTB OUTPUT PRIORITY Function Priority(1) RB0 RB0 RB1 RB1 RB2 RB2 RB3 CCP2 RB3 RB4 RB4 RB5 RB5 RB6 ICDCLK RB6 RB7 ICDDAT RB7 Priority listed from highest to lowest. The ANSELB bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. DS41458B-page 122 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 REGISTER 12-6: PORTB: PORTB REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared RB<7:0>: PORTB General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. REGISTER 12-7: TRISB: PORTB TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 TRISB<7:0>: PORTB Tri-State Control bits 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output REGISTER 12-8: LATB: PORTB DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: LATB<7:0>: PORTB Output Latch Value bits(1) Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. 2011 Microchip Technology Inc. Preliminary DS41458B-page 123 PIC16(L)F1526/27 REGISTER 12-9: ANSELB: PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 -- -- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 ANSB<5:0>: Analog Select between Analog or Digital Function on pins RB<5:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 12-10: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: 2: WPUB<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. TABLE 12-6: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 APFCON -- -- -- -- -- -- ANSELB -- -- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 124 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 123 LATB Bit 1 Bit 0 Register on Page Bit 7 T3CKISEL CCP2SEL 124 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 123 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 123 WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 124 Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTB. DS41458B-page 124 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 12.4 12.4.1 PORTC Registers PORTC is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 12-12). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 12-1 shows how to initialize an I/O port. Reading the PORTC register (Register 12-11) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATC). PORTC FUNCTIONS AND OUTPUT PRIORITIES Each PORTC pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 12-7. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output. Certain digital input functions override other port functions and are included in Table 12-7. TABLE 12-7: Pin Name The TRISC register (Register 12-12) controls the PORTC pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. Preliminary Function Priority(1) RC0 SOSCO RC0 RC1 SOSCI CCP2 RC1 RC2 CCP1 RC2 RC3 SCL1 SCK1 RC3(2) RC4 SDA1 RC4(2) RC5 SDO1 RC5 RC6 CK1 TX1 RC6 RC7 DT1 RC7 Note 1: 2: 2011 Microchip Technology Inc. PORTC OUTPUT PRIORITY Priority listed from highest to lowest. RC3 and RC4 read the I2C ST input when I2C mode is enabled. DS41458B-page 125 PIC16(L)F1526/27 REGISTER 12-11: PORTC: PORTC REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared RC<7:0>: PORTC General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values. REGISTER 12-12: TRISC: PORTC TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared TRISC<7:0>: PORTC Tri-State Control bits(1) 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output bit 7-0 REGISTER 12-13: LATC: PORTC DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: LATC<7:0>: PORTC Output Latch Value bits(1) Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values. DS41458B-page 126 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 TABLE 12-8: Name APFCON LATC SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 -- -- -- -- -- -- LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 Bit 1 Bit 0 T3CKISEL CCP2SEL LATC1 Register on Page 124 LATC0 123 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 123 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 123 Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTC. 2011 Microchip Technology Inc. Preliminary DS41458B-page 127 PIC16(L)F1526/27 12.5 12.5.2 PORTD Registers PORTD is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISD (Register 12-15). Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 12-1 shows how to initialize an I/O port. Reading the PORTD register (Register 12-14) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATD). Each PORTD pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 12-9. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output. Certain digital input functions override other port functions and are included in Table 12-9. TABLE 12-9: Pin Name The TRISD register (Register 12-15) controls the PORTD pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISD register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. 12.5.1 ANSELD REGISTER The ANSELD register (Register 12-17) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELD bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELD bits has no effect on digital output functions. A pin with TRIS clear and ANSELD set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: PORTD FUNCTIONS AND OUTPUT PRIORITIES PORTD OUTPUT PRIORITY Function Priority(1) RD0 RD0 RD1 RD1 RD2 RD2 RD3 RD3 RD4 SDO2 RD4 RD5 SDA2 RD5(2) RD6 SCL2 SCK2 RD6(2) RD7 RD7 Note 1: 2: Priority listed from highest to lowest. RD5 and RD6 read the I2C ST input when I2C mode is enabled. The ANSELD bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. DS41458B-page 128 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 REGISTER 12-14: PORTD: PORTD REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared RD<7:0>: PORTD General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is return of actual I/O pin values. REGISTER 12-15: TRISD: PORTD TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 TRISD<7:0>: PORTD Tri-State Control bits 1 = PORTD pin configured as an input (tri-stated) 0 = PORTD pin configured as an output REGISTER 12-16: LATD: PORTB DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: LATD<7:0>: PORTD Output Latch Value bits(1) Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is return of actual I/O pin values. 2011 Microchip Technology Inc. Preliminary DS41458B-page 129 PIC16(L)F1526/27 REGISTER 12-17: ANSELD: PORTD ANALOG SELECT REGISTER U-0 U-0 -- U-0 -- -- U-0 R/W-1 R/W-1 R/W-1 R/W-1 -- ANSD3 ANSD2 ANSD1 ANSD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 ANSD<3:0>: Analog Select between Analog or Digital Function on pins RD<3:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 12-18: WPUD: WEAK PULL-UP PORTD REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: 2: WPUD<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. TABLE 12-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- -- -- -- ANSD3 ANSD2 ANSD1 ANSD0 124 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 123 Name ANSELD LATD PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 123 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 123 WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 130 WPUD Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTD. DS41458B-page 130 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 12.6 12.6.2 PORTE Registers PORTE is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISE (Register 12-20). Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 12-1 shows how to initialize an I/O port. Reading the PORTE register (Register 12-19) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATE). PORTE FUNCTIONS AND OUTPUT PRIORITIES Each PORTE pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 12-11. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output. Certain digital input functions override other port functions and are included in Table 12-11. TABLE 12-11: PORTE OUTPUT PRIORITY Pin Name Function Priority(1) The TRISE register (Register 12-20) controls the PORTE pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISE register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. RE0 RE0 RE1 RE1 RE2 CCP10 RE2 RE3 CCP9 RE3 12.6.1 RE4 CCP8 RE4 RE5 CCP7 RE5 RE6 CCP6 RE6 RE7 CCP2 RE7 ANSELE REGISTER The ANSELE register (Register 12-22) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELE bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELE bits has no effect on digital output functions. A pin with TRIS clear and ANSELE set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: Note 1: Priority listed from highest to lowest. The ANSELE bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. 2011 Microchip Technology Inc. Preliminary DS41458B-page 131 PIC16(L)F1526/27 REGISTER 12-19: PORTE: PORTE REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared RE<7:0>: PORTE General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is return of actual I/O pin values. REGISTER 12-20: TRISE: PORTE TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 TRISE<7:0>: PORTE Tri-State Control bits 1 = PORTE pin configured as an input (tri-stated) 0 = PORTE pin configured as an output REGISTER 12-21: LATE: PORTE DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: LATE<7:0>: PORTE Output Latch Value bits(1) Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is return of actual I/O pin values. DS41458B-page 132 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 REGISTER 12-22: ANSELE: PORTE ANALOG SELECT REGISTER U-0 U-0 -- U-0 -- U-0 -- -- U-0 R/W-1 R/W-1 R/W-1 -- ANSE2 ANSE1 ANSE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-3 Unimplemented: Read as `0' bit 2-0 ANSE<2:0>: Analog Select between Analog or Digital Function on pins RE<2:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 12-23: WPUE: WEAK PULL-UP PORTE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUE7 WPUE6 WPUE5 WPUE4 WPUE3 WPUE2 WPUE1 WPUE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: 2: WPUE<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. TABLE 12-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Name Bit 6 Bit 5 Bit 4 Bit 3 APFCON -- -- -- -- -- -- ANSELE -- -- -- -- -- ANSE2 ANSE1 ANSE0 133 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 132 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 132 LATE PORTE Bit 2 Bit 1 Bit 0 Register on Page Bit 7 T3CKISEL CCP2SEL 124 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 132 WPUE WPUE7 WPUE6 WPUE5 WPUE4 WPUE3 WPUE2 WPUE1 WPUE0 133 Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTE. 2011 Microchip Technology Inc. Preliminary DS41458B-page 133 PIC16(L)F1526/27 12.7 12.7.2 PORTF Registers PORTF is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISF (Register 12-25). Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 12-1 shows how to initialize an I/O port. Reading the PORTF register (Register 12-24) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATF). Each PORTF pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 12-13. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output. Certain digital input functions override other port functions and are included in Table 12-13. TABLE 12-13: PORTF OUTPUT PRIORITY Pin Name The TRISF register (Register 12-25) controls the PORTF pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISF register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. 12.7.1 ANSELF REGISTER The ANSELF register (Register 12-27) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELF bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. PORTE FUNCTIONS AND OUTPUT PRIORITIES Note 1: 2: Function Priority(1) RF0 VCAP(2) RF0 RF1 RF1 RF2 RF2 RF3 RF3 RF4 RF4 RF5 RF5 RF6 RF6 RF7 RF7 Priority listed from highest to lowest. PIC16F1526/27 only The state of the ANSELF bits has no effect on digital output functions. A pin with TRIS clear and ANSELF set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELF bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. DS41458B-page 134 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 REGISTER 12-24: PORTF: PORTF REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared RF<7:0>: PORTF General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Writes to PORTF are actually written to corresponding LATF register. Reads from PORTF register is return of actual I/O pin values. REGISTER 12-25: TRISF: PORTF TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 TRISF<7:0>: PORTF Tri-State Control bits 1 = PORTF pin configured as an input (tri-stated) 0 = PORTF pin configured as an output REGISTER 12-26: LATF: PORTF DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: LATF<7:0>: PORTF Output Latch Value bits(1) Writes to PORTF are actually written to corresponding LATF register. Reads from PORTF register is return of actual I/O pin values. 2011 Microchip Technology Inc. Preliminary DS41458B-page 135 PIC16(L)F1526/27 REGISTER 12-27: ANSELF: PORTF ANALOG SELECT REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSF7 ANSF6 ANSF5 ANSF4 ANSF3 ANSF2 ANSF1 ANSF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: ANSF<7:0>: Analog Select between Analog or Digital Function on pins RF<7:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. TABLE 12-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELF ANSF7 ANSF6 ANSF5 ANSF4 ANSF3 ANSF2 ANSF1 ANSF0 136 LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 135 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 135 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 135 Name PORTF TRISF Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTF. TABLE 12-15: SUMMARY OF CONFIGURATION WORD WITH PORTF Name CONFIG2 Legend: Note 1: Bits Bit -/7 13:8 7:0 Bit -/6 -- -- -- Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 LVP DEBUG LPBOR BORV STVREN -- -- VCAPEN(1) -- -- WRT<1:0> Register on Page 48 -- = unimplemented locations read as `0'. Shaded cells are not used by PORTF. PIC16F1526/27 only. DS41458B-page 136 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 12.8 12.8.2 PORTG Registers PORTG is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISG (Register 12-29). Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., disable the output driver). Clearing a TRISG bit (= 0) will make the corresponding PORTG pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is RG5, which is input only and its TRIS bit will always read as `1'. Example 12-1 shows how to initialize an I/O port. Reading the PORTG register (Register 12-28) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATG). Each PORTG pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 12-16. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input functions, such as ADC, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with Table 12-16. TABLE 12-16: PORTG OUTPUT PRIORITY Pin Name The TRISG register (Register 12-29) controls the PORTG pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISG register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. 12.8.1 ANSELG REGISTER The ANSELG register (Register 12-31) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELG bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. PORTG FUNCTIONS AND OUTPUT PRIORITIES Function Priority(1) RG0 CCP3 RG0 RG1 CK2 TX2 RG1 RG2 DT2 RG2 RG3 CCP4 RG3 RG4 CCP5 RG4 RG5 Input only pin Note 1: Priority listed from highest to lowest. The state of the ANSELG bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELG bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. 2011 Microchip Technology Inc. Preliminary DS41458B-page 137 PIC16(L)F1526/27 REGISTER 12-28: PORTG: PORTG REGISTER U-0 U-0 R-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u -- RG5 RG4 RG3 RG2 RG1 RG0 -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 RG<5:0>: PORTG I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: Writes to PORTG are actually written to corresponding LATG register. Reads from PORTG register is return of actual I/O pin values. REGISTER 12-29: TRISG: PORTG TRI-STATE REGISTER U-0 U-0 U-1(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- -- TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5 Unimplemented: Read as `1' bit 4-0 TRISG<4:0>: RG<4:0> Tri-State Control bits(1) 1 = PORTG pin configured as an input (tri-stated) 0 = PORTG pin configured as an output Note 1: Unimplemented, read as `1'. DS41458B-page 138 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 REGISTER 12-30: LATG: PORTG DATA LATCH REGISTER U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u -- -- -- LATG4 LATG3 LATG2 LATG1 LATG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4-0 LATG<4:0>: PORTG Output Latch Value bits(1) Note 1: Writes to PORTG are actually written to corresponding LATG register. Reads from PORTG register is return of actual I/O pin values. REGISTER 12-31: ANSELG: PORTG ANALOG SELECT REGISTER U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 U-0 -- -- -- ANSG4 ANSG3 ANSG2 ANSG1 -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4-1 ANSG<4:1>: Analog Select between Analog or Digital Function on Pins RG<4:1>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. bit 0 Unimplemented: Read as `0' Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. 2011 Microchip Technology Inc. Preliminary DS41458B-page 139 PIC16(L)F1526/27 REGISTER 12-32: WPUG: WEAK PULL-UP PORTG REGISTER U-0 U-0 R/W-1/1 U-0 U-0 U-0 U-0 U-0 -- -- WPUG5 -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5 WPUG5: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled bit 4-0 Note 1: 2: Unimplemented: Read as `0' Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. TABLE 12-17: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELG -- -- -- ANSG4 ANSG3 ANSG2 ANSG1 -- 139 LATG -- -- -- LATG4 LATG3 LATG2 LATG1 LATG0 139 PORTG -- -- RG5 RG4 RG3 RG2 RG1 RG0 138 TRISG -- -- TRISG5 TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 138 WPUG -- -- WPUG5 -- -- -- -- -- 140 Name Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTG. TABLE 12-18: SUMMARY OF CONFIGURATION WORD WITH PORTG Name CONFIG1 Legend: Bits Bit -/7 Bit 13/5 Bit 12/4 Bit 11/3 FCMEN IESO CLKOUTEN MCLRE PWRTE -- 13:8 7:0 Bit -/6 CP Bit 10/2 WDTE<1:0> Bit 9/1 BOREN<1:0> FOSC<2:0> Bit 8/0 -- Register on Page 48 -- = unimplemented location, read as `0'. Shaded cells are not used by PORTG. DS41458B-page 140 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 13.0 INTERRUPT-ON-CHANGE 13.3 The PORTB pins can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual PORTB pin, or combination of PORTB pins, can be configured to generate an interrupt. The interrupt-on-change module has the following features: * * * * Interrupt-on-Change enable (Master Switch) Individual pin configuration Rising and falling edge detection Individual pin interrupt flags The IOCBFx bits located in the IOCBF register are status flags that correspond to the Interrupt-on-change pins of PORTB. If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set. The IOCIF bit of the INTCON register reflects the status of all IOCBFx bits. 13.4 Clearing Interrupt Flags The individual status flags, (IOCBFx bits), can be cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. Figure 13-1 is a block diagram of the IOC module. 13.1 Interrupt Flags Enabling the Module To allow individual PORTB pins to generate an interrupt, the IOCIE bit of the INTCON register must be set. If the IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. In order to ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits should be performed. The following sequence is an example of what should be performed. EXAMPLE 13-1: 13.2 Individual Pin Configuration For each PORTB pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated IOCBPx bit of the IOCBP register is set. To enable a pin to detect a falling edge, the associated IOCBNx bit of the IOCBN register is set. A pin can be configured to detect rising and falling edges simultaneously by setting both the IOCBPx bit and the IOCBNx bit of the IOCBP and IOCBN registers, respectively. 2011 Microchip Technology Inc. MOVLW XORWF ANDWF 13.5 0xff IOCBF, W IOCBF, F Operation in Sleep The interrupt-on-change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the IOCBF register will be updated prior to the first instruction executed out of Sleep. Preliminary DS41458B-page 141 PIC16(L)F1526/27 FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCBNx D Q4Q1 Q CK edge detect R RBx IOCBPx D data bus = 0 or 1 Q write IOCBFx CK D S Q to data bus IOCBFx CK IOCIE R Q2 from all other IOCBFx individual pin detectors Q1 Q3 Q4 Q4Q1 DS41458B-page 142 Q1 Q1 Q2 Q2 Q2 Q3 Q4 Q4Q1 IOC interrupt to CPU core Q3 Q4 Q4 Q4Q1 Preliminary Q4Q1 2011 Microchip Technology Inc. PIC16(L)F1526/27 13.6 Interrupt-On-Change Registers REGISTER 13-1: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 IOCBP<7:0>: Interrupt-on-Change PORTB Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin REGISTER 13-2: IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 IOCBN<7:0>: Interrupt-on-Change PORTB Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin REGISTER 13-3: IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HS - Bit is set in hardware bit 7-0 IOCBF<7:0>: Interrupt-on-Change PORTB Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling edge was detected on RBx. 0 = No change was detected, or the user cleared the detected change. 2011 Microchip Technology Inc. Preliminary DS41458B-page 143 PIC16(L)F1526/27 TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELB -- -- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 124 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 80 Name IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 143 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 143 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 143 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 123 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used by Interrupt-on-Change. DS41458B-page 144 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 14.0 FIXED VOLTAGE REFERENCE (FVR) 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC module is routed through two independent programmable gain amplifiers. Each amplifier can be configured to amplify the reference voltage by 1x, 2x or 4x, to produce the three possible voltage levels. The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Reference Section 16.0 "Analog-to-Digital Converter (ADC) Module" for additional information. * ADC input channel * ADC positive reference The FVR can be enabled by setting the FVREN bit of the FVRCON register. 14.2 FVR Stabilization Period When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See Section 25.0 "Electrical Specifications" for the minimum delay requirement. FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> 2 x1 x2 x4 FVR BUFFER1 (To ADC Module) 1.024V Fixed Reference + FVREN FVRRDY - Any peripheral requiring the Fixed Reference (See Table 14-1) TABLE 14-1: Peripheral HFINTOSC BOR LDO PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR) Conditions Description FOSC<2:0> = 100 and IRCF<3:0> = 000x INTOSC is active and device is not in Sleep. BOREN<1:0> = 11 BOR always enabled. BOREN<1:0> = 10 and BORFS = 1 BOR disabled in Sleep mode, BOR Fast Start enabled. BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start enabled. All PIC16F1526/27 devices, when VREGPM = 1 and not in Sleep The device runs off of the low-power regulator when in Sleep mode. 2011 Microchip Technology Inc. Preliminary DS41458B-page 145 PIC16(L)F1526/27 14.3 FVR Control Registers REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 R/W-0/0 U-0 U-0 FVREN FVRRDY(1) TSEN TSRNG -- -- R/W-0/0 R/W-0/0 ADFVR<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Reference Enable bit 0 = Fixed Voltage Reference is disabled 1 = Fixed Voltage Reference is enabled bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 0 = Fixed Voltage Reference output is not ready or not enabled 1 = Fixed Voltage Reference output is ready for use bit 5 TSEN: Temperature Indicator Enable bit 0 = Temperature Indicator is disabled 1 = Temperature Indicator is enabled bit 4 TSRNG: Temperature Indicator Range Selection bit 0 = VOUT = VDD - 2VT (Low Range) 1 = VOUT = VDD - 4VT (High Range) bit 3-2 Unimplemented: Read as `0' bit 1-0 ADFVR<1:0>: ADC Fixed Voltage Reference Selection bits 00 = ADC Fixed Voltage Reference Peripheral output is off 01 = ADC Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 = ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 11 = ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) Note 1: 2: FVRRDY is always `1' on PIC16F1526/27 only. Fixed Voltage Reference output cannot exceed VDD. TABLE 14-2: Name FVRCON Legend: SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 FVREN FVRRDY TSEN TSRNG -- -- Bit 1 Bit 0 ADFVR<1:0> Register on page 146 Shaded cells are unused by the Fixed Voltage Reference module. DS41458B-page 146 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 15.0 TEMPERATURE INDICATOR MODULE FIGURE 15-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit's range of operating temperature falls between of -40C and +85C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. VDD TSEN TSRNG The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A one-point calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN1333, "Use and Calibration of the Internal Temperature Indicator" (DS01333) for more details regarding the calibration process. 15.1 TEMPERATURE CIRCUIT DIAGRAM VOUT ADC MUX ADC n CHS bits (ADCON0 register) Circuit Operation Figure 15-1 shows a simplified block diagram of the temperature circuit. The proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. Equation 15-1 describes the output characteristics of the temperature indicator. EQUATION 15-1: VOUT RANGES High Range: VOUT = VDD - 4VT 15.2 Minimum Operating VDD vs. Minimum Sensing Temperature When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. When the temperature circuit is operated in high range, the device operating voltage, VDD, must be high enough to ensure that the temperature circuit is correctly biased. Table 15-1 shows the recommended minimum VDD vs. range setting. Low Range: VOUT = VDD - 2VT TABLE 15-1: The temperature sense circuit is integrated with the Fixed Voltage Reference (FVR) module. See Section 14.0 "Fixed Voltage Reference (FVR)" for more information. The circuit is enabled by setting the TSEN bit of the FVRCON register. When disabled, the circuit draws no current. The circuit operates in either high or low range. The high range, selected by setting the TSRNG bit of the FVRCON register, provides a wider output voltage. This provides more resolution over the temperature range, but may be less consistent from part to part. This range requires a higher bias voltage to operate and thus, a higher VDD is needed. The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2011 Microchip Technology Inc. RECOMMENDED VDD VS. RANGE Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0 3.6V 1.8V 15.3 Temperature Output The output of the circuit is measured using the internal analog-to-digital converter. A channel is reserved for the temperature circuit output. Refer to Section 16.0 "Analog-to-Digital Converter (ADC) Module" for detailed information. 15.4 ADC Acquisition Time To ensure accurate temperature measurements, the user must wait at least 200 s after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200 s between sequential conversions of the temperature indicator output. Preliminary DS41458B-page 147 PIC16(L)F1526/27 NOTES: DS41458B-page 148 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 16.0 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESH:ADRESL register pair). Figure 16-1 shows the block diagram of the ADC. The ADC voltage reference is software selectable to be either internally generated or externally supplied. FIGURE 16-1: ADC BLOCK DIAGRAM VDD ADPREF = 00 ADPREF = 11 VREF AN0 00000 AN1 00001 AN2 00010 VREF+/AN3 00011 AN4 00100 AN5 00101 AN6 00110 ADPREF = 10 ADC 10 GO/DONE ADFM AN29 11101 Temp Indicator 11110 FVR Buffer1 11111 0 = Left Justify 1 = Right Justify ADON(1) 16 VSS ADRESH ADRESL CHS<4:0>(2) Note 1: 2: When ADON = 0, all multiplexer inputs are disconnected. See ADCON0 register (Example 16-1) for detailed analog channel selection per device. 2011 Microchip Technology Inc. Preliminary DS41458B-page 149 PIC16(L)F1526/27 16.1 16.1.4 ADC Configuration When configuring and using the ADC the following functions must be considered: * * * * * * Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 16.1.1 The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 12.0 "I/O Ports" for more information. Note: 16.1.2 The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: * * * * * * * PORT CONFIGURATION Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal oscillator) The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11.5 TAD periods as shown in Figure 16-2. For correct conversion, the appropriate TAD specification must be met. Refer to the A/D conversion requirements in Section 25.0 "Electrical Specifications" for more information. Table 16-1 gives examples of appropriate ADC clock selections. Note: CHANNEL SELECTION CONVERSION CLOCK There are 32 channel selections available: * AN<29:0> pins * Temperature Indicator * FVR (Fixed Voltage Reference) Output Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. Refer to Section 14.0 "Fixed Voltage Reference (FVR)" and Section 15.0 "Temperature Indicator Module" for more information on these channel selections. The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 16.2 "ADC Operation" for more information. 16.1.3 ADC VOLTAGE REFERENCE The ADPREF bits of the ADCON1 register provides control of the positive voltage reference. The positive voltage reference can be: * * * * VREF+ pin VDD FVR 2.048V FVR 4.096V (Not available on LF devices) See Section 14.0 "Fixed Voltage Reference (FVR)" for more details on the Fixed Voltage Reference. DS41458B-page 150 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz FOSC/2 000 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s FOSC/4 100 (2) 200 ns (2) 250 ns (2) FOSC/8 001 400 ns(2) 0.5 s(2) FOSC/16 101 800 ns 010 FOSC/64 FRC FOSC/32 Legend: Note 1: 2: 3: 4: 1.0 s 4.0 s 1.0 s 2.0 s 8.0 s(3) 1.0 s 2.0 s 4.0 s 16.0 s(3) 1.6 s 2.0 s 4.0 s 110 3.2 s 4.0 s x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 500 ns 8.0 s (3) 1.0-6.0 s(1,4) 8.0 s (3) 16.0 s (3) 1.0-6.0 s(1,4) 32.0 s(3) 64.0 s(3) 1.0-6.0 s(1,4) Shaded cells are outside of recommended range. The FRC source has a typical TAD time of 1.6 s for VDD. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the device in Sleep mode. FIGURE 16-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b4 b1 b0 b6 b7 b2 b9 b8 b3 b5 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. 2011 Microchip Technology Inc. Preliminary DS41458B-page 151 PIC16(L)F1526/27 16.1.5 INTERRUPTS 16.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format. Figure 16-3 shows the two output formats. Note 1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. FIGURE 16-3: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH (ADFM = 0) ADRESL MSB LSB bit 7 bit 0 bit 7 Unimplemented: Read as `0' 10-bit A/D Result (ADFM = 1) MSB bit 7 LSB bit 0 Unimplemented: Read as `0' DS41458B-page 152 bit 0 bit 7 bit 0 10-bit A/D Result Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 16.2 16.2.1 16.2.4 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a `1'. Setting the GO/DONE bit of the ADCON0 register to a `1' will start the Analog-to-Digital conversion. Note: 16.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 16.2.6 "A/D Conversion Procedure". COMPLETION OF A CONVERSION When the conversion is complete, the ADC module will: * Clear the GO/DONE bit * Set the ADIF Interrupt Flag bit * Update the ADRESH and ADRESL registers with new conversion result 16.2.3 TERMINATING A CONVERSION If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRESH and ADRESL registers will be updated with the partially complete Analog-to-Digital conversion sample. Incomplete bits will match the last bit converted. Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2011 Microchip Technology Inc. ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. 16.2.5 SPECIAL EVENT TRIGGER The Special Event Trigger of the CCPx module allows periodic ADC measurements without software intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to zero. TABLE 16-2: SPECIAL EVENT TRIGGER Device CCP PIC16(L)F1526/27 CCP10 Using the Special Event Trigger does not assure proper ADC timing. It is the user's responsibility to ensure that the ADC timing requirements are met. Refer to Section 20.0 "Capture/Compare/PWM Modules" for more information. Preliminary DS41458B-page 153 PIC16(L)F1526/27 16.2.6 A/D CONVERSION PROCEDURE EXAMPLE 16-1: This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8. Configure Port: * Disable pin output driver (Refer to the TRIS register) * Configure pin as analog (Refer to the ANSEL register) Configure the ADC module: * Select ADC conversion clock * Configure voltage reference * Select ADC input channel * Turn on ADC module Configure ADC interrupt (optional): * Clear ADC interrupt flag * Enable ADC interrupt * Enable peripheral interrupt * Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: * Polling the GO/DONE bit * Waiting for the ADC interrupt (interrupts enabled) Read ADC Result. Clear the ADC interrupt flag (required if interrupt is enabled). A/D CONVERSION ;This code block configures the ADC ;for polling, Vdd and Vss references, Frc ;clock and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL ADCON1 ; MOVLW B'11110000' ;Right justify, Frc ;clock MOVWF ADCON1 ;Vdd and Vss Vref BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input BANKSEL ANSEL ; BSF ANSEL,0 ;Set RA0 to analog BANKSEL ADCON0 ; MOVLW B'00000001' ;Select channel AN0 MOVWF ADCON0 ;Turn ADC On CALL SampleTime ;Acquisiton delay BSF ADCON0,ADGO ;Start conversion BTFSC ADCON0,ADGO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 16.4 "A/D Acquisition Requirements". DS41458B-page 154 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 16.3 ADC Register Definitions The following registers are used to control the operation of the ADC. REGISTER 16-1: U-0 ADCON0: A/D CONTROL REGISTER 0 R/W-0/0 R/W-0/0 -- R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> R/W-0/0 R/W-0/0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6-2 CHS<4:0>: Analog Channel Select bits 00000 = AN0 00001 = AN1 00010 = AN2 00011 = AN3 00100 = AN4 00101 = AN5 00110 = AN6 * * * 11101 = AN29 11110 = Temperature Indicator(2). 11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(1) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: 2: See Section 14.0 "Fixed Voltage Reference (FVR)" for more information. See Section 15.0 "Temperature Indicator Module" for more information. 2011 Microchip Technology Inc. Preliminary DS41458B-page 155 PIC16(L)F1526/27 REGISTER 16-2: R/W-0/0 ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 U-0 -- -- R/W-0/0 R/W-0/0 ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are set to `0' when the conversion result is loaded. 0 = Left justified. Six Least Significant bits of ADRESL are set to `0' when the conversion result is loaded. bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock supplied from a dedicated RC oscillator) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock supplied from a dedicated RC oscillator) bit 3-2 Unimplemented: Read as `0' bit 1-0 ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits 00 = VREF is connected to VDD 01 = Reserved 10 = VREF is connected to external VREF pin(1) 11 = VREF is connected to internal Fixed Voltage Reference (FVR) module(1) Note 1: When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See Section 25.0 "Electrical Specifications" for details. DS41458B-page 156 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 REGISTER 16-3: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 16-4: R/W-x/u ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x/u ADRES<1:0> R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. 2011 Microchip Technology Inc. Preliminary DS41458B-page 157 PIC16(L)F1526/27 REGISTER 16-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u -- -- -- -- -- -- R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper 2 bits of 10-bit conversion result REGISTER 16-6: R/W-x/u ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result DS41458B-page 158 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 16.4 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 16-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 16-4. The maximum recommended impedance for analog sources is 10 k. As the EQUATION 16-1: Assumptions: source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 16-1 may be used. This equation assumes that 1/2 LSb error is used (1,024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. ACQUISITION TIME EXAMPLE Temperature = 50C and external impedance of 10k 5.0V V DD T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = T AMP + T C + T COFF = 2s + T C + Temperature - 25C 0.05s/C The value for TC can be approximated with the following equations: 1 = V CHOLD V AP P LI ED 1 - -------------------------n+1 2 -1 ;[1] VCHOLD charged to within 1/2 lsb -TC ---------- RC V AP P LI ED 1 - e = V CHOLD ;[2] VCHOLD charge response to VAPPLIED - Tc --------- 1 RC ;combining [1] and [2] V AP P LI ED 1 - e = V A PP LIE D 1 - -------------------------n+1 2 -1 Note: Where n = number of bits of the ADC. Solving for TC: T C = - C HOLD R IC + R SS + R S ln(1/2047) = - 10pF 1k + 7k + 10k ln(0.000488) = 1.37 s Therefore: T A CQ = 2s + 1.37s + 50C- 25C 0.05 s/C = 4.62s Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 2011 Microchip Technology Inc. Preliminary DS41458B-page 159 PIC16(L)F1526/27 FIGURE 16-4: ANALOG INPUT MODEL VDD Analog Input pin Rs VT 0.6V CPIN 5 pF VA RIC 1k Sampling Switch SS Rss I LEAKAGE(1) VT 0.6V CHOLD = 10 pF VSS/VREF- Legend: CHOLD CPIN 6V 5V VDD 4V 3V 2V = Sample/Hold Capacitance = Input Capacitance RSS I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance RSS = Resistance of Sampling Switch SS = Sampling Switch VT = Threshold Voltage 5 6 7 8 9 10 11 Sampling Switch (k) Note 1: Refer to Section 25.0 "Electrical Specifications". FIGURE 16-5: ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh ADC Output Code 3FDh 3FCh 3FBh 03h 02h 01h 00h Analog Input Voltage 0.5 LSB VREF- DS41458B-page 160 1.5 LSB Zero-Scale Transition Full-Scale Transition Preliminary VREF+ 2011 Microchip Technology Inc. PIC16(L)F1526/27 TABLE 16-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 ADCON0 -- ADCON1 ADFM Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 -- -- CHS<4:0> ADCS<2:0> Bit 1 Bit 0 GO/DONE ADON ADPREF<1:0> Register on Page 155 156 ADRESH A/D Result Register High 157, 158 ADRESL A/D Result Register Low 157, 158 ANSELA -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 121 ANSELB -- -- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 124 ANSELD -- -- -- -- ANSD3 ANSD2 ANSD1 ANSD0 130 ANSELE -- -- -- -- -- ANSE2 ANSE1 ANSE0 133 ANSELF ANSF7 ANSF6 ANSF5 ANSF4 ANSF3 ANSF2 ANSF1 ANSF0 136 ANSELG -- -- -- ANSG4 ANSG3 ANSG2 ANSG1 -- 139 CCP1CON -- -- DC1B<1:0> CCP1M<3:0> 197 CCP2CON -- -- DC2B<1:0> CCP2M<3:0> 197 CCP3CON -- -- DC3B<1:0> CCP3M<3:0> 197 CCP4CON -- -- DC4B<1:0> CCP4M<3:0> 197 CCP5CON -- -- DC5B<1:0> CCP5M<3:0> 197 CCP6CON -- -- DC6B<1:0> CCP6M<3:0> 197 CCP7CON -- -- DC7B<1:0> CCP7M<3:0> 197 CCP8CON -- -- DC8B<1:0> CCP8M<3:0> 197 CCP9CON -- -- DC9B<1:0> CCP9M<3:0> 197 CCP10CON -- -- DC10B<1:0> CCP10M<3:0> 197 FVRCON FVREN FVRRDY TSEN TSRNG INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 81 PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 85 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 120 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 123 CDAFVR<1:0> ADFVR<1:0> 146 80 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 129 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 132 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 135 TRISG -- -- -- TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 138 Legend: -- = unimplemented read as `0'. Shaded cells are not used for ADC module. 2011 Microchip Technology Inc. Preliminary DS41458B-page 161 PIC16(L)F1526/27 NOTES: DS41458B-page 162 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 17.0 17.1.2 TIMER0 MODULE In 8-Bit Counter mode, the Timer0 module will increment on either the rising or falling edge of the T0CKI pin. The edge that increments the counter is determined by the TMR0SE bit in the OPTION_REG register. TMR0SE = 1 selects the falling edge. The Timer0 module is an 8-bit timer/counter with the following features: * * * * * * 8-BIT COUNTER MODE 8-bit timer/counter register (TMR0) 8-bit prescaler (independent of Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow TMR0 can be used to gate Timer1/3/5 The 8-bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to `1'. Figure 17-1 is a block diagram of the Timer0 module. 17.1 Timer0 Operation The Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 17.1.1 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-Bit Timer mode is selected by clearing the TMR0CS bit of the OPTION_REG register. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. FIGURE 17-1: BLOCK DIAGRAM OF THE TIMER0 FOSC/4 Data Bus 0 8 T0CKI 1 Sync 2 TCY 1 TMR0 0 TMR0SE TMR0CS 8-bit Prescaler PSA Set Flag bit TMR0IF on Overflow Overflow to Timer1/3/5 8 PS<2:0> 2011 Microchip Technology Inc. Preliminary DS41458B-page 163 PIC16(L)F1526/27 17.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION_REG register. The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler. 17.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: 17.1.5 The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 8-BIT COUNTER MODE SYNCHRONIZATION When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section 25.0 "Electrical Specifications". 17.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41458B-page 164 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 17.2 Timer0 Control Register REGISTER 17-1: OPTION_REG: OPTION REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUEN INTEDG TMR0CS TMR0SE PSA R/W-1/1 R/W-1/1 R/W-1/1 PS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 WPUEN: Weak Pull-up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled) 0 = Weak pull-ups are enabled by individual WPUA latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 TMR0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 TMR0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is not assigned to the Timer0 module 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits TABLE 17-1: Name INTCON TRISA Timer0 Rate 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 80 OPTION_REG WPUEN TMR0 Bit Value INTEDG TMR0CS TMR0SE PSA PS<2:0> 165 Timer0 Module Register TRISA7 TRISA6 TRISA5 163* TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 120 Legend: -- = Unimplemented locations, read as `0'. Shaded cells are not used by the Timer0 module. * Page provides register information. 2011 Microchip Technology Inc. Preliminary DS41458B-page 165 PIC16(L)F1526/27 NOTES: DS41458B-page 166 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 18.0 * * * * TIMER1/3/5 MODULE WITH GATE CONTROL The Timer1/3/5 module is a 16-bit timer/counter with the following features: Figure 18-1 is a block diagram of the Timer1/3/5 module. * * * * * * * * 16-bit timer/counter register pair (TMRxH:TMRxL) Programmable internal or external clock source 2-bit prescaler Dedicated 32 kHz oscillator circuit Optionally synchronized comparator out Multiple Timer1/3/5 gate (count enable) sources Interrupt on overflow Wake-up on overflow (external clock, Asynchronous mode only) * Time base for the Capture/Compare function * Special Event Trigger (with CCP) * Selectable Gate Source Polarity FIGURE 18-1: Gate Toggle mode Gate Single-pulse mode Gate Value Status Gate Event Interrupt . The `x' variable used in this section is used to designate Timer1, Timer3 or Timer5. For example, TxCON references T1CON, T3CON or T5CON. PRx references PR1, PR3 or PR5. Note: TIMER1/3/5 BLOCK DIAGRAM TxGSS<1:0> TxG TxGSPM 00 From Timer0 Overflow 01 Timer2/4/6 Overflow(4) 10 Timer10 Overflow 11 0 TxG_IN TxGVAL 0 Single Pulse TMRxON TxGTM TxGPOL D Q CK R Q 1 Acq. Control 1 Q1 Data Bus D Q RD T1GCON EN Interrupt TxGGO/DONE Set TMRxGIF det TMRxGE Set flag bit TMRxIF on Overflow TMRxON To Comparator Module TMRx(2) TMRxH EN TMRxL Q D TxCLK Synchronized clock input 0 1 TMRxCS<1:0> LFINTOSC Secondary Oscillator SOSC/TxCKI TxSYNC 11 det 10 (See Figure 18-2) Note 1: 2: 3: 4: Synchronize(3) Prescaler 1, 2, 4, 8 FOSC Internal Clock 01 FOSC/4 Internal Clock 00 2 TxCKPS<1:0> FOSC/2 Internal Clock Sleep input ST Buffer is high-speed type when using TxCKI. Timer1 register increments on rising edge. Synchronize does not operate while in Sleep. See Table 18-4 for Timer selection. 2011 Microchip Technology Inc. Preliminary DS41458B-page 167 PIC16(L)F1526/27 FIGURE 18-2: TIMER1/3/5 CLOCK SOURCE DIAGRAM To Clock Switching (SOSC users) (1) TMR1CS<1:0> 0 10 SOSCO/T1CKI OUT 1 Secondary Oscillator SOSCI Timer 1 EN LFINTOSC 11 FOSC/4 00 FOSC 01 Timer1 T1CON[SOSCEN] T3CON[SOSCEN] T5CON[SOSCEN] TMR3CS<1:0> 1 10 (1) T3CKI 0 Timer 3 LFINTOSC 11 FOSC/4 00 FOSC 01 Timer3 TMR5CS<1:0> 1 10 (1) T5CKI 0 LFINTOSC 11 FOSC/4 00 FOSC 01 Timer5 Timer 5 Note 1: ST Buffer is high-speed type when using TxCKI. DS41458B-page 168 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 18.1 Timer1/3/5 Operation 18.2 The Timer1/3/5 module is a 16-bit incrementing counter which is accessed through the TMRxH:TMRxL register pair. Writes to TMRxH or TMRxL directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. Timer1/3/5 is enabled by configuring the TMRxON and TMRxGE bits in the TxCON and TxGCON registers, respectively. Table 18-1 displays the Timer1/3/5 enable selections. TABLE 18-1: TIMER1/3/5 ENABLE SELECTIONS Clock Source Selection The TMRxCS<1:0> and SOSCEN bits of the TxCON register are used to select the clock source for Timer1/3/5. Table 18-2 displays the clock source selections. 18.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected the TMRxH:TMRxL register pair will increment on multiples of FOSC as determined by the Timer1/3/5 prescaler. When the FOSC internal clock source is selected, the Timer1/3/5 register value will increment by four counts every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1/3/5 value. To utilize the full resolution of Timer1/3/5, an asynchronous input signal must be used to gate the Timer1/3/5 clock input. The following asynchronous sources may be used: Timer1/3/5 Operation TMRxON TMRxGE 0 0 Off 0 1 Off 1 0 Always On 1 1 Count Enabled * Asynchronous event on the TxG pin to Timer1/3/5 gate 18.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1/3/5 module may work as a timer or a counter. When enabled to count, Timer1/3/5 is incremented on the rising edge of the external clock input TxCKI. These external clock inputs (TxCKI) can be synchronized to the microcontroller system clock or they can run asynchronously. When used as a timer with a clock oscillator, an external 32.768 kHz crystal can be used in conjunction with the dedicated internal oscillator circuit. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: *Timer1/3/5 enabled after POR *Write to TMRxH or TMRxL *Timer1/3/5 is disabled *Timer1/3/5 is disabled (TMRxON = 0) when TxCKI is high then Timer1/3/5 is enabled (TMRxON = 1) when TxCKI is low. TABLE 18-2: CLOCK SOURCE SELECTIONS TMRxCS<1:0> SOSCEN Clock Source 00 x Instruction Clock (FOSC/4) 01 x System Clock (FOSC) 0 External Clocking on TxCKI Pin 1 Secondary Oscillator Circuit on SOSCI/SOSCO Pins x LFINTOSC 10 11 2011 Microchip Technology Inc. Preliminary DS41458B-page 169 PIC16(L)F1526/27 18.3 18.5.1 Timer1/3/5 Prescaler Timer1/3/5 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The TxCKPS bits of the TxCON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMRxH or TMRxL. 18.4 Timer1/3/5 Oscillator READING AND WRITING TIMER1/3/5 IN ASYNCHRONOUS COUNTER MODE Reading TMRxH or TMRxL while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. A dedicated low-power 32.768 kHz oscillator circuit is built-in between pins SOSCI (input) and SOSCO (amplifier output). This internal circuit is to be used in conjunction with an external 32.768 kHz crystal. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMRxH:TMRxL register pair. The oscillator circuit is enabled by setting the SOSCEN bit of the TxCON register. The oscillator will continue to run during Sleep. 18.6 Note: 18.5 The oscillator requires a start-up and stabilization time before use. Thus, SOSCEN should be set and a suitable delay observed prior to enabling Timer1/3/5. Timer1/3/5 Operation in Asynchronous Counter Mode Note: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment. DS41458B-page 170 Timer1/3/5 can be configured to count freely or the count can be enabled and disabled using Timer1/3/5 gate circuitry. This is also referred to as Timer1/3/5 Gate Enable. Timer1/3/5 gate can also be driven by multiple selectable sources. 18.6.1 If control bit TxSYNC of the TxCON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If the external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 18.5.1 "Reading and Writing Timer1/3/5 in Asynchronous Counter Mode"). Timer1/3/5 Gate TIMER1/3/5 GATE ENABLE The Timer1/3/5 Gate Enable mode is enabled by setting the TMRxGE bit of the TxGCON register. The polarity of the Timer1/3/5 Gate Enable mode is configured using the TxGPOL bit of the TxGCON register. When Timer1/3/5 Gate Enable mode is enabled, Timer1/3/5 will increment on the rising edge of the Timer1/3/5 clock source. When Timer1/3/5 Gate Enable mode is disabled, no incrementing will occur and Timer1/3/5 will hold the current count. See Figure 18-4 for timing details. TABLE 18-3: TIMER1/3/5 GATE ENABLE SELECTIONS Timer1/3/5 Operation TxCLK TxGPOL TxG 0 0 Counts 0 1 Holds Count 1 0 Holds Count 1 1 Counts Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 18.6.2 TIMER1/3/5 GATE SOURCE SELECTION The Timer1/3/5 gate source can be selected from one of four different sources. Source selection is controlled by the TxGSS bits of the TxGCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the TxGPOL bit of the TxGCON register. TABLE 18-4: T1GSS 00 TIMER1/3/5 GATE SOURCES Timer1 Gate Source T1G Pin T3G Pin Timer2 match PR2 (TMR2 increments to match PR2) 18.6.4 TxG Pin Gate Operation Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1/3/5 gate circuitry. 18.6.3 TIMER1/3/5 GATE TOGGLE MODE When Timer1/3/5 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1/3/5 gate signal, as opposed to the duration of a single level pulse. The Timer1/3/5 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 18-5 for timing details. Timer1/3/5 Gate Toggle mode is enabled by setting the TxGTM bit of the TxGCON register. When the TxGTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. Note: Timer6 match PR6 Timer10 match PR10 The TxG pin is one source for Timer1/3/5 gate control. It can be used to supply an external source to the Timer1/3/5 gate circuitry. 18.6.2.2 T5G Pin Timer4 match PR4 11 18.6.2.1 Timer5 Gate Source Overflow of Timer0 (TMR0 increments from FFh to 00h) 01 10 Timer3 Gate Source Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. 2011 Microchip Technology Inc. TIMER1/3/5 GATE SINGLE-PULSE MODE When Timer1/3/5 Gate Single-Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1/3/5 Gate Single-Pulse mode is first enabled by setting the TxGSPM bit in the TxGCON register. Next, the TxGGO/DONE bit in the TxGCON register must be set. The Timer1/3/5 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the TxGGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1/3/5 until the TxGGO/DONE bit is once again set in software. See Figure 18-6 for timing details. If the Single Pulse Gate mode is disabled by clearing the TxGSPM bit in the TxGCON register, the TxGGO/DONE bit should also be cleared. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1/3/5 gate source to be measured. See Figure 18-7 for timing details. 18.6.5 TIMER1/3/5 GATE VALUE STATUS When Timer1/3/5 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the TxGVAL bit in the TxGCON register. The TxGVAL bit is valid even when the Timer1/3/5 gate is not enabled (TMRxGE bit is cleared). Preliminary DS41458B-page 171 PIC16(L)F1526/27 18.6.6 TIMER1/3/5 GATE EVENT INTERRUPT 18.9 When Timer1/3/5 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of TxGVAL occurs, the TMRxGIF flag bit in the PIR1 register will be set. If the TMRxGIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMRxGIF flag bit operates even when the Timer1/3/5 gate is not enabled (TMRxGE bit is cleared). 18.7 Timer1/3/5 Interrupt The Timer1/3/5 register pair (TMRxH:TMRxL) increments to FFFFh and rolls over to 0000h. When Timer1/3/5 rolls over, the Timer1/3/5 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: * * * * TMRxON bit of the TxCON register TMRxIE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMRxIF bit in the Interrupt Service Routine. Note: 18.8 The TMRxH:TMRxL register pair and the TMRxIF bit should be cleared before enabling interrupts. Timer1/3/5 Operation During Sleep Timer1/3/5 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: * * * * * TMRxON bit of the TxCON register must be set TMRxIE bit of the PIE1 register must be set PEIE bit of the INTCON register must be set TxSYNC bit of the TxCON register must be set TMRxCS bits of the TxCON register must be configured * SOSCEN bit of the TxCON register must be configured ECCP/CCP Capture/Compare Time Base The CCP module uses the TMRxH:TMRxL register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMRxH:TMRxL register pair is copied into the CCPR1H:CCPR1L register pair on a configured event. In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in the TMRxH:TMRxL register pair. This event can be a Special Event Trigger. For more information, see "Capture/Compare/PWM Modules". Section 20.0 18.10 ECCP/CCP Special Event Trigger When the CCP is configured to trigger a special event, the trigger will clear the TMRxH:TMRxL register pair. This special event does not cause a Timer1/3/5 interrupt. The CCP module may still be configured to generate a CCP interrupt. In this mode of operation, the CCPR1H:CCPR1L register pair becomes the period register for Timer1/3/5. Timer1/3/5 should be synchronized and FOSC/4 should be selected as the clock source in order to utilize the Special Event Trigger. Asynchronous operation of Timer1/3/5 can cause a Special Event Trigger to be missed. In the event that a write to TMRxH or TMRxL coincides with a Special Event Trigger from the CCP, the write will take precedence. For more information, see Section 16.2.5 "Special Event Trigger". The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine. Timer1/3/5 oscillator will continue to operate in Sleep regardless of the TxSYNC bit setting. DS41458B-page 172 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 18-3: TIMER1/3/5 INCREMENTING EDGE TXCKI = 1 when TMR1 Enabled TXCKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. FIGURE 18-4: TIMER1/3/5 GATE ENABLE MODE TMRxGE TxGPOL TxG_IN TxCKI TxGVAL Timer1/3/5 N 2011 Microchip Technology Inc. N+1 Preliminary N+2 N+3 N+4 DS41458B-page 173 PIC16(L)F1526/27 FIGURE 18-5: TIMER1/3/5 GATE TOGGLE MODE TMRxGE TxGPOL TxGTM TxG_IN TxCKI TxGVAL Timer1/3/5 FIGURE 18-6: N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 TIMER1/3/5 GATE SINGLE-PULSE MODE TMRxGE TxGPOL TxGSPM TxGGO/ Cleared by hardware on falling edge of TxGVAL Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL Timer1/3/5 TMRxGIF DS41458B-page 174 N N+1 N+2 Set by hardware on falling edge of TxGVAL Cleared by software Preliminary Cleared by software 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 18-7: TIMER1/3/5 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMRxGE TxGPOL TxGSPM TxGTM TxGGO/ Cleared by hardware on falling edge of TxGVAL Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL Timer1/3/5 TMRxGIF N Cleared by software 2011 Microchip Technology Inc. N+1 N+2 N+3 Set by hardware on falling edge of TxGVAL Preliminary N+4 Cleared by software DS41458B-page 175 PIC16(L)F1526/27 18.11 Timer1/3/5 Control Register The Timer1/3/5 Control register (TxCON), shown in Register 18-1, is used to control Timer1/3/5 and select the various features of the Timer1/3/5 module. REGISTER 18-1: R/W-0/u TXCON: TIMER1/3/5 CONTROL REGISTER R/W-0/u R/W-0/u TMRxCS<1:0> R/W-0/u TxCKPS<1:0> R/W-0/u R/W-0/u U-0 R/W-0/u SOSCEN TxSYNC -- TMRxON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 TMRxCS<1:0>: Timer1/3/5 Clock Source Select bits 11 = Timer1/3/5 clock source is LFINTOSC 10 = Timer1/3/5 clock source is pin or oscillator: If SOSCEN = 0: External clock from TxCKI pin (on the rising edge) If SOSCEN = 1: Crystal oscillator on SOSCI/SOSCO pins 01 = Timer1/3/5 clock source is system clock (FOSC) 00 = Timer1/3/5 clock source is instruction clock (FOSC/4) bit 5-4 TxCKPS<1:0>: Timer1/3/5 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 SOSCEN: LP Oscillator Enable Control bit 1 = Dedicated secondary oscillator circuit enabled 0 = Dedicated secondary oscillator circuit disabled bit 2 TxSYNC: Timer1/3/5 External Clock Input Synchronization Control bit TMRxCS<1:0> = 1X: 1 = Do not synchronize external clock input 0 = Synchronize external clock input with system clock (FOSC) TMRxCS<1:0> = 0X: This bit is ignored. bit 1 Unimplemented: Read as `0' bit 0 TMRxON: Timer1/3/5 On bit 1 = Enables Timer1/3/5 0 = Stops Timer1/3/5 Clears Timer1/3/5 gate flip-flop DS41458B-page 176 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 18.12 Timer1/3/5 Gate Control Register The Timer1/3/5 Gate Control register (TxGCON), shown in Register 18-2, is used to control Timer1/3/5 Gate. REGISTER 18-2: TXGCON: TIMER1/3/5 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x TMRxGE TxGPOL TxGTM TxGSPM TxGGO/ DONE TxGVAL R/W-0/u R/W-0/u TxGSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Bit is cleared by hardware bit 7 TMRxGE: Timer1/3/5 Gate Enable bit If TMRxON = 0: This bit is ignored If TMRxON = 1: 1 = Timer1/3/5 counting is controlled by the Timer1/3/5 gate function 0 = Timer1/3/5 counts regardless of Timer1/3/5 gate function bit 6 TxGPOL: Timer1/3/5 Gate Polarity bit 1 = Timer1/3/5 gate is active-high (Timer1/3/5 counts when gate is high) 0 = Timer1/3/5 gate is active-low (Timer1/3/5 counts when gate is low) bit 5 TxGTM: Timer1/3/5 Gate Toggle Mode bit 1 = Timer1/3/5 Gate Toggle mode is enabled 0 = Timer1/3/5 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1/3/5 gate flip-flop toggles on every rising edge. bit 4 TxGSPM: Timer1/3/5 Gate Single-Pulse Mode bit 1 = Timer1/3/5 Gate Single-Pulse mode is enabled and is controlling Timer1/3/5 gate 0 = Timer1/3/5 Gate Single-Pulse mode is disabled bit 3 TxGGO/DONE: Timer1/3/5 Gate Single-Pulse Acquisition Status bit 1 = Timer1/3/5 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1/3/5 gate single-pulse acquisition has completed or has not been started bit 2 TxGVAL: Timer1/3/5 Gate Current State bit Indicates the current state of the Timer1/3/5 gate that could be provided to TMRxH:TMRxL. Unaffected by Timer1/3/5 Gate Enable (TMRxGE). bit 1-0 TxGSS<1:0>: Timer1/3/5 Gate Source Select bits 00 = Timer1/3/5 gate pin 01 = Timer0 overflow output 10 = Timer2/4/6/8 match PR2/PR4/PR6/PR8(1) 11 = Timer10 match PR10 Note 1: See Table 18-4 for Timer selection. 2011 Microchip Technology Inc. Preliminary DS41458B-page 177 PIC16(L)F1526/27 18.12.1 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 12.1 "Alternate Pin Function" for more information. TABLE 18-5: Name ANSELA SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1/3/5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 -- -- ANSA5 -- ANSA3 ANSA2 Bit 1 Bit 0 Register on Page ANSA1 ANSA0 121 T3CKISEL CCP2SEL APFCON -- -- CCP1CON -- -- DC1B<1:0> CCP1M<3:0> 197 CCP2CON -- -- DC2B<1:0> CCP2M<3:0> 197 CCP3CON -- -- DC3B<1:0> CCP3M<3:0> 197 CCP4CON -- -- DC4B<1:0> CCP4M<3:0> 197 CCP5CON -- -- DC5B<1:0> CCP5M<3:0> 197 CCP6CON -- -- DC6B<1:0> CCP6M<3:0> 197 CCP7CON -- -- DC7B<1:0> CCP7M<3:0> 197 CCP8CON -- -- DC8B<1:0> CCP8M<3:0> 197 CCP9CON -- -- DC9B<1:0> CCP9M<3:0> 197 CCP10CON INTCON -- -- GIE PEIE -- -- -- DC10B<1:0> -- CCP10M<3:0> TMR0IE INTE IOCIE 118 197 TMR0IF INTF IOCIF 80 PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 81 PIE2 OSFIE TMR5GIE TMR3GIE -- BCL1IE TMR10IE TMR8IE CCP2IE 82 PIE3 CCP6IE CCP5IE CCP4IE CCP3IE TMR6IE TMR5IE TMR4IE TMR3IE 83 PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 85 PIR2 OSFIF TMR5GIF TMR3GIF -- BCL1IF TMR10IF TMR8IF CCP2IF 86 PIR3 CCP6IF CCP5IF CCP4IF CCP3IF TMR6IF TMR5IF TMR4IF TMR3IF 87 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 172* TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register 172* TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register 172* TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 172* TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register 172* TMR5L Holding Register for the Least Significant Byte of the 16-bit TMR5 Register 172* TRISA3 TRISA2 TRISA1 TRISA0 120 T1CON TMR1CS<1:0> T1CKPS<1:0> SOSCEN T1SYNC -- TMR1ON 176 T3CON TMR3CS<1:0> T3CKPS<1:0> SOSCEN T3SYNC -- TMR3ON 176 T5CON TMR5CS<1:0> T5CKPS<1:0> SOSCEN T5SYNC -- TMR5ON 176 TRISA TRISA7 TRISA6 TRISA5 TRISA4 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL T1GSS<1:0> 177 T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/ DONE T3GVAL T3GSS<1:0> 177 T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/ DONE T5GVAL T5GSS<1:0> 177 Legend: * -- = unimplemented, read as `0'. Shaded cells are not used by the Timer1/3/5 module. Page provides register information. DS41458B-page 178 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 19.0 TIMER2/4/6/8/10 MODULES There are up to five identical Timer2-type modules available. To maintain pre-existing naming conventions, the Timers are called Timer2, Timer4, Timer6, Timer8 and Timer10 (also Timer2/4/6/8/10). Note: The `x' variable used in this section is used to designate Timer2, Timer4, Timer6, Timer8 or Timer10. For example, TxCON references T2CON, T4CON, T6CON, T8CON or T10CON. PRx references PR2, PR4, PR6, PR8 or PR10. The Timer2/4/6/8/10 modules incorporate the following features: * 8-bit Timer and Period registers (TMR2/4/6/8/10 and PR2/4/6/8/10, respectively) * Readable and writable (both registers) * Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) * Software programmable postscaler (1:1 to 1:16) * Interrupt on TMR2/4/6/8/10 match with PR2/4/6/8/10, respectively * Optional use as the shift clock for the MSSPx modules (Timer2 only) See Figure 19-1 Timer2/4/6/8/10. for FIGURE 19-1: TIMER2/4/6/8/10 BLOCK DIAGRAM FOSC/4 a block Prescaler 1:1, 1:4, 1:16, 1:64 2 diagram of TMRx Comparator Reset EQ TMRx Output Postscaler 1:1 to 1:16 Sets Flag bit TMRxIF TxCKPS<1:0> 4 PRx TxOUTPS<3:0> 2011 Microchip Technology Inc. Preliminary DS41458B-page 179 PIC16(L)F1526/27 19.1 Timer2/4/6/8/10 Operation 19.3 The clock input to the Timer2/4/6/8/10 modules is the system instruction clock (FOSC/4). TMR2/4/6/8/10 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, TxCKPS<1:0> of the TxCON register. The value of TMR2/4/6/8/10 is compared to that of the Period register, PR2/4/6/8/10, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2/4/6/8/10 to 00h on the next cycle and drives the output counter/postscaler (see Section 19.2 "Timer2/4/6/8/10 Interrupt"). Timer2/4/6/8/10 Output The unscaled output of TMR2/4/6/8/10 is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode. Timer2 can be optionally used as the shift clock source for the MSSPx modules operating in SPI mode. Additional information is provided in Section X.X "SSP Module Overview" 19.4 Timer2/4/6/8/10 Operation During Sleep The Timer2/4/6/8/10 timers cannot be operated while the processor is in Sleep mode. The contents of the TMR2/4/6/8/10 and PR2/4/6/8/10 registers will remain unchanged while the processor is in Sleep mode. The TMR2/4/6/8/10 and PR2/4/6/8/10 registers are both directly readable and writable. The TMR2/4/6/8/10 register is cleared on any device Reset, whereas the PR2/4/6/8/10 register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events: * * * * * * * * * a write to the TMR2/4/6/8/10 register a write to the TxCON register Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset Watchdog Timer (WDT) Reset Stack Overflow Reset Stack Underflow Reset RESET Instruction Note: 19.2 TMR2/4/6/8/10 is not cleared when TxCON is written. Timer2/4/6/8/10 Interrupt Timer2/4/6/8/10 can also generate an optional device interrupt. The Timer2/4/6/8/10 output signal (TMRx-to-PRx match) provides the input for the 4-bit counter/postscaler. This counter generates the TMRx match interrupt flag which is latched in TMRxIF of the PIRx register. The interrupt is enabled by setting the TMR2/4/6/8/10 Match Interrupt Enable bit, TMRxIE of the PIEx register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, TxOUTPS<3:0>, of the TxCON register. DS41458B-page 180 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 19.5 Timer2/4/6/8/10 Control Register REGISTER 19-1: U-0 TXCON: TIMER2/TIMER4/TIMER6/TIMER8/TIMER10 CONTROL REGISTER R/W-0/0 -- R/W-0/0 R/W-0/0 R/W-0/0 TxOUTPS<3:0> R/W-0/0 R/W-0/0 TMRxON bit 7 R/W-0/0 TxCKPS<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6-3 TxOUTPS<3:0>: Timerx Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Postscaler 0100 = 1:5 Postscaler 0101 = 1:6 Postscaler 0110 = 1:7 Postscaler 0111 = 1:8 Postscaler 1000 = 1:9 Postscaler 1001 = 1:10 Postscaler 1010 = 1:11 Postscaler 1011 = 1:12 Postscaler 1100 = 1:13 Postscaler 1101 = 1:14 Postscaler 1110 = 1:15 Postscaler 1111 = 1:16 Postscaler bit 2 TMRxON: Timerx On bit 1 = Timer2/4/6 is on 0 = Timer2/4/6 is off bit 1-0 TxCKPS<1:0>: Timer2-type Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 10 = Prescaler is 16 11 = Prescaler is 64 2011 Microchip Technology Inc. Preliminary DS41458B-page 181 PIC16(L)F1526/27 TABLE 19-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6/8/10 Bit 6 CCP1CON -- -- DC1B<1:0> CCP1M<3:0> 197 CCP2CON -- -- DC2B<1:0> CCP2M<3:0> 197 CCP3CON -- -- DC3B<1:0> CCP3M<3:0> 197 CCP4CON -- -- DC4B<1:0> CCP4M<3:0> 197 CCP5CON -- -- DC5B<1:0> CCP5M<3:0> 197 CCP6CON -- -- DC6B<1:0> CCP6M<3:0> 197 CCP7CON -- -- DC7B<1:0> CCP7M<3:0> 197 CCP8CON -- -- DC8B<1:0> CCP8M<3:0> 197 CCP9CON -- -- DC9B<1:0> CCP9M<3:0> 197 CCP10CON -- -- DC10B<1:0> CCP10M<3:0> GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 80 PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 81 PIE2 OSFIE TMR5GIE TMR3GIE -- BCL1IE TMR10IE TMR8IE CCP2IE 82 PIE3 CCP6IE CCP5IE CCP4IE CCP3IE TMR6IE TMR5IE TMR4IE TMR3IE 83 PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 85 PIR2 OSFIF TMR5GIF TMR3GIF -- BCL1IF TMR10IF TMR8IF CCP2IF 86 PIR3 CCP6IF CCP5IF CCP4IF CCP3IF TMR6IF TMR5IF TMR4IF TMR3IF INTCON Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page Bit 7 197 87 PR2 Timer2 Module Period Register 213* PR4 Timer4 Module Period Register 213* PR6 Timer6 Module Period Register 213* PR8 Timer8 Module Period Register 213* PR10 Timer10 Module Period Register 213* T2CON -- T2OUTPS<3:0> TMR2ON T2CKPS1 T2CKPS0 215 T4CON -- T4OUTPS<3:0> TMR4ON T4CKPS1 T4CKPS0 215 T6CON -- T6OUTPS<3:0> TMR6ON T6CKPS1 T6CKPS0 215 T8CON -- T8OUTPS<3:0> TMR8ON T8CKPS1 T8CKPS0 215 T10CON -- T10OUTPS<3:0> TMR10ON T10CKPS1 T10CKPS0 215 TMR2 Holding Register for the 8-bit TMR2 Register 213* TMR4 Holding Register for the 8-bit TMR4 Register(1) 213* TMR6 Holding Register for the 8-bit TMR6 Register(1) 213* TMR8 Holding Register for the 8-bit TMR8 Register(1) 213* TMR10 Holding Register for the 8-bit TMR10 Register(1) 213* Legend: * -- = unimplemented location, read as `0'. Shaded cells are not used for Timer2/4/6/8/10 module. Page provides register information. DS41458B-page 182 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 20.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. This device contains ten standard Capture/Compare/PWM modules (CCP1 through CCP10). The capture and compare functions are identical for all CCP modules. Note 1: In devices with more than one CCP module, it is very important to pay close attention to the register names used. A number placed after the module acronym is used to distinguish between separate modules. For example, the CCP1CON and CCP2CON control the same operational aspects of two completely different CCP modules. 2: Throughout this section, generic references to a CCP module in any of its operating modes may be interpreted as being equally applicable to any CCPx module. Register names, module signals, I/O pins, and bit names may use the generic designator 'x' to indicate the use of a numeral to distinguish a particular module, when required. 2011 Microchip Technology Inc. Preliminary DS41458B-page 183 PIC16(L)F1526/27 20.1 20.1.2 Capture Mode The Capture mode function described in this section is available and identical for CCP modules. Capture mode makes use of the 16-bit Timer1/3/5 resource. When an event occurs on the CCPx pin, the 16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMRxH:TMRxL register pair, respectively. An event is defined as one of the following and is configured by the CCPxM<3:0> bits of the CCPxCON register: * * * * Timer1/3/5 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. See Section 18.0 "Timer1/3/5 Module with Gate Control" for more information on configuring Timer1/3/5. TABLE 20-1: Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge When a capture is made, the Interrupt Request flag bit CCPxIF of the PIRx register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPRxH, CCPRxL register pair is read, the old captured value is overwritten by the new captured value. Figure 20-1 shows a simplified diagram of the Capture operation. 20.1.1 CCP PIN CONFIGURATION In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit. Also, the CCP2x pin function can be moved to alternative pins using the APFCON register. Refer to Section 12.1 "Alternate Pin Function" for more details. Note: If the CCPx pin is configured as an output, a write to the port can cause a capture condition. FIGURE 20-1: Prescaler 1, 4, 16 TIMER1/3/5 MODE RESOURCE CCPx CAPTURE TIMER1/3/5 RESOURCES CCP TMR1 TMR3 CCP1 CCP2 CCP3 CCP4 CCP5 CCP6 CCP7 CCP8 CCP9 CCP10 20.1.3 TMR5 SOFTWARE INTERRUPT MODE When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit of the PIEx register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF interrupt flag bit of the PIRx register following any change in Operating mode. CAPTURE MODE OPERATION BLOCK DIAGRAM Set Flag bit CCPxIF (PIRx register) CCPx Pin CCPRxH and Edge Detect CCPRxL Capture Enable TMRxH TMRxL CCPxM<3:0> System Clock (FOSC) DS41458B-page 184 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 20.1.4 CCP PRESCALER 20.1.6 There are four prescaler settings specified by the CCPxM<3:0> bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the prescaler. Equation 20-1 demonstrates the code to perform this function. EXAMPLE 20-1: ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 12.1 "Alternate Pin Function" for more information. CHANGING BETWEEN CAPTURE PRESCALERS BANKSEL CCPxCON CLRF MOVLW MOVWF 20.1.5 ;Set Bank bits to point ;to CCPxCON CCPxCON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ;the new prescaler ;move value and CCP ON CCPxCON ;Load CCPxCON with this ;value CAPTURE DURING SLEEP Capture mode depends upon the Timer1/3/5 module for proper operation. There are two options for driving the Timer1/3/5 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. When Timer1/3/5 is clocked by FOSC/4, Timer1/3/5 will not increment during Sleep. When the device wakes from Sleep, Timer1/3/5 will continue from its previous state. Capture mode will operate during Sleep when Timer1/3/5 is clocked by an external clock source. 2011 Microchip Technology Inc. Preliminary DS41458B-page 185 PIC16(L)F1526/27 TABLE 20-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Register on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 APFCON -- -- -- -- -- -- T3CKISEL CCP2SEL CCP1CON -- -- DC1B<1:0> CCP1M<3:0> 197 CCP2CON -- -- DC2B<1:0> CCP2M<3:0> 197 CCP3CON -- -- DC3B<1:0> CCP3M<3:0> 197 CCP4CON -- -- DC4B<1:0> CCP4M<3:0> 197 CCP5CON -- -- DC5B<1:0> CCP5M<3:0> 197 CCP6CON -- -- DC6B<1:0> CCP6M<3:0> 197 CCP7CON -- -- DC7B<1:0> CCP7M<3:0> 197 CCP8CON -- -- DC8B<1:0> CCP8M<3:0> 197 CCP9CON -- -- DC9B<1:0> CCP9M<3:0> 197 CCP10CON -- -- DC10B<1:0> CCP10M<3:0> 197 118 CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) 184* CCPR2L Capture/Compare/PWM Register 2 Low Byte (LSB) 184* CCPR3L Capture/Compare/PWM Register 3 Low Byte (LSB) 184* CCPR4L Capture/Compare/PWM Register 4 Low Byte (LSB) 184* CCPR5L Capture/Compare/PWM Register 5 Low Byte (LSB) 184* CCPR6L Capture/Compare/PWM Register 6 Low Byte (LSB) 184* CCPR7L Capture/Compare/PWM Register 7 Low Byte (LSB) 184* CCPR8L Capture/Compare/PWM Register 8 Low Byte (LSB) 184* CCPR9L Capture/Compare/PWM Register 9 Low Byte (LSB) 184* CCPR10L Capture/Compare/PWM Register 10 Low Byte (LSB) 184* CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) 184* CCPR2H Capture/Compare/PWM Register 2 High Byte (MSB) 184* CCPR3H Capture/Compare/PWM Register 3 High Byte (MSB) 184* CCPR4H Capture/Compare/PWM Register 4 High Byte (MSB) 184* CCPR5H Capture/Compare/PWM Register 5 High Byte (MSB) 184* CCPR6H Capture/Compare/PWM Register 6 High Byte (MSB) 184* CCPR7H Capture/Compare/PWM Register 7 High Byte (MSB) 184* CCPR8H Capture/Compare/PWM Register 8 High Byte (MSB) 184* CCPR9H Capture/Compare/PWM Register 9 High Byte (MSB) 184* CCPR10H Capture/Compare/PWM Register 10 High Byte (MSB) INTCON 184* GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 80 PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 81 PIE2 OSFIE TMR5GIE TMR3GIE -- BCL1IE TMR10IE TMR8IE CCP2IE 82 PIE3 CCP6IE CCP5IE CCP4IE CCP3IE TMR6IE TMR5IE TMR4IE TMR3IE 83 PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 84 PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 85 PIR2 OSFIF TMR5GIF TMR3GIF -- BCL1IF TMR10IF TMR8IF CCP2IF 86 PIR3 CCP6IF CCP5IF CCP4IF CCP3IF TMR6IF TMR5IF TMR4IF TMR3IF 87 PIR4 CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF 88 T1CON TMR1CS<1:0> T1CKPS<1:0> SOSCEN T1SYNC -- TMR1ON 176 T3CON TMR3CS<1:0> T3CKPS<1:0> SOSCEN T3SYNC -- TMR3ON 176 T5CON TMR5CS<1:0> T5CKPS<1:0> SOSCEN T5SYNC -- TMR5ON 176 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 177 T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/DONE T3GVAL T3GSS<1:0> 177 Legend: -- = Unimplemented location, read as `0'. Shaded cells are not used by Capture mode. * Page provides register information. DS41458B-page 186 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 TABLE 20-2: Name T5GCON SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TMR5GE T5GPOL T5GTM T5GSPM T5GGO/DONE T5GVAL Bit 1 Bit 0 T5GSS<1:0> Register on Page 177 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 172* TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register 172* TMR6L Holding Register for the Least Significant Byte of the 16-bit TMR6 Register 172* TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 172* TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register 172* TMR6H Holding Register for the Most Significant Byte of the 16-bit TMR6 Register TRISA Legend: TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 172* TRISA2 TRISA1 TRISA0 120 -- = Unimplemented location, read as `0'. Shaded cells are not used by Capture mode. * Page provides register information. 2011 Microchip Technology Inc. Preliminary DS41458B-page 187 PIC16(L)F1526/27 20.2 20.2.1 Compare Mode CCP PIN CONFIGURATION The Compare mode function described in this section is available and identical for CCP modules. The user must configure the CCPx pin as an output by clearing the associated TRIS bit. Compare mode makes use of the 16-bit Timer1/3/5 resource. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMRxH:TMRxL register pair. When a match occurs, one of the following events can occur: Also, the CCPx pin function can be moved to alternative pins using the APFCON register. Refer to Section 12.1 "Alternate Pin Function" for more details. * * * * * Toggle the CCPx output Set the CCPx output Clear the CCPx output Generate a Special Event Trigger Generate a Software Interrupt Note: 20.2.2 The action on the pin is based on the value of the CCPxM<3:0> control bits of the CCPxCON register. At the same time, the interrupt flag CCPxIF bit is set. Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. TIMER1/3/5 MODE RESOURCE In Compare mode, Timer1/3/5 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. All Compare modes can generate an interrupt. Figure 20-2 shows a simplified diagram of the Compare operation. FIGURE 20-2: TABLE 20-3: COMPARE MODE OPERATION BLOCK DIAGRAM CCPxM<3:0> Mode Select Set CCPxIF Interrupt Flag (PIRx) 4 CCPRxH CCPRxL CCPx Pin Q S R Output Logic Match TRIS Output Enable Special Event Trigger Comparator TMRxH TMRxL CCP TMR1 TMR3 CCP1 CCP2 CCP3 CCP4 CCP5 CCP6 CCP7 CCP8 CCP9 CCP10 TMR5 See Section 18.0 "Timer1/3/5 Module with Gate Control" for more information on configuring Timer1/3/5. Note: DS41458B-page 188 CCPx COMPARE TIMER1/3/5 RESOURCES Preliminary Clocking Timer1/3/5 from the system clock (FOSC) should not be used in Compare mode. In order for Compare mode to recognize the trigger event on the CCPx pin, Timer1/3/5 must be clocked from the instruction clock (FOSC/4) or from an external clock source. 2011 Microchip Technology Inc. PIC16(L)F1526/27 20.2.3 SOFTWARE INTERRUPT MODE 20.2.5 COMPARE DURING SLEEP When Generate Software Interrupt mode is chosen (CCPxM<3:0> = 1010), the CCPx module does not assert control of the CCPx pin (see the CCPxCON register). The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. 20.2.4 20.2.6 SPECIAL EVENT TRIGGER When Special Event Trigger mode is chosen (CCPxM<3:0> = 1011), the CCPx module does the following: * Resets Timer1/3/5 * Starts an ADC conversion if ADC is enabled The CCPx module does not assert control of the CCPx pin in this mode. ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 12.1 "Alternate Pin Function" for more information. The Special Event Trigger output of the CCP occurs immediately upon a match between the TMRxH, TMRxL register pair and the CCPRxH, CCPRxL register pair. The TMRxH, TMRxL register pair is not reset until the next rising edge of the Timer1/3/5 clock. The Special Event Trigger output starts an A/D conversion (if the A/D module is enabled). This allows the CCPRxH, CCPRxL register pair to effectively provide a 16-bit programmable period register for Timer1/3/5. TABLE 20-4: SPECIAL EVENT TRIGGER Device CCPx PIC16(L)F1526/27 CCP10 Refer to Section 16.2.5 "Special Event Trigger" for more information. Note 1: The Special Event Trigger from the CCP module does not set interrupt flag bit TMRxIF of the PIRx register. 2: Removing the match condition by changing the contents of the CCPRxH and CCPRxL register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1/3/5 Reset, will preclude the Reset from occurring. 2011 Microchip Technology Inc. Preliminary DS41458B-page 189 PIC16(L)F1526/27 TABLE 20-5: Name SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Register on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 APFCON -- -- -- -- -- -- T3CKISEL CCP2SEL CCP1CON -- -- DC1B<1:0> CCP1M<3:0> 197 CCP2CON -- -- DC2B<1:0> CCP2M<3:0> 197 CCP3CON -- -- DC3B<1:0> CCP3M<3:0> 197 CCP4CON -- -- DC4B<1:0> CCP4M<3:0> 197 CCP5CON -- -- DC5B<1:0> CCP5M<3:0> 197 CCP6CON -- -- DC6B<1:0> CCP6M<3:0> 197 CCP7CON -- -- DC7B<1:0> CCP7M<3:0> 197 CCP8CON -- -- DC8B<1:0> CCP8M<3:0> 197 CCP9CON -- -- DC9B<1:0> CCP9M<3:0> 197 CCP10CON -- -- DC10B<1:0> CCP10M<3:0> 197 118 CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) 184* CCPR2L Capture/Compare/PWM Register 2 Low Byte (LSB) 184* CCPR3L Capture/Compare/PWM Register 3 Low Byte (LSB) 184* CCPR4L Capture/Compare/PWM Register 4 Low Byte (LSB) 184* CCPR5L Capture/Compare/PWM Register 5 Low Byte (LSB) 184* CCPR6L Capture/Compare/PWM Register 6 Low Byte (LSB) 184* CCPR7L Capture/Compare/PWM Register 7 Low Byte (LSB) 184* CCPR8L Capture/Compare/PWM Register 8 Low Byte (LSB) 184* CCPR9L Capture/Compare/PWM Register 9 Low Byte (LSB) 184* CCPR10L Capture/Compare/PWM Register 10 Low Byte (LSB) 184* CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) 184* CCPR2H Capture/Compare/PWM Register 2 High Byte (MSB) 184* CCPR3H Capture/Compare/PWM Register 3 High Byte (MSB) 184* CCPR4H Capture/Compare/PWM Register 4 High Byte (MSB) 184* CCPR5H Capture/Compare/PWM Register 5 High Byte (MSB) 184* CCPR6H Capture/Compare/PWM Register 6 High Byte (MSB) 184* CCPR7H Capture/Compare/PWM Register 7 High Byte (MSB) 184* CCPR8H Capture/Compare/PWM Register 8 High Byte (MSB) 184* CCPR9H Capture/Compare/PWM Register 9 High Byte (MSB) 184* CCPR10H Capture/Compare/PWM Register 10 High Byte (MSB) INTCON 184* GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 80 PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 81 PIE2 OSFIE TMR5GIE TMR3GIE -- BCL1IE TMR10IE TMR8IE CCP2IE 82 PIE3 CCP6IE CCP5IE CCP4IE CCP3IE TMR6IE TMR5IE TMR4IE TMR3IE 83 PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 84 PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 85 PIR2 OSFIF TMR5GIF TMR3GIF -- BCL1IF TMR10IF TMR8IF CCP2IF 86 PIR3 CCP6IF CCP5IF CCP4IF CCP3IF TMR6IF TMR5IF TMR4IF TMR3IF 87 PIR4 CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF 88 T1CON TMR1CS<1:0> T1CKPS<1:0> SOSCEN T1SYNC -- TMR1ON 176 T3CON TMR3CS<1:0> T3CKPS<1:0> SOSCEN T3SYNC -- TMR3ON 176 T5CON TMR5CS<1:0> T5CKPS<1:0> SOSCEN T5SYNC -- TMR5ON 176 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 177 T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/DONE T3GVAL T3GSS<1:0> 177 Legend: -- = Unimplemented location, read as `0'. Shaded cells are not used by Compare mode. * Page provides register information. DS41458B-page 190 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 TABLE 20-5: Name T5GCON SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TMR5GE T5GPOL T5GTM T5GSPM T5GGO/DONE T5GVAL Bit 1 Bit 0 T5GSS<1:0> Register on Page 177 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 172* TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register 172* TMR6L Holding Register for the Least Significant Byte of the 16-bit TMR6 Register 172* TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 172* TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register 172* TMR6H Holding Register for the Most Significant Byte of the 16-bit TMR6 Register TRISA Legend: TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 172* TRISA2 TRISA1 TRISA0 120 -- = Unimplemented location, read as `0'. Shaded cells are not used by Compare mode. * Page provides register information. 2011 Microchip Technology Inc. Preliminary DS41458B-page 191 PIC16(L)F1526/27 20.3 FIGURE 20-3: PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete cycle or the total amount of on and off time combined. Period Pulse Width TMRx = 0 FIGURE 20-4: CCPRxH(2) (Slave) CCPx TMRx Comparator Note 1: The standard PWM mode generates a Pulse-Width modulation (PWM) signal on the CCPx pin with up to 10 bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: 2: Clearing the CCPxCON register will relinquish control of the CCPx pin. DS41458B-page 192 S (1) 2: Clear Timer, toggle CCPx pin and latch duty cycle The 8-bit timer TMRx register is concatenated with the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. In PWM mode, CCPRxH is a read-only register. TABLE 20-6: Note 1: The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. Q TRIS PRx Figure 20-4 shows a simplified block diagram of PWM operation. R Comparator STANDARD PWM OPERATION PRx registers TxCON registers CCPRxL registers CCPxCON registers CCPxCON<5:4> CCPRxL Figure 20-3 shows a typical waveform of the PWM signal. * * * * SIMPLIFIED PWM BLOCK DIAGRAM Duty Cycle Registers The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. The standard PWM function described in this section is available and identical for CCP modules. TMRx = PRx TMRx = CCPRxH:CCPxCON<5:4> PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. 20.3.1 CCP PWM OUTPUT SIGNAL CCPx PWM TIMER2/4/6/8/10 RESOURCES CCP TMR2 TMR4 TMR6 CCP1 CCP2 CCP3 CCP4 CCP5 CCP6 CCP7 CCP8 CCP9 CCP10 Preliminary TMR8 TMR10 2011 Microchip Technology Inc. PIC16(L)F1526/27 20.3.2 SETUP FOR PWM OPERATION 20.3.4 The following steps should be taken when configuring the CCP module for standard PWM operation: 1. 2. 3. 4. 5. 6. Disable the CCPx pin output driver by setting the associated TRIS bit. Load the PRx register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRxL register and the DCxBx bits of the CCPxCON register, with the PWM duty cycle value. Configure and start Timer2/4/6/8/10: * Select the Timer2/4/6/8/10 resource to be used for PWM generation by setting the CxTSEL<1:0> bits in the CCPTMRSx register. * Clear the TMRxIF interrupt flag bit of the PIRx register. See Note below. * Configure the TxCKPS bits of the TxCON register with the Timer prescale value. * Enable the Timer by setting the TMRxON bit of the TxCON register. Enable PWM output pin: * Wait until the Timer overflows and the TMRxIF bit of the PIRx register is set. See Note below. * Enable the CCPx pin output driver by clearing the associated TRIS bit. Note: 20.3.3 PWM PERIOD The PWM period is specified by the PRx register of Timer2/4/6/8/10. The PWM period can be calculated using the formula of Equation 20-1. EQUATION 20-1: PWM PERIOD PWM Period = PRx + 1 4 T OSC (TMRx Prescale Value) Note 1: TOSC = 1/FOSC When TMRx is equal to PRx, the following three events occur on the next increment cycle: * TMRx is cleared * The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) * The PWM duty cycle is latched from CCPRxL into CCPRxH. Note: The Timer postscaler (see Section 19.1 "Timer2/4/6/8/10 Operation" is not used in the determination of the PWM frequency. In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. TIMER2/4/6/8/10 TIMER RESOURCE The PWM standard mode makes use of one of the 8-bit Timer2/4/6/8/10 timer resources to specify the PWM period. Configuring the CxTSEL<1:0> bits in the CCPTMRSx register selects which Timer2/4/6/8/10 timer is used. See Table 20-6 for CCPx PWM Timer2/4/6/8/10 resources. 2011 Microchip Technology Inc. Preliminary DS41458B-page 193 PIC16(L)F1526/27 20.3.5 PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPRxL register and DCxB<1:0> bits of the CCPxCON register. The CCPRxL contains the eight MSbs and the DCxB<1:0> bits of the CCPxCON register contain the two LSbs. CCPRxL and DCxB<1:0> bits of the CCPxCON register can be written to at any time. The duty cycle value is not latched into CCPRxH until after the period completes (i.e., a match between PRx and TMRx registers occurs). While using the PWM, the CCPRxH register is read-only. Equation 20-2 is used to calculate the PWM pulse width. Equation 20-3 is used to calculate the PWM duty cycle ratio. EQUATION 20-2: T OSC (TMRx Prescale Value) 20.3.6 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. PWM RESOLUTION log 4 PRx + 1 Resolution = ------------------------------------------ bits log 2 DUTY CYCLE RATIO Note: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency Timer Prescale (1, 4, 16) PRx Value Maximum Resolution (bits) TABLE 20-8: When the 10-bit time base matches the CCPRxH and 2-bit latch, then the CCPx pin is cleared (see Figure 20-4). EQUATION 20-4: CCPRxL:CCPxCON<5:4> Duty Cycle Ratio = ----------------------------------------------------------------------4 PRx + 1 TABLE 20-7: The 8-bit timer TMRx register is concatenated with either the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2/4/6/8/10 prescaler is set to 1:1. The maximum PWM resolution is 10 bits when PRx is 255. The resolution is a function of the PRx register value as shown by Equation 20-4. PULSE WIDTH Pulse Width = CCPRxL:CCPxCON<5:4> EQUATION 20-3: The CCPRxH register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency Timer Prescale (1, 4, 16) PRx Value Maximum Resolution (bits) DS41458B-page 194 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 16 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 20.3.7 OPERATION IN SLEEP MODE 20.3.9 In Sleep mode, the TMRx register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMRx will continue from its previous state. 20.3.8 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 5.0 "Oscillator Module (With Fail-Safe Clock Monitor)" for additional details. TABLE 20-9: EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. 20.3.10 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 12.1 "Alternate Pin Function" for more information. SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page APFCON -- -- -- -- -- -- T3CKISEL CCP2SEL 118 CCP1CON -- -- DC1B<1:0> CCP1M<3:0> 197 CCP2CON -- -- DC2B<1:0> CCP2M<3:0> 197 CCP3CON -- -- DC3B<1:0> CCP3M<3:0> 197 CCP4CON -- -- DC4B<1:0> CCP4M<3:0> 197 CCP5CON -- -- DC5B<1:0> CCP5M<3:0> 197 CCP6CON -- -- DC6B<1:0> CCP6M<3:0> 197 CCP7CON -- -- DC7B<1:0> CCP7M<3:0> 197 CCP8CON -- -- DC8B<1:0> CCP8M<3:0> 197 CCP9CON -- -- DC9B<1:0> CCP9M<3:0> 197 CCP10CON -- -- DC10B<1:0> CCP10M<3:0> 197 Name GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 80 PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 81 PIE2 OSFIE TMR5GIE TMR3GIE -- BCL1IE TMR10IE TMR8IE CCP2IE 82 PIE3 CCP6IE CCP5IE CCP4IE CCP3IE TMR6IE TMR5IE TMR4IE TMR3IE 83 PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 84 PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 85 PIR2 OSFIF TMR5GIF TMR3GIF -- BCL1IF TMR10IF TMR8IF CCP2IF 86 PIR3 CCP6IF CCP5IF CCP4IF CCP3IF TMR6IF TMR5IF TMR4IF TMR3IF 87 PIR4 CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF 88 INTCON PR2 Timer2 Period Register 179* PR4 Timer4 Period Register 179* PR6 Timer6 Period Register 179* PR8 Timer8 Period Register 179* PR10 Timer10 Period Register 179* T2CON -- T2OUTPS<3:0> TMR2ON T2CKPS<:0>1 176 T4CON -- T4OUTPS<3:0> TMR4ON T4CKPS<:0>1 176 T6CON -- T6OUTPS<3:0> TMR6ON T6CKPS<:0>1 176 Legend: -- = Unimplemented location, read as `0'. Shaded cells are not used by the PWM. * Page provides register information. 2011 Microchip Technology Inc. Preliminary DS41458B-page 195 PIC16(L)F1526/27 TABLE 20-10: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T8CON -- T8OUTPS<3:0> TMR8ON T8CKPS<:0>1 T10CON -- T10OUTPS<3:0> TMR10ON T10CKPS<:0>1 Register on Page 176 176 TMR2 Timer2 Module Register 179* TMR4 Timer4 Module Register 179* TMR6 Timer6 Module Register 179* TMR8 Timer8 Module Register 179* TMR10 Timer10 Module Register TRISA TRISA7 TRISA6 179* TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 120 Legend: -- = Unimplemented location, read as `0'. Shaded cells are not used by the PWM. * Page provides register information. DS41458B-page 196 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 20.4 CCP Control Registers REGISTER 20-1: CCPxCON: CCPx CONTROL REGISTER U-0 U-0 -- -- R/W-0/0 R/W-0/0 R/W-0/0 DCxB<1:0> R/W-0/0 R/W-0/0 R/W-0/0 CCPxM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset `1' = Bit is set `0' = Bit is cleared bit 7-6 bit 5-4 Unimplemented: Read as `0' DCxB<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM<3:0>: CCPx Mode Select bits 0000 = 0001 = 0010 = 0011 = Capture/Compare/PWM off (resets CCPx module) Reserved Compare mode: toggle output on match Reserved 0100 = 0101 = 0110 = 0111 = Capture mode: every falling edge Capture mode: every rising edge Capture mode: every 4th rising edge Capture mode: every 16th rising edge 1000 = 1001 = 1010 = 1011 = Compare mode: set output on compare match (set CCPxIF) Compare mode: clear output on compare match (set CCPxIF) Compare mode: generate software interrupt only Compare mode: Special Event Trigger (sets CCP10IF bit (CCP10), starts A/D conversion if A/D module is enabled)(1) 11xx = PWM mode 2011 Microchip Technology Inc. Preliminary DS41458B-page 197 PIC16(L)F1526/27 REGISTER 20-2: R/W-0/0 CCPTMRS0: CCP TIMER SELECTION CONTROL REGISTER 0 R/W-0/0 C4TSEL<1:0> R/W-0/0 R/W-0/0 R/W-0/0 C3TSEL<1:0> R/W-0/0 R/W-0/0 C2TSEL<1:0> R/W-0/0 C1TSEL<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 C4TSEL<1:0>: CCP4 Timer Selection bits When in Capture/Compare mode: x0 = CCP4 is based off Timer1 in Capture/Compare mode x1 = CCP4 is based off Timer3 in Capture/Compare mode When in PWM mode: 00 = CCP4 is based off Timer2 in PWM mode 01 = CCP4 is based off Timer4 in PWM mode 10 = CCP4 is based off Timer6 in PWM mode 11 = Reserved bit 5-4 C3TSEL<1:0>: CCP3 Timer Selection bits When in Capture/Compare mode: x0 = CCP3 is based off Timer1 in Capture/Compare mode x1 = CCP3 is based off Timer3 in Capture/Compare mode When in PWM mode: 00 = CCP3 is based off Timer2 in PWM mode 01 = CCP3 is based off Timer4 in PWM mode 10 = CCP3 is based off Timer6 in PWM mode 11 = Reserved bit 3-2 C2TSEL<1:0>: CCP2 Timer Selection bits When in Capture/Compare mode: x0 = CCP2 is based off Timer1 in Capture/Compare mode x1 = CCP2 is based off Timer3 in Capture/Compare mode When in PWM mode: 00 = CCP2 is based off Timer2 in PWM mode 01 = CCP2 is based off Timer4 in PWM mode 10 = CCP2 is based off Timer6 in PWM mode 11 = Reserved bit 1-0 C1TSEL<1:0>: CCP1 Timer Selection bits When in Capture/Compare mode: x0 = CCP1 is based off Timer1 in Capture/Compare mode x1 = CCP1 is based off Timer3 in Capture/Compare mode When in PWM mode: 00 = CCP1 is based off Timer2 in PWM mode 01 = CCP1 is based off Timer4 in PWM mode 10 = CCP1 is based off Timer6 in PWM mode 11 = Reserved DS41458B-page 198 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 REGISTER 20-3: R/W-0/0 CCPTMRS1: CCP TIMER SELECTION CONTROL REGISTER 1 R/W-0/0 C8TSEL<1:0> R/W-0/0 R/W-0/0 R/W-0/0 C7TSEL<1:0> R/W-0/0 R/W-0/0 C6TSEL<1:0> bit 7 R/W-0/0 C5TSEL<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 C8TSEL<1:0>: CCP8 Timer Selection bits When in Capture/Compare mode: x0 = CCP8 is based off Timer1 in Capture/Compare mode x1 = CCP8 is based off Timer5 in Capture/Compare mode When in PWM mode: 00 = CCP8 is based off Timer2 in PWM mode 01 = CCP8 is based off Timer8 in PWM mode 10 = CCP8 is based off Timer10 in PWM mode 11 = Reserved bit 5-4 C7TSEL<1:0>: CCP7 Timer Selection bits When in Capture/Compare mode: x0 = CCP7 is based off Timer1 in Capture/Compare mode x1 = CCP7 is based off Timer5 in Capture/Compare mode When in PWM mode: 00 = CCP7 is based off Timer2 in PWM mode 01 = CCP7 is based off Timer6 in PWM mode 10 = CCP7 is based off Timer8 in PWM mode 11 = Reserved bit 3-2 C6TSEL<1:0>: CCP6 Timer Selection bits When in Capture/Compare mode: x0 = CCP6 is based off Timer1 in Capture/Compare mode x1 = CCP6 is based off Timer5 in Capture/Compare mode When in PWM mode: 00 = CCP6 is based off Timer2 in PWM mode 01 = CCP6 is based off Timer6 in PWM mode 10 = CCP6 is based off Timer8 in PWM mode 11 = Reserved bit 1-0 C5TSEL<1:0>: CCP5 Timer Selection bits When in Capture/Compare mode: x0 = CCP5 is based off Timer1 in Capture/Compare mode x1 = CCP5 is based off Timer5 in Capture/Compare mode When in PWM mode: 00 = CCP5 is based off Timer2 in PWM mode 01 = CCP5 is based off Timer6 in PWM mode 10 = CCP5 is based off Timer8 in PWM mode 11 = Reserved 2011 Microchip Technology Inc. Preliminary DS41458B-page 199 PIC16(L)F1526/27 REGISTER 20-4: CCPTMRS2: CCP TIMER SELECTION CONTROL REGISTER 2 U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 C10TSEL<1:0> R/W-0/0 C9TSEL<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-2 C10TSEL<1:0>: CCP10 Timer Selection bits When in Capture/Compare mode: x0 = CCP10 is based off Timer1 in Capture/Compare mode x1 = CCP10 is based off Timer5 in Capture/Compare mode When in PWM mode: 00 = CCP10 is based off Timer2 in PWM mode 01 = CCP10 is based off Timer8 in PWM mode 10 = CCP10 is based off Timer10 in PWM mode 11 = Reserved bit 1-0 C9TSEL<1:0>: CCP9 Timer Selection bits When in Capture/Compare mode: x0 = CCP9 is based off Timer1 in Capture/Compare mode x1 = CCP9 is based off Timer5 in Capture/Compare mode When in PWM mode: 00 = CCP9 is based off Timer2 in PWM mode 01 = CCP9 is based off Timer8 in PWM mode 10 = CCP9 is based off Timer10 in PWM mode 11 = Reserved DS41458B-page 200 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 21.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP1 AND MSSP2) MODULE 21.1 Master SSPx (MSSPx) Module Overview The Master Synchronous Serial Port (MSSPx) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSPx module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2CTM) The SPI interface supports the following modes and features: * * * * * Master mode Slave mode Clock Parity Slave Select Synchronization (Slave mode only) Daisy-chain connection of slave devices Figure 21-1 is a block diagram of the SPI interface module. FIGURE 21-1: MSSPX BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSPxBUF Reg SDIx SSPxSR Reg SDOx bit 0 SSx SSx Control Enable Shift Clock 2 (CKP, CKE) Clock Select Edge Select SSPxM<3:0> 4 SCKx Edge Select TRIS bit 2011 Microchip Technology Inc. Preliminary ( TMR22Output ) Prescaler TOSC 4, 16, 64 Baud Rate Generator (SSPxADD) DS41458B-page 201 PIC16(L)F1526/27 The I2C interface supports the following modes and features: Master mode Slave mode Byte NACKing (Slave mode) Limited Multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDAx hold times Note 1: In devices with more than one MSSP module, it is very important to pay close attention to SSPxCONx register names. SSP1CON1 and SSP1CON2 registers control different operational aspects of the same module, while SSP1CON1 and SSP2CON1 control the same features for two different modules. 2: Throughout this section, generic references to an MSSP module in any of its operating modes may be interpreted as being equally applicable to MSSP1 or MSSP2. Register names, module I/O signals, and bit names may use the generic designator `x' to indicate the use of a numeral to distinguish a particular module when required. Figure 21-2 is a block diagram of the I2C Interface module in Master mode. Figure 21-3 is a diagram of the I2C interface module in Slave mode. MSSPX BLOCK DIAGRAM (I2CTM MASTER MODE) Internal data bus Read [SSPxM 3:0] Write SSPxBUF SDAx Baud rate generator (SSPxADD) Shift Clock SDAx in Receive Enable (RCEN) SCLx SCLx in Bus Collision DS41458B-page 202 LSb Start bit, Stop bit, Acknowledge Generate (SSPxCON2) Start bit detect, Stop bit detect Write collision detect Clock arbitration State counter for end of XMIT/RCV Address Match detect Preliminary Clock Cntl SSPxSR MSb (Hold off clock source) FIGURE 21-2: Clock arbitrate/BCOL detect * * * * * * * * * * * * * The PIC16F1527 has two MSSP modules, MSSP1 and MSSP2, each module operating independently from the other. Set/Reset: S, P, SSPxSTAT, WCOL, SSPxOV Reset SEN, PEN (SSPxCON2) Set SSPxIF, BCLxIF 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 21-3: MSSPX BLOCK DIAGRAM (I2CTM SLAVE MODE) Internal Data Bus Read Write SSPxBUF Reg SCLx Shift Clock SSPxSR Reg SDAx MSb LSb SSPxMSK Reg Match Detect Addr Match SSPxADD Reg Start and Stop bit Detect 2011 Microchip Technology Inc. Preliminary Set, Reset S, P bits (SSPxSTAT Reg) DS41458B-page 203 PIC16(L)F1526/27 21.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a Chip Select known as Slave Select. The SPI bus specifies four signal connections: * * * * During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the master device is sending out the MSb from its shift register (on its SDOx pin) and the slave device is reading this bit and saving it as the LSb of its shift register, that the slave device is also sending out the MSb from its shift register (on its SDOx pin) and the master device is reading this bit and saving it as the LSb of its shift register. After 8 bits have been shifted out, the master and slave have exchanged register values. Serial Clock (SCKx) Serial Data Out (SDOx) Serial Data In (SDIx) Slave Select (SSx) If there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. Figure 21-1 shows the block diagram of the MSSPx module when operating in SPI mode. The SPI bus operates with a single master device and one or more slave devices. When multiple slave devices are used, an independent Slave Select connection is required from the master device to each slave device. Figure 21-4 shows a typical connection between a master device and multiple slave devices. The master selects only one slave at a time. Most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. Transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. With either the master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three scenarios for data transmission: * Master sends useful data and slave sends dummy data. * Master sends useful data and slave sends useful data. * Master sends dummy data and slave sends useful data. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. Every slave device connected to the bus that has not been selected through its slave select line must disregard the clock and transmission signals and must not transmit out any data of its own. Figure 21-5 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDOx output pin which is connected to, and received by, the slave's SDIx input pin. The slave device transmits information out on its SDOx output pin, which is connected to, and received by, the master's SDIx input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register. DS41458B-page 204 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 21-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCKx SCKx SDOx SDIx SDIx SDOx General I/O General I/O SSx General I/O SCKx SDIx SDOx SPI Slave #1 SPI Slave #2 SSx SCKx SDIx SDOx SPI Slave #3 SSx 21.2.1 SPI MODE REGISTERS The MSSPx module has five registers for SPI mode operation. These are: * * * * * * MSSPx STATUS register (SSPxSTAT) MSSPx Control Register 1 (SSPxCON1) MSSPx Control Register 3 (SSPxCON3) MSSPx Data Buffer register (SSPxBUF) MSSPx Address register (SSPxADD) MSSPx Shift register (SSPxSR) (Not directly accessible) SSPxCON1 and SSPxSTAT are the control and STATUS registers in SPI mode operation. The SSPxCON1 register is readable and writable. The lower 6 bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. In one SPI Master mode, SSPxADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in Section 21.7 "Baud Rate Generator". SSPxSR is the shift register used for shifting data in and out. SSPxBUF provides indirect access to the SSPxSR register. SSPxBUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSPxSR and SSPxBUF together create a buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR. 2011 Microchip Technology Inc. Preliminary DS41458B-page 205 PIC16(L)F1526/27 21.2.2 SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). These control bits allow the following to be specified: * * * * Master mode (SCKx is the clock output) Slave mode (SCKx is the clock input) Clock Polarity (Idle state of SCKx) Data Input Sample Phase (middle or end of data output time) * Clock Edge (output data on rising/falling edge of SCKx) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) To enable the serial port, SSPx Enable bit, SSPxEN of the SSPxCON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPxEN bit, re-initialize the SSPxCONx registers and then set the SSPxEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: * SDIx must have corresponding TRIS bit set * SDOx must have corresponding TRIS bit cleared * SCKx (Master mode) must have corresponding TRIS bit cleared * SCKx (Slave mode) must have corresponding TRIS bit set * SSx must have corresponding TRIS bit set FIGURE 21-5: Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. The MSSPx consists of a transmit/receive shift register (SSPxSR) and a buffer register (SSPxBUF). The SSPxSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPxSR until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPxBUF register. Then, the Buffer Full Detect bit, BF of the SSPxSTAT register, and the interrupt flag bit, SSPxIF, are set. This double-buffering of the received data (SSPxBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPxBUF register during transmission/reception of data will be ignored and the write collision detect bit WCOL of the SSPxCON1 register, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSPxBUF register to complete successfully. When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte of data to transfer is written to the SSPxBUF. The Buffer Full bit, BF of the SSPxSTAT register, indicates when SSPxBUF has been loaded with the received data (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSPx interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. SPI MASTER/SLAVE CONNECTION SPI Master SSPxM<3:0> = 00xx = 1010 SDOx SPI Slave SSPxM<3:0> = 010x SDIx Serial Input Buffer (BUF) LSb SCKx General I/O Processor 1 DS41458B-page 206 SDOx SDIx Shift Register (SSPxSR) MSb Serial Input Buffer (SSPxBUF) Serial Clock Slave Select (optional) Preliminary Shift Register (SSPxSR) MSb LSb SCKx SSx Processor 2 2011 Microchip Technology Inc. PIC16(L)F1526/27 21.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx line. The master determines when the slave (Processor 2, Figure 21-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input). The SSPxSR register will continue to shift in the signal present on the SDIx pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as if a normal received byte (interrupts and Status bits appropriately set). The clock polarity is selected by appropriately programming the CKP bit of the SSPxCON1 register and the CKE bit of the SSPxSTAT register. This then, would give waveforms for SPI communication as shown in Figure 21-6, Figure 21-8 and Figure 21-9, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: * * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 Fosc/(4 * (SSPxADD + 1)) Figure 21-6 shows the waveforms for Master mode. When the CKE bit is set, the SDOx data is valid before there is a clock edge on SCKx. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown. FIGURE 21-6: SPI MODE WAVEFORM (MASTER MODE) Write to SSPxBUF SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) 4 Clock Modes SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) SDOx (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDOx (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDIx (SMP = 1) bit 0 bit 7 Input Sample (SMP = 1) SSPxIF SSPxSR to SSPxBUF 2011 Microchip Technology Inc. Preliminary DS41458B-page 207 PIC16(L)F1526/27 21.2.4 21.2.5 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCKx pin. The Idle state is determined by the CKP bit of the SSPxCON1 register. While in Slave mode, the external clock is supplied by the external clock source on the SCKx pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. The shift register is clocked from the SCKx pin input and when a byte is received, the device will generate an interrupt. If enabled, the device will wake-up from Sleep. 21.2.4.1 Daisy-Chain Configuration The SPI bus can sometimes be connected in a daisy-chain configuration. The first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on. The final slave output is connected to the master input. Each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole chain acts as one large communication shift register. The daisy-chain feature only requires a single Slave Select line from the master device. Figure 21-7 shows the block diagram of a typical daisy-chain connection when operating in SPI mode. In a daisy-chain configuration, only the most recent byte on the bus is required by the slave. Setting the BOEN bit of the SSPxCON3 register will enable writes to the SSPxBUF register, even if the previous byte has not been read. This allows the software to ignore data that may not apply to it. SLAVE SELECT SYNCHRONIZATION The Slave Select can also be used to synchronize communication. The Slave Select line is held high until the master device is ready to communicate. When the Slave Select line is pulled low, the slave knows that a new transmission is starting. If the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the Slave Select line returns to a high state. The slave is then ready to receive a new transmission when the Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will eventually become out of sync with the master. If the slave misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select line allows the slave and master to align themselves at the beginning of each transmission. The SSx pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SSx pin control enabled (SSPxCON1<3:0> = 0100). When the SSx pin is low, transmission and reception are enabled and the SDOx pin is driven. When the SSx pin goes high, the SDOx pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SSx pin control enabled (SSPxCON1<3:0> = 0100), the SPI module will reset if the SSx pin is set to VDD. 2: When the SPI is used in Slave mode with CKE set; the user must enable SSx pin control. 3: While operated in SPI Slave mode the SMP bit of the SSPxSTAT register must remain clear. When the SPI module resets, the bit counter is forced to `0'. This can be done by either forcing the SSx pin to a high level or clearing the SSPxEN bit. DS41458B-page 208 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 21-7: SPI DAISY-CHAIN CONNECTION SPI Master SCK SCK SDOx SDIx SDIx SDOx General I/O SPI Slave #1 SSx SCK SDIx SDOx SPI Slave #2 SSx SCK SDIx SDOx SPI Slave #3 SSx FIGURE 21-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SSx SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPxSR and bit count are reset SSPxBUF to SSPxSR SDOx bit 7 bit 6 bit 7 SDIx bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF 2011 Microchip Technology Inc. Preliminary DS41458B-page 209 PIC16(L)F1526/27 FIGURE 21-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active FIGURE 21-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active DS41458B-page 210 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 21.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSPx clock is much faster than the system clock. In Slave mode, when MSSPx interrupts are enabled, after the master completes sending data, an MSSPx interrupt will wake the controller from Sleep. If an exit from Sleep mode is not desired, MSSPx interrupts should be disabled. TABLE 21-1: Name ANSELF In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the MSSPx interrupt flag bit will be set and if enabled, will wake the device. SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSF7 ANSF6 ANSF5 ANSF4 ANSF3 ANSF2 ANSF1 ANSF0 136 80 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 81 PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 84 PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 85 PIR4 CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF 88 INTCON SSP1BUF MSSPx Receive Buffer/Transmit Register SSP2BUF MSSPx Receive Buffer/Transmit Register 205* 205* SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> SSP2CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 253 SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 253 SSP1STAT SMP CKE D/A P S R/W UA BF 249 SSP2STAT 251 251 SMP CKE D/A P S R/W UA BF 249 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 126 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 129 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 135 Legend: * -- = Unimplemented location, read as `0'. Shaded cells are not used by the MSSPx in SPI mode. Page provides register information. 2011 Microchip Technology Inc. Preliminary DS41458B-page 211 PIC16(L)F1526/27 21.3 I2C MODE OVERVIEW FIGURE 21-11: The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A slave device is controlled through addressing. VDD SCLx The I2C bus specifies two signal connections: * Serial Clock (SCLx) * Serial Data (SDAx) Figure 21-11 shows a typical connection between two processors configured as master and slave devices. The I2C bus can operate with one or more master devices and one or more slave devices. There are four potential modes of operation for a given device: * Master Transmit mode (master is transmitting data to a slave) * Master Receive mode (master is receiving data from a slave) * Slave Transmit mode (slave is transmitting data to a master) * Slave Receive mode (slave is receiving data from the master) SDAx The Acknowledge bit (ACK) is an active-low signal, which holds the SDAx line low to indicate to the transmitter that the slave device has received the transmitted data and is ready to receive more. The transition of a data bit is always performed while the SCLx line is held low. Transitions that occur while the SCLx line is held high are used to indicate Start and Stop bits. If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the master device is in Master Transmit mode and the slave is in Slave Receive mode. If the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ACK bit. In this example, the master device is in Master Receive mode and the slave is Slave Transmit mode. To begin communication, a master device starts out in Master Transmit mode. The master device sends out a Start bit followed by the address byte of the slave it intends to communicate with. This is followed by a single Read/Write bit, which determines whether the master intends to transmit to or receive data from the slave device. If the requested slave exists on the bus, it will respond with an Acknowledge bit, otherwise known as an ACK. The master then continues in either Transmit mode or Receive mode and the slave continues in the complement, either in Receive mode or Transmit mode, respectively. A Start bit is indicated by a high-to-low transition of the SDAx line while the SCLx line is held high. Address and data bytes are sent out, Most Significant bit (MSb) first. The Read/Write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. DS41458B-page 212 Slave SDAx Figure 21-11 shows the block diagram of the MSSPx module when operating in I2C mode. SCLx VDD Master Both the SCLx and SDAx connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. I2C MASTER/ SLAVE CONNECTION On the last byte of data communicated, the master device may end the transmission by sending a Stop bit. If the master device is in Receive mode, it sends the Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-high transition of the SDAx line while the SCLx line is held high. In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If so, the master device may send another Start bit in place of the Stop bit or last ACK bit when it is in Receive mode. The I2C bus specifies three message protocols; * Single message where a master writes data to a slave. * Single message where a master reads data from a slave. * Combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves. Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCLx line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDAx line, it is called arbitration. Arbitration ensures that there is only one master device communicating at any single time. 21.3.1 CLOCK STRETCHING When a slave device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. An addressed slave device may hold the SCLx clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. The master that is communicating with the slave will attempt to raise the SCLx line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the SCLx connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 21.3.2 ARBITRATION Each master device must monitor the bus for Start and Stop bits. If the device detects that the bus is busy, it cannot begin a new message until the bus returns to an Idle state. However, two master devices may try to initiate a transmission on or about the same time. When this occurs, the process of arbitration begins. Each transmitter checks the level of the SDAx data line and compares it to the level that it expects to find. The first transmitter to observe that the two levels do not match, loses arbitration, and must stop transmitting on the SDAx line. For example, if one transmitter holds the SDAx line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the SDAx line will be low. The first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDAx line. If this transmitter is also a master device, it also must stop driving the SCLx line. It then can monitor the lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDAx line continues with its original transmission. It can do so without any complications, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support. 2011 Microchip Technology Inc. Preliminary DS41458B-page 213 PIC16(L)F1526/27 21.4 I2C MODE OPERATION TABLE 21-2: All MSSPx I2C communication is byte oriented and shifted out MSb first. Six SFR registers and 2 interrupt flags interface the module with the PIC(R) microcontroller and user software. Two pins, SDAx and SCLx, are exercised by the module to communicate with other external I2C devices. 21.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back. After the 8th falling edge of the SCLx line, the device outputting data on the SDAx changes that pin to an input and reads in an acknowledge value on the next clock pulse. The clock signal, SCLx, is provided by the master. Data is valid to change while the SCLx signal is low, and sampled on the rising edge of the clock. Changes on the SDAx line while the SCLx line is high define special conditions on the bus, explained below. 21.4.2 DEFINITION OF I2C TERMINOLOGY There is language and terminology in the description of I2C communication that have definitions specific to I2C. That word usage is defined below and may be used in the rest of this document without explanation. This table was adapted from the Philips I2C specification. 21.4.3 SDAX AND SCLX PINS Selection of any I2C mode with the SSPxEN bit set, forces the SCLx and SDAx pins to be open-drain. These pins should be set by the user to inputs by setting the appropriate TRIS bits. Note: Data is tied to output zero when an I2C mode is enabled. 21.4.4 SDAX HOLD TIME The hold time of the SDAx pin is selected by the SDAHT bit of the SSPxCON3 register. Hold time is the time SDAx is held valid after the falling edge of SCLx. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. DS41458B-page 214 TERM I2C BUS TERMS Description Transmitter The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus. Master The device that initiates a transfer, generates clock signals and terminates a transfer. Slave The device addressed by the master. Multi-master A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration ensures that the message is not corrupted. Synchronization Procedure to synchronize the clocks of two or more devices on the bus. Idle No master is controlling the bus, and both SDAx and SCLx lines are high. Active Any time one or more master devices are controlling the bus. Addressed Slave device that has received a Slave matching address and is actively being clocked by a master. Matching Address byte that is clocked into a Address slave that matches the value stored in SSPxADD. Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Slave. This data is the next and all following bytes until a Restart or Stop. Clock Stretching When a device on the bus hold SCLx low to stall communication. Bus Collision Any time the SDAx line is sampled low by the module while it is outputting and expected high state. Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 21.4.5 21.4.7 START CONDITION The I2C specification defines a Start condition as a transition of SDAx from a high to a low state while SCLx line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 21-10 shows wave forms for Start and Stop conditions. A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave. A bus collision can occur on a Start condition if the module samples the SDAx line low before asserting it low. This does not conform to the I2C Specification that states no bus collision can occur on a Start. 21.4.6 RESTART CONDITION In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can issue a Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to clock out data. STOP CONDITION A Stop condition is a transition of the SDAx line from low-to-high state while the SCLx line is high. After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained. Until a Stop condition, a high address with R/W clear, or high address match fails. Note: At least one SCLx low time must appear before a Stop is valid, therefore, if the SDAx line goes low then high again while the SCLx line stays high, only the Start condition is detected. 21.4.8 START/STOP CONDITION INTERRUPT MASKING The SCIE and PCIE bits of the SSPxCON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. FIGURE 21-12: I2C START AND STOP CONDITIONS SDAx SCLx S Start P Change of Change of Data Allowed Data Allowed Condition FIGURE 21-13: Stop Condition I2C RESTART CONDITION Sr Change of Change of Data Allowed Restart Data Allowed Condition 2011 Microchip Technology Inc. Preliminary DS41458B-page 215 PIC16(L)F1526/27 21.4.9 ACKNOWLEDGE SEQUENCE 21.5 The 9th SCLx pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDAx line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDAx line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more. The result of an ACK is placed in the ACKSTAT bit of the SSPxCON2 register. Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to the transmitter. The ACKDT bit of the SSPxCON2 register is set/cleared to determine the response. Slave hardware will generate an ACK response if the AHEN and DHEN bits of the SSPxCON3 register are clear. There are certain conditions where an ACK will not be sent by the slave. If the BF bit of the SSPxSTAT register or the SSPxOV bit of the SSPxCON1 register are set when a byte is received. When the module is addressed, after the 8th falling edge of SCLx on the bus, the ACKTIM bit of the SSPxCON3 register is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is enabled. I2C SLAVE MODE OPERATION The MSSPx Slave mode operates in one of four modes selected in the SSPxM bits of SSPxCON1 register. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. Modes with Start and Stop bit interrupts operated the same as the other modes with SSPxIF additionally getting set upon detection of a Start, Restart, or Stop condition. 21.5.1 SLAVE MODE ADDRESSES The SSPxADD register (Register 21-6) contains the Slave mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches, the value is loaded into the SSPxBUF register and an interrupt is generated. If the value does not match, the module goes Idle and no indication is given to the software that anything happened. The SSPx Mask register (Register 21-5) affects the address matching process. See Section 21.5.9 "SSPx Mask Register" for more information. 21.5.1.1 I2C Slave 7-bit Addressing Mode In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match. 21.5.1.2 I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of `1 1 1 1 0 A9 A8 0'. A9 and A8 are the two MSb of the 10-bit address and stored in bits 2 and 1 of the SSPxADD register. After the acknowledge of the high byte the UA bit is set and SCLx is held low until the user updates SSPxADD with the low address. The low address byte is clocked in and all 8 bits are compared to the low address value in SSPxADD. Even if there is not an address match; SSPxIF and UA are set, and SCLx is held low until SSPxADD is updated to receive a high byte again. When SSPxADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match. DS41458B-page 216 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 21.5.2 21.5.2.2 SLAVE RECEPTION When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSPxSTAT register is set, or bit SSPxOV of the SSPxCON1 register is set. The BOEN bit of the SSPxCON3 register modifies this operation. For more information see Register 21-4. An MSSPx interrupt is generated for each transferred data byte. Flag bit, SSPxIF, must be cleared by software. When the SEN bit of the SSPxCON2 register is set, SCLx will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit of the SSPxCON1 register, except sometimes in 10-bit mode. See Section 21.2.3 "SPI Master Mode" for more detail. 21.5.2.1 7-bit Addressing Reception This section describes a standard sequence of events for the MSSPx module configured as an I2C slave in 7-bit Addressing mode. All decisions made by hardware or software and their effect on reception. Figure 21-13 and Figure 21-14 is used as a visual reference for this description. This is a step by step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Start bit detected. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is received. The slave pulls SDAx low sending an ACK to the master, and sets SSPxIF bit. Software clears the SSPxIF bit. Software reads received address from SSPxBUF clearing the BF flag. If SEN = 1; Slave software sets CKP bit to release the SCLx line. The master clocks out a data byte. Slave drives SDAx low sending an ACK to the master, and sets SSPxIF bit. Software clears SSPxIF. Software reads the received byte from SSPxBUF clearing BF. Steps 8-12 are repeated for all received bytes from the master. Master sends Stop condition, setting P bit of SSPxSTAT, and the bus goes Idle. 2011 Microchip Technology Inc. 7-bit Reception with AHEN and DHEN Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the 8th falling edge of SCLx. These additional interrupts allow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds support for PMBusTM that was not present on previous versions of this module. This list describes the steps that need to be taken by slave software to use these options for I2C communication. Figure 21-15 displays a module using both address and data holding. Figure 21-16 includes the operation with the SEN bit of the SSPxCON2 register set. 1. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 2. Matching address with R/W bit clear is clocked in. SSPxIF is set and CKP cleared after the 8th falling edge of SCLx. 3. Slave clears the SSPxIF. 4. Slave can look at the ACKTIM bit of the SSPxCON3 register to determine if the SSPxIF was after or before the ACK. 5. Slave reads the address value from SSPxBUF, clearing the BF flag. 6. Slave sets ACK value clocked out to the master by setting ACKDT. 7. Slave releases the clock by setting CKP. 8. SSPxIF is set after an ACK, not after a NACK. 9. If SEN = 1 the slave hardware will stretch the clock after the ACK. 10. Slave clears SSPxIF. Note: SSPxIF is still set after the 9th falling edge of SCLx even if there is no clock stretching and BF has been cleared. Only if NACK is sent to master is SSPxIF not set 11. SSPxIF set and CKP cleared after 8th falling edge of SCLx for a received data byte. 12. Slave looks at ACKTIM bit of SSPxCON3 to determine the source of the interrupt. 13. Slave reads the received data from SSPxBUF clearing BF. 14. Steps 7-14 are the same for each received data byte. 15. Communication is ended by either the slave sending an ACK = 1, or the master sending a Stop condition. If a Stop is sent and Interrupt on Stop Detect is disabled, the slave will only know by polling the P bit of the SSTSTAT register. Preliminary DS41458B-page 217 DS41458B-page 218 Preliminary SSPxOV BF SSPxIF S 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 D4 5 D3 6 D2 7 D1 SSPxBUF is read Cleared by software 3 D5 Receiving Data 8 9 2 D6 First byte of data is available in SSPxBUF 1 D0 ACK D7 4 D4 5 D3 6 D2 7 D1 8 D0 SSPxOV set because SSPxBUF is still full. ACK is not sent. Cleared by software 3 D5 Receiving Data From Slave to Master 9 P SSPxIF set on 9th falling edge of SCLx ACK = 1 FIGURE 21-14: SCLx SDAx Receiving Address Bus Master sends Stop condition PIC16(L)F1526/27 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0) 2011 Microchip Technology Inc. 2011 Microchip Technology Inc. Preliminary CKP SSPxOV BF SSPxIF 1 SCLx S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to `1' in software, releasing SCLx SSPxBUF is read Cleared by software Clock is held low until CKP is set to `1' 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSPxBUF 6 D2 7 D1 SSPxOV set because SSPxBUF is still full. ACK is not sent. Cleared by software 2 D6 CKP is written to `1' in software, releasing SCLx 1 D7 Receive Data 8 D0 9 ACK SCLx is not held low because ACK= 1 SSPxIF set on 9th falling edge of SCLx P FIGURE 21-15: SDAx Receive Address Bus Master sends Stop condition PIC16(L)F1526/27 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) DS41458B-page 219 DS41458B-page 220 Preliminary P S ACKTIM CKP ACKDT BF SSPxIF S Receiving Address 1 3 5 6 7 8 ACK the received byte Slave software clears ACKDT to Address is read from SSBUF If AHEN = 1: SSPxIF is set 4 ACKTIM set by hardware on 8th falling edge of SCLx When AHEN=1: CKP is cleared by hardware and SCLx is stretched 2 A7 A6 A5 A4 A3 A2 A1 Receiving Data 9 2 3 4 5 6 7 ACKTIM cleared by hardware in 9th rising edge of SCLx When DHEN=1: CKP is cleared by hardware on 8th falling edge of SCLx SSPxIF is set on 9th falling edge of SCLx, after ACK 1 8 ACK D7 D6 D5 D4 D3 D2 D1 D0 Received Data 1 2 4 5 6 ACKTIM set by hardware on 8th falling edge of SCLx CKP set by software, SCLx is released 8 Slave software sets ACKDT to not ACK 7 Cleared by software 3 D7 D6 D5 D4 D3 D2 D1 D0 Data is read from SSPxBUF 9 ACK 9 P No interrupt after not ACK from Slave ACK=1 Master sends Stop condition FIGURE 21-16: SCLx SDAx Master Releases SDAx to slave for ACK sequence PIC16(L)F1526/27 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1) 2011 Microchip Technology Inc. 2011 Microchip Technology Inc. Preliminary P S ACKTIM CKP ACKDT BF SSPxIF S Receiving Address 4 5 6 7 8 When AHEN = 1; on the 8th falling edge of SCLx of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte Received address is loaded into SSPxBUF 2 3 ACKTIM is set by hardware on 8th falling edge of SCLx 1 A7 A6 A5 A4 A3 A2 A1 9 ACK Receive Data 2 3 4 5 6 7 8 ACKTIM is cleared by hardware on 9th rising edge of SCLx When DHEN = 1; on the 8th falling edge of SCLx of a received data byte, CKP is cleared Received data is available on SSPxBUF Cleared by software 1 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK Receive Data 1 3 4 5 6 7 8 Set by software, release SCLx Slave sends not ACK SSPxBUF can be read any time before next byte is loaded 2 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK CKP is not cleared if not ACK No interrupt after if not ACK from Slave P Master sends Stop condition FIGURE 21-17: SCLx SDAx R/W = 0 Master releases SDAx to slave for ACK sequence PIC16(L)F1526/27 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1) DS41458B-page 221 PIC16(L)F1526/27 21.5.3 SLAVE TRANSMISSION 21.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission. Figure 21-17 can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit and the SCLx pin is held low (see Section 21.5.6 "Clock Stretching" for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. 1. The transmit data must be loaded into the SSPxBUF register which also loads the SSPxSR register. Then the SCLx pin should be released by setting the CKP bit of the SSPxCON1 register. The eight data bits are shifted out on the falling edge of the SCLx input. This ensures that the SDAx signal is valid during the SCLx high time. The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCLx input pulse. This ACK value is copied to the ACKSTAT bit of the SSPxCON2 register. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is latched by the slave, the slave goes Idle and waits for another occurrence of the Start bit. If the SDAx line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, the SCLx pin must be released by setting bit CKP. An MSSPx interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared by software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. 21.5.3.1 Slave Mode Bus Collision A slave receives a Read request and begins shifting data out on the SDAx line. If a bus collision is detected and the SBCDE bit of the SSPxCON3 register is set, the BCLxIF bit of the PIRx register is set. Once a bus collision is detected, the slave goes Idle and waits to be addressed again. User software can use the BCLxIF bit to handle a slave bus collision. DS41458B-page 222 Master sends a Start condition on SDAx and SCLx. 2. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 3. Matching address with R/W bit set is received by the slave setting SSPxIF bit. 4. Slave hardware generates an ACK and sets SSPxIF. 5. SSPxIF bit is cleared by user. 6. Software reads the received address from SSPxBUF, clearing BF. 7. R/W is set so CKP was automatically cleared after the ACK. 8. The slave software loads the transmit data into SSPxBUF. 9. CKP bit is set releasing SCLx, allowing the master to clock the data out of the slave. 10. SSPxIF is set after the ACK response from the master is loaded into the ACKSTAT register. 11. SSPxIF bit is cleared. 12. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data. Note 1: If the master ACKs the clock will be stretched. 2: ACKSTAT is the only bit updated on the rising edge of SCLx (9th) rather than the falling. 13. Steps 9-13 are repeated for each transmitted byte. 14. If the master sends a not ACK; the clock is not held, but SSPxIF is still set. 15. The master sends a Restart condition or a Stop. 16. The slave is no longer addressed. Preliminary 2011 Microchip Technology Inc. 2011 Microchip Technology Inc. Preliminary P S D/A R/W ACKSTAT CKP BF SSPxIF S Receiving Address 1 2 5 6 7 8 Indicates an address has been received R/W is copied from the matching address byte 9 R/W = 1 Automatic ACK Received address is read from SSPxBUF 4 When R/W is set SCLx is always held low after 9th SCLx falling edge 3 A7 A6 A5 A4 A3 A2 A1 Transmitting Data Automatic 2 3 4 5 Set by software Data to transmit is loaded into SSPxBUF Cleared by software 1 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Transmitting Data 2 3 4 5 7 8 CKP is not held for not ACK 6 Masters not ACK is copied to ACKSTAT BF is automatically cleared after 8th falling edge of SCLx 1 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK P FIGURE 21-18: SCLx SDAx Master sends Stop condition PIC16(L)F1526/27 I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0) DS41458B-page 223 PIC16(L)F1526/27 21.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt is set. Figure 21-18 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts Idle. Master sends Start condition; the S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 3. Master sends matching address with R/W bit set. After the 8th falling edge of the SCLx line the CKP bit is cleared and SSPxIF interrupt is generated. 4. Slave software clears SSPxIF. 5. Slave software reads ACKTIM bit of SSPxCON3 register, and R/W and D/A of the SSPxSTAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSPxBUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets ACKDT bit of the SSPxCON2 register accordingly. 8. Slave sets the CKP bit releasing SCLx. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSPxIF after the ACK if the R/W bit is set. 11. Slave software clears SSPxIF. 12. Slave loads value to transmit to the master into SSPxBUF setting the BF bit. Note: SSPxBUF cannot be loaded until after the ACK. 13. Slave sets CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the 9th SCLx pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSPxCON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCLx line to receive a Stop. DS41458B-page 224 Preliminary 2011 Microchip Technology Inc. 2011 Microchip Technology Inc. Preliminary D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSPxIF S Receiving Address 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCLx 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSPxBUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address. 1 A7 A6 A5 A4 A3 A2 A1 3 4 5 6 Cleared by software 2 Set by software, releases SCLx Data to transmit is loaded into SSPxBUF 1 7 8 9 Transmitting Data Automatic D7 D6 D5 D4 D3 D2 D1 D0 ACK ACKTIM is cleared on 9th rising edge of SCLx Automatic Transmitting Data 1 3 4 5 6 7 after not ACK CKP not cleared Master's ACK response is copied to SSPxSTAT BF is automatically cleared after 8th falling edge of SCLx 2 8 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK P Master sends Stop condition FIGURE 21-19: SCLx SDAx Master releases SDAx to slave for ACK sequence PIC16(L)F1526/27 I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1) DS41458B-page 225 PIC16(L)F1526/27 21.5.4 21.5.5 SLAVE MODE 10-BIT ADDRESS RECEPTION This section describes a standard sequence of events for the MSSPx module configured as an I2C slave in 10-bit Addressing mode. Figure 21-19 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle. Master sends Start condition; S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. Master sends matching high address with R/W bit clear; UA bit of the SSPxSTAT register is set. Slave sends ACK and SSPxIF is set. Software clears the SSPxIF bit. Software reads received address from SSPxBUF clearing the BF flag. Slave loads low address into SSPxADD, releasing SCLx. Master sends matching low address byte to the slave; UA bit is set. 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSPxADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCLx line is held low are the same. Figure 21-20 can be used as a reference of a slave in 10-bit addressing with AHEN set. Figure 21-21 shows a standard waveform for a slave transmitter in 10-bit Addressing mode. Note: Updates to the SSPxADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSPxIF is set. Note: If the low address does not match, SSPxIF and UA are still set so that the slave software can set SSPxADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSPxIF. 11. Slave reads the received matching address from SSPxBUF clearing BF. 12. Slave loads high address into SSPxADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the 9th SCLx pulse; SSPxIF is set. 14. If SEN bit of SSPxCON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSPxIF. 16. Slave reads the received byte from SSPxBUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCLx. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission. DS41458B-page 226 Preliminary 2011 Microchip Technology Inc. 2011 Microchip Technology Inc. Preliminary CKP UA BF SSPxIF S 1 1 2 1 5 6 7 0 A9 A8 8 Set by hardware on 9th falling edge 4 1 When UA = 1; SCLx is held low 9 ACK If address matches SSPxADD it is loaded into SSPxBUF 3 1 Receive First Address Byte 1 3 4 5 6 7 8 Software updates SSPxADD and releases SCLx 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receive Second Address Byte 1 3 4 5 6 7 8 9 1 3 4 5 6 7 Data is read from SSPxBUF SCLx is held low while CKP = 0 2 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Receive Data Set by software, When SEN = 1; releasing SCLx CKP is cleared after 9th falling edge of received byte Receive address is read from SSPxBUF Cleared by software 2 D7 D6 D5 D4 D3 D2 D1 D0 ACK Receive Data P FIGURE 21-20: SCLx SDAx Master sends Stop condition PIC16(L)F1526/27 I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) DS41458B-page 227 DS41458B-page 228 Preliminary ACKTIM CKP UA ACKDT BF 2 1 5 0 6 A9 7 A8 Set by hardware on 9th falling edge 4 1 ACKTIM is set by hardware on 8th falling edge of SCLx If when AHEN = 1; on the 8th falling edge of SCLx of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte 3 1 8 R/W = 0 9 ACK UA 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 Update to SSPxADD is not allowed until 9th falling edge of SCLx SSPxBUF can be read anytime before the next received byte Cleared by software 1 A7 Receive Second Address Byte 8 A0 9 ACK UA 2 D6 3 D5 4 D4 6 D2 Set CKP with software releases SCLx 7 D1 Update of SSPxADD, clears UA and releases SCLx 5 D3 Receive Data Cleared by software 1 D7 8 9 2 Received data is read from SSPxBUF 1 D6 D5 Receive Data D0 ACK D7 FIGURE 21-21: SSPxIF 1 SCLx S 1 SDAx Receive First Address Byte PIC16(L)F1526/27 I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0) 2011 Microchip Technology Inc. 2011 Microchip Technology Inc. Preliminary D/A R/W ACKSTAT CKP UA BF SSPxIF 4 5 6 7 Set by hardware 3 Indicates an address has been received UA indicates SSPxADD must be updated SSPxBUF loaded with received address 2 8 9 1 SCLx S Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK 1 3 4 5 6 7 8 After SSPxADD is updated, UA is cleared and SCLx is released Cleared by software 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receiving Second Address Byte 1 4 5 6 7 8 Set by hardware 2 3 R/W is copied from the matching address byte When R/W = 1; CKP is cleared on 9th falling edge of SCLx High address is loaded back into SSPxADD Received address is read from SSPxBUF Sr 1 1 1 1 0 A9 A8 Receive First Address Byte 9 ACK 2 3 4 5 6 7 8 Masters not ACK is copied Set by software releases SCLx Data to transmit is loaded into SSPxBUF 1 D7 D6 D5 D4 D3 D2 D1 D0 Transmitting Data Byte 9 P Master sends Stop condition ACK = 1 Master sends not ACK FIGURE 21-22: SDAx Master sends Restart event PIC16(L)F1526/27 I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0) DS41458B-page 229 PIC16(L)F1526/27 21.5.6 21.5.6.2 CLOCK STRETCHING Clock stretching occurs when a device on the bus holds the SCLx line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCLx. The CKP bit of the SSPxCON1 register is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCLx line to go low and then hold it. Setting CKP will release SCLx and allow more communication. 21.5.6.1 Normal Clock Stretching Following an ACK if the R/W bit of SSPxSTAT is set, a read request, the slave hardware will clear CKP. This allows the slave time to update SSPxBUF with data to transfer to the master. If the SEN bit of SSPxCON2 is set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP is set by software and communication resumes. Note 1: The BF bit has no effect on if the clock will be stretched or not. This is different than previous versions of the module that would not stretch the clock, clear CKP, if SSPxBUF was read before the 9th falling edge of SCLx. 2: Previous versions of the module did not stretch the clock for a transmission if SSPxBUF was loaded before the 9th falling edge of SCLx. It is now always cleared for read requests. FIGURE 21-23: 10-bit Addressing Mode In 10-bit Addressing mode, when the UA bit is set, the clock is always stretched. This is the only time the SCLx is stretched without CKP being cleared. SCLx is released immediately after a write to SSPxADD. Note: Previous versions of the module did not stretch the clock if the second address byte did not match. 21.5.6.3 Byte NACKing When AHEN bit of SSPxCON3 is set; CKP is cleared by hardware after the 8th falling edge of SCLx for a received matching address byte. When DHEN bit of SSPxCON3 is set; CKP is cleared after the 8th falling edge of SCLx for received data. Stretching after the 8th falling edge of SCLx allows the slave to look at the received address or data and decide if it wants to ACK the received data. 21.5.7 CLOCK SYNCHRONIZATION AND THE CKP BIT Any time the CKP bit is cleared, the module will wait for the SCLx line to go low and then hold it. However, clearing the CKP bit will not assert the SCLx output low until the SCLx output is already sampled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C master device has already asserted the SCLx line. The SCLx output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCLx. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCLx (see Figure 21-22). CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDAx DX - 1 DX SCLx CKP Master device asserts clock Master device releases clock WR SSPxCON1 DS41458B-page 230 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 21.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge. If the AHEN bit of the SSPxCON3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the 8th falling edge of SCLx. The slave must then set its ACKDT value and release the clock with communication progressing as it would normally. The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit of the SSPxCON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSPxADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave software can read SSPxBUF and respond. Figure 21-23 shows a general call reception sequence. FIGURE 21-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 General Call Address SDAx SCLx S 1 2 3 4 5 6 7 8 9 1 Receiving Data ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 SSPxIF BF (SSPxSTAT<0>) Cleared by software SSPxBUF is read GCEN (SSPxCON2<7>) '1' 21.5.9 SSPX MASK REGISTER An SSPx Mask (SSPxMSK) register (Register 21-5) is available in I2C Slave mode as a mask for the value held in the SSPxSR register during an address comparison operation. A zero (`0') bit in the SSPxMSK register has the effect of making the corresponding bit of the received address a "don't care". This register is reset to all `1's upon any Reset condition and, therefore, has no effect on standard SSPx operation until written with a mask value. The SSPx Mask register is active during: * 7-bit Address mode: address compare of A<7:1>. * 10-bit Address mode: address compare of A<7:0> only. The SSPx mask has no effect during the reception of the first (high) byte of the address. 2011 Microchip Technology Inc. Preliminary DS41458B-page 231 PIC16(L)F1526/27 21.6 I2C MASTER MODE 21.6.1 I2C MASTER MODE OPERATION Master mode is enabled by setting and clearing the appropriate SSPxM bits in the SSPxCON1 register and by setting the SSPxEN bit. In Master mode, the SDA and SCK pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSPx module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle. In Master Transmitter mode, serial data is output through SDAx, while SCLx outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic `0'. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDAx and SCLx lines. The following events will cause the SSPx Interrupt flag bit, SSPxIF, to be set (SSPx interrupt, if enabled): * * * * * Start condition detected Stop condition detected Data transfer byte transmitted/received Acknowledge transmitted/received Repeated Start generated Note 1: The MSSPx module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not occur In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic `1'. Thus, the first byte transmitted is a 7-bit slave address followed by a `1' to indicate the receive bit. Serial data is received via SDAx, while SCLx outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. A Baud Rate Generator is used to set the clock frequency output on SCLx. See Section 21.7 "Baud Rate Generator" for more detail. 2: When in Master mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and the generation is complete. DS41458B-page 232 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 21.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 21-25). FIGURE 21-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDAx DX - 1 DX SCLx deasserted but slave holds SCLx low (clock arbitration) SCLx allowed to transition high SCLx BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCLx is sampled high, reload takes place and BRG starts its count BRG Reload 21.6.3 WCOL STATUS FLAG If the user writes the SSPxBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not Idle. Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPxCON2 is disabled until the Start condition is complete. 2011 Microchip Technology Inc. Preliminary DS41458B-page 233 PIC16(L)F1526/27 21.6.4 I2C MASTER MODE START by hardware; the Baud Rate Generator is suspended, leaving the SDAx line held low and the Start condition is complete. CONDITION TIMING To initiate a Start condition, the user sets the Start Enable bit, SEN bit of the SSPxCON2 register. If the SDAx and SCLx pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and starts its count. If SCLx and SDAx are both sampled high when the Baud Rate Generator times out (TBRG), the SDAx pin is driven low. The action of the SDAx being driven low while SCLx is high is the Start condition and causes the S bit of the SSPxSTAT1 register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSPxCON2 register will be automatically cleared FIGURE 21-26: Note 1: If at the beginning of the Start condition, the SDAx and SCLx pins are already sampled low, or if during the Start condition, the SCLx line is sampled low before the SDAx line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLxIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. 2: The Philips I2C Specification states that a bus collision cannot occur on a Start. FIRST START BIT TIMING Set S bit (SSPxSTAT<3>) Write to SEN bit occurs here At completion of Start bit, hardware clears SEN bit and sets SSPxIF bit SDAx = 1, SCLx = 1 TBRG TBRG Write to SSPxBUF occurs here SDAx 1st bit 2nd bit TBRG SCLx S DS41458B-page 234 Preliminary TBRG 2011 Microchip Technology Inc. PIC16(L)F1526/27 21.6.5 I2C MASTER MODE REPEATED SSPxCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDAx pin held low. As soon as a Start condition is detected on the SDAx and SCLx pins, the S bit of the SSPxSTAT register will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out. START CONDITION TIMING A Repeated Start condition occurs when the RSEN bit of the SSPxCON2 register is programmed high and the master state machine is no longer active. When the RSEN bit is set, the SCLx pin is asserted low. When the SCLx pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDAx pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDAx is sampled high, the SCLx pin will be deasserted (brought high). When SCLx is sampled high, the Baud Rate Generator is reloaded and begins counting. SDAx and SCLx must be sampled high for one TBRG. This action is then followed by assertion of the SDAx pin (SDAx = 0) for one TBRG while SCLx is high. SCLx is asserted low. Following this, the RSEN bit of the FIGURE 21-27: Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: * SDAx is sampled low when SCLx goes from low-to-high. * SCLx goes low before SDAx is asserted low. This may indicate that another master is attempting to transmit a data `1'. REPEAT START CONDITION WAVEFORM S bit set by hardware Write to SSPxCON2 occurs here SDAx = 1, SCLx (no change) At completion of Start bit, hardware clears RSEN bit and sets SSPxIF SDAx = 1, SCLx = 1 TBRG TBRG TBRG 1st bit SDAx Write to SSPxBUF occurs here TBRG SCLx Sr TBRG Repeated Start 2011 Microchip Technology Inc. Preliminary DS41458B-page 235 PIC16(L)F1526/27 21.6.6 I2C MASTER MODE TRANSMISSION 21.6.6.3 Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted. SCLx is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCLx is released high. When the SCLx pin is released high, it is held that way for TBRG. The data on the SDAx pin must remain stable for that duration and some hold time after the next falling edge of SCLx. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDAx. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPxIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPxBUF, leaving SCLx low and SDAx unchanged (Figure 21-27). After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCLx until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will release the SDAx pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDAx pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT Status bit of the SSPxCON2 register. Following the falling edge of the ninth clock transmission of the address, the SSPxIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPxBUF takes place, holding SCLx low and allowing SDAx to float. 21.6.6.1 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit of the SSPxCON2 register is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 21.6.6.4 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. BF Status Flag Typical transmit sequence: The user generates a Start condition by setting the SEN bit of the SSPxCON2 register. SSPxIF is set by hardware on completion of the Start. SSPxIF is cleared by software. The MSSPx module will wait the required start time before any other operation takes place. The user loads the SSPxBUF with the slave address to transmit. Address is shifted out the SDAx pin until all 8 bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSPx module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. The MSSPx module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. The user loads the SSPxBUF with eight bits of data. Data is shifted out the SDAx pin until all 8 bits are transmitted. The MSSPx module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. Steps 8-11 are repeated for all transmitted data bytes. The user generates a Stop or Restart condition by setting the PEN or RSEN bits of the SSPxCON2 register. Interrupt is generated once the Stop/Restart condition is complete. In Transmit mode, the BF bit of the SSPxSTAT register is set when the CPU writes to SSPxBUF and is cleared when all 8 bits are shifted out. 21.6.6.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission. DS41458B-page 236 Preliminary 2011 Microchip Technology Inc. 2011 Microchip Technology Inc. S Preliminary R/W PEN SEN BF (SSPxSTAT<0>) SSPxIF SCLx SDAx A6 A5 A4 A3 A2 A1 3 4 5 Cleared by software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPxBUF written 1 D7 1 SCLx held low while CPU responds to SSPxIF ACK = 0 R/W = 0 SSPxBUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPxBUF is written by software Cleared by software service routine from SSPx interrupt 2 D6 Transmitting Data or Second Half of 10-bit Address P ACKSTAT in SSPxCON2 = 1 Cleared by software 9 ACK From slave, clear ACKSTAT bit SSPxCON2<6> FIGURE 21-28: SEN = 0 Write SSPxCON2<0> SEN = 1 Start condition begins PIC16(L)F1526/27 I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) DS41458B-page 237 PIC16(L)F1526/27 21.6.7 I2C MASTER MODE RECEPTION 21.6.7.4 Master mode reception is enabled by programming the Receive Enable bit, RCEN bit of the SSPxCON2 register. Note: The MSSPx module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCLx pin changes (high-to-low/low-to-high) and data is shifted into the SSPxSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPxSR are loaded into the SSPxBUF, the BF flag bit is set, the SSPxIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCLx low. The MSSPx is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable, ACKEN bit of the SSPxCON2 register. 21.6.7.1 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from SSPxSR. It is cleared when the SSPxBUF register is read. 11. 21.6.7.2 12. SSPxOV Status Flag In receive operation, the SSPxOV bit is set when 8 bits are received into the SSPxSR and the BF flag bit is already set from a previous reception. 13. 14. 21.6.7.3 15. WCOL Status Flag If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPxSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). DS41458B-page 238 Preliminary Typical Receive Sequence: The user generates a Start condition by setting the SEN bit of the SSPxCON2 register. SSPxIF is set by hardware on completion of the Start. SSPxIF is cleared by software. User writes SSPxBUF with the slave address to transmit and the R/W bit set. Address is shifted out the SDAx pin until all 8 bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSPx module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. The MSSPx module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. User sets the RCEN bit of the SSPxCON2 register and the master clocks in a byte from the slave. After the 8th falling edge of SCLx, SSPxIF and BF are set. Master clears SSPxIF and reads the received byte from SSPxUF, clears BF. Master sets ACK value sent to slave in ACKDT bit of the SSPxCON2 register and initiates the ACK by setting the ACKEN bit. Masters ACK is clocked out to the slave and SSPxIF is set. User clears SSPxIF. Steps 8-13 are repeated for each received byte from the slave. Master sends a not ACK or Stop to end communication. 2011 Microchip Technology Inc. 2011 Microchip Technology Inc. S Preliminary RCEN ACKEN SSPxOV BF (SSPxSTAT<0>) SDAx = 0, SCLx = 1 while CPU responds to SSPxIF SSPxIF SCLx SDAx 1 A7 2 4 5 6 Cleared by software 3 A6 A5 A4 A3 A2 Transmit Address to Slave 7 8 9 ACK Receiving Data from Slave 2 3 5 6 7 8 D0 9 ACK Receiving Data from Slave 2 3 4 RCEN cleared automatically 5 6 7 Cleared by software Set SSPxIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 ACK from Master SDAx = ACKDT = 0 Cleared in software Set SSPxIF at end of receive 9 ACK is not sent ACK RCEN cleared automatically P Set SSPxIF interrupt at end of Acknowledge sequence Bus master terminates transfer Set P bit (SSPxSTAT<4>) and SSPxIF PEN bit = 1 written here SSPxOV is set because SSPxBUF is still full 8 D0 RCEN cleared automatically Set ACKEN, start Acknowledge sequence SDAx = ACKDT = 1 D7 D6 D5 D4 D3 D2 D1 Last bit is shifted into SSPxSR and contents are unloaded into SSPxBUF Cleared by software Set SSPxIF interrupt at end of receive 4 Cleared by software 1 D7 D6 D5 D4 D3 D2 D1 Master configured as a receiver by programming SSPxCON2<3> (RCEN = 1) A1 R/W RCEN = 1, start next receive ACK from Master SDAx = ACKDT = 0 FIGURE 21-29: RCEN cleared automatically Master configured as a receiver by programming SSPxCON2<3> (RCEN = 1) SEN = 0 Write to SSPxBUF occurs here, ACK from Slave start XMIT Write to SSPxCON2<0>(SEN = 1), begin Start condition Write to SSPxCON2<4> to start Acknowledge sequence SDAx = ACKDT (SSPxCON2<5>) = 0 PIC16(L)F1526/27 I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) DS41458B-page 239 PIC16(L)F1526/27 21.6.8 ACKNOWLEDGE SEQUENCE TIMING 21.6.9 A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPxCON2 register. At the end of a receive/transmit, the SCLx line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDAx line low. When the SDAx line is sampled low, the Baud Rate Generator is reloaded and counts down to `0'. When the Baud Rate Generator times out, the SCLx pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDAx pin will be deasserted. When the SDAx pin is sampled high while SCLx is high, the P bit of the SSPxSTAT register is set. A TBRG later, the PEN bit is cleared and the SSPxIF bit is set (Figure 21-30). An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN bit of the SSPxCON2 register. When this bit is set, the SCLx pin is pulled low and the contents of the Acknowledge data bit are presented on the SDAx pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCLx pin is deasserted (pulled high). When the SCLx pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCLx pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSPx module then goes into Idle mode (Figure 21-29). 21.6.8.1 21.6.9.1 WCOL Status Flag If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL Status Flag If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 21-30: STOP CONDITION TIMING ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSPxCON2 ACKEN = 1, ACKDT = 0 ACKEN automatically cleared TBRG TBRG SDAx SCLx ACK D0 8 9 SSPxIF SSPxIF set at the end of receive Cleared in software Cleared in software SSPxIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. DS41458B-page 240 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 21-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG after SDAx sampled high. P bit (SSPxSTAT<4>) is set. Write to SSPxCON2, set PEN PEN bit (SSPxCON2<2>) is cleared by hardware and the SSPxIF bit is set Falling edge of 9th clock TBRG SCLx SDAx ACK P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 21.6.10 SLEEP OPERATION 21.6.13 2 While in Sleep mode, the I C slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSPx interrupt is enabled). 21.6.11 EFFECTS OF A RESET A Reset disables the MSSPx module and terminates the current transfer. 21.6.12 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSPx module is disabled. Control of the I 2C bus may be taken when the P bit of the SSPxSTAT register is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the SSPx interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDAx line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCLxIF bit. The states where arbitration can be lost are: * * * * * Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDAx pin, arbitration takes place when the master outputs a `1' on SDAx, by letting SDAx float high and another master asserts a `0'. When the SCLx pin floats high, data should be stable. If the expected data on SDAx is a `1' and the data sampled on the SDAx pin is `0', then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLxIF and reset the I2C port to its Idle state (Figure 21-31). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDAx and SCLx lines are deasserted and the SSPxBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDAx and SCLx lines are deasserted and the respective control bits in the SSPxCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDAx and SCLx pins. If a Stop condition occurs, the SSPxIF bit will be set. A write to the SSPxBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared. 2011 Microchip Technology Inc. Preliminary DS41458B-page 241 PIC16(L)F1526/27 FIGURE 21-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCLx = 0 SDAx line pulled low by another source SDAx released by master Sample SDAx. While SCLx is high, data does not match what is driven by the master. Bus collision has occurred. SDAx SCLx Set bus collision interrupt (BCLxIF) BCLxIF DS41458B-page 242 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 21.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDAx or SCLx are sampled low at the beginning of the Start condition (Figure 21-32). SCLx is sampled low before SDAx is asserted low (Figure 21-33). During a Start condition, both the SDAx and the SCLx pins are monitored. If the SDAx pin is sampled low during this count, the BRG is reset and the SDAx line is asserted early (Figure 21-34). If, however, a `1' is sampled on the SDAx pin, the SDAx pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCLx pin is sampled as `0' during this time, a bus collision does not occur. At the end of the BRG count, the SCLx pin is asserted low. Note: If the SDAx pin is already low, or the SCLx pin is already low, then all of the following occur: * the Start condition is aborted, * the BCLxIF flag is set and * the MSSPx module is reset to its Idle state (Figure 21-32). The Start condition begins with the SDAx and SCLx pins deasserted. When the SDAx pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCLx pin is sampled low while SDAx is high, a bus collision occurs because it is assumed that another master is attempting to drive a data `1' during the Start condition. FIGURE 21-33: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDAx before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. BUS COLLISION DURING START CONDITION (SDAX ONLY) SDAx goes low before the SEN bit is set. Set BCLxIF, S bit and SSPxIF set because SDAx = 0, SCLx = 1. SDAx SCLx Set SEN, enable Start condition if SDAx = 1, SCLx = 1 SEN cleared automatically because of bus collision. SSPx module reset into Idle state. SEN BCLxIF SDAx sampled low before Start condition. Set BCLxIF. S bit and SSPxIF set because SDAx = 0, SCLx = 1. SSPxIF and BCLxIF are cleared by software S SSPxIF SSPxIF and BCLxIF are cleared by software 2011 Microchip Technology Inc. Preliminary DS41458B-page 243 PIC16(L)F1526/27 FIGURE 21-34: BUS COLLISION DURING START CONDITION (SCLX = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 SCLx SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF. BCLxIF Interrupt cleared by software S '0' '0' SSPxIF '0' '0' FIGURE 21-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDAx = 0, SCLx = 1 Set S Less than TBRG SDAx SCLx TBRG SDAx pulled low by other master. Reset BRG and assert SDAx. S SCLx pulled low after BRG time-out SEN BCLxIF Set SSPxIF Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 '0' S SSPxIF SDAx = 0, SCLx = 1, set SSPxIF DS41458B-page 244 Preliminary Interrupts cleared by software 2011 Microchip Technology Inc. PIC16(L)F1526/27 21.6.13.2 Bus Collision During a Repeated Start Condition If SDAx is low, a bus collision has occurred (i.e., another master is attempting to transmit a data `0', Figure 21-35). If SDAx is sampled high, the BRG is reloaded and begins counting. If SDAx goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDAx at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDAx when SCLx goes from low level to high level. SCLx goes low before SDAx is asserted low, indicating that another master is attempting to transmit a data `1'. If SCLx goes from high-to-low before the BRG times out and SDAx has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data `1' during the Repeated Start condition, see Figure 21-36. When the user releases SDAx and the pin is allowed to float high, the BRG is loaded with SSPxADD and counts down to zero. The SCLx pin is then deasserted and when sampled high, the SDAx pin is sampled. FIGURE 21-36: If, at the end of the BRG time-out, both SCLx and SDAx are still high, the SDAx pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCLx pin, the SCLx pin is driven low and the Repeated Start condition is complete. BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDAx SCLx Sample SDAx when SCLx goes high. If SDAx = 0, set BCLxIF and release SDAx and SCLx. RSEN BCLxIF Cleared by software S '0' SSPxIF '0' FIGURE 21-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDAx SCLx BCLxIF SCLx goes low before SDAx, set BCLxIF. Release SDAx and SCLx. Interrupt cleared by software RSEN '0' S SSPxIF 2011 Microchip Technology Inc. Preliminary DS41458B-page 245 PIC16(L)F1526/27 21.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to 0. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data `0' (Figure 21-37). If the SCLx pin is sampled low before SDAx is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data `0' (Figure 21-38). Bus collision occurs during a Stop condition if: a) b) After the SDAx pin has been deasserted and allowed to float high, SDAx is sampled low after the BRG has timed out. After the SCLx pin is deasserted, SCLx is sampled low before SDAx goes high. FIGURE 21-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG SDAx sampled low after TBRG, set BCLxIF TBRG SDAx SDAx asserted low SCLx PEN BCLxIF P '0' SSPxIF '0' FIGURE 21-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDAx SCLx goes low before SDAx goes high, set BCLxIF Assert SDAx SCLx PEN BCLxIF P '0' SSPxIF '0' DS41458B-page 246 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 TABLE 21-3: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH I2CTM OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: 80 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 81 PIE2 OSFIE TMR5GIE TMR3GIE -- BCL1IE TMR10IE TMR8IE CCP2IE 82 PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 84 PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 85 PIR2 OSFIF TMR5GIF TMR3GIF -- BCL1IF TMR10IF TMR8IF CCP2IF 86 PIR4 CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF 88 SSP1ADD ADD<7:0> SSP2ADD 254 ADD<7:0> SSP1BUF MSSPx Receive Buffer/Transmit Register SSP2BUF MSSPx Receive Buffer/Transmit Register SSPOV SSPEN 254 205* 205* SSP1CON1 WCOL CKP SSPM<3:0> SSP2CON1 WCOL SSPOV SSPEN CKP SSP1CON2 GCEN ACKSTAT ACKDT ACKEN SSP2CON2 GCEN ACKSTAT ACKDT ACKEN SSP1CON3 ACKTIM PCIE SCIE BOEN SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT 251 SSPM<3:0> RCEN 251 PEN RSEN SEN 252 RCEN PEN SDAHT SBCDE RSEN SEN 252 AHEN DHEN 253 SBCDE AHEN DHEN 253 SSP1MSK MSK<7:0> 254 SSP2MSK MSK<7:0> 254 SSP1STAT SMP CKE D/A P S R/W UA BF 249 SSP2STAT SMP CKE D/A P S R/W UA BF 249 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 126 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 129 Legend: * Note 1: -- = unimplemented location, read as `0'. Shaded cells are not used by the MSSP module in I2CTM mode. Page provides register information. PIC16(L)F1527 only. 2011 Microchip Technology Inc. Preliminary DS41458B-page 247 PIC16(L)F1526/27 21.7 BAUD RATE GENERATOR The MSSPx module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register (Register 21-6). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSPx is being operated in. Table 21-4 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. EQUATION 21-1: FOSC FCLOCK = ------------------------------------------------ SSPxADD + 1 4 An internal signal "Reload" in Figure 21-39 triggers the value from SSPxADD to be loaded into the BRG counter. This occurs twice for each oscillation of the FIGURE 21-40: BAUD RATE GENERATOR BLOCK DIAGRAM SSPxM<3:0> SSPxM<3:0> Reload SSPxADD<7:0> Reload Control SCLx SSPxCLK BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 21-4: Note 1: MSSPX CLOCK RATE W/BRG FOSC FCY BRG Value FCLOCK (2 Rollovers of BRG) 16 MHz 4 MHz 09h 400 kHz(1) 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application. DS41458B-page 248 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 21.8 MSSP Control Registers REGISTER 21-1: SSPxSTAT: SSPx STATUS REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) In SPI Master or Slave mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I2 CTM mode only: 1 = Enable input logic so that thresholds are compliant with SMBus specification 0 = Disable SMBus specific inputs bit 5 bit 4 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: Stop bit (I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is `0' on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is `0' on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I2 C Slave mode: 1 = Read 0 = Write In I2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated 2011 Microchip Technology Inc. Preliminary DS41458B-page 249 PIC16(L)F1526/27 REGISTER 21-1: bit 0 SSPxSTAT: SSPx STATUS REGISTER (CONTINUED) BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty DS41458B-page 250 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 REGISTER 21-2: SSPxCON1: SSPx CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSPxOV SSPxEN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSPxM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPxOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register (must be cleared in software). 0 = No overflow 2 In I C mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte. SSPxOV is a "don't care" in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSPxEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I2C mode: 1 = Enables the serial port and configures the SDAx and SCLx pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C Slave mode: SCLx release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I2C Master mode: Unused in this mode bit 3-0 SSPxM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled 0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC/(4 * (SSPxADD+1))(4) 1001 = Reserved 1010 = SPI Master mode, clock = FOSC/(4 * (SSPxADD+1))(5) 1011 = I2C firmware controlled Master mode (Slave idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Note 1: 2: 3: 4: 5: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. When enabled, these pins must be properly configured as input or output. When enabled, the SDAx and SCLx pins must be configured as inputs. SSPxADD values of 0, 1 or 2 are not supported for I2C mode. SSPxADD value of `0' is not supported. Use SSPxM = 0000 instead. 2011 Microchip Technology Inc. Preliminary DS41458B-page 251 PIC16(L)F1526/27 REGISTER 21-3: SSPxCON2: SSPx CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only) SCKx Release Control: 1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enabled bit (in I2C Master mode only) In Master mode: 1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). DS41458B-page 252 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 REGISTER 21-4: SSPxCON3: SSPx CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCLx clock 0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCLx clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSPxSTAT register already set, SSPxOV bit of the SSPxCON1 register is set, and the buffer is not updated In I2C Master mode and SPI Master mode: This bit is ignored. In I2C Slave mode: 1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPxOV bit only if the BF bit = 0. 0 = SSPxBUF is only updated when SSPxOV is clear bit 3 SDAHT: SDAx Hold Time Selection bit (I2C mode only) 1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx 0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the BCLxIF bit of the PIR2 register is set, and bus goes Idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCLx for a matching received address byte; CKP bit of the SSPxCON1 register will be cleared and the SCLx will be held low. 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the CKP bit of the SSPxCON1 register and SCLx is held low. 0 = Data holding is disabled Note 1: 2: 3: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPxOV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF. This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set. 2011 Microchip Technology Inc. Preliminary DS41458B-page 253 PIC16(L)F1526/27 REGISTER 21-5: R/W-1/1 SSPxMSK: SSPx MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPxADD<n> to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSPxM<3:0> = 0111 or 1111): 1 = The received address bit 0 is compared to SSPxADD<0> to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored REGISTER 21-6: R/W-0/0 SSPxADD: MSSPx ADDRESS AND BAUD RATE REGISTER (I2C MODE) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared Master mode: bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCLx pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave mode -- Most Significant Address byte: bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a "don't care". Bit pattern sent by master is fixed by I2C specification and must be equal to `11110'. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a "don't care". 10-Bit Slave mode -- Least Significant Address byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD<7:1>: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a "don't care". DS41458B-page 254 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 22.0 Note: These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The EUSART module includes the following capabilities: * * * * * * * * * * The PIC16(L)F1526/27 devices have two EUSARTs. Therefore, all information in this section refers to both EUSART 1 and EUSART 2. The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. FIGURE 22-1: Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous master Half-duplex synchronous slave Programmable clock and data polarity The EUSART module implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems: * Automatic detection and calibration of the baud rate * Wake-up on Break reception * 13-bit Break character transmit Block diagrams of the EUSART transmitter and receiver are shown in Figure 22-1 and Figure 22-2. EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXxIE Interrupt TXxIF TXxREG Register 8 MSb LSb (8) 0 * * * TXx/CKx pin Pin Buffer and Control Transmit Shift Register (TSR) TXEN TRMT Baud Rate Generator FOSC /n TX9 n BRG16 +1 SPxBRGH SPxBRGL Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 2011 Microchip Technology Inc. TX9D Preliminary DS41458B-page 255 PIC16(L)F1526/27 FIGURE 22-2: EUSART RECEIVE BLOCK DIAGRAM CREN RXx/DTx pin Baud Rate Generator Data Recovery FOSC SPxBRGH SPxBRGL x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 (8) *** 7 1 LSb 0 START RX9 /n BRG16 Multiplier Stop RCIDL RSR Register MSb Pin Buffer and Control +1 OERR n FERR RX9D RCxREG Register 8 FIFO Data Bus RCxIF RCxIE Interrupt The operation of the EUSART module is controlled through three registers: * Transmit Status and Control (TXxSTA) * Receive Status and Control (RCxSTA) * Baud Rate Control (BAUDxCON) These registers are detailed in Register 22-1, Register 22-2 and Register 22-3, respectively. For all modes of EUSART operation, the TRIS control bits corresponding to the RXx/DTx and TXx/CKx pins should be set to `1'. The EUSART control will automatically reconfigure the pin from input to output, as needed. When the receiver or transmitter section is not enabled then the corresponding RXx/DTx or TXx/CKx pin may be used for general purpose input and output. DS41458B-page 256 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 22.1 22.1.1.2 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a `1' data bit, and a VOL space state which represents a `0' data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is 8 bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 22-5 for examples of baud rate configurations. Transmitting Data A transmission is initiated by writing a character to the TXxREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXxREG until the Stop bit of the previous character has been transmitted. The pending character in the TXxREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXxREG. 22.1.1.3 Transmit Data Polarity The EUSART transmits and receives the LSb first. The EUSART's transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. The polarity of the transmit data can be controlled with the CKTXP bit of the BAUDxCON register. The default state of this bit is `0' which selects high true transmit idle and data bits. Setting the CKTXP bit to `1' will invert the transmit data resulting in low true idle and data bits. The CKTXP bit controls transmit data polarity only in Asynchronous mode. In Synchronous mode the CKTXP bit has a different function. 22.1.1 22.1.1.4 EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 22-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXxREG register. 22.1.1.1 Enabling the Transmitter The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: * TXEN = 1 * SYNC = 0 * SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXxSTA register enables the transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXxSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCxSTA register enables the EUSART. The programmer must set the corresponding TRIS bit to configure the TXx/CKx I/O pin as an output. If the TXx/CKx pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note: Transmit Interrupt Flag The TXxIF interrupt flag bit of the PIR1/PIR4 register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the TXxREG. In other words, the TXxIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXxREG. The TXxIF flag bit is not cleared immediately upon writing TXxREG. TXxIF becomes valid in the second instruction cycle following the write execution. Polling TXxIF immediately following the TXxREG write will return invalid results. The TXxIF bit is read-only, it cannot be set or cleared by software. The TXxIF interrupt can be enabled by setting the TXxIE interrupt enable bit of the PIE1/PIE4 register. However, the TXxIF flag bit will be set whenever the TXxREG is empty, regardless of the state of TXxIE enable bit. To use interrupts when transmitting data, set the TXxIE bit only when there is more data to send. Clear the TXxIE interrupt enable bit upon writing the last character of the transmission to the TXxREG. The TXxIF transmitter interrupt flag is set when the TXEN enable bit is set. 2011 Microchip Technology Inc. Preliminary DS41458B-page 257 PIC16(L)F1526/27 22.1.1.5 TSR Status 22.1.1.7 The TRMT bit of the TXxSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXxREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user needs to poll this bit to determine the TSR status. Note: 22.1.1.6 The TSR register is not mapped in data memory, so it is not available to the user. 1. 2. 3. 4. Transmitting 9-Bit Characters The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXxSTA register is set the EUSART will shift 9 bits out for each character transmitted. The TX9D bit of the TXxSTA register is the ninth, and Most Significant, data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the 8 Least Significant bits into the TXxREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXxREG is written. 5. A special 9-bit Address mode is available for use with multiple receivers. See Section 22.1.2.8 "Address Detection" for more information on the Address mode. 8. FIGURE 22-3: Write to TXxREG BRG Output (Shift Clock) TXx/CKx pin TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) DS41458B-page 258 6. 7. 9. Asynchronous Transmission Set-up: Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 22.4 "EUSART Baud Rate Generator (BRG)"). Set the RXx/DTx and TXx/CKx TRIS controls to `1'. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the 8 Least Significant data bits are an address when the receiver is set for address detection. Set the CKTXP control bit if inverted transmit data polarity is desired. Enable the transmission by setting the TXEN control bit. This will cause the TXxIF interrupt bit to be set. If interrupts are desired, set the TXxIE interrupt enable bit. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXxREG register. This will start the transmission. ASYNCHRONOUS TRANSMISSION Word 1 Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 1 TCY Word 1 Transmit Shift Reg Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 22-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXxREG Word 1 BRG Output (Shift Clock) TXx/CKx pin Word 2 Start bit bit 0 bit 1 Word 1 1 TCY TXxIF bit (Interrupt Reg. Flag) bit 7/8 Stop bit Start bit Word 2 bit 0 1 TCY TRMT bit (Transmit Shift Reg. Empty Flag) Word 1 Transmit Shift Reg Word 2 Transmit Shift Reg This timing diagram shows two consecutive transmissions. Note: TABLE 22-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page BAUD1CON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 266 BAUD2CON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 266 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93 94 INTCON PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 97 PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 98 PIR4 CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF 97 RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 265 RC2STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 265 SP1BRGL EUSART1 Baud Rate Generator, Low Byte 267* SP1BRGH EUSART1 Baud Rate Generator, High Byte 267* SP2BRGL EUSART2 Baud Rate Generator, Low Byte 267* SP2BRGH EUSART2 Baud Rate Generator, High Byte 267* EUSART1 Transmit Register 257* TX1REG TX1STA CSRC TX9 TXEN TX2REG TX2STA Legend: * SYNC SENDB BRGH TRMT TX9D EUSART2 Transmit Register CSRC TX9 TXEN SYNC SENDB 264 257* BRGH TRMT TX9D 264 -- = unimplemented locations, read as `0'. Shaded bits are not used for asynchronous transmission. Page provides register information. 2011 Microchip Technology Inc. Preliminary DS41458B-page 259 PIC16(L)F1526/27 22.1.2 EUSART ASYNCHRONOUS RECEIVER 22.1.2.2 The Asynchronous mode would typically be used in RS-232 systems. The receiver block diagram is shown in Figure 22-2. The data is received on the RXx/DTx pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all 8 or 9 bits of the character have been shifted in, they are immediately transferred to a two character First-In-First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCxREG register. 22.1.2.1 Enabling the Receiver The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits: * CREN = 1 * SYNC = 0 * SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the CREN bit of the RCxSTA register enables the receiver circuitry of the EUSART. Clearing the SYNC bit of the TXxSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCxSTA register enables the EUSART. The programmer must set the corresponding TRIS bit to configure the RXx/DTx I/O pin as an input. Note 1: If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. If the RXx/DTx pin is shared with an analog peripheral the analog I/O function must be disabled by clearing the corresponding ANSEL bit. DS41458B-page 260 Receiving Data The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting `0' or `1' is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a `1'. If the data recovery circuit samples a `0' in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. See Section 22.1.2.5 "Receive Framing Error" for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RCxIF interrupt flag bit of the PIR1/PIR4 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCxREG register. Note: 22.1.2.3 If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See Section 22.1.2.6 "Receive Overrun Error" for more information on overrun errors. Receive Data Polarity The polarity of the receive data can be controlled with the DTRXP bit of the BAUDxCON register. The default state of this bit is `0' which selects high true receive idle and data bits. Setting the DTRXP bit to `1' will invert the receive data resulting in low true idle and data bits. The DTRXP bit controls receive data polarity only in Asynchronous mode. In Synchronous mode the DTRXP bit has a different function. Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 22.1.2.4 Receive Interrupts 22.1.2.7 The RCxIF interrupt flag bit of the PIR1/PIR4 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCxIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCxIF interrupts are enabled by setting the following bits: * RCxIE interrupt enable bit of the PIE1/PIE4 register * PEIE peripheral interrupt enable bit of the INTCON register * GIE global interrupt enable bit of the INTCON register The RCxIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. 22.1.2.5 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCxSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCxREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set, the EUSART will shift 9 bits into the RSR for each character received. The RX9D bit of the RCxSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCxREG. 22.1.2.8 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCxSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCxIF interrupt bit. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit. The FERR bit can be forced clear by clearing the SPEN bit of the RCxSTA register which resets the EUSART. Clearing the CREN bit of the RCxSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: 22.1.2.6 If all receive characters in the receive FIFO have framing errors, repeated reads of the RCxREG will not clear the FERR bit. Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCxSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCxSTA register or by resetting the EUSART by clearing the SPEN bit of the RCxSTA register. 2011 Microchip Technology Inc. Preliminary DS41458B-page 261 PIC16(L)F1526/27 22.1.2.9 Asynchronous Reception Set-up: 1. 22.1.2.10 Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 22.4 "EUSART Baud Rate Generator (BRG)"). 2. Set the RXx/DTx and TXx/CKx TRIS controls to `1'. 3. Enable the serial port by setting the SPEN bit and the RXx/DTx pin TRIS bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCxIE interrupt enable bit and set the GIE and PEIE bits of the INTCON register. 5. If 9-bit reception is desired, set the RX9 bit. 6. Set the DTRXP if inverted receive polarity is desired. 7. Enable reception by setting the CREN bit. 8. The RCxIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCxIE interrupt enable bit was also set. 9. Read the RCxSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 10. Get the received 8 Least Significant data bits from the receive buffer by reading the RCxREG register. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. DS41458B-page 262 9-bit Address Detection Mode Set-up Preliminary Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 22.4 "EUSART Baud Rate Generator (BRG)"). Set the RXx/DTx and TXx/CKx TRIS controls to `1'. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. If interrupts are desired, set the RCxIE interrupt enable bit and set the GIE and PEIE bits of the INTCON register. Enable 9-bit reception by setting the RX9 bit. Enable address detection by setting the ADDEN bit. Set the DTRXP if inverted receive polarity is desired. Enable reception by setting the CREN bit. The RCxIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCxIE interrupt enable bit was also set. Read the RCxSTA register to get the error flags. The ninth data bit will always be set. Get the received 8 Least Significant data bits from the receive buffer by reading the RCxREG register. Software determines if this is the device's address. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 22-5: ASYNCHRONOUS RECEPTION Start bit bit 0 RXx/DTx pin bit 1 bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg Start bit bit 7/8 Stop bit bit 0 bit 7/8 Stop bit Word 2 RCxREG Word 1 RCxREG RCIDL Start bit Read Rcv Buffer Reg RCxREG RCxIF (Interrupt Flag) OERR bit CREN This timing diagram shows three words appearing on the RXx/DTx input. The RCxREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. Note: TABLE 22-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUD1CON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 266 BAUD2CON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 266 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 94 PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 97 PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 98 PIR4 CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF 97 SPEN RX9 SREN FERR OERR RX9D SPEN RX9 SREN FERR OERR RX9D INTCON PIE1 RC1REG RC1STA EUSART1 Receive Register RC2REG RC2STA CREN ADDEN 260* EUSART2 Receive Register CREN ADDEN 265 260* 265 SP1BRGL EUSART1 Baud Rate Generator, Low Byte SP1BRGH EUSART1 Baud Rate Generator, High Byte 267* SP2BRGL EUSART2 Baud Rate Generator, Low Byte 267* SP2BRGH EUSART2 Baud Rate Generator, High Byte 267* TRISC TX1STA TX2STA Legend: * 267* TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 134 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 264 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 264 -- = unimplemented locations, read as `0'. Shaded bits are not used for asynchronous reception. Page provides register information. 2011 Microchip Technology Inc. Preliminary DS41458B-page 263 PIC16(L)F1526/27 22.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (HFINTOSC). However, the HFINTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. 22.3 The first (preferred) method uses the OSCTUNE register to adjust the HFINTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. See Section 5.2 "Clock Source Types" for more information. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see Section 22.4.1 "Auto-Baud Detect"). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. USART Control Registers REGISTER 22-1: TXxSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don't care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don't care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS41458B-page 264 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 REGISTER 22-2: RCxSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don't care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave Don't care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don't care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCxREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. 2011 Microchip Technology Inc. Preliminary DS41458B-page 265 PIC16(L)F1526/27 REGISTER 22-3: BAUDxCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don't care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don't care bit 5 Unimplemented: Read as `0' bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmit inverted data to the TXx/CKx pin 0 = Transmit non-inverted data to the TXx/CKx pin Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as `0' bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally Synchronous mode: Don't care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don't care DS41458B-page 266 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 22.4 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDxCON register selects 16-bit mode. The SPxBRGH:SPxBRGL register pair determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXxSTA register and the BRG16 bit of the BAUDxCON register. In Synchronous mode, the BRGH bit is ignored. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock. EXAMPLE 22-1: For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: F OS C Desired Baud Rate = -------------------------------------------------------------------------64 [SPxBRGH:SPxBRG] + 1 Solving for SPxBRGH:SPxBRGL: F OS C --------------------------------------------Desired Baud Rate SPxBRGH: SPxBRGL = --------------------------------------------- - 1 64 Example 22-1 provides a sample calculation for determining the desired baud rate, actual baud rate, and baud rate % error. Typical baud rates and error values for various Asynchronous modes have been computed for your convenience and are shown in Table 22-5. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. Writing a new value to the SPxBRGH, SPxBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. TABLE 22-3: CALCULATING BAUD RATE ERROR 16000000 -----------------------9600 = ------------------------ - 1 64 = 25.042 = 25 16000000 64 25 + 1 ActualBaudRate = --------------------------= 9615 Calc. Baud Rate - Desired Baud Rate Baud Rate % Error = -------------------------------------------------------------------------------------------Desired Baud Rate 9615 - 9600 = ---------------------------------- = 0.16% 9600 BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 1 Legend: FOSC/[16 (n+1)] FOSC/[4 (n+1)] x = Don't care, n = value of SPxBRGH, SPxBRGL register pair 2011 Microchip Technology Inc. Preliminary DS41458B-page 267 PIC16(L)F1526/27 TABLE 22-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page BAUD1CON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 266 BAUD2CON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 266 RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 265 RC2STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 265 SP1BRGL EUSART1 Baud Rate Generator, Low Byte 267* SP1BRGH EUSART1 Baud Rate Generator, High Byte 267* SP2BRGL EUSART2 Baud Rate Generator, Low Byte 267* SP2BRGH EUSART2 Baud Rate Generator, High Byte 267* TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 264 TX2STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 264 Legend: * -- = unimplemented, read as `0'. Shaded bits are not used by the BRG. Page provides register information. DS41458B-page 268 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 16.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 -- -- -- -- -- -- -- -- -- -- -- -- 1200 1221 1.73 255 1200 0.00 239 1202 0.16 207 1200 0.00 143 2400 2404 0.16 129 2400 0.00 119 2404 0.16 103 2400 0.00 71 9600 9470 -1.36 32 9600 0.00 29 9615 0.16 25 9600 0.00 17 10417 10417 0.00 29 10286 -1.26 27 10417 0.00 23 10165 -2.42 16 19.2k 19.53k 1.73 15 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8 57.6k -- -- -- 57.60k 0.00 7 -- -- -- 57.60k 0.00 2 115.2k -- -- -- -- -- -- -- -- -- -- -- -- SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 1.000 MHz Actual Rate % Error SPBRG value (decimal) 300 -- -- -- 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 -- -- -- 9600 9615 0.16 12 -- -- -- 9600 0.00 5 -- -- -- 10417 10417 0.00 11 10417 0.00 5 -- -- -- -- -- -- 19.2k -- -- -- -- -- -- 19.20k 0.00 2 -- -- -- 57.6k -- -- -- -- -- -- 57.60k 0.00 0 -- -- -- 115.2k -- -- -- -- -- -- -- -- -- -- -- -- SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 16.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 -- -- -- -- -- -- -- -- -- -- -- -- 1200 -- -- -- -- -- -- -- -- -- -- -- -- 2400 -- -- -- -- -- -- -- -- -- -- -- -- 9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 56.82k -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 113.64k -1.36 10 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5 2011 Microchip Technology Inc. Preliminary DS41458B-page 269 PIC16(L)F1526/27 TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 -- -- -- -- -- -- -- 1202 -- 0.16 -- 207 -- 1200 -- 0.00 -- 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 -- 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 -- -- 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 -- -- -- 57.6k 55556 -3.55 8 -- -- -- 57.60k 0.00 3 -- -- -- 115.2k -- -- -- -- -- -- 115.2k 0.00 1 -- -- -- SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 20.000 MHz Actual Rate FOSC = 18.432 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 16.000 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 11.0592 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 300.0 -0.01 4166 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303 1200 1200 -0.03 1041 1200 0.00 959 1200.5 0.04 832 1200 0.00 575 2400 2399 -0.03 520 2400 0.00 479 2398 -0.08 416 2400 0.00 287 9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 56.818 -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 113.636 -1.36 10 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5 SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate FOSC = 4.000 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 3.6864 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 -- -- -- 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 -- -- -- 57.6k 55556 -3.55 8 -- -- -- 57.60k 0.00 3 -- -- -- 115.2k -- -- -- -- -- -- 115.2k 0.00 1 -- -- -- DS41458B-page 270 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200.1 0.00 0.01 13332 3332 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.02 2082 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151 9600 9597 -0.03 520 9600 0.00 479 9592 -0.08 416 9600 0.00 287 10417 10417 0.00 479 10425 0.08 441 10417 0.00 383 10433 0.16 264 Actual Rate % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 19.2k 19.23k 0.16 259 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143 57.6k 57.47k -0.22 86 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47 115.2k 116.3k 0.94 42 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate FOSC = 4.000 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 3.6864 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 -- -- -- 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 -- -- -- 2011 Microchip Technology Inc. Preliminary DS41458B-page 271 PIC16(L)F1526/27 22.4.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RXx signal, the RXx signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII "U") which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge. Setting the ABDEN bit of the BAUDxCON register starts the auto-baud calibration sequence (Figure 22.4.2). While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the Start bit, the SPxBRGL begins counting up using the BRG counter clock as shown in Table 22-6. The fifth rising edge will occur on the RXx/DTx pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in the SPxBRGH:SPxBRGL register pair, the ABDEN bit is automatically cleared, and the RCxIF interrupt flag is set. A read operation on the RCxREG needs to be performed to clear the RCxIF interrupt. RCxREG content should be discarded. When calibrating for modes that do not use the SPxBRGH register the user can verify that the SPxBRGL register did not overflow by checking for 00h in the SPxBRGH register. The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 22-6. During ABD, both the SPxBRGH and SPxBRGL registers are used as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the SPxBRGH and SPxBRGL registers are clocked at FIGURE 22-6: Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 22.4.3 "Auto-Wake-up on Break"). 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible. 3: During the auto-baud process, the auto-baud counter starts counting at 1. Upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the SPxBRGH:SPxBRGL register pair. TABLE 22-6: BRG COUNTER CLOCK RATES BRG16 BRGH BRG Base Clock BRG ABD Clock 0 0 FOSC/64 FOSC/512 0 1 FOSC/16 FOSC/128 1 0 FOSC/16 FOSC/128 1 1 FOSC/4 FOSC/32 Note: During the ABD sequence, SPxBRGL and SPxBRGH registers are both used as a 16-bit counter, independent of BRG16 setting. AUTOMATIC BAUD RATE CALIBRATION XXXXh BRG Value 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. RXx/DTx pin 0000h 001Ch Start Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 Edge #5 Stop bit BRG Clock Auto Cleared Set by User ABDEN bit RCIDL RCxIF bit (Interrupt) Read RCxREG SPxBRGL XXh 1Ch SPxBRGH XXh 00h Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode. DS41458B-page 272 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 22.4.2 AUTO-BAUD OVERFLOW 22.4.3.1 During the course of automatic baud detection, the ABDOVF bit of the BAUDxCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPxBRGH:SPxBRGL register pair. After the ABDOVF has been set, the counter continues to count until the fifth rising edge is detected on the RXx/DTx pin. Upon detecting the fifth RXx/DTx edge, the hardware will set the RCxIF interrupt flag and clear the ABDEN bit of the BAUDxCON register. The RCxIF flag can be subsequently cleared by reading the RCxREG. The ABDOVF flag can be cleared by software directly. To terminate the auto-baud process before the RCxIF flag is set, clear the ABDEN bit then clear the ABDOVF bit. The ABDOVF bit will remain set if the ABDEN bit is not cleared first. 22.4.3 AUTO-WAKE-UP ON BREAK During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RXx/DTx line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDxCON register. Once set, the normal receive sequence on RXx/DTx is disabled, and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RXx/DTx line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) The EUSART module generates an RCxIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure 22-7), and asynchronously if the device is in Sleep mode (Figure 22-8). The interrupt condition is cleared by reading the RCxREG register. Special Considerations Break Character To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. Therefore, the initial character in the transmission must be all `0's. This must be 10 or more bit times, 13-bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices. Oscillator Startup Time Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS mode). The Sync Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. WUE Bit The wake-up event causes a receive interrupt by setting the RCxIF bit. The WUE bit is cleared by hardware by a rising edge on RXx/DTx. The interrupt condition is then cleared by software by reading the RCxREG register and discarding its contents. To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. The WUE bit is automatically cleared by the low-to-high transition on the RXx line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character. 2011 Microchip Technology Inc. Preliminary DS41458B-page 273 PIC16(L)F1526/27 FIGURE 22-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RXx/DTx Line RCxIF Note 1: Cleared due to User Read of RCxREG The EUSART remains in Idle while the WUE bit is set. FIGURE 22-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 OSC1 Auto Cleared Bit Set by User WUE bit RXx/DTx Line Note 1 RCxIF Sleep Command Executed Note 1: 2: Sleep Ends Cleared due to User Read of RCxREG If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set. DS41458B-page 274 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 22.4.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 `0' bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXxSTA register. The Break character transmission is then initiated by a write to the TXxREG. The value of data written to TXxREG will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). The TRMT bit of the TXxSTA register indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 22-9 for the timing of the Break character sequence. 22.4.4.1 Break and Sync Transmit Sequence The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master. 1. 2. 3. 4. 5. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to enable the Break sequence. Load the TXxREG with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXxREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. FIGURE 22-9: Write to TXxREG When the TXxREG becomes empty, as indicated by the TXxIF, the next data byte can be written to TXxREG. 22.4.5 RECEIVING A BREAK CHARACTER The Enhanced EUSART module can receive a Break character in two ways. The first method to detect a Break character uses the FERR bit of the RCxSTA register and the Received data as indicated by RCxREG. The Baud Rate Generator is assumed to have been initialized to the expected baud rate. A Break character has been received when; * RCxIF bit is set * FERR bit is set * RCxREG = 00h The second method uses the Auto-Wake-up feature described in Section 22.4.3 "Auto-Wake-up on Break". By enabling this feature, the EUSART will sample the next two transitions on RXx/DTx, cause an RCxIF interrupt, and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDxCON register before placing the EUSART in Sleep mode. SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TXx/CKx (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXxIF bit (Transmit interrupt Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB (send Break control bit) 2011 Microchip Technology Inc. SENDB Sampled Here Preliminary Auto Cleared DS41458B-page 275 PIC16(L)F1526/27 22.5 22.5.1.2 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The EUSART can operate as either a master or slave device. Start and Stop bits are not used in synchronous transmissions. 22.5.1 SYNCHRONOUS MASTER MODE The following bits are used to configure the EUSART for Synchronous Master operation: * * * * * SYNC = 1 CSRC = 1 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 Clock Polarity A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the CKTXP bit of the BAUDxCON register. Setting the CKTXP bit sets the clock Idle state as high. When the CKTXP bit is set, the data changes on the falling edge of each clock and is sampled on the rising edge of each clock. Clearing the CKTXP bit sets the Idle state as low. When the CKTXP bit is cleared, the data changes on the rising edge of each clock and is sampled on the falling edge of each clock. 22.5.1.3 Synchronous Master Transmission Data is transferred out of the device on the RXx/DTx pin. The RXx/DTx and TXx/CKx pin output drivers are automatically enabled when the EUSART is configured for synchronous master transmit operation. A transmission is initiated by writing a character to the TXxREG register. If the TSR still contains all or part of a previous character the new character data is held in the TXxREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXxREG. Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. Setting the SYNC bit of the TXxSTA register configures the device for synchronous operation. Setting the CSRC bit of the TXxSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCxSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCxSTA register enables the EUSART. If the RXx/DTx or TXx/CKx pins are shared with an analog peripheral the analog I/O functions must be disabled by clearing the corresponding ANSEL bits. Note: 22.5.1.4 The TSR register is not mapped in data memory, so it is not available to the user. Data Polarity The polarity of the transmit and receive data can be controlled with the DTRXP bit of the BAUDxCON register. The default state of this bit is `0' which selects high true transmit and receive data. Setting the DTRXP bit to `1' will invert the data resulting in low true transmit and receive data. The TRIS bits corresponding to the RXx/DTx and TXx/CKx pins should be set. 22.5.1.1 Master Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TXx/CKx line. The TXx/CKx pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. DS41458B-page 276 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 22.5.1.5 1. 2. 3. Synchronous Master Transmission Set-up: 4. Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 22.4 "EUSART Baud Rate Generator (BRG)"). Set the RXx/DTx and TXx/CKx TRIS controls to `1'. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Set the TRIS bits corresponding to the RXx/DTx and TXx/CKx I/O pins. 5. 6. 7. FIGURE 22-10: 8. 9. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit. If 9-bit transmission is desired, set the TX9 bit. If interrupts are desired, set the TXxIE, GIE and PEIE interrupt enable bits. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. Start transmission by loading data to the TXxREG register. SYNCHRONOUS TRANSMISSION RXx/DTx pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TXx/CKx pin (SCKP = 0) TXx/CKx pin (SCKP = 1) Write to TXxREG Reg Write Word 1 Write Word 2 TXxIF bit (Interrupt Flag) TRMT bit TXEN bit Note: `1' `1' Sync Master mode, SPxBRGL = 0, continuous transmission of two 8-bit words. FIGURE 22-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RXx/DTx pin bit 0 bit 1 bit 2 bit 6 bit 7 TXx/CKx pin Write to TXxREG reg TXxIF bit TRMT bit TXEN bit 2011 Microchip Technology Inc. Preliminary DS41458B-page 277 PIC16(L)F1526/27 TABLE 22-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUD1CON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 266 BAUD2CON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 266 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93 94 INTCON PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 97 PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 98 PIR4 CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF 97 RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 265 RC2STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 265 SP1BRGL EUSART1 Baud Rate Generator, Low Byte 267* SP1BRGH EUSART1 Baud Rate Generator, High Byte 267* SP2BRGL EUSART2 Baud Rate Generator, Low Byte 267* SP2BRGH EUSART2 Baud Rate Generator, High Byte 267* TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 TRISG -- -- -- TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 TX1REG TX1STA EUSART1 Transmit Register CSRC TX9 TXEN CSRC TX9 TXEN TX2REG TX2STA Legend: * SYNC SENDB SENDB 134 257* BRGH TRMT TX9D BRGH TRMT TX9D EUSART2 Transmit Register SYNC 134 264 257* 264 -- = unimplemented locations, read as `0'. Shaded bits are not used for synchronous master transmission. Page provides register information. DS41458B-page 278 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 22.5.1.6 Synchronous Master Reception Data is received at the RXx/DTx pin. The RXx/DTx pin output driver must be disabled by setting the corresponding TRIS bits when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCxSTA register) or the Continuous Receive Enable bit (CREN of the RCxSTA register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence. To initiate reception, set either SREN or CREN. Data is sampled at the RXx/DTx pin on the trailing edge of the TXx/CKx clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RCxIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCxREG. The RCxIF bit remains set as long as there are un-read characters in the receive FIFO. 22.5.1.7 Slave Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a slave receives the clock on the TXx/CKx line. The TXx/CKx pin output driver must be disabled by setting the associated TRIS bit when the device is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits. 22.5.1.8 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCxREG is read to access the FIFO. When this happens the OERR bit of the RCxSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCxREG. 2011 Microchip Technology Inc. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. 22.5.1.9 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set the EUSART will shift 9-bits into the RSR for each character received. The RX9D bit of the RCxSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCxREG. 22.5.1.10 Synchronous Master Reception Set-up: 1. Initialize the SPxBRGH, SPxBRGL register pair for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Set the RXx/DTx and TXx/CKx TRIS controls to `1'. 3. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Disable RXx/DTx and TXx/CKx output drivers by setting the corresponding TRIS bits. 4. Ensure bits CREN and SREN are clear. 5. If using interrupts, set the GIE and PEIE bits of the INTCON register and set RCxIE. 6. If 9-bit reception is desired, set bit RX9. 7. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 8. Interrupt flag bit RCxIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCxIE was set. 9. Read the RCxSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. Read the 8-bit received data by reading the RCxREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. Preliminary DS41458B-page 279 PIC16(L)F1526/27 FIGURE 22-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RXx/DTx pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TXx/CKx pin (SCKP = 0) TXx/CKx pin (SCKP = 1) Write to bit SREN SREN bit CREN bit `0' `0' RCxIF bit (Interrupt) Read RCxREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 22-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUD1CON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 266 BAUD2CON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 266 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93 PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 94 PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 97 PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 98 PIR4 CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF INTCON RC1REG RC1STA EUSART1 Receive Register SPEN RX9 SREN RC2REG RC2STA CREN ADDEN FERR OERR RX9D EUSART2 Receive Register SPEN RX9 SREN CREN ADDEN 97 260* 265 260* FERR OERR RX9D 265 SP1BRGL EUSART1 Baud Rate Generator, Low Byte 267* SP1BRGH EUSART1 Baud Rate Generator, High Byte 267* SP2BRGL EUSART2 Baud Rate Generator, Low Byte 267* SP2BRGH EUSART2 Baud Rate Generator, High Byte TX1STA TX2STA Legend: * 267* CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 264 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 264 -- = unimplemented locations, read as `0'. Shaded bits are not used for synchronous master reception. Page provides register information. DS41458B-page 280 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 22.5.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for Synchronous slave operation: * * * * * SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 If two words are written to the TXxREG and then the SLEEP instruction is executed, the following will occur: 1. 2. 3. 4. Setting the SYNC bit of the TXxSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXxSTA register configures the device as a slave. Clearing the SREN and CREN bits of the RCxSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCxSTA register enables the EUSART. If the RXx/DTx or TXx/CKx pins are shared with an analog peripheral the analog I/O functions must be disabled by clearing the corresponding ANSEL bits. 5. 22.5.2.2 1. RXx/DTx and TXx/CKx pin output drivers must be disabled by setting the corresponding TRIS bits. 2. 22.5.2.1 3. 4. EUSART Synchronous Slave Transmit The operation of the Synchronous Master and Slave Section 22.5.1.3 modes are identical (see "Synchronous Master Transmission"), except in the case of the Sleep mode. 5. 6. 7. 8. 2011 Microchip Technology Inc. The first character will immediately transfer to the TSR register and transmit. The second word will remain in TXxREG register. The TXxIF bit will not be set. After the first character has been shifted out of TSR, the TXxREG register will transfer the second character to the TSR and the TXxIF bit will now be set. If the PEIE and TXxIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine. Preliminary Synchronous Slave Transmission Set-up: Set the SYNC and SPEN bits and clear the CSRC bit. Set the RXx/DTx and TXx/CKx TRIS controls to `1'. Clear the CREN and SREN bits. If using interrupts, ensure that the GIE and PEIE bits of the INTCON register are set and set the TXxIE bit. If 9-bit transmission is desired, set the TX9 bit. Enable transmission by setting the TXEN bit. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. Start transmission by writing the Least Significant 8 bits to the TXxREG register. DS41458B-page 281 PIC16(L)F1526/27 TABLE 22-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUD1CON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 266 BAUD2CON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 266 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93 94 INTCON PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 97 PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 98 PIR4 CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF 97 RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 265 RC2STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 265 SP1BRGL EUSART1 Baud Rate Generator, Low Byte 267* SP1BRGH EUSART1 Baud Rate Generator, High Byte 267* SP2BRGL EUSART2 Baud Rate Generator, Low Byte 267* SP2BRGH EUSART2 Baud Rate Generator, High Byte TRISC TRISC7 TRISC6 TRISC5 CSRC TX9 TXEN TX1REG TX1STA Legend: * TRISC3 TRISC2 267* TRISC1 TRISC0 TRMT TX9D EUSART1 Transmit Register TX2REG TX2STA TRISC4 SYNC SENDB 257* BRGH EUSART2 Transmit Register CSRC TX9 TXEN SYNC SENDB 134 264 257* BRGH TRMT TX9D 264 -- = unimplemented locations, read as `0'. Shaded bits are not used for synchronous slave transmission. Page provides register information. DS41458B-page 282 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 22.5.2.3 EUSART Synchronous Slave Reception 22.5.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 22.5.1.6 "Synchronous Master Reception"), with the following exceptions: * Sleep * CREN bit is always set, therefore the receiver is never Idle * SREN bit, which is a "don't care" in Slave mode 1. 2. 3. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCxREG register. If the RCxIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector. 4. 5. 6. 7. 8. 9. Synchronous Slave Reception Set-up: Set the SYNC and SPEN bits and clear the CSRC bit. Set the RXx/DTx and TXx/CKx TRIS controls to `1'. If using interrupts, ensure that the GIE and PEIE bits of the INTCON register are set and set the RCxIE bit. If 9-bit reception is desired, set the RX9 bit. Set the CREN bit to enable reception. The RCxIF bit will be set when reception is complete. An interrupt will be generated if the RCxIE bit was set. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCxSTA register. Retrieve the 8 Least Significant bits from the receive FIFO by reading the RCxREG register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 22-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUD1CON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 266 BAUD2CON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 266 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 94 PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 97 PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 98 PIR4 CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF 97 SPEN RX9 SREN FERR OERR RX9D SPEN RX9 SREN FERR OERR RX9D INTCON PIE1 RC1REG RC1STA EUSART1 Receive Register RC2REG RC2STA CREN ADDEN 260* EUSART2 Receive Register CREN ADDEN 265 260* 265 SP1BRGL EUSART1 Baud Rate Generator, Low Byte 267* SP1BRGH EUSART1 Baud Rate Generator, High Byte 267* SP2BRGL EUSART2 Baud Rate Generator, Low Byte 267* SP2BRGH EUSART2 Baud Rate Generator, High Byte 267* TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 264 TX2STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 264 Legend: * -- = unimplemented locations, read as `0'. Shaded bits are not used for synchronous slave reception. Page provides register information. 2011 Microchip Technology Inc. Preliminary DS41458B-page 283 PIC16(L)F1526/27 NOTES: DS41458B-page 284 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 23.0 IN-CIRCUIT SERIAL PROGRAMMINGTM (ICSPTM) ICSPTM programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSPTM programming: * ICSPCLK * ICSPDAT * MCLR/VPP * VDD * VSS In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSPTM refer to the "PIC16F/LF151X/152X Memory Programming Specification" (DS41422). 23.1 High-Voltage Programming Entry Mode The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. Some programmers produce VPP greater than VIHH (9.0V), an external circuit is required to limit the VPP voltage. See Figure 23-1 for example circuit. FIGURE 23-1: VPP LIMITER EXAMPLE CIRCUIT RJ11-6PIN 6 5 4 3 2 1 1 VPP 2 VDD 3 VSS 4 ICSP_DATA 5 ICSP_CLOCK 6 NC RJ11-6PIN (R) To MPLAB ICD 2 R1 To Target Board 270 Ohm LM431BCMX 1 2 A K 3 A U1 6 A NC 4 7 A NC 5 R2 VREF 8 10k 1% Note: R3 24k 1% The MPLAB(R) ICD 2 produces a VPP voltage greater than the maximum VPP specification of the PIC16(L)F1526/27. 2011 Microchip Technology Inc. Preliminary DS41458B-page 285 PIC16(L)F1526/27 23.2 FIGURE 23-2: Low-Voltage Programming Entry Mode The Low-Voltage Programming Entry mode allows the PIC16(L)F1526/27 devices to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Word 2 is set to `1', the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to `0'. VDD Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2. ICD RJ-11 STYLE CONNECTOR INTERFACE ICSPDAT NC 2 4 6 ICSPCLK 1 3 5 VPP/MCLR MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. VSS Pin Description* Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. 1 = VPP/MCLR If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See Section 6.3 "Low-Power Brown-out Reset (LPBOR)" for more information. 4 = ICSPDAT 2 = VDD Target 3 = VSS (ground) 5 = ICSPCLK 6 = No Connect The LVP bit can only be reprogrammed to `0' by using the High-Voltage Programming mode. 23.3 Target PC Board Bottom Side Another connector often found in use with the PICkitTM programmers is a standard 6-pin header with 0.1 inch spacing. Refer to Figure 23-3. Common Programming Interfaces Connection to a target device is typically done through an ICSPTM header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6 pin, 6 connector) configuration. See Figure 23-2. FIGURE 23-3: PICkitTM STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 2 3 4 5 6 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect * DS41458B-page 286 The 6-pin header (0.100" spacing) accepts 0.025" square pins. Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 23-4 for more information. FIGURE 23-4: TYPICAL CONNECTION FOR ICSPTM PROGRAMMING External Programming Signals Device to be Programmed VDD VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required). 2011 Microchip Technology Inc. Preliminary DS41458B-page 287 PIC16(L)F1526/27 NOTES: DS41458B-page 288 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 24.0 INSTRUCTION SET SUMMARY 24.1 Read-Modify-Write Operations * Byte Oriented * Bit Oriented * Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register. The literal and control category contains the most varied instruction word format. TABLE 24-1: Each PIC16 instruction is a 14-bit word containing the operation code (opcode) and all required operands. The opcodes are broken into three broad categories. Table 24-3 lists the instructions recognized by the MPASMTM assembler. All instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: * Subroutine takes two cycles (CALL, CALLW) * Returns from interrupts or subroutines take two cycles (RETURN, RETLW, RETFIE) * Program branching takes two cycles (GOTO, BRA, BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) * One additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. One instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution rate of 1 MHz. All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit. OPCODE FIELD DESCRIPTIONS Field f Description Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. n FSR or INDF number. (0-1) mm Pre-post increment-decrement mode selection TABLE 24-2: ABBREVIATION DESCRIPTIONS Field PC Program Counter TO Time-out bit C DC Z PD 2011 Microchip Technology Inc. Description Preliminary Carry bit Digit carry bit Zero bit Power-down bit DS41458B-page 289 PIC16(L)F1526/27 FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal) k = 11-bit immediate value MOVLP instruction only 13 OPCODE 7 6 0 k (literal) k = 7-bit immediate value MOVLB instruction only 13 OPCODE 5 4 0 k (literal) k = 5-bit immediate value BRA instruction only 13 OPCODE 9 8 0 k (literal) k = 9-bit immediate value FSR Offset instructions 13 OPCODE 7 6 n 5 0 k (literal) n = appropriate FSR k = 6-bit immediate value FSR Increment instructions 13 OPCODE 3 2 1 0 n m (mode) n = appropriate FSR m = 2-bit mode value OPCODE only 13 0 OPCODE DS41458B-page 290 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 TABLE 24-3: INSTRUCTION SET 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f Clear W Complement f Decrement f Increment f Inclusive OR W with f Move f Move W to f Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Subtract with Borrow W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 11 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 0111 1101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffff ffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z C, DC, Z Z C, Z C, Z C, Z Z Z Z Z Z Z Z C C C, DC, Z C, DC, Z Z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BYTE ORIENTED SKIP OPERATIONS DECFSZ INCFSZ f, d f, d Decrement f, Skip if 0 Increment f, Skip if 0 BCF BSF f, b f, b Bit Clear f Bit Set f 1(2) 1(2) 00 00 1, 2 1, 2 1011 dfff ffff 1111 dfff ffff BIT-ORIENTED FILE REGISTER OPERATIONS 1 1 01 01 00bb bfff ffff 01bb bfff ffff 2 2 1, 2 1, 2 BIT-ORIENTED SKIP OPERATIONS BTFSC BTFSS f, b f, b Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 (2) 1 (2) 01 01 10bb bfff ffff 11bb bfff ffff 1 1 1 1 1 1 1 1 11 11 11 00 11 11 11 11 1110 1001 1000 0000 0001 0000 1100 1010 LITERAL OPERATIONS ADDLW ANDLW IORLW MOVLB MOVLP MOVLW SUBLW XORLW k k k k k k k k Add literal and W AND literal with W Inclusive OR literal with W Move literal to BSR Move literal to PCLATH Move literal to W Subtract W from literal Exclusive OR literal with W kkkk kkkk kkkk 001k 1kkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z Z Z C, DC, Z Z Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. 2011 Microchip Technology Inc. Preliminary DS41458B-page 291 PIC16(L)F1526/27 TABLE 24-3: INSTRUCTION SET (CONTINUED) Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS 2 2 2 2 2 2 2 2 BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k - k - k k k - Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine CLRWDT NOP OPTION RESET SLEEP TRIS - - - - - f Clear Watchdog Timer No Operation Load OPTION_REG register with W Software device Reset Go into Standby mode Load TRIS register with W ADDFSR MOVIW n, k n mm MOVWI k[n] n mm Add Literal k to FSRn Move Indirect FSRn to W with pre/post inc/dec modifier, mm Move INDFn to W, Indexed Indirect. Move W to Indirect FSRn with pre/post inc/dec modifier, mm Move W to INDFn, Indexed Indirect. 11 00 10 00 10 00 11 00 001k 0000 0kkk 0000 1kkk 0000 0100 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 1011 kkkk 1010 kkkk 1001 kkkk 1000 00 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0110 0000 0110 0000 0110 0110 0100 TO, PD 0000 0010 0001 0011 TO, PD 0fff INHERENT OPERATIONS 1 1 1 1 1 1 C-COMPILER OPTIMIZED k[n] 1 1 11 00 0001 0nkk kkkk 0000 0001 0nmm Z 2, 3 1 1 11 00 1111 0nkk kkkk Z 0000 0001 1nmm 2 2, 3 1 11 1111 1nkk kkkk 2 Note 1:If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. 3: See Table in the MOVIW and MOVWI instruction descriptions. DS41458B-page 292 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 24.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32 k 31 n [ 0, 1] Operands: 0 k 255 Operation: FSR(n) + k FSR(n) Status Affected: None Description: The signed 6-bit literal `k' is added to the contents of the FSRnH:FSRnL register pair. k Operation: (W) .AND. (k) (W) Status Affected: Z Description: The contents of W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. FSRn is limited to the range 0000h FFFFh. Moving beyond these bounds will cause the FSR to wrap-around. ADDLW Add literal and W ANDWF AND W with f Syntax: [ label ] ADDLW Syntax: [ label ] ANDWF Operands: 0 f 127 d 0,1 Operation: (W) .AND. (f) (destination) Status Affected: Z Description: AND the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. ASRF Arithmetic Right Shift k Operands: 0 k 255 Operation: (W) + k (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal `k' and the result is placed in the W register. f,d ADDWF Add W and f Syntax: [ label ] ADDWF Syntax: [ label ] ASRF Operands: 0 f 127 d 0,1 Operands: 0 f 127 d [0,1] Operation: (W) + (f) (destination) Operation: (f<7>) dest<7> (f<7:1>) dest<6:0>, (f<0>) C, f,d Status Affected: C, DC, Z Description: Add the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. ADDWFC ADD W and CARRY bit to f Syntax: [ label ] ADDWFC Operands: 0 f 127 d [0,1] Status Affected: C, Z Description: The contents of register `f' are shifted one bit to the right through the Carry flag. The MSb remains unchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. register f C f {,d} Operation: (W) + (f) + (C) dest Status Affected: C, DC, Z Description: Add W, the Carry flag and data memory location `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location `f'. 2011 Microchip Technology Inc. f {,d} Preliminary DS41458B-page 293 PIC16(L)F1526/27 BCF Bit Clear f Syntax: [ label ] BCF f,b BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operands: Operation: 0 (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Description: Bit `b' in register `f' is cleared. Description: If bit `b' in register `f' is `1', the next instruction is executed. If bit `b', in register `f', is `0', the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. BRA Relative Branch BTFSS Bit Test f, Skip if Set Syntax: [ label ] BRA label [ label ] BRA $+k Syntax: [ label ] BTFSS f,b Operands: Operands: -256 label - PC + 1 255 -256 k 255 0 f 127 0b<7 Operation: skip if (f<b>) = 1 Operation: (PC) + 1 + k PC Status Affected: None Status Affected: None Description: Description: Add the signed 9-bit literal `k' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + k. This instruction is a two-cycle instruction. This branch has a limited range. If bit `b' in register `f' is `0', the next instruction is executed. If bit `b' is `1', then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. BRW Relative Branch with W Syntax: [ label ] BRW Operands: None Operation: (PC) + (W) PC Status Affected: None Description: Add the contents of W (unsigned) to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + (W). This instruction is a two-cycle instruction. BSF Bit Set f Syntax: [ label ] BSF Operands: 0 f 127 0b7 Operation: 1 (f<b>) Status Affected: None Description: Bit `b' in register `f' is set. DS41458B-page 294 f,b Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 k 2047 Operands: None Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<6:3>) PC<14:11> Operation: Status Affected: None 00h WDT 0 WDT prescaler, 1 TO 1 PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. CALLW Subroutine Call With W COMF Complement f Syntax: [ label ] CALLW Syntax: [ label ] COMF Operands: None Operands: Operation: (PC) +1 TOS, (W) PC<7:0>, (PCLATH<6:0>) PC<14:8> 0 f 127 d [0,1] Operation: (f) (destination) Status Affected: Z Description: The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. DECF Decrement f Syntax: [ label ] DECF f,d Status Affected: None Description: Subroutine call with W. First, the return address (PC + 1) is pushed onto the return stack. Then, the contents of W is loaded into PC<7:0>, and the contents of PCLATH into PC<14:8>. CALLW is a two-cycle instruction. CLRF Clear f Syntax: [ label ] CLRF f f,d Operands: 0 f 127 Operands: Operation: 00h (f) 1Z 0 f 127 d [0,1] Operation: (f) - 1 (destination) Status Affected: Z Status Affected: Z Description: The contents of register `f' are cleared and the Z bit is set. Description: Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h (W) 1Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. 2011 Microchip Technology Inc. Preliminary DS41458B-page 295 PIC16(L)F1526/27 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', then a NOP is executed instead, making it a 2-cycle instruction. Description: The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', a NOP is executed instead, making it a 2-cycle instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] Syntax: [ label ] GOTO k INCFSZ f,d IORLW k Operands: 0 k 2047 Operands: 0 k 255 Operation: k PC<10:0> PCLATH<6:3> PC<14:11> Operation: (W) .OR. k (W) Status Affected: Z Status Affected: None Description: Description: GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction. The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) + 1 (destination) Operation: (W) .OR. (f) (destination) Status Affected: Z Status Affected: Z Description: The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. Description: Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. DS41458B-page 296 INCF f,d Preliminary IORWF f,d 2011 Microchip Technology Inc. PIC16(L)F1526/27 LSLF Logical Left Shift f {,d} MOVF Move f Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> Operation: (f) (dest) Status Affected: C, Z Description: The contents of register `f' are shifted one bit to the left through the Carry flag. A `0' is shifted into the LSb. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. C register f 0 Status Affected: Z Description: The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. Words: 1 Cycles: 1 Example: Logical Right Shift Syntax: [ label ] LSLF Operands: 0 f 127 d [0,1] Operation: 0 dest<7> (f<7:1>) dest<6:0>, (f<0>) C, Status Affected: C, Z Description: The contents of register `f' are shifted one bit to the right through the Carry flag. A `0' is shifted into the MSb. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. 2011 Microchip Technology Inc. f {,d} register f MOVF FSR, 0 After Instruction W = value in FSR register Z = 1 LSRF 0 MOVF f,d C Preliminary DS41458B-page 297 PIC16(L)F1526/27 MOVIW Move INDFn to W Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] Operands: n [0,1] mm [00,01, 10, 11] -32 k 31 Operation: INDFn W Effective address is determined by * FSR + 1 (preincrement) * FSR - 1 (predecrement) * FSR + k (relative offset) After the Move, the FSR value will be either: * FSR + 1 (all increments) * FSR - 1 (all decrements) * Unchanged Status Affected: MOVLP Move literal to PCLATH Syntax: [ label ] MOVLP k Operands: 0 k 127 Operation: k PCLATH Status Affected: None Description: The seven-bit literal `k' is loaded into the PCLATH register. MOVLW Move literal to W Syntax: [ label ] Operands: 0 k 255 Operation: k (W) Status Affected: None Description: The eight-bit literal `k' is loaded into W register. The "don't cares" will assemble as `0's. Words: 1 1 Z Mode Syntax mm Cycles: Preincrement ++FSRn 00 Example: Predecrement --FSRn 01 Postincrement FSRn++ 10 Postdecrement FSRn-- 11 Description: Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn. Syntax: [ label ] MOVLB k Operands: 0 k 15 Operation: k BSR Status Affected: None Description: The five-bit literal `k' is loaded into the Bank Select Register (BSR). DS41458B-page 298 0x5A MOVWF Move W to f Syntax: [ label ] MOVWF Operands: 0 f 127 Operation: (W) (f) 0x5A f Status Affected: None Description: Move data from W register to register `f'. Words: 1 Cycles: 1 Example: FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap-around. Move literal to BSR MOVLW After Instruction W = This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. MOVLB MOVLW k Preliminary MOVWF OPTION_REG Before Instruction OPTION_REG = 0xFF W = 0x4F After Instruction OPTION_REG = 0x4F W = 0x4F 2011 Microchip Technology Inc. PIC16(L)F1526/27 MOVWI Move W to INDFn Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] Operands: Operation: Status Affected: n [0,1] mm [00,01, 10, 11] -32 k 31 W INDFn Effective address is determined by * FSR + 1 (preincrement) * FSR - 1 (predecrement) * FSR + k (relative offset) After the Move, the FSR value will be either: * FSR + 1 (all increments) * FSR - 1 (all decrements) Unchanged None No Operation Syntax: [ label ] Operands: None Operation: No operation Status Affected: None Description: No operation. Words: 1 Cycles: 1 Example: OPTION Load OPTION_REG Register with W Syntax: [ label ] OPTION Operands: None Operation: (W) OPTION_REG Status Affected: None Description: Move data from W register to OPTION_REG register. 1 Syntax Preincrement ++FSRn 00 Predecrement --FSRn 01 Postincrement FSRn++ 10 Words: Postdecrement FSRn-- 11 Cycles: 1 Example: OPTION Before Instruction OPTION_REG = 0xFF W = 0x4F After Instruction OPTION_REG = 0x4F W = 0x4F This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn. FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap-around. The increment/decrement operation on FSRn WILL NOT affect any Status bits. 2011 Microchip Technology Inc. NOP NOP Mode Description: mm NOP RESET Software Reset Syntax: [ label ] RESET Operands: None Operation: Execute a device Reset. Resets the nRI flag of the PCON register. Status Affected: None Description: This instruction provides a way to execute a hardware Reset by software. Preliminary DS41458B-page 299 PIC16(L)F1526/27 RETFIE Return from Interrupt Syntax: [ label ] RETURN RETFIE Return from Subroutine Syntax: [ label ] None RETURN Operands: None Operands: Operation: TOS PC, 1 GIE Operation: TOS PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = GIE = TOS 1 Return with literal in W RLF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: Operation: k (W); TOS PC 0 f 127 d [ 0, 1] Operation: See description below Status Affected: None Status Affected: C Description: The W register is loaded with the eight bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. Description: The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'. Words: 1 Cycles: 2 RETLW Example: TABLE RETLW k C CALL TABLE;W contains table ;offset value * ;W now has table value * * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table Before Instruction W = After Instruction W = DS41458B-page 300 RLF Words: 1 Cycles: 1 Example: RLF f,d Register f REG1,0 Before Instruction REG1 C After Instruction REG1 W C = = 1110 0110 0 = = = 1110 0110 1100 1100 1 0x07 value of k8 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 SUBLW Subtract W from literal Syntax: [ label ] RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. The W register is subtracted (2's complement method) from the eight-bit literal `k'. The result is placed in the W register. RRF f,d C SUBLW k Operands: 0 k 255 Operation: k - (W) W) Register f C=0 Wk C=1 Wk DC = 0 W<3:0> k<3:0> DC = 1 W<3:0> k<3:0> SLEEP Enter Sleep mode SUBWF Subtract W from f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: (f) - (W) destination) Status Affected: C, DC, Z Description: Subtract (2's complement method) W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f. SLEEP Operands: None Operation: 00h WDT, 0 WDT prescaler, 1 TO, 0 PD Status Affected: TO, PD Description: The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. 2011 Microchip Technology Inc. SUBWF f,d C=0 Wf C=1 Wf DC = 0 W<3:0> f<3:0> DC = 1 W<3:0> f<3:0> SUBWFB Subtract W from f with Borrow Syntax: SUBWFB Operands: 0 f 127 d [0,1] Operation: (f) - (W) - (B) dest f {,d} Status Affected: C, DC, Z Description: Subtract W and the BORROW flag (CARRY) from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. Preliminary DS41458B-page 301 PIC16(L)F1526/27 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: SWAPF f,d (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register. Status Affected: None Description: The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in register `f'. TRIS Load TRIS Register with W XORWF Exclusive OR W with f Syntax: [ label ] TRIS f Syntax: [ label ] Operands: 5f7 Operands: Operation: (W) TRIS register `f' 0 f 127 d [0,1] Status Affected: None Operation: (W) .XOR. (f) destination) Status Affected: Z Description: Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. Description: DS41458B-page 302 Move data from W register to TRIS register. When `f' = 5, TRISA is loaded. When `f' = 6, TRISB is loaded. When `f' = 7, TRISC is loaded. Preliminary XORWF f,d 2011 Microchip Technology Inc. PIC16(L)F1526/27 25.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings() Ambient temperature under bias....................................................................................................... -40C to +125C Storage temperature ........................................................................................................................ -65C to +150C Voltage on VDD with respect to VSS, PIC16F1526/7 .......................................................................... -0.3V to +6.5V Voltage on VDD with respect to VSS, PIC16LF1526/7 ........................................................................ -0.3V to +4.0V Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) ............................................................................................................................... 800 mW Maximum current out of VSS pin, -40C TA +85C for industrial............................................................... 425 mA Maximum current out of VSS pin, -40C TA +125C for extended ............................................................ 175 mA Maximum current into VDD pin, -40C TA +85C for industrial.................................................................. 425 mA Maximum current into VDD pin, -40C TA +125C for extended ............................................................... 175 mA Clamp current, IK (VPIN < 0 or VPIN > VDD) 20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL). NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. 2011 Microchip Technology Inc. Preliminary DS41458B-page 303 PIC16(L)F1526/27 PIC16F1526/7 VOLTAGE FREQUENCY GRAPH, -40C TA +125C FIGURE 25-1: VDD (V) 5.5 2.5 2.3 0 4 10 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 25-1 for each Oscillator mode's supported frequencies. PIC16LF1526/7 VOLTAGE FREQUENCY GRAPH, -40C TA +125C VDD (V) FIGURE 25-2: 3.6 2.5 1.8 0 4 10 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 25-1 for each Oscillator mode's supported frequencies. DS41458B-page 304 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 25.1 DC Characteristics: PIC16(L)F1526/27-I/E (Industrial, Extended) PIC16LF1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended PIC16F1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param. No. D001 Sym. VDD Characteristic VDR Typ Max. Units Conditions PIC16LF1526/7 1.8 2.5 -- -- 3.6 3.6 V V FOSC 16 MHz: FOSC 20 MHz PIC16F1526/7 2.3 2.5 -- -- 5.5 5.5 V V FOSC 16 MHz: FOSC 20 MHz Supply Voltage D001 D002* Min. RAM Data Retention Voltage(1) D002* PIC16LF1526/7 1.5 -- -- V Device in Sleep mode PIC16F1526/7 1.7 -- -- V Device in Sleep mode -- 1.6 -- V VPOR* Power-on Reset Release Voltage VPORR* Power-on Reset Rearm Voltage PIC16LF1526/7 -- 0.8 -- V Device in Sleep mode PIC16F1526/7 -- 1.7 -- V Device in Sleep mode D003 VADFVR Fixed Voltage Reference Voltage for ADC, Initial Accuracy -7 -8 -7 -8 -7 -8 6 6 6 6 6 6 % 1.024V, VDD 2.5V, 85C (NOTE 2) 1.024V, VDD 2.5V, 125C (NOTE 2) 2.048V, VDD 2.5V, 85C 2.048V, VDD 2.5V, 125C 4.096V, VDD 4.75V, 85C 4.096V, VDD 4.75V, 125C D003A VCDAFVR Fixed Voltage Reference Voltage for Comparator and DAC, Initial Accuracy -11 -11 -11 -11 -11 -11 7 7 7 7 7 7 % 1.024V, VDD 2.5V, 85C 1.024V, VDD 2.5V, 125C 2.048V, VDD 2.5V, 85C 2.048V, VDD 2.5V, 125C 4.096V, VDD 4.75V, 85C 4.096V, VDD 4.75V, 125C D004* SVDD VDD Rise Rate to ensure internal Power-on Reset signal 0.05 -- V/ms -- See Section 6.1 "Power-on Reset (POR)" for details. * Note These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: For proper operation, the minimum value of the ADC positive voltage reference must be 1.8V or greater. When selecting the FVR or the VREF+ pin as the source of the ADC positive voltage reference, be aware that the voltage must be 1.8V or greater. 2011 Microchip Technology Inc. Preliminary DS41458B-page 305 PIC16(L)F1526/27 FIGURE 25-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(2) Note 1: 2: 3: DS41458B-page 306 TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 25.2 DC Characteristics: PIC16(L)F1526/27-I/E (Industrial, Extended) PIC16LF1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended PIC16F1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Characteristics Conditions Min. Typ Max. Units Note VDD Supply Current (IDD)(1, 2) D010 D010 D011 D011 D012 D012 D014 D014 D015 D015 -- 8.0 -- A 1.8 -- 12.0 -- A 3.0 -- 11 -- A 2.3 -- 13 -- A 3.0 -- 14 -- A 5.0 -- 60 -- A 1.8 -- 110 -- A 3.0 -- 92 -- A 2.3 -- 135 -- A 3.0 -- 170 -- A 5.0 -- 145 -- A 1.8 -- 260 -- A 3.0 -- 190 -- A 2.3 -- 305 -- A 3.0 -- 365 -- A 5.0 -- 118 -- A 1.8 -- 210 -- A 3.0 -- 156 -- A 2.3 -- 260 -- A 3.0 -- 330 -- A 5.0 -- 2.0 -- A 1.8 -- 4.0 -- A 3.0 -- 18 -- A 2.3 -- 24 -- A 3.0 -- 25 -- A 5.0 FOSC = 32 kHz LP Oscillator mode FOSC = 32 kHz LP Oscillator mode FOSC = 1 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 4 MHz EC Oscillator mode, Medium-power mode FOSC = 4 MHz EC Oscillator mode Medium-power mode FOSC = 31 kHz LFINTOSC mode FOSC = 31 kHz LFINTOSC mode * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k 2011 Microchip Technology Inc. Preliminary DS41458B-page 307 PIC16(L)F1526/27 25.2 DC Characteristics: PIC16(L)F1526/27-I/E (Industrial, Extended) (Continued) PIC16LF1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended PIC16F1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Characteristics Conditions Min. Typ Max. Units VDD Note Supply Current (IDD)(1, 2) D016 D016 D017* D017* D018 D018 -- 110 -- A 1.8 -- 150 -- A 3.0 -- 150 -- A 2.3 -- 210 -- A 3.0 -- 335 -- A 5.0 -- 0.25 -- mA 1.8 -- 0.45 -- mA 3.0 -- 0.35 -- mA 2.3 -- 0.69 -- mA 3.0 -- 0.75 -- mA 5.0 -- 0.47 -- mA 1.8 -- 0.84 -- mA 3.0 -- 0.70 -- mA 2.3 -- 1.00 -- mA 3.0 FOSC = 500 kHz HFINTOSC mode FOSC = 500 kHz HFINTOSC mode FOSC = 8 MHz HFINTOSC mode FOSC = 8 MHz HFINTOSC mode FOSC = 16 MHz HFINTOSC mode FOSC = 16 MHz HFINTOSC mode -- 1.17 -- mA 5.0 D019A -- 1.15 -- mA 3.0 FOSC = 20 MHz ECH mode D019A -- 1.15 -- mA 3.0 -- 1.3 -- mA 5.0 FOSC = 20 MHz ECH mode -- 8 -- A 1.8 -- 10 -- A 3.0 -- 10 -- A 3.0 -- 11 -- A 5.0 -- 25 -- A 1.8 -- 35 -- A 3.0 -- 35 -- A 3.0 -- 40 -- A 5.0 D019B D019B D019C D019C FOSC = 32 kHz ECL mode FOSC = 32 kHz ECL mode FOSC = 500 kHz ECL mode FOSC = 500 kHz ECL mode * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k DS41458B-page 308 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 25.2 DC Characteristics: PIC16(L)F1526/27-I/E (Industrial, Extended) (Continued) PIC16LF1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended PIC16F1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Characteristics Conditions Min. Typ Max. Units VDD Note Supply Current (IDD)(1, 2) D020 D020 D021 D021 -- 1.0 -- mA 3.0 -- 1.2 -- mA 3.6 -- 1.4 -- mA 3.0 -- 1.7 -- mA 5.0 -- 300 -- A 1.8 -- 500 -- A 3.0 -- 165 -- A 2.3 -- 280 -- A 3.0 -- 350 -- A 5.0 FOSC = 20 MHz HS Oscillator mode FOSC = 20 MHz HS Oscillator mode FOSC = 4 MHz EXTRC mode (Note 3) FOSC = 4 MHz EXTRC mode (Note 3) * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k 2011 Microchip Technology Inc. Preliminary DS41458B-page 309 PIC16(L)F1526/27 25.3 DC Characteristics: PIC16(L)F1526/27-I/E (Power-Down) PIC16LF1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended PIC16F1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Characteristics Power-down Base Current Min. Conditions Max. +85C Max. +125C Units 20 -- -- nA 1.8 Typ VDD Note (IPD)(2) D022 -- -- 30 -- -- nA 3.0 D022 -- 300 -- -- nA 3.0 -- 470 -- -- nA 5.0 WDT, BOR, FVR, and SOSC disabled, all peripherals inactive, low-power regulator active -- 300 -- -- nA 1.8 LPWDT Current (Note 1) -- 750 -- -- nA 3.0 -- 500 -- -- nA 2.3 -- 770 -- -- nA 3.0 D023 D023 D023A D023A -- 850 -- -- nA 5.0 -- 8.5 -- -- A 1.8 -- 8.5 -- -- A 3.0 -- 18 -- -- A 2.3 -- 18.5 -- -- A 3.0 5.0 WDT, BOR, FVR, and SOSC disabled, all peripherals inactive LPWDT Current (Note 1) FVR current (Note 1) FVR current (Note 1) -- 19 -- -- A D024 -- 8.0 -- -- A 3.0 BOR Current (Note 1) D024 -- 7 -- -- A 3.0 BOR Current (Note 1) -- 9 -- -- A 5.0 D024A -- 300 -- -- nA 3.0 LPBOR Current D024A -- 300 -- -- nA 3.0 LPBOR Current -- 450 -- -- nA 5.0 D025 -- 0.6 -- -- A 1.8 -- 1.8 -- -- A 3.0 -- 0.7 -- -- A 2.3 -- 3 -- -- A 3.0 -- 6 -- -- A 5.0 -- 0.1 -- -- A 1.8 -- 0.1 -- -- A 3.0 -- 160 -- -- nA 2.3 -- 400 -- -- nA 3.0 -- 500 -- -- nA 5.0 D025 D026 D026 * Note 1: 2: 3: SOSC Current (Note 1) SOSC Current (Note 1) A/D Current (Note 1, Note 3), no conversion in progress A/D Current (Note 1, Note 3), no conversion in progress These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. A/D oscillator source is FRC. DS41458B-page 310 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 25.3 DC Characteristics: PIC16(L)F1526/27-I/E (Power-Down) (Continued) PIC16LF1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended PIC16F1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Characteristics Min. Power-down Base Current (IPD) D026A* D026A* * Note 1: 2: 3: Typ Conditions Max. +85C Max. +125C Units VDD Note (2) -- 250 -- -- A 1.8 -- 250 -- -- A 3.0 -- 280 -- -- A 2.3 -- 280 -- -- A 3.0 -- 280 -- -- A 5.0 A/D Current (Note 1, Note 3), conversion in progress A/D Current (Note 1, Note 3), conversion in progress These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. A/D oscillator source is FRC. 2011 Microchip Technology Inc. Preliminary DS41458B-page 311 PIC16(L)F1526/27 25.4 DC Characteristics: PIC16(L)F1526/27-I/E DC CHARACTERISTICS Param No. Sym. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions Input Low Voltage I/O PORT: D030 -- -- 0.8 V 4.5V VDD 5.5V -- -- 0.15 VDD V 1.8V VDD 4.5V with Schmitt Trigger buffer -- -- 0.2 VDD V 2.0V VDD 5.5V with I2CTM levels -- -- 0.3 VDD V with SMBus levels with TTL buffer D030A D031 D032 D033 VIH -- -- 0.8 V MCLR, OSC1 (RC mode)(1) -- -- 0.2 VDD V OSC1 (HS mode) -- -- 0.3 VDD V -- -- Input High Voltage I/O ports: D040 2.0 -- -- V 4.5V VDD 5.5V 0.25 VDD + 0.8 -- -- V 1.8V VDD 4.5V with Schmitt Trigger buffer 0.8 VDD -- -- V 2.0V VDD 5.5V with I2CTM levels 0.7 VDD -- -- V with TTL buffer D040A D041 with SMBus levels D042 2.7V VDD 5.5V MCLR 2.1 -- -- V 0.8 VDD -- -- V 2.7V VDD 5.5V D043A OSC1 (HS mode) 0.7 VDD -- -- V D043B OSC1 (RC mode) 0.9 VDD -- -- V (Note 1) nA IIL Input Leakage Current(2) D060 I/O ports -- 5 125 5 1000 nA VSS VPIN VDD, Pin at highimpedance at 85C 125C D061 MCLR(3) -- 50 200 nA VSS VPIN VDD at 85C 25 25 100 140 200 300 A VDD = 3.3V, VPIN = VSS VDD = 5.0V, VPIN = VSS -- -- 0.6 V IOL = 8mA, VDD = 5V IOL = 6mA, VDD = 3.3V IOL = 1.8mA, VDD = 1.8V VDD - 0.7 -- -- V IOH = 3.5mA, VDD = 5V IOH = 3mA, VDD = 3.3V IOH = 1mA, VDD = 1.8V -- -- 15 pF -- -- 50 pF IPUR Weak Pull-up Current D070* VOL D080 Output Low Voltage(4) I/O ports VOH D090 Output High Voltage(4) I/O ports Capacitive Loading Specs on Output Pins D101* COSC2 OSC2 pin D101A* CIO * Note 1: 2: 3: 4: All I/O pins In XT, HS and LP modes when external clock is used to drive OSC1 These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Including OSC2 in CLKOUT mode. DS41458B-page 312 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 25.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C DC CHARACTERISTICS Param No. Sym. Characteristic Min. Typ Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP pin 8.0 -- 9.0 V D111 IDDP Supply Current during Programming -- -- 10 mA VDD for Bulk Erase 2.7 -- VDD max. V D112 D113 VPEW VDD for Write or Row Erase VDD min. -- VDD max. V D114 IPPPGM Current on MCLR/VPP during Erase/ Write -- -- 1.0 mA D115 IDDPGM Current on VDD during Erase/Write -- 5.0 mA D121 EP Cell Endurance 10K -- -- E/W D122 VPR VDD for Read VDD min. -- VDD max. V D123 TIW Self-timed Write Cycle Time -- 2 2.5 ms D124 TRETD Characteristic Retention 40 -- -- Year (Note 2, Note 3) Program Flash Memory -40C to +85C (Note 1) Provided no other specifications are violated Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Self-write and Block Erase. 2: Required only if single-supply programming is disabled. 3: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be placed between the ICD 2 and target system when programming or debugging with the ICD 2. 2011 Microchip Technology Inc. Preliminary DS41458B-page 313 PIC16(L)F1526/27 25.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. TH01 TH02 TH03 TH04 TH05 Sym. Characteristic JA Thermal Resistance Junction to Ambient JC TJMAX PD Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Typ. Units Conditions TBD C/W 64-pin TQFP package TBD C/W 64-pin QFN package TBD C/W 64-pin TQFP package TBD C/W 64-pin QFN package 150 C -- W PD = PINTERNAL + PI/O -- W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation -- W PI/O = (IOL * VOL) + (IOH * (VDD - VOH)) TH07 PDER Derated Power -- W PDER = PDMAX (TJ - TA)/JA(2) Legend: TBD = To Be Determined Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature. 3: TJ = Junction Temperature. DS41458B-page 314 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 25.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDIx do SDO dt Data in io I/O PORT mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low FIGURE 25-4: T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCKx SS T0CKI T1CKI WR P R V Z Period Rise Valid High-impedance LOAD CONDITIONS Load Condition Pin CL VSS Legend: CL = 50 pF for all pins, 15 pF for OSC2 output 2011 Microchip Technology Inc. Preliminary DS41458B-page 315 PIC16(L)F1526/27 25.8 AC Characteristics: PIC16(L)F1526/27-I/E FIGURE 25-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 25-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. OS01 Sym. FOSC Characteristic External CLKIN Frequency(1) Oscillator Frequency(1) OS02 TOSC External CLKIN Period(1) Oscillator Period(1) OS03 TCY Instruction Cycle Time(1) OS04* TosH, TosL External CLKIN High, External CLKIN Low TosR, TosF External CLKIN Rise, External CLKIN Fall OS05* Min. Typ Max. Units Conditions DC -- 0.5 MHz EC Oscillator mode (low) DC -- 4 MHz EC Oscillator mode (medium) DC -- 20 MHz EC Oscillator mode (high) -- 32.768 -- kHz LP Oscillator mode 0.1 -- 4 MHz XT Oscillator mode 1 -- 4 MHz HS Oscillator mode, VDD 2.7V 1 -- 20 MHz HS Oscillator mode, VDD > 2.7V DC -- 4 MHz RC Oscillator mode 27 -- s LP Oscillator mode 250 -- ns XT Oscillator mode 50 -- ns HS Oscillator mode 50 -- ns EC Oscillator mode -- 30.5 -- s LP Oscillator mode 250 -- 10,000 ns XT Oscillator mode 50 -- 1,000 ns HS Oscillator mode 250 -- -- ns RC Oscillator mode 125 -- DC ns TCY = FOSC/4 2 -- -- s LP oscillator 100 -- -- ns XT oscillator 20 -- -- ns HS oscillator 0 -- ns LP oscillator 0 -- ns XT oscillator 0 -- ns HS oscillator * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. DS41458B-page 316 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 TABLE 25-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. Sym. Characteristic Freq. Tolerance Min. Typ Max. Units OS08 HFOSC Internal Calibrated HFINTOSC Frequency(2) 10% -- 16.0 -- MHz OS09 LFOSC Internal LFINTOSC Frequency -- -- 31 -- kHz OS10* TIOSC ST HFINTOSC Wake-up from Sleep Start-up Time -- -- 5 8 s Conditions 0C TA +85C * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to the OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 3: By design. FIGURE 25-6: Cycle CLKOUT AND I/O TIMING Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS16 OS13 OS18 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 2011 Microchip Technology Inc. Preliminary DS41458B-page 317 PIC16(L)F1526/27 TABLE 25-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. Sym. Characteristic Min. Typ Max. Units Conditions -- -- 70 ns VDD = 3.3-5.0V -- -- 72 ns VDD = 3.3-5.0V FOSC to CLKOUT (1) OS11 TosH2ckL OS12 TosH2ckH FOSC to CLKOUT (1) OS13 TckL2ioV CLKOUT to Port out valid OS14 OS15 OS16 TioV2ckH TosH2ioV TosH2ioI OS17 TioV2osH OS18 TioR Port input valid before CLKOUT(1) Fosc (Q1 cycle) to Port out valid Fosc (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to Fosc(Q2 cycle) (I/O in setup time) Port output rise time(2) OS19 TioF Port output fall time(2) (1) -- -- 20 ns TOSC + 200 ns -- 50 -- 50 -- -- 70* -- ns ns ns 20 -- -- ns -- -- -- -- 25 25 40 15 28 15 -- -- 72 32 55 30 -- -- ns OS20* Tinp OS21* Tioc INT pin input high or low time Interrupt-on-change new input level time * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. 2: Includes OSC2 in CLKOUT mode. FIGURE 25-7: ns VDD = 3.3-5.0V VDD = 3.3-5.0V VDD = 1.8V VDD = 3.3-5.0V VDD = 1.8V VDD = 3.3-5.0V ns ns RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR PWRT Time-out 33 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 34 31 34 I/O pins Note 1: Asserted low. DS41458B-page 318 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 25-8: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33(1) (due to BOR) Note 1: 64 ms delay only if PWRTE bit in the Configuration Word 1 is programmed to `0'. 2 ms delay if PWRTE = 0 and VREGEN = 1. 2011 Microchip Technology Inc. Preliminary DS41458B-page 319 PIC16(L)F1526/27 TABLE 25-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. Sym. Characteristic MCLR Pulse Width (low) Min. Typ Max. Units Conditions 2 5 -- -- -- -- s s VDD = 3.3-5V, -40C to +85C VDD = 3.3-5V 10 16 27 ms VDD = 3.3V-5V, 1:16 Prescaler used 30 TMCL 31 TWDTLP Low-Power Watchdog Timer Time-out Period 32 TOST Oscillator Start-up Timer Period(1), (2) -- 1024 -- Tosc (Note 3) 33* TPWRT Power-up Timer Period, PWRTE = 0 40 65 140 ms 34* TIOZ I/O high-impedance from MCLR Low or Watchdog Timer Reset -- -- 2.0 s 35 VBOR Brown-out Reset Voltage 2.38 1.80 2.5 1.9 2.65 2.05 V 36* VHYST Brown-out Reset Hysteresis 0 25 50 mV -40C to +85C 37* TBORDC Brown-out Reset DC Response Time 1 3 5 s VDD VBOR 38 VLPBOR Low-Power Brown-out Reset Voltage TBD TBD TBD V LPBOR = 1 * Note 1: 2: 3: 4: BORV=2.5V BORV=1.9V These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to the OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. By design. Period of the slower clock. To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. DS41458B-page 320 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 25-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 25-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width Min. No Prescaler TT0L T0CKI Low Pulse Width No Prescaler TT0P T0CKI Period 45* TT1H T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler -- -- ns -- -- ns 0.5 TCY + 20 -- -- ns 10 -- -- ns Greater of: 20 or TCY + 40 N -- -- ns 0.5 TCY + 20 -- -- ns 15 -- -- ns Asynchronous 46* TT1L T1CKI Low Time 30 -- -- ns Synchronous, No Prescaler 0.5 TCY + 20 -- -- ns Synchronous, with Prescaler 15 -- -- ns Asynchronous 30 -- -- ns Greater of: 30 or TCY + 40 N -- -- ns 47* TT1P T1CKI Input Synchronous Period 48 FT1 Secondary Oscillator Input Frequency Range (oscillator enabled by setting bit SOSCEN) 49* TCKEZTMR1 Delay from External Clock Edge to Timer Increment Asynchronous * Units 10 With Prescaler 42* Max. 0.5 TCY + 20 With Prescaler 41* Typ 60 -- -- ns 32.4 32.768 33.1 kHz 2 TOSC -- 7 TOSC -- Conditions N = prescale value (2, 4, ..., 256) N = prescale value (1, 2, 4, 8) Timers in Sync mode These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2011 Microchip Technology Inc. Preliminary DS41458B-page 321 PIC16(L)F1526/27 FIGURE 25-10: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCP (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 25-4 for load conditions. TABLE 25-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param Sym. No. Characteristic CC01* TccL CCP Input Low Time CC02* TccH CCP Input High Time CC03* TccP * Min. Typ Max. Units 0.5TCY + 20 -- -- ns With Prescaler 20 -- -- ns No Prescaler 0.5TCY + 20 -- -- ns With Prescaler 20 -- -- ns 3TCY + 40 N -- -- ns No Prescaler CCP Input Period Conditions N = prescale value (1, 4 or 16) These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 25-7: PIC16(L)F1526/27 A/D CONVERTER (ADC) CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param Sym. No. Characteristic Min. Typ Max. Units Conditions AD01 NR Resolution -- -- 10 AD02 EIL Integral Error -- -- 1.7 AD03 EDL Differential Error -- -- 1 LSb No missing codes VREF = 3.0V AD04 EOFF Offset Error -- -- 2 LSb VREF = 3.0V AD05 EGN LSb VREF = 3.0V AD06 VREF Reference Voltage(3) AD07 VAIN Full-Scale Range AD08 ZAIN Recommended Impedance of Analog Voltage Source * Note 1: 2: 3: 4: 5: Gain Error bit LSb VREF = 3.0V -- -- 1.5 1.8 -- VDD V VSS -- VREF V -- -- 10 k VREF = (VREF+ minus VREF-) (NOTE 5) Can go higher if external 0.01F capacitor is present on input pin. These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Total Absolute Error includes integral, differential, offset and gain errors. The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. ADC VREF is from external VREF, VDD pin or FVREF, whichever is selected as reference input. When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. FVR voltage selected must be 2.048V or 4.096V. DS41458B-page 322 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 TABLE 25-8: PIC16(L)F1526/27 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. Sym. Characteristic AD130* TAD AD131 TCNV AD132* TACQ Min. Typ Max. Units Conditions A/D Clock Period 1.0 -- 9.0 s TOSC-based A/D Internal RC Oscillator Period 1.0 1.6 6.0 s ADCS<1:0> = 11 (ADRC mode) Conversion Time (not including Acquisition Time)(1) -- 11 -- TAD Set GO/DONE bit to conversion complete Acquisition Time -- 5.0 -- s * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle. FIGURE 25-11: PIC16(L)F1526/27 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 1 TCY (TOSC/2(1)) AD131 Q4 AD130 A/D CLK 7 A/D Data 6 5 4 3 OLD_DATA ADRES 1 0 NEW_DATA 1 TCY ADIF GO Sample 2 DONE AD132 Sampling Stopped Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2011 Microchip Technology Inc. Preliminary DS41458B-page 323 PIC16(L)F1526/27 FIGURE 25-12: PIC16(L)F1526/27 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO (TOSC/2 + TCY(1)) AD134 1 TCY AD131 Q4 AD130 A/D CLK 7 A/D Data 5 6 3 4 1 0 NEW_DATA OLD_DATA ADRES 2 ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 25-9: PIC16(L)F1526/27 LOW DROPOUT (LDO) REGULATOR CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param Sym. No. LD001 LD002 * Characteristic Min. Typ Max. Units LDO Regulation Voltage -- 3.2 -- V LDO External Capacitor 0.1 -- 1 F Conditions These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 25-13: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US120 Note: US122 Refer to Figure 25-4 for load conditions. DS41458B-page 324 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 TABLE 25-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. Symbol Characteristic Min. Max. Units -- 80 ns US120 TCKH2DTV SYNC XMIT (Master and Slave) Clock high to data-out valid 3.0-5.5V 1.8-5.5V -- 100 ns US121 TCKRF Clock out rise time and fall time (Master mode) 3.0-5.5V -- 45 ns 1.8-5.5V -- 50 ns US122 TDTRF Data-out rise time and fall time 3.0-5.5V -- 45 ns 1.8-5.5V -- 50 ns FIGURE 25-14: Conditions USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure 25-4 for load conditions. TABLE 25-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. Symbol Characteristic US125 TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK (DT hold time) US126 TCKL2DTL Data-hold after CK (DT hold time) 2011 Microchip Technology Inc. Preliminary Min. Max. Units 10 -- ns 15 -- ns Conditions DS41458B-page 325 PIC16(L)F1526/27 FIGURE 25-15: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SSx SP70 SCKx (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCKx (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDOx LSb SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 25-4 for load conditions. FIGURE 25-16: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SSx SP81 SCKx (CKP = 0) SP71 SP72 SP79 SP73 SCKx (CKP = 1) SP80 SDOx MSb SP78 bit 6 - - - - - -1 LSb SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 25-4 for load conditions. DS41458B-page 326 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 25-17: SPI SLAVE MODE TIMING (CKE = 0) SSx SP70 SCKx (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCKx (CKP = 1) SP80 MSb SDOx LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 25-4 for load conditions. FIGURE 25-18: SSx SPI SLAVE MODE TIMING (CKE = 1) SP82 SP70 SP83 SCKx (CKP = 0) SP71 SP72 SCKx (CKP = 1) SP80 MSb SDOx bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 25-4 for load conditions. 2011 Microchip Technology Inc. Preliminary DS41458B-page 327 PIC16(L)F1526/27 TABLE 25-12: SPI MODE REQUIREMENTS Param No. Symbol Characteristic Min. Typ Max. Units Conditions SP70* TSSL2SCH, SSx to SCKx or SCKx input TSSL2SCL TCY -- -- ns SP71* TSCH SCKx input high time (Slave mode) TCY + 20 -- -- ns SP72* TSCL SCKx input low time (Slave mode) TCY + 20 -- -- ns 100 -- -- ns 100 -- -- ns 3.0-5.5V -- 10 25 ns 1.8-5.5V -- 25 50 ns -- 10 25 ns SP73* TDIV2SCH, Setup time of SDIx data input to SCKx edge TDIV2SCL SP74* TSCH2DIL, TSCL2DIL Hold time of SDIx data input to SCKx edge SP75* TDOR SDO data output rise time SP76* TDOF SDOx data output fall time SP77* TSSH2DOZ SSx to SDOx output high-impedance 10 -- 50 ns SP78* TSCR SCKx output rise time (Master mode) -- 10 25 ns SP79* TSCF SCKx output fall time (Master mode) 3.0-5.5V -- 25 50 ns -- 10 25 ns 3.0-5.5V -- -- 50 ns 1.8-5.5V -- -- 145 ns SP81* TDOV2SCH, SDOx data output setup to SCKx edge TDOV2SCL Tcy -- -- ns SDOx data output valid after SS edge -- -- 50 ns 1.5TCY + 40 -- -- ns SP80* TSCH2DOV, SDOx data output valid after TSCL2DOV SCKx edge SP82* TSSL2DOV 1.8-5.5V SP83* TSCH2SSH, SSx after SCKx edge TSCL2SSH * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 25-19: I2CTM BUS START/STOP BITS TIMING SCLx SP93 SP91 SP90 SP92 SDAx Stop Condition Start Condition Note: Refer to Figure 25-4 for load conditions. DS41458B-page 328 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 FIGURE 25-20: I2CTM BUS DATA TIMING SP103 SCLx SP100 SP90 SP102 SP101 SP106 SP107 SP91 SDAx In SP92 SP110 SP109 SP109 SDAx Out Note: Refer to Figure 25-4 for load conditions. 2011 Microchip Technology Inc. Preliminary DS41458B-page 329 PIC16(L)F1526/27 TABLE 25-13: I2CTM BUS DATA REQUIREMENTS Param. No. Symbol SP100* THIGH Characteristic Clock high time Min. Max. Units 100 kHz mode 4.0 -- s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 -- s Device must operate at a minimum of 10 MHz SSP module SP101* TLOW Clock low time 1.5TCY -- -- 100 kHz mode 4.7 -- s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 -- s Device must operate at a minimum of 10 MHz 1.5TCY -- -- 100 kHz mode -- 1000 ns 400 kHz mode 20 + 0.1CB 300 ns SDAx and SCLx fall 100 kHz mode time 400 kHz mode -- 250 ns 20 + 0.1CB 250 ns SSP module SP102* TR SP103* TF SP106* THD:DAT SP107* TSU:DAT SP109* TAA SP110* SP111 * Note 1: 2: TBUF CB SDAx and SCLx rise time Data input hold time 100 kHz mode 0 -- ns 400 kHz mode 0 0.9 s Data input setup time 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns Output valid from clock 100 kHz mode -- 3500 ns 400 kHz mode -- -- ns Bus free time Conditions 100 kHz mode 4.7 -- s 400 kHz mode 1.3 -- s -- 400 pF Bus capacitive loading CB is specified to be from 10-400 pF CB is specified to be from 10-400 pF (Note 2) (Note 1) Time the bus must be free before a new transmission can start These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2CTM bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCLx signal. If such a device does stretch the low period of the SCLx signal, it must output the next data bit to the SDAx line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCLx line is released. DS41458B-page 330 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 26.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Graphs and charts are not available at this time. 2011 Microchip Technology Inc. Preliminary DS41458B-page 331 PIC16(L)F1526/27 NOTES: DS41458B-page 332 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 27.0 DEVELOPMENT SUPPORT 27.1 The PIC(R) microcontrollers and dsPIC(R) digital signal controllers are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers - MPLAB ICD 3 - PICkitTM 3 Debug Express * Device Programmers - PICkitTM 2 Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either C or assembly) * One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. 2011 Microchip Technology Inc. Preliminary DS41458B-page 333 PIC16(L)F1526/27 27.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip's PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 27.3 HI-TECH C for Various Device Families For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip's PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. 27.4 27.5 * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction 27.6 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process DS41458B-page 334 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 27.7 MPLAB SIM Software Simulator 27.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 27.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 2011 Microchip Technology Inc. MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC(R) Flash microcontrollers and dsPIC(R) DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 27.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC(R) and dsPIC(R) Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software. Preliminary DS41458B-page 335 PIC16(L)F1526/27 27.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 27.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkitTM 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip's Flash families of microcontrollers. The full featured Windows(R) programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip's powerful MPLAB Integrated Development Environment (IDE) the PICkitTM 2 enables in-circuit debugging on most PIC(R) microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software. 27.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS41458B-page 336 The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 64-Lead TQFP (10x10x1mm) Example XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC16LF1527 -E/PT e3 1045253 64-Lead QFN (9X9X0.9mm) Example PIC16LF1527 -E/MR e3 1045253 XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2011 Microchip Technology Inc. Preliminary DS41458B-page 337 PIC16(L)F1526/27 28.2 Package Details The following sections give the technical details of the packages. /HDG3ODVWLF7KLQ4XDG)ODWSDFN 37 [[PP%RG\PP>74)3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D D1 E e E1 N b NOTE 1 123 NOTE 2 A c A2 A1 L L1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI/HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG3LWFK H 2YHUDOO+HLJKW $ %6& 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ )RRW/HQJWK / )RRWSULQW / 5() )RRW$QJOH 2YHUDOO:LGWK ( %6& 2YHUDOO/HQJWK ' %6& 0ROGHG3DFNDJH:LGWK ( %6& 0ROGHG3DFNDJH/HQJWK ' %6& /HDG7KLFNQHVV F /HDG:LGWK E 0ROG'UDIW$QJOH7RS 0ROG'UDIW$QJOH%RWWRP 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD &KDPIHUVDWFRUQHUVDUHRSWLRQDOVL]HPD\YDU\ 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS41458B-page 338 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 /HDG3ODVWLF7KLQ4XDG)ODWSDFN 37 [[PP%RG\PP>74)3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ 2011 Microchip Technology Inc. Preliminary DS41458B-page 339 PIC16(L)F1526/27 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41458B-page 340 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc. Preliminary DS41458B-page 341 PIC16(L)F1526/27 NOTES: DS41458B-page 342 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 APPENDIX A: DATA SHEET REVISION HISTORY Revision A Original release (01/2011) Revision B Electrical Spec updates (05/2011) 2011 Microchip Technology Inc. Preliminary DS41458B-page 343 PIC16(L)F1526/27 NOTES: DS41458B-page 344 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 INDEX A A/D Specifications.................................................... 322, 323 Absolute Maximum Ratings .............................................. 303 AC Characteristics Industrial and Extended ............................................ 316 Load Conditions ........................................................ 315 ACKSTAT ......................................................................... 236 ACKSTAT Status Flag ...................................................... 236 ADC .................................................................................. 149 Acquisition Requirements ......................................... 159 Associated registers.................................................. 161 Block Diagram........................................................... 149 Calculating Acquisition Time..................................... 159 Channel Selection..................................................... 150 Configuration............................................................. 150 Configuring Interrupt ................................................. 154 Conversion Clock...................................................... 150 Conversion Procedure .............................................. 154 Internal Sampling Switch (RSS) Impedance.............. 159 Interrupts................................................................... 152 Operation .................................................................. 153 Operation During Sleep ............................................ 153 Port Configuration ..................................................... 150 Reference Voltage (VREF)......................................... 150 Source Impedance.................................................... 159 Special Event Trigger................................................ 153 Starting an A/D Conversion ...................................... 152 ADCON0 Register....................................................... 30, 155 ADCON1 Register....................................................... 30, 156 ADDFSR ........................................................................... 293 ADDWFC .......................................................................... 293 ADRESH Register............................................................... 30 ADRESH Register (ADFM = 0) ......................................... 157 ADRESH Register (ADFM = 1) ......................................... 158 ADRESL Register (ADFM = 0).......................................... 157 ADRESL Register (ADFM = 1).......................................... 158 Alternate Pin Function....................................................... 118 Analog-to-Digital Converter. See ADC ANSELA Register ............................................................. 121 ANSELB Register ............................................................. 124 ANSELD Register ............................................................. 130 ANSELE Register ............................................................. 133 ANSELF Register.............................................................. 136 ANSELG Register ............................................................. 139 APFCON0Register............................................................ 118 Assembler MPASM Assembler................................................... 334 B BAUDCON Register.......................................................... 266 BF ............................................................................. 236, 238 BF Status Flag .......................................................... 236, 238 Block Diagrams .......................................................................... 5, 12, 18 (CCP) Capture Mode Operation ............................... 184 ADC .......................................................................... 149 ADC Transfer Function ............................................. 160 Analog Input Model ................................................... 160 CCP PWM................................................................. 192 Clock Source............................................................... 52 Compare ................................................................... 188 Crystal Operation .................................................. 54, 55 2011 Microchip Technology Inc. EUSART Receive ..................................................... 256 EUSART Transmit .................................................... 255 External RC Mode ...................................................... 55 Fail-Safe Clock Monitor (FSCM)................................. 62 Generic I/O Port........................................................ 117 Interrupt Logic............................................................. 75 On-Chip Reset Circuit................................................. 67 PIC16(L)F1526/27 ........................................................ 4 Resonator Operation .................................................. 54 Timer0 ...................................................................... 163 Timer1/3/5 ................................................................ 167 Timer1/3/5 Clock Source .......................................... 168 Timer1/3/5 Gate........................................ 173, 174, 175 Timer2/4/6/8/10 ........................................................ 179 Voltage Reference.................................................... 145 BORCON Register.............................................................. 69 BRA .................................................................................. 294 Break Character (12-bit) Transmit and Receive ............... 275 Brown-out Reset (BOR)...................................................... 69 Specifications ........................................................... 320 Timing and Characteristics ....................................... 319 C C Compilers MPLAB C18.............................................................. 334 CALL................................................................................. 295 CALLW ............................................................................. 295 Capture Module. See Enhanced Capture/Compare/ PWM (ECCP) Capture/Compare/PWM ................................................... 183 Capture/Compare/PWM (CCP) Associated Registers w/ Capture ..................... 186, 187 Associated Registers w/ Compare ................... 190, 191 Associated Registers w/ PWM ......................... 195, 196 Capture Mode........................................................... 184 CCPx Pin Configuration............................................ 184 Compare Mode......................................................... 188 CCPx Pin Configuration.................................... 188 Software Interrupt Mode ........................... 184, 189 Special Event Trigger ....................................... 189 Timer1 Mode Resource ............................ 184, 188 Prescaler .................................................................. 185 PWM Mode Duty Cycle ........................................................ 194 Effects of Reset ................................................ 195 Example PWM Frequencies and Resolutions, 20 MHZ................................ 194 Example PWM Frequencies and Resolutions, 8 MHz .................................. 194 Operation in Sleep Mode.................................. 195 Resolution ........................................................ 194 System Clock Frequency Changes .................. 195 PWM Operation ........................................................ 192 PWM Overview......................................................... 192 PWM Period ............................................................. 193 PWM Setup .............................................................. 193 Specifications ........................................................... 322 CCP1CON Register................................................ 32, 33, 35 CCPR1H Register................................................... 32, 33, 35 CCPR1L Register ................................................... 32, 33, 35 CCPTMRS0 Register........................................................ 198 CCPTMRS1 Register........................................................ 199 CCPTMRS2 Register........................................................ 200 CCPxCON (CCPx) Register ............................................. 197 Preliminary DS41458B-page 345 PIC16(L)F1526/27 Clock Accuracy with Asynchronous Operation ................. 264 Clock Sources External Modes ........................................................... 53 EC ....................................................................... 53 HS ....................................................................... 53 LP........................................................................ 53 OST..................................................................... 54 RC....................................................................... 55 XT ....................................................................... 53 Internal Modes ............................................................ 56 HFINTOSC.......................................................... 56 Internal Oscillator Clock Switch Timing............... 57 LFINTOSC .......................................................... 56 Clock Switching................................................................... 59 Code Examples A/D Conversion ......................................................... 154 Changing Between Capture Prescalers .................... 185 Initializing PORTA ..................................................... 117 Initializing PORTG .................................................... 138 Writing to Flash Program Memory ............................ 110 Compare Module. See Enhanced Capture/Compare/ PWM (ECCP) CONFIG1 Register.............................................................. 46 CONFIG2 Register.............................................................. 48 Core Function Register ....................................................... 29 Customer Change Notification Service ............................. 351 Customer Notification Service........................................... 351 Customer Support ............................................................. 351 D Data Memory....................................................................... 22 DC and AC Characteristics ............................................... 331 DC Characteristics Extended and Industrial ............................................ 312 Industrial and Extended ............................................ 305 Development Support ....................................................... 333 Device Configuration........................................................... 45 Code Protection .......................................................... 49 Configuration Word ..................................................... 45 User ID .................................................................. 49, 50 Device ID Register .............................................................. 50 Device Overview ........................................................... 11, 97 E ECCP/CCP. See Enhanced Capture/Compare/PWM Effects of Reset PWM mode ............................................................... 195 Electrical Specifications .................................................... 303 Enhanced Capture/Compare/PWM (ECCP) ..................... 184 Enhanced Mid-Range CPU................................................. 17 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................... 255 Errata .................................................................................... 9 EUSART............................................................................ 255 Asynchronous Mode ................................................. 257 12-bit Break Transmit and Receive................... 275 Associated Registers, Receive ......................... 263 Associated Registers, Transmit ........................ 259 Auto-Wake-up on Break.................................... 273 Baud Rate Generator (BRG)............................. 267 Clock Accuracy ................................................. 264 Receiver............................................................ 260 Setting up 9-bit Mode with Address Detect....... 262 Transmitter........................................................ 257 Baud Rate Generator (BRG) Associated Registers ........................................ 268 DS41458B-page 346 Auto Baud Rate Detect..................................... 272 Baud Rate Error, Calculating............................ 267 Baud Rates, Asynchronous Modes .................. 269 Formulas........................................................... 267 High Baud Rate Select (BRGH Bit) .................. 267 Clock polarity Synchronous Mode........................................... 276 Data Polarity Asynchronous Receive..................................... 260 Data polarity Asynchronous Transmit.................................... 257 Synchronous Mode........................................... 276 Interrupts Asynchronous Receive..................................... 261 Asynchronous Transmit.................................... 257 Synchronous Master Mode............................... 276, 281 Associated Registers, Receive......................... 280 Associated Registers, Transmit................ 277, 282 Reception ......................................................... 279 Transmission .................................................... 276 Synchronous Slave Mode Associated Registers, Receive......................... 283 Reception ......................................................... 283 Transmission .................................................... 281 Extended Instruction Set ADDFSR ................................................................... 293 F Fail-Safe Clock Monitor ...................................................... 62 Fail-Safe Condition Clearing....................................... 62 Fail-Safe Detection ..................................................... 62 Fail-Safe Operation..................................................... 62 Reset or Wake-up from Sleep .................................... 62 Firmware Instructions ....................................................... 289 Fixed Voltage Reference (FVR)........................................ 145 Associated Registers ................................................ 146 Flash Program Memory .................................................... 101 Associated Registers ................................................ 116 Configuration Word w/ Flash Program Memory........ 116 Erasing ..................................................................... 105 Modifying .................................................................. 111 Write Verify ............................................................... 113 Writing ...................................................................... 107 FSR Register ...................................................................... 29 FVRCON (Fixed Voltage Reference Control) Register..... 146 I I2C Mode (MSSPx) Acknowledge Sequence Timing ............................... 240 Bus Collision During a Repeated Start Condition................... 245 During a Stop Condition ................................... 246 Effects of a Reset ..................................................... 241 I2C Clock Rate w/BRG.............................................. 248 Master Mode Operation.......................................................... 232 Reception ......................................................... 238 Start Condition Timing .............................. 234, 235 Transmission .................................................... 236 Multi-Master Communication, Bus Collision and Arbitration ......................................................... 241 Multi-Master Mode .................................................... 241 Read/Write Bit Information (R/W Bit) ........................ 217 Slave Mode Transmission .................................................... 222 Sleep Operation........................................................ 241 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 Stop Condition Timing............................................... 240 INDF Register ..................................................................... 29 Indirect Addressing ............................................................. 40 Instruction Format ............................................................. 290 Instruction Set ................................................................... 289 ADDLW ..................................................................... 293 ADDWF..................................................................... 293 ADDWFC .................................................................. 293 ANDLW ..................................................................... 293 ANDWF..................................................................... 293 BRA........................................................................... 294 CALL ......................................................................... 295 CALLW...................................................................... 295 LSLF ......................................................................... 297 LSRF......................................................................... 297 MOVF........................................................................ 297 MOVIW ..................................................................... 298 MOVLB ..................................................................... 298 MOVWI ..................................................................... 299 OPTION .................................................................... 299 RESET ...................................................................... 299 SUBWFB................................................................... 301 TRIS.......................................................................... 302 BCF........................................................................... 294 BSF ........................................................................... 294 BTFSC ...................................................................... 294 BTFSS ...................................................................... 294 CALL ......................................................................... 295 CLRF......................................................................... 295 CLRW ....................................................................... 295 CLRWDT................................................................... 295 COMF ....................................................................... 295 DECF ........................................................................ 295 DECFSZ.................................................................... 296 GOTO ....................................................................... 296 INCF.......................................................................... 296 INCFSZ ..................................................................... 296 IORLW ...................................................................... 296 IORWF ...................................................................... 296 MOVLW .................................................................... 298 MOVWF .................................................................... 298 NOP .......................................................................... 299 RETFIE ..................................................................... 300 RETLW ..................................................................... 300 RETURN ................................................................... 300 RLF ........................................................................... 300 RRF........................................................................... 301 SLEEP ...................................................................... 301 SUBLW ..................................................................... 301 SUBWF ..................................................................... 301 SWAPF ..................................................................... 302 XORLW..................................................................... 302 XORWF..................................................................... 302 INTCON Register ................................................................ 80 Internal Oscillator Block INTOSC Specifications.................................................... 317 Internal Sampling Switch (RSS) Impedance ...................... 159 Internet Address................................................................ 351 Interrupt-On-Change ......................................................... 141 Associated Registers ................................................ 143 Interrupts ............................................................................. 75 ADC .......................................................................... 154 Associated registers w/ Interrupts............................... 89 Configuration Word w/ Clock Sources ........................ 65 2011 Microchip Technology Inc. TMRx ........................................................................ 172 INTOSC Specifications ..................................................... 317 IOCBF Register ................................................................ 143 IOCBN Register ................................................................ 143 IOCBP Register ................................................................ 142 L LATA Register .......................................................... 120, 126 LATB Register .................................................................. 123 LATD Register .................................................................. 129 LATE Register .................................................................. 132 LATF Register................................................................... 135 LATG Register .................................................................. 139 LDO Configuration Word w/ LDO........................................ 95 Load Conditions................................................................ 315 LSLF ................................................................................. 297 LSRF ................................................................................ 297 M Master Synchronous Serial Port. See MSSPx MCLR ................................................................................. 70 Internal........................................................................ 70 Memory Organization ......................................................... 19 Data ............................................................................ 22 Program...................................................................... 19 Microchip Internet Web Site.............................................. 351 MOVIW ............................................................................. 298 MOVLB ............................................................................. 298 MOVWI ............................................................................. 299 MPLAB ASM30 Assembler, Linker, Librarian ................... 334 MPLAB Integrated Development Environment Software.. 333 MPLAB PM3 Device Programmer .................................... 336 MPLAB REAL ICE In-Circuit Emulator System ................ 335 MPLINK Object Linker/MPLIB Object Librarian ................ 334 MSSPx.............................................................................. 201 I2C Mode .................................................................. 212 I2C Mode Operation.................................................. 214 SPI Mode.................................................................. 204 SSPxBUF Register ................................................... 207 SSPxSR Register ..................................................... 207 O OPCODE Field Descriptions............................................. 289 OPTION ............................................................................ 299 OPTION_REG Register.................................................... 165 OSCCON Register.............................................................. 64 Oscillator Associated Registers.................................................. 65 Oscillator Module ................................................................ 51 ECH ............................................................................ 51 ECL............................................................................. 51 ECM............................................................................ 51 HS............................................................................... 51 INTOSC ...................................................................... 51 LP ............................................................................... 51 RC .............................................................................. 51 XT ............................................................................... 51 Oscillator Parameters ....................................................... 317 Oscillator Specifications.................................................... 316 Oscillator Start-up Timer (OST) Specifications ........................................................... 320 Oscillator Switching Fail-Safe Clock Monitor .............................................. 62 Two-Speed Clock Start-up ......................................... 60 OSCSTAT Register ............................................................ 65 Preliminary DS41458B-page 347 PIC16(L)F1526/27 P Packaging ......................................................................... 337 Marking ..................................................................... 337 PDIP Details.............................................................. 338 PCL and PCLATH ............................................................... 18 PCL Register....................................................................... 29 PCLATH Register................................................................ 29 PCON Register ............................................................. 30, 73 PIE1 Register ................................................................ 30, 81 PIE2 Register ................................................................ 30, 82 PIE3 Register ...................................................................... 83 PIE4 Register ...................................................................... 84 PIR1 Register................................................................ 30, 85 PIR2 Register................................................................ 30, 86 PIR3 Register...................................................................... 87 PIR4 Register...................................................................... 88 PMADR Registers ............................................................. 101 PMADRH Registers .......................................................... 101 PMADRL Register............................................................. 114 PMADRL Registers ........................................................... 101 PMCON1 Register .................................................... 101, 115 PMCON2 Register .................................................... 101, 116 PMDATH Register............................................................. 114 PMDATL Register ............................................................. 114 PORTA.............................................................................. 119 ANSELA Register ..................................................... 119 Associated Registers ................................................ 121 Configuration Word w/ PORTA ................................. 121 PORTA Register ................................................... 30, 31 Specifications ............................................................ 318 PORTA Register ............................................................... 120 PORTB.............................................................................. 122 ANSELB Register ..................................................... 122 Associated Registers ................................................ 124 PORTB Register ................................................... 30, 31 PORTB Register ............................................................... 123 PORTC.............................................................................. 125 Associated Registers ................................................ 127 PORTC Register ................................................... 30, 31 PORTC Register ............................................................... 126 PORTD.............................................................................. 128 ANSELD Register ..................................................... 128 Associated Registers ................................................ 130 PORTD Register ................................................... 30, 31 PORTD Register ............................................................... 129 PORTE.............................................................................. 131 ANSELE Register ..................................................... 131 Associated Registers ................................................ 133 PORTE Register ................................................... 30, 31 PORTE Register ............................................................... 132 PORTF .............................................................................. 134 ANSELF Register...................................................... 134 Associated Registers ................................................ 136 Configuration Word w/ PORTF ................................. 136 PORTF Register................................................................ 135 PORTG ............................................................................. 137 ANSELG Register ..................................................... 137 Associated Registers ................................................ 140 Configuration Word w/ PORTG................................. 140 PORTG Register ............................................................... 138 Power-Down Mode (Sleep) ................................................. 91 Associated Registers .................................................. 94 Power-on Reset .................................................................. 68 Power-up Time-out Sequence ............................................ 70 Power-up Timer (PWRT)..................................................... 68 DS41458B-page 348 Specifications ........................................................... 320 PR2 Register ................................................................ 30, 35 Precision Internal Oscillator Parameters .......................... 317 Program Memory ................................................................ 19 Map and Stack............................................................ 19 Map and Stack (PIC16(L)F1527 ................................. 20 Programming, Device Instructions .................................... 289 R RCREG............................................................................. 262 RCREG Register ................................................................ 31 RCSTA Register ......................................................... 31, 265 Reader Response............................................................. 352 Read-Modify-Write Operations ......................................... 289 Register RCREG Register ...................................................... 272 Registers ADCON0 (ADC Control 0) ........................................ 155 ADCON1 (ADC Control 1) ........................................ 156 ADRESH (ADC Result High) with ADFM = 0) .......... 157 ADRESH (ADC Result High) with ADFM = 1) .......... 158 ADRESL (ADC Result Low) with ADFM = 0)............ 157 ADRESL (ADC Result Low) with ADFM = 1)............ 158 ANSELA (PORTA Analog Select)............................. 121 ANSELB (PORTB Analog Select)............................. 124 ANSELD (PORTD Analog Select) ............................ 130 ANSELE (PORTE Analog Select)............................. 133 ANSELF (PORTF Analog Select) ............................. 136 ANSELG (PORTG Analog Select)............................ 139 APFCON (Alternate Pin Function Control) ............... 118 BAUDCON (Baud Rate Control)............................... 266 BORCON Brown-out Reset Control) .......................... 69 CCPTMRS0 (CCP Timer Selection Control 0) ......... 198 CCPTMRS1 (CCP Timer Selection Control 1) ......... 199 CCPTMRS2 (CCP Timer Selection Control 2) ......... 200 CCPxCON (CCPx Control) ....................................... 197 Configuration Word 1.................................................. 46 Configuration Word 2.................................................. 48 Core Function, Summary............................................ 29 Device ID .................................................................... 50 FVRCON................................................................... 146 INTCON (Interrupt Control)......................................... 80 IOCBF (Interrupt-on-Change PORTB Flag).............. 143 IOCBN (Interrupt-on-Change PORTB Negative Edge) ................................................................ 143 IOCBP (Interrupt-on-Change PORTB Positive Edge) ................................................................ 142 LATA (Data Latch PORTA)....................................... 120 LATB (Data Latch PORTB)....................................... 123 LATC (Data Latch PORTC) ...................................... 126 LATD (Data Latch PORTD) ...................................... 129 LATE (Data Latch PORTE)....................................... 132 LATF (Data Latch PORTF) ....................................... 135 LATG (Data Latch PORTG)...................................... 139 OPTION_REG (OPTION) ......................................... 165 OSCCON (Oscillator Control) ..................................... 64 OSCSTAT (Oscillator Status) ..................................... 65 PCON (Power Control) ............................................... 73 PIE1 (Peripheral Interrupt Enable 1)........................... 81 PIE2 (Peripheral Interrupt Enable 2)........................... 82 PIE3 (Peripheral Interrupt Enable 3)........................... 83 PIE4 (Peripheral Interrupt Enable 4)........................... 84 PIR1 (Peripheral Interrupt Register 1) ........................ 85 PIR2 (Peripheral Interrupt Request 2) ........................ 86 PIR3 (Peripheral Interrupt Request 3) ........................ 87 PIR4 (Peripheral Interrupt Request 4) ........................ 88 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 PMADRL (Program Memory Address)...................... 114 PMCON1 (Program Memory Control 1).................... 115 PMCON2 (Program Memory Control 2).................... 116 PMDATH (Program Memory Data) ........................... 114 PMDATL (EEPROM Data)........................................ 114 PORTA...................................................................... 120 PORTB...................................................................... 123 PORTC ..................................................................... 126 PORTD ..................................................................... 129 PORTE...................................................................... 132 PORTF...................................................................... 135 PORTG ..................................................................... 138 RCxSTA (Receive Status and Control)..................... 265 Special Function, Summary ........................................ 30 SSPxADD (MSSPx Address and Baud Rate, I2C Mode) ......................................................... 254 SSPxCON1 (MSSPx Control 1) ................................ 251 SSPxCON2 (SSPx Control 2) ................................... 252 SSPxCON3 (SSPx Control 3) ................................... 253 SSPxMSK (SSPx Mask) ........................................... 254 SSPxSTAT (SSPx Status) ........................................ 249 STATUS...................................................................... 23 TRISA (Tri-State PORTA)......................................... 120 TRISB (Tri-State PORTB)......................................... 123 TRISC (Tri-State PORTC) ........................................ 126 TRISD (Tri-State PORTD) ........................................ 129 TRISE (Tri-State PORTE)......................................... 132 TRISF (Tri-State PORTF) ......................................... 135 TRISG (Tri-State PORTG) ........................................ 138 TXCON ..................................................................... 181 TxCON (Timer1/3/5 Control)..................................... 176 TxGCON (Timer1/3/5 Gate Control) ......................... 177 TXxSTA (Transmit Status and Control) .................... 264 VREGCON (Voltage Regulator Control) ..................... 94 WDTCON (Watchdog Timer Control) ......................... 99 WPUB (Weak Pull-up PORTB) ................................. 124 WPUD (Weak Pull-up PORTD)................................. 130 WPUE (Weak Pull-up PORTE) ................................. 133 RESET .............................................................................. 299 Reset................................................................................... 67 Reset Instruction ................................................................. 70 Resets ................................................................................. 67 Associated Registers .................................................. 74 Revision History ................................................................ 343 S Software Simulator (MPLAB SIM)..................................... 335 SPBRG ............................................................................. 267 SPBRG Register ................................................................. 31 SPBRGH ........................................................................... 267 Special Event Trigger........................................................ 153 Special Function Registers (SFRs) ..................................... 30 SPI Mode (MSSPx) Associated Registers ................................................ 211 SPI Clock .................................................................. 207 SSP1CON Register ............................................................ 32 SSP2CON Register ............................................................ 32 SSPADD Register ............................................................... 32 SSPBUF Register ............................................................... 32 SSPSTAT Register ............................................................. 32 SSPxADD Register ........................................................... 254 SSPxCON1 Register......................................................... 251 SSPxCON2 Register......................................................... 252 SSPxCON3 Register......................................................... 253 SSPxMSK Register ........................................................... 254 SSPxOV ............................................................................ 238 2011 Microchip Technology Inc. SSPxOV Status Flag ........................................................ 238 SSPxSTAT Register ......................................................... 249 R/W Bit ..................................................................... 217 Stack................................................................................... 38 Accessing ................................................................... 38 Reset .......................................................................... 40 Stack Overflow/Underflow .................................................. 70 STATUS Register ............................................................... 23 SUBWFB .......................................................................... 301 T T1CON Register ................................................................. 30 T2CON Register ........................................................... 30, 35 Temperature Indicator Module.......................................... 147 Thermal Considerations.................................................... 314 Timer0 .............................................................................. 163 Associated Registers................................................ 165 Operation.................................................................. 163 Specifications ........................................................... 321 Timer1 .............................................................................. 167 Specifications ........................................................... 321 Timer1/3/5 Associated registers ................................................. 178 Asynchronous Counter Mode ................................... 170 Reading and Writing ......................................... 170 Clock Source Selection ............................................ 169 Interrupt .................................................................... 172 Operation.................................................................. 169 Operation During Sleep ............................................ 172 Oscillator................................................................... 170 Prescaler .................................................................. 170 Timer1/3/5 Gate Selecting Source .............................................. 170 TMRxH Register ....................................................... 167 TMRxL Register........................................................ 167 Timer2/4/6/8/10 ................................................................ 179 Associated registers ................................................. 182 Timers Timer1/3/5 TxCON.............................................................. 176 TxGCON........................................................... 177 Timer2/4/6/8/10 TXCON ............................................................. 181 Timing Diagrams A/D Conversion ........................................................ 323 A/D Conversion (Sleep Mode).................................. 324 Acknowledge Sequence ........................................... 240 Asynchronous Reception.......................................... 263 Asynchronous Transmission .................................... 258 Asynchronous Transmission (Back to Back) ............ 259 Auto Wake-up Bit (WUE) During Normal Operation. 274 Auto Wake-up Bit (WUE) During Sleep .................... 274 Automatic Baud Rate Calculator .............................. 273 Baud Rate Generator with Clock Arbitration............. 233 BRG Reset Due to SDA Arbitration During Start Condition .......................................................... 244 Brown-out Reset (BOR)............................................ 319 Brown-out Reset Situations ........................................ 69 Bus Collision During a Repeated Start Condition (Case 1)............................................................ 245 Bus Collision During a Repeated Start Condition (Case 2)............................................................ 245 Bus Collision During a Start Condition (SCL = 0) ..... 244 Bus Collision During a Stop Condition (Case 1)....... 246 Bus Collision During a Stop Condition (Case 2)....... 246 Bus Collision During Start Condition (SDA only) ...... 243 Preliminary DS41458B-page 349 PIC16(L)F1526/27 Bus Collision for Transmit and Acknowledge............ 242 Capture/Compare/PWM (CCP)................................. 322 CLKOUT and I/O....................................................... 317 Clock Synchronization .............................................. 230 Clock Timing ............................................................. 316 Fail-Safe Clock Monitor (FSCM) ................................. 63 First Start Bit Timing ................................................. 234 I2C Bus Data ............................................................. 329 I2C Bus Start/Stop Bits.............................................. 328 I2C Master Mode (7 or 10-Bit Transmission) ............ 237 I2C Master Mode (7-Bit Reception) ........................... 239 I2C Stop Condition Receive or Transmit Mode ......... 241 INT Pin Interrupt.......................................................... 78 Internal Oscillator Switch Timing................................. 58 Repeat Start Condition.............................................. 235 Reset Start-up Sequence............................................ 71 Reset, WDT, OST and Power-up Timer ................... 318 Send Break Character Sequence ............................. 275 SPI Master Mode (CKE = 1, SMP = 1) ..................... 326 SPI Mode (Master Mode) .......................................... 207 SPI Slave Mode (CKE = 0) ....................................... 327 SPI Slave Mode (CKE = 1) ....................................... 327 Synchronous Reception (Master Mode, SREN) ....... 280 Synchronous Transmission....................................... 277 Synchronous Transmission (Through TXEN) ........... 277 Timer0 and Timer1 External Clock ........................... 321 Timer1/3/5 Incrementing Edge.................................. 173 Two Speed Start-up .................................................... 61 USART Synchronous Receive (Master/Slave) ......... 325 USART Synchronous Transmission (Master/Slave) . 324 Wake-up from Interrupt ............................................... 92 Timing Parameter Symbology........................................... 315 Timing Requirements I2C Bus Data ............................................................. 330 SPI Mode .................................................................. 328 TMR0 Register .................................................................... 30 TMR1H Register ................................................................. 30 TMR1L Register .................................................................. 30 TMR2 Register .............................................................. 30, 35 TRIS .................................................................................. 302 TRISA................................................................................ 119 TRISA Register ........................................................... 30, 120 TRISB................................................................................ 122 TRISB Register ........................................................... 30, 123 TRISC ............................................................................... 125 TRISC Register ........................................................... 30, 126 TRISD ............................................................................... 128 TRISD Register ........................................................... 30, 129 TRISE................................................................................ 131 TRISE Register ........................................................... 30, 132 TRISF................................................................................ 134 TRISF Register ................................................................. 135 TRISG ............................................................................... 137 TRISG Register................................................................. 138 Two-Speed Clock Start-up Mode ........................................ 60 TXCON (Timer2/4/6/8/10) Register................................... 181 TxCON Register................................................................ 176 TxGCON Register ............................................................. 177 TXREG.............................................................................. 257 TXREG Register ................................................................. 31 TXSTA Register .......................................................... 31, 264 BRGH Bit .................................................................. 267 DS41458B-page 350 U USART Synchronous Master Mode Requirements, Synchronous Receive .............. 325 Requirements, Synchronous Transmission...... 325 Timing Diagram, Synchronous Receive ........... 325 Timing Diagram, Synchronous Transmission... 324 V VREF. SEE ADC Reference Voltage VREGCON Register ........................................................... 94 W Wake-up on Break ............................................................ 273 Wake-up Using Interrupts ................................................... 92 Watchdog Timer (WDT)...................................................... 70 Associated Registers ................................................ 100 Configuration Word w/ Watchdog Timer................... 100 Modes ......................................................................... 98 Specifications ........................................................... 320 WCOL ....................................................... 233, 236, 238, 240 WCOL Status Flag.................................... 233, 236, 238, 240 WDTCON Register ............................................................. 99 WPUB Register................................................................. 124 WPUD Register ................................................................ 130 WPUE Register................................................................. 133 Write Protection .................................................................. 49 WWW Address ................................................................. 351 WWW, On-Line Support ....................................................... 9 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions. 2011 Microchip Technology Inc. Preliminary DS41458B-page 351 PIC16(L)F1526/27 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16(L)F1526/27 Literature Number: DS41458B Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41458B-page 352 Preliminary 2011 Microchip Technology Inc. PIC16(L)F1526/27 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO. Device Device: - X Tape and Reel Temperature Option Range /XX XXX Package Pattern Examples: a) b) PIC16F1526, PIC16LF1526 PIC16F1527, PIC16LF1527 c) Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel(1) Temperature Range: I E = -40C to +85C = -40C to +125C Package: MR PT Pattern: QTP, SQTP, Code or Special Requirements (blank otherwise) = = (Industrial) (Extended) Plastic Quad Flat, no lead (QFN) Plastic Thin Quad Flatpack (TQFP) 2011 Microchip Technology Inc. PIC16F1526T - I/MR 301 Tape and Reel, Industrial temperature, QFN package, QTP pattern #301 PIC16F1527 - I/PT Industrial temperature TQFP package PIC16F1527 - E/MR Extended temperature, QFN package Preliminary Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. DS41458B-page 353 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hangzhou Tel: 86-571-2819-3180 Fax: 86-571-2819-3189 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 DS41458B-page 354 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 05/02/11 Preliminary 2011 Microchip Technology Inc.