General Description
The MAX5974_ provide control for wide-input-voltage,
active-clamped, current-mode PWM, forward converters
in Power-over-Ethernet (PoE) powered device (PD) appli-
cations. The MAX5974A/MAX5974C are well-suited for
universal or telecom input range, while the MAX5974B/
MAX5974D also accommodate low input voltage down
to 10.5V.
The devices include several features to enhance supply
efficiency. The AUX driver recycles magnetizing cur-
rent instead of wasting it in a dissipative clamp circuit.
Programmable dead time between the AUX and main
driver allows for zero-voltage switching (ZVS). Under
light-load conditions, the devices reduce the switching fre-
quency (frequency foldback) to reduce switching losses.
The MAX5974A/MAX5974B feature unique circuitry to
achieve output regulation without using an optocoupler,
while the MAX5974C/MAX5974D utilize the traditional
optocoupler feedback method. An internal error amplifier
with a 1% reference is very useful in nonisolated design,
eliminating the need for an external shunt regulator.
The devices feature a unique feed-forward maximum
duty-cycle clamp that makes the maximum clamp volt-
age during transient conditions independent of the line
voltage, allowing the use of a power MOSFET with lower
breakdown voltage. The programmable frequency dither-
ing feature provides low-EMI, spread-spectrum operation.
The MAX5974_ are available in 16-pin TQFN-EP pack-
ages and are rated for operation over the -40°C to +85°C
temperature range.
Features
●Peak Current-Mode Control, Active-Clamped Forward
PWM Controller
●Regulation Without Optocoupler (MAX5974A/
MAX5974B)
●Internal 1% Error Amplifier
●100kHz to 600kHz Programmable ±8% Switching
Frequency, Synchronization Up to 1.2MHz
●Programmable Frequency Dithering for Low-EMI,
Spread-Spectrum Operation
●Programmable Dead Time, PWM Soft-Start, Current
Slope Compensation
●Programmable Feed-Forward Maximum Duty-Cycle
Clamp, 80% Maximum Limit
●Frequency Foldback for High-Efficiency Light-Load
Operation
●Internal Bootstrap UVLO with Large Hysteresis
● 100μA (typ) Startup Supply Current
●Fast Cycle-by-Cycle Peak Current-Limit, 35ns Typical
Propagation Delay
●115ns Current-Sense Internal Leading-Edge Blanking
●Output Short-Circuit Protection with Hiccup Mode
●Reverse Current Limit to Prevent Transformer
Saturation Due to Reverse Current
●Internal 18V Zener Clamp on Supply Input
●3mm x 3mm, Lead-Free, 16-Pin TQFN-EP
Applications
●PoE IEEE® 802.3af/at Powered Devices
●High-Power PD (Beyond the 802.3af/at Standard)
●Active-Clamped Forward DC-DC Converters
●IP Phones
●Wireless Access Nodes
●Security Cameras
19-5331; Rev 6; 7/17
IEEE is a registered service mark of the Institute of Electrical
and Electronics Engineers, Inc.
Ordering Information/Selector Guide appears at end of data
sheet.
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
EVALUATION KIT AVAILABLE
IN to GND (VEN = 0V) ........................................... -0.3V to +26V
NDRV, AUXDRV to GND ............................-0.3V to (VIN + 0.3V)
RT, DT, FFB, COMP, SS, DCLMP, DITHER/SYNC
to GND ................................................................. -0.3V to +6V
FB to GND (MAX5974A/MAX5974B only) .................-6V to +6V
FB to GND (MAX5974C/MAX5974D only) .............. -0.3V to +6V
CS, CSSC to GND ..................................................-0.8V to +6V
PGND to GND ......................................................-0.3V to +0.3V
Maximum Input/Output Current (continuous)
EN ..................................................................................... 1mA
NDRV, AUXDRV (pulsed for less than 100ns) ..................±1A
Continuous Power Dissipation (TA = +70°C)
16-Pin TQFN (derate 20.8mW/°C above +70°C) ......1666mW
Operating Temperature Range ......................... -40°C to +105°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range ............................ -65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) ....................................... +260°C
PACKAGE TYPE: 16 TQFN
Package Code T1633+4
Outline Number 21-0136
Land Pattern Number 90-0031
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θJA) 48°C/W
Junction to Case (θJC) 7°C/W
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 17V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND,
VEN = +2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kΩ, RDT = 25kΩ, CIN = 1µF, TA = -40°C to +85°C (MAX5974B,
MAX5974C, MAX5974D), TA = -40°C to +105°C (MAX5974A), unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
UNDERVOLTAGE LOCKOUT/STARTUP (IN)
Bootstrap UVLO Wakeup Level VINUVR VIN rising
MAX5974A/C 15.4 16 16.5
V
MAX5974B/D
-40°C to
+85°C 8 8.4 8.85
-40°C to
+125°C 7.95 8.4 8.85
Bootstrap UVLO Shutdown
Level VINUVF VIN falling -40°C to +85°C 6.65 7 7.35 V
-40°C to +125°C 6.6 7 7.35
IN Clamp Voltage VIN_CLAMP IIN = 2mA (sinking) 17 18.5 20 V
IN Supply Current in
Undervoltage Lockout ISTART
VIN = +15V (for
MAX5974A/C);
VIN = +7.5V (for
MAX5974B/D), when
in bootstrap UVLO
-40°C to +85°C 100 150
µA
-40°C to +125°C 100 250
IN Supply Current After Startup ICVIN = +12V -40°C to +85°C 1.8 3 mA
-40°C to +125°C 1.8 4
ENABLE (EN)
Enable Threshold
VENR VEN rising -40°C to +85°C 1.17 1.215 1.26
V
-40°C to +125°C 1.17 1.2155 1.2655
VENF VEN falling -40°C to +85°C 1.09 1.14 1.19
-40°C to +125°C 1.085 1.14 1.19
Input Current IEN
-40°C to +85°C 1 µA
-40°C to +105°C 1.5
OSCILLATOR (RT)
RT Bias Voltage VRT 1.23 V
NDRV Switching Frequency
Range fSW 100 600 kHz
NDRV Switching Frequency
Accuracy
-40°C to +85°C -8 +8
%
-40°C to +105°C -11 +11
Maximum Duty Cycle DMAX fSW = 250kHz -40°C to +85°C 79 80 82 %
-40°C to +125°C 79 80 83
SYNCHRONIZATION (SYNC)
Synchronization Logic-High
Input VIH-SYNC 2.91 V
Synchronization Pulse Width 50 ns
Synchronization Frequency
Range fSYNCIN
1.1 x
fSW
2 x
fSW
kHz
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Electrical Characteristics
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 17V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND,
VEN = +2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kΩ, RDT = 25kΩ, CIN = 1µF, TA = -40°C to +85°C (MAX5974B,
MAX5974C, MAX5974D), TA = -40°C to +105°C (MAX5974A), unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Maximum Duty Cycle During
Synchronization
DMAX x fSYNC/
fSW
%
DITHERING RAMP GENERATOR (DITHER)
Charging Current VDITHER = 0V -40°C to +85°C 45 50 55 µA
-40°C to +125°C 44.5 50 55.5
Discharging Current VDITHER = 2.2V -40°C to +85°C 43 50 57 µA
-40°C to +125°C 42 50 58
Ramp’s High Trip Point 2 V
Ramp’s Low Trip Point 0.4 V
SOFT-START AND RESTART (SS)
Charging Current ISS-CH
-40°C to +85°C 9.5 10 10.5 µA
-40°C to +125°C 9 10 11
Discharging Current
ISS-D VSS = 2V, normal shutdown 0.65 1.34 2 mA
ISS-DH
(VEN < VENF or VIN < VINUVF),
VSS = 2V, hiccup mode discharge for
tRSTRT (Note 2)
1.6 2 2.4 µA
Discharge Threshold to Disable
Hiccup and Restart VSS-DTH 0.15 V
Minimum Restart Time During
Hiccup Mode tRSTRT-MIN 1024 Clock
Cycles
Normal Operating High Voltage VSS-HI 5 V
Duty-Cycle Control Range VSS-DMAX DMAX (typ) = (VSS-DMAX/2.43V) 0 2 V
DUTY-CYCLE CLAMP (DCLMP)
DCLMP Input Current IDCLMP VDCLMP = 0 to 5V -100 0 +100 nA
Duty-Cycle Control Range VDCLMP-R
VDCLMP = 0.5V 73 75.4 77.5
%
DMAX (typ) =
1 - (VDCLMP/2.43V)
VDCLMP = 1V 54 56 58
VDCLMP = 2V 14.7 16.5 18.3
NDRV DRIVER
Pulldown Impedance RNDRV-N
INDRV (sinking) =
100mA
-40°C to +85°C 1.9 3.4 Ω
-40°C to +125°C 1.9 3.5
Pullup Impedance RNDRV-P INDRV (sourcing) = 50mA 4.7 8.3 Ω
Peak Sink Current 1 A
Peak Source Current 0.65 A
Fall Time tNDRV-F CNDRV = 1nF 14 ns
Rise Time tNDRV-R CNDRV = 1nF 27 ns
AUXDRV DRIVER
Pulldown Impedance RAUX-N
IAUXDRV (sinking) =
50mA
-40°C to +85°C 4.3 7.7 Ω
-40°C to +125°C 4.3 7.95
Pullup Impedance RAUX-P IAUXDRV (sourcing) = 25mA 10.6 18.9 Ω
Peak Sink Current 0.5 A
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Electrical Characteristics (continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 17V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND,
VEN = +2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kΩ, RDT = 25kΩ, CIN = 1µF, TA = -40°C to +85°C (MAX5974B,
MAX5974C, MAX5974D), TA = -40°C to +105°C (MAX5974A), unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Peak Source Current 0.3 A
Fall Time tAUX-F CAUXDRV = 1nF 24 ns
Rise Time tAUX-R CAUXDRV = 1nF 45 ns
DEAD-TIME PROGRAMMING (DT)
DT Bias Voltage VDT 1.215 V
NDRV to AUXDRV Delay
(Dead Time) tDT
From NDRV falling
to AUXDRV falling
RDT = 10kΩ 40 ns
RDT = 100kΩ 300 350 410
From AUXDRV rising
to NDRV rising
RDT = 10kΩ 40 ns
RDT = 100kΩ 310 360 420
CURRENT-LIMIT COMPARATOR (CS)
Cycle-by-Cycle Peak
Current-Limit Threshold VCS-PEAK 375 393 410 mV
Cycle-by-Cycle Reverse
Current-Limit Threshold VCS-REV
Turns AUXDRV off
for the remaining
cycle if reverse
current limit is
exceeded
-40°C to +85°C -118 -100 -88
mV
-40°C to +105°C -124 -100 -88
Current-Sense Blanking Time for
Reverse Current Limit
tCS-BLANK-
REV
From AUXDRV falling edge 115 ns
Number of Consecutive Peak
Current-Limit Events to Hiccup NHICCUP 8 Events
Current-Sense Leading-Edge
Blanking Time tCS-BLANK From NDRV rising edge 115 ns
Propagation Delay from
Comparator Input to NDRV tPDCS
From CS rising (10mV overdrive) to
NDRV falling (excluding leading-edge
blanking)
35 ns
Minimum On-Time tON-MIN 100 150 200 ns
SLOPE COMPENSATION (CSSC)
Slope Compensation Current
Ramp Height
Current ramp’s peak
added to CSSC
input per switching
cycle
-40°C to +85°C 47 52 58
µA
-40°C to +125°C 46.5 52 59.5
PWM COMPARATOR
Comparator Offset Voltage VPWM-OS VCOMP - VCSSC
-40°C to +85°C 1.35 1.7 2 V
-40°C to +125°C 1.34 1.7 2
Current-Sense Gain ACS-PWM ΔVCOMP/ΔVCSSC (Note 3) 3.1 3.33 3.6 V/V
Current-Sense Leading-Edge
Blanking Time tCSSC-BLANK From NDRV rising edge 115 ns
Comparator Propagation Delay tPWM
Change in VCSSC = 10mV (including
internal leading-edge blanking) 150 ns
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Electrical Characteristics (continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 17V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND,
VEN = +2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kΩ, RDT = 25kΩ, CIN = 1µF, TA = -40°C to +85°C (MAX5974B,
MAX5974C, MAX5974D), TA = -40°C to +105°C (MAX5974A), unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
Note 1: All devices are 100% production tested at TA = +25°C. Limits over temperature are guaranteed by design.
Note 2: See the Output Short-Circuit Protection with Hiccup Mode section.
Note 3: The parameter is measured at the trip point of latch with VFB = 0V. Gain is defined as ∆VCOMP/∆VCSSC for 0.15V <
∆VCSSC < 0.25V.
Note 4: Operates over the -40°C to +125°C operating temperature range.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ERROR AMPLIFIER
FB Reference Voltage VREF
VFB when ICOMP =
0, VCOMP = 2.5V
MAX5974A/B 1.5 1.52 1.54
V
MAX5974C/D 1.202 1.215 1.227
MAX5974DATE
(Note 4) 1.202 1.215 1.230
FB Input Bias Current IFB VFB = 0 to 1.75V
MAX5974A/B -250 +250
nA
MAX5974C/D -500 +100
MAX5974DATE
(Note 4) -1000 +100
Voltage Gain AEAMP 80 dB
Transconductance gM
MAX5974A/B 1.8 2.55 3.2 mS
MAX5974C/D 1.8 2.66 3.5
Transconductance Bandwidth BW
Open loop (typical
gain = 1) -3dB
frequency
MAX5974A/B 2
MHz
MAX5974C/D 30
Source Current VFB = 1V, VCOMP = 2.5V 300 375 455 µA
Sink Current VFB = 1.75V, VCOMP = 1V 300 375 455 µA
FREQUENCY FOLDBACK (FFB)
VCSAVG-to-FFB Comparator
Gain 10 V/V
FFB Bias Current IFFB
VFFB = 0V,
VCS = 0V (not in
FFB mode)
-40°C to +85°C 26 30 33
µA
-40°C to +125°C 26 30 33.5
NDRV Switching Frequency
During Foldback fSW-FB fSW/2 kHz
THERMAL SHUTDOWN
Thermal-Shutdown Threshold TSD Temperature rising 165 °C
Thermal-Shutdown Hysteresis Temperature falling 10 °C
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Electrical Characteristics (continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 17V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP =
VGND, VEN = 2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kΩ, RDT = 25kΩ, unless otherwise noted.)
TEMPERATURE (°C)
IN UVLO WAKE-UP LEVEL (V)
603510-15
8.1
8.2
8.3
8.4
8.5
8.6
8.0
-40 85
IN UVLO WAKE-UP LEVEL
vs. TEMPERATURE
MAX5974A/B/C/D toc02
MAX5974B/MAX5974D
IN UVLO SHUTDOWN LEVEL
vs. TEMPERATURE
MAX5974A/B/C/D toc03
TEMPERATURE (°C)
IN UVLO SHUTDOWN LEVEL
603510-15
6.9
7.0
7.1
7.2
7.3
6.8
-40 85
EN RISING THRESHOLD
vs. TEMPERATURE
MAX5974A/B/C/D toc04
TEMPERATURE (°C)
EN RISING THRESHOLD (V)
603510-15
1.212
1.214
1.216
1.218
1.220
1.210
-40 85
EN FALLING THRESHOLD
vs. TEMEPRATURE
MAX5974A/B/C/D toc05
TEMPERATURE (°C)
EN FALLING THRESHOLD (V)
6035-15 10
1.143
1.144
1.145
1.146
1.148
1.147
1.149
1.150
1.142
-40 85
UVLO SHUTDOWN CURRENT
vs. TEMPERATURE
MAX5974A/B/C/D toc06
TEMPERATURE (°C)
UVLO CURRENT (µA)
603510-15
80
100
120
140
60
-40 85
MAX5974A/MAX5974C
MAX5974B/MAX5974D
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX5974A/MAX5974C)
MAX5974A/B/C/D toc07
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
18161412108642
100
1000
10,000
10
0 20
TA = -40°C
TA = +85°C
TEMPERATURE (°C)
IN UVLO WAKE-UP LEVEL (V)
603510-15
15.8
15.9
16.0
16.1
16.2
16.3
15.7
-40 85
IN UVLO WAKE-UP LEVEL
vs. TEMPERATURE
MAX5974A/B/C/D toc01
MAX5974A/MAX5974C
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX5974B/MAX5974D)
MAX5974A/B/C/D toc08
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
18161412108642
100
1000
10,000
10
0 20
TA = -40°C
TA = +85°C
SUPPLY CURRENT
vs. SWITCHING FREQUENCY
MAX5974A/B/C/D toc09
SWITCHING FREQUENCY (kHz)
SUPPLY CURRENT (mA)
700600500400300200100
0.4
0.8
1.2
1.6
2.0
2.4
0
0 800
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Operating Characteristics
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 17V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP =
VGND, VEN = 2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kΩ, RDT = 25kΩ, unless otherwise noted.)
SWITCHING FREQUENCY
vs. RRT VALUE
MAX5974A/B/C/D toc11
RRT VALUE (kΩ)
SWITCHING FREQUENCY (kHz)
100
1000
10
10010
SWITCHING FREQUENCY
vs. TEMPERATURE
MAX5974A/B/C/D toc12
TEMPERATURE (°C)
SWITCHING FREQUENCY (kHz)
6035-15 10
245
246
247
248
250
249
251
252
244
-40 85
FREQUENCY DITHERING
vs. RDITHER
MAX5974A/B/C/D toc13
RDITHER (kΩ)
FREQUENCY DITHERING (%)
900800700600500400
2
4
6
8
10
12
14
0
300 1000
MAXIMUM DUTY CYCLE
vs. SWITCHING FREQUENCY
MAX5974A/B/C/D toc14
SWITCHING FREQUENCY (kHz)
MAXIMUM DUTY CYCLE (%)
700600100 200 300 400 500
76
77
78
79
80
81
82
83
75
0 800
MAXIMUM DUTY CYCLE
vs. TEMPERATURE
MAX5974A/B/C/D toc15
TEMPERATURE (°C)
MAXIMUM DUTY CYCLE (%)
6035-15 10
80.3
80.4
80.5
80.6
80.8
80.7
80.9
81.0
80.2
-40 85
MAXIMUM DUTY CYCLE
vs. SYNC FREQUENCY
MAX5974A/B/C/D toc16
SYNC FREQUENCY (kHz)
MAXIMUM DUTY CYCLE (%)
450400350300
5
10
15
20
25
30
35
40
45
0
250 500
VSS = 0.5V
SOFT-START CHARGING CURRENT
vs. TEMPERATURE
MAX5974A/B/C/D toc10
TEMPERATURE (°C)
SOFT-START CHARGING CURRENT (µA)
603510-15
9.98
9.99
10.00
10.01
10.02
10.03
10.04
10.05
10.06
9.97
-40 85
MAXIMUM DUTY CYCLE
vs. VSS
MAX5974A/B/C/D toc17
VSS (V)
MAXIMUM DUTY CYCLE (%)
2.01.51.00.5
10
20
30
40
50
60
70
80
90
100
0
0 2.5
MAXIMUM DUTY CYCLE
vs. VDCLMP
MAX5974A/B/C/D toc18
VDCLMP (V)
MAXIMUM DUTY CYCLE (%)
2.01.51.00.5
10
20
30
40
50
60
70
80
90
100
0
0 2.5
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Operating Characteristics (continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 17V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP =
VGND, VEN = 2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kΩ, RDT = 25kΩ, unless otherwise noted.)
DEAD TIME vs. TEMPERATURE
MAX5974A/B/C/D toc20
TEMPERATURE (°C)
DEAD TIME (ns)
11085603510-15
90
92
94
96
98
100
102
88
-40
PEAK CURRENT-LIMIT THRESHOLD
vs. TEMPERATURE
MAX5974A/B/C/D toc21
TEMPERATURE (°C)
PEAK CURRENT-LIMIT THRESHOLD (mV)
603510-15
389
390
391
392
393
394
395
396
397
398
388
-40 85
REVERSE CURRENT-LIMIT THRESHOLD
vs. TEMPERATURE
MAX5974A/B/C/D toc22
TEMPERATURE (°C)
REVERSE CURRENT-LIMIT THRESHOLD (mV)
603510-15
-106
-105
-104
-103
-102
-101
-100
-99
-98
-97
-107
-40 85
SLOPE COMPENSATION CURRENT
vs. TEMPERATURE
MAX5974A/B/C/D toc23
TEMPERATURE (°C)
SLOPE COMPENSATION CURRENT (mA)
6035-15 10
50.5
51.0
51.5
52.0
53.0
52.5
53.5
54.0
50.0
-40 85
NDRV MINIMUM ON-TIME
vs. TEMPERATURE
MAX5974A/B/C/D toc24
TEMPERATURE (°C)
NDRV MINIMUM ON-TIME (ns)
603510-15
145
150
155
160
165
170
140
-40 85
CURRENT-SENSE GAIN
vs. TEMPERATURE
MAX5974A/B/C/D toc25
TEMPERATURE (°C)
CURRENT-SENSE GAIN (V/V)
603510-15
3.31
3.32
3.33
3.34
3.35
3.36
3.37
3.38
3.39
3.40
3.30
-40 85
DEAD TIME vs. RDT VALUE
MAX5974A/B/C/D toc19
RDT VALUE (kΩ)
DEAD TIME (ns)
908020 30 40 6050 70
50
100
150
200
250
300
350
400
0
10 100
FEEDBACK VOLTAGE
vs. TEMPERATURE
MAX5974A/B/C/D toc26
TEMPERATURE (°C)
FEEDBACK VOLTAGE (V)
603510-15
1.211
1.212
1.213
1.214
1.215
1.216
1.217
1.218
1.219
1.220
1.210
-40 85
MAX5974C/MAX5974D
FEEDBACK VOLTAGE
vs. TEMPERATURE
MAX5974A/B/C/D toc27
TEMPERATURE (°C)
FEEDBACK VOLTAGE (V)
603510-15
1.517
1.518
1.519
1.520
1.521
1.522
1.516
-40 85
Maxim Integrated
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Operating Characteristics (continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 17V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP =
VGND, VEN = 2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kΩ, RDT = 25kΩ, unless otherwise noted.)
TRANSCONDUCTANCE HISTOGRAM
(MAX5974A/MAX5974B)
MAX5974A/B/C/D toc29
TRANSCONDUCTANCE (mS)
N (%)
2.642.622.602.582.562.542.522.502.482.46
5
10
15
20
25
0
2.44
TRANSCONDUCTANCE HISTOGRAM
(MAX5974C/MAX5974D)
MAX5974A/B/C/D toc30
TRANSCONDUCTANCE (mS)
N (%)
2.762.742.722.702.682.662.642.622.602.58
5
10
15
20
25
0
2.56
ENABLE RESPONSE
MAX5974A/B/C/D toc31
VEN
5V/div
VNDRV
10V/div
VAUXDRV
10V/div
VOUT
5V/div
200µs/div
SHUTDOWN RESPONSE
MAX5974A/B/C/D toc32
100µs/div
VEN
5V/div
VNDRV
10V/div
VAUXDRV
10V/div
VOUT
5V/div
VSS RAMP RESPONSE
MAX5974A/B/C/D toc33
10µs/div
VSS
2V/div
VNDRV
10V/div
VAUXDRV
10V/div
TRANSCONDUCTANCE
vs. TEMPERATURE
MAX5974A/B/C/D toc28
TEMPERATURE (°C)
TRANSCONDUCTANCE (mS)
603510-15
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
2.0
-40 85
MAX5974C/MAX5974D
MAX5974A/MAX5974B
VDCLMP RAMP RESPONSE
MAX5974A/B/C/D toc34
10µs/div
VDCLMP
2V/div
VNDRV
10V/div
VAUXDRV
10V/div
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Operating Characteristics (continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 17V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP =
VGND, VEN = 2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kΩ, RDT = 25kΩ, unless otherwise noted.)
NDRV 90% TO 10% FALL TIME
MAX5974A/B/C/D toc36
10ns/div
VNDRV
2V/div
0ns
13.8ns
AUXDRV 10% TO 90% RISE TIME
MAX5974A/B/C/D toc37
10ns/div
VAUXDRV
2V/div
0ns
45.6ns
AUXDRV 90% TO 10% FALL TIME
MAX5974A/B/C/D toc38
10ns/div
VAUXDRV
2V/div
0ns
21ns
PEAK NDRV CURRENT
MAX5974A/B/C/D toc39
200ns/div
INDRV
0.5A/div
PEAK SOURCE CURRENT
PEAK SINK CURRENT
PEAK AUXDRV CURRENT
MAX5974A/B/C/D toc40
400ns/div
IAUXDRV
0.2A/div
PEAK SOURCE
CURRENT
PEAK SINK CURRENT
NDRV 10% TO 90% RISE TIME
MAX5974A/B/C/D toc35
10ns/div
VNDRV
2V/div
0ns
27.6ns
SHORT-CURRENT BEHAVIOR
MAX5974A/B/C/D toc41
VIN
5V/div
15V
5V
VNDRV
10V/div
VCS
500mV/div
40ms/div
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11
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Operating Characteristics (continued)
PIN NAME FUNCTION
1 DT
Dead-Time Programming Resistor Connection. Connect resistor RDT from DT to GND to set the
desired dead time between the NDRV and AUXDRV signals. See the Dead Time section to calculate
the resistor value for a particular dead time.
2DITHER/
SYNC
Frequency Dithering Programming or Synchronization Connection. For spread-spectrum frequency
operation, connect a capacitor from DITHER to GND and a resistor from DITHER to RT. To
synchronize the internal oscillator to the externally applied frequency, connect DITHER/SYNC to the
synchronization pulse.
3RT
Switching Frequency Programming Resistor Connection. Connect resistor RRT from RT to GND to set
the PWM switching frequency. See the Oscillator/Switching Frequency section to calculate the resistor
value for the desired oscillator frequency.
4 FFB
Frequency Foldback Threshold Programming Input. Connect a resistor from FFB to GND to set the
output average current threshold below which the converter folds back the switching frequency to 1/2
of its original value. Connect to GND to disable frequency foldback.
5 COMP
Transconductance Amplier Output and PWM Comparator Input. COMP is level shifted down and
connected to the inverting input of the PWM comparator. COMP is actively pulled low by the controller
after shutdown.
1516 14 13
5 6 7
RT
FFB
8
DT
PGND
CS
AUXDRV
1
3
EN
4
12
10
9
DCLMP
SS
CSSC
GND
FB
COMP
EP
MAX5974A
MAX5974B
MAX5974C
MAX5974D
DITHER/
SYNC NDRV
211
IN
16 TQFN
(3mm x 3mm)
TOP VIEW
+
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Pin Description
Pin Conguration
PIN NAME FUNCTION
6 FB Transconductance Amplier Inverting Input
7 GND Signal Ground
8 CSSC Current Sense with Slope Compensation Input. A resistor connected from CSSC to CS programs the
amount of slope compensation. See the Programmable Slope Compensation section.
9 CS Current-Sense Input. Current-sense connection for average current sense and cycle-by-cycle current
limit. Peak current-limit trip voltage is 400mV and reverse current-limit trip voltage is -100mV.
10 PGND Power Ground. PGND is the return path for gate-driver switching currents.
11 NDRV Main Switch Gate-Driver Output
12 AUXDRV pMOS Active Clamp Switch Gate-Driver Output. AUXDRV can also be used to drive a pulse
transformer for synchronous yback application.
13 IN Converter Supply Input. IN has wide UVLO hysteresis, enabling the design of efcient power supplies.
See the Enable Input section to determine if an external zener diode is required at IN.
14 EN
Enable Input. The gate drivers are disabled and the device is in a low-power UVLO mode when the
voltage on EN is below VENF. When the voltage on EN is above VENR, the device checks for other
enable conditions. See the Enable Input section for more information about interfacing to EN.
15 DCLMP
Feed-Forward Maximum Duty-Cycle Clamp Programming Input. Connect a resistive divider between
the input supply voltage DCLMP and GND. The voltage at DCLMP sets the maximum duty cycle
(DMAX) of the converter inversely proportional to the input supply voltage, so that the MOSFET
remains protected during line transients.
16 SS
Soft-Start Programming Capacitor Connection. Connect a capacitor from SS to GND to program the
soft-start period. This capacitor also determines hiccup mode current-limit restart time. A resistor from
SS to GND can also be used to set the DMAX below 75%.
— EP Exposed Pad. Internally connected to GND. Connect to a large ground plane to maximize thermal
performance. Not intended as an electrical connection point.
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Pin Description (continued)
DRIVER
1A/-0.65A
DEAD-TIME
CONTROL
11NDRV
SS16
CS9
CSSC8
COMP5
FB6
IN13
EN14
VC
PGND
DRIVER
0.5A/-0.3A
12
AUXDRV
1DT
3
15
4
20% < DMAX < 80%
RT
DCLMP
FFB
SYNC
VB
30µA/
90µA
NDRV
BLANKING
PULSE
SS
VC
PGND
FFB COMP
VCSAVG
DEAD TIME
NDRV
AUXDRV
POK
OSCILLATOR
DRIVER LOGIC
REVERSE ILIM LIMIT TURNS
OFF AUX IMMEDIATELY
PEAK ILIM
COMP
400mV
2
DITHE
R/
SYNC
7GND
10PGND
VB
50µA/
-50µA
2V/400mV
10X
QSET
QCLR
SCOUNT 8
EVENTS
HICCUP
LATCH
115ns
BLANKING
5V
REGULATOR
ENABLE
1.215V
18V
POK
VB
THERMAL
SHUTDOWN
UVLO
115ns
BLANKING
R
VSS < 150mV
REVERSE ILIM COMP
-100mV
2µA
10µA
2mA
POK
PWM
COMP
R1
2 x R1
VB
S/H
1.52V
VB
VB
gM
VB SLOPE
COMPENSATION
LOW-POWER UVLO
VINUVR = 16V (MAX5974A)
VINUVR = 8.4V (MAX5974B)
VINUVF = 7V
MAX5974A
MAX5974B
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14
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Block Diagrams
DRIVER
1A/-0.65A
DEAD-TIME
CONTROL
11NDRV
SS16
CS9
CSSC8
COMP5
FB6
IN13
EN14
VC
PGND
DRIVER
0.5A/-0.3A
12
AUXDRV
1DT
3
15
4
20% < DMAX < 80%
RT
DCLMP
FFB
SYNC
VB
30µA/
90µA
NDRV
BLANKING
PULSE
SS
VC
PGND
FFB COMP
VCSAVG
DEAD TIME
NDRV
AUXDRV
POK
OSCILLATOR
DRIVER LOGIC
REVERSE ILIM LIMIT TURNS
OFF AUX IMMEDIATELY
PEAK ILIM
COMP
400mV
2
DITHE
R/
SYNC
7GND
10PGND
VB
50µA/
-50µA
2V/400mV
10X
QSET
QCLR
SCOUNT 8
EVENTS
HICCUP
LATCH
115ns
BLANKING
5V
REGULATOR
ENABLE
1.215V
POK
VB
THERMAL
SHUTDOWN
UVLO
115ns
BLANKING
R
VSS < 150mV
REVERSE ILIM COMP
-100mV
2µA
10µA
2mA
POK
PWM
COMP
R1
2 x R1
VB
1.215V
VB
VB
gM
VB SLOPE
COMPENSATION
LOW-POWER UVLO
VINUVR = 16V (MAX5974C)
VINUVR = 8.4V (MAX5974D)
VINUVF = 7V
MAX5974C
MAX5974D
18V
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15
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Block Diagrams (continued)
Detailed Description
The MAX5974A/MAX5974B/MAX5974C/MAX5974D are
optimized for controlling a 25W to 50W active-clamped,
self-driven synchronous rectification forward converter in
continuous-conduction mode. The main switch gate driver
(NDRV) and the active-clamped switch driver (AUXDRV)
are sized to optimize efficiency for 25W design. The
features-rich devices are ideal for PoE IEEE 802.3af/at-
powered devices.
The MAX5974A/MAX5974C offer a 16V bootstrap UVLO
wake-up level with a 9V wide hysteresis. The low startup
and operating currents allow the use of a smaller storage
capacitor at the input without compromising startup and
hold times. The MAX5974A/MAX5974C are well-suited
for universal input (rectified 85V AC to 265V AC) or tele-
com (-36V DC to -72V DC) power supplies.
The MAX5974B/MAX5974D have a UVLO rising threshold
of 8.4V and can accommodate for low-input voltage (12V
DC to 24V DC) power sources such as wall adapters.
Power supplies designed with the MAX5974A/MAX5974C
use a high-value startup resistor, RIN, that charges a res-
ervoir capacitor, CIN (see the Typical Application Circuits).
During this initial period, while the voltage is less than
the internal bootstrap UVLO threshold, the device typi-
cally consumes only 100µA of quiescent current. This low
startup current and the large bootstrap UVLO hysteresis
help to minimize the power dissipation across RIN even at
the high end of the universal AC input voltage (265V AC).
Feed-forward maximum duty-cycle clamping detects
changes in line conditions and adjusts the maximum duty
cycle accordingly to eliminate the clamp voltage’s (i.e.,
the main power FET’s drain voltage) dependence on the
input voltage.
For EMI-sensitive applications, the programmable fre-
quency dithering feature allows up to ±10% variation in
the switching frequency. This spread-spectrum modula-
tion technique spreads the energy of switching harmonics
over a wider band while reducing their peaks, helping to
meet stringent EMI goals.
The devices include a cycle-by-cycle current limit that
turns off the main and AUX drivers whenever the internal-
ly set threshold of 400mV is exceeded. Eight consecutive
occurrences of current-limit events trigger hiccup mode,
which protects external components by halting switching
for a period of time (tRSTRT) and allowing the overload
current to dissipate in the load and body diode of the syn-
chronous rectifier before soft-start is reattempted.
The reverse current-limit feature of the devices turns the
AUX driver off for the remaining off period when VCS
exceeds the -100mV threshold. This protects the trans-
former core from saturation due to excess reverse current
under some extreme transient conditions.
Current-Mode Control Loop
The advantages of current-mode control over voltage-
mode control are twofold. First, there is the feed-forward
characteristic brought on by the controller’s ability to
adjust for variations in the input voltage on a cycle-by-
cycle basis. Second, the stability requirements of the cur-
rent-mode controller are reduced to that of a single-pole
system, unlike the double pole in voltage-mode control.
The devices use a current-mode control loop where the
scaled output of the error amplifier (COMP) is compared
to a slope-compensated current-sense signal at CSSC.
Input Clamp
When the device is enabled, an internal 18V input clamp
is active. During an overvoltage condition, the clamp pre-
vents the voltage at the supply input IN from rising above
18.5V (typ).
When the device is disabled, the input clamp circuitry is
also disabled.
Enable Input
The enable input is used to enable or disable the device.
Driving EN low disables the device. Note that the inter-
nal 18V input clamp is also disabled when EN is low.
Therefore, an external 18V zener diode is needed for
certain operating conditions as described below.
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
UVLO on Power Source
The enable input has an accurate threshold of 1.26V
(max). For applications that require a UVLO on the
power source, connect a resistive divider from the power
source to EN to GND as shown in Figure 1. A zener diode
between IN and GND is required to prevent the NDRV
and AUXDRV gate-drive voltages from exceeding 20V,
the maximum allowed gate voltage of power FETs.
The external zener diode should clamp in the following
range:
>>
Z UVLO(MAX)
20V V V
where VZ is the zener voltage and VUVLO(MAX) is the
maximum wakeup level (16.5V or 8.85V depending on the
device version). An 18V zener diode is the best choice.
Design the resistive divider by first selecting the value of
REN1 to be on the order of 100kΩ. Then calculate REN2
as follows:
= × _
EN(MAX)
EN2 EN1 S(UVLO) EN(MAX)
V
VR VV
where VEN(MAX) is the maximum enable threshold volt-
age and is equal to 1.26V and VS(UVLO) is the desired
UVLO threshold for the power source, below which the
device is disabled.
The digital output connected to EN should be capable of
withstanding more than the maximum supply voltage.
MCU Control of Enable Input
When using a microcontroller GPIO to control the enable
input, an 18V zener diode is required on IN as shown in
Figure 2.
High-Voltage Logic Control of Enable Input
In the case where EN is externally controlled by a high-
voltage open-drain/collector output (e.g., PGOOD indi-
cator of a powered device controller), connect IN to EN
through a resistor REN and connect EN to an open-drain
or open-collector output as shown in Figure 3. Select REN
such that the voltage at IN, when EN is low, is less than
20V (i.e., the maximum gate voltage of the main and AUX
FETs):
×<
+
EN
S(MAX)
EN IN
R
V 20V
RR
where VS(MAX) is the maximum supply voltage. Obeying
this relationship eliminates the need for an external zener
diode.
The digital output connected to EN should be capable of
withstanding more than 20V.
Figure 1. Programmable UVLO for the Power Source Figure 2. MCU Control of the Enable Input
RIN
VS
REN1
DIGITAL
CONTROL
IN
EN
18V
REN2
CIN
N
MAX5974
CIN
18V
IN
RIN
VS
IN
EN
MCU
I/O
MAX5974_
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Always-On Operation
For always-on operation, connect EN to IN as shown
in Figure 4. No external zener diode is needed for this
configuration.
Bootstrap Undervoltage Lockout
The devices have an internal bootstrap UVLO that is very
useful when designing high-voltage power supplies (see
the Block Diagrams). This allows the device to bootstrap
itself during initial power-up. The MAX5974A/MAX5974C
soft-start when VIN exceeds the bootstrap UVLO thresh-
old of VINUVR (16V typ).
Because the MAX5974B/MAX5974D are designed for
use with low-voltage power sources such as wall adapters
outputting 12V to 24V, they have a lower UVLO wake-up
threshold of 8.4V.
Startup Operation
The device starts up when the voltage at IN exceeds 16V
(MAX5974A/MAX5974C) or 8.4V (MAX5974B/MAX5974D)
and the enable input voltage is greater than 1.26V.
During normal operation, the voltage at IN is nor-
mally derived from a tertiary winding of the transformer
(MAX5974C/MAX5974D). However, at startup there is no
energy being delivered through the transformer; hence,
a special bootstrap sequence is required. In the Typical
Application Circuits, CIN charges through the startup
resistor, RIN, to an intermediate voltage. Only 100µA of
the current supplied through RIN is used by the ICs, the
remaining input current charges CIN until VIN reaches the
bootstrap UVLO wake-up level. Once VIN exceeds this
level, NDRV begins switching the n-channel MOSFET
and transfers energy to the secondary and tertiary out-
puts. If the voltage on the tertiary output builds to higher
than 7V (the bootstrap UVLO shutdown level), then start-
up has been accomplished and sustained operation com-
mences. If VIN drops below 7V before startup is complete,
the device goes back to low-current UVLO. In this case,
increase the value of CIN in order to store enough energy
to allow for the voltage at the tertiary winding to build up.
While the MAX5974A/MAX5974B derive their input volt-
age from the coupled inductor output during normal
operation, the startup behavior is similar to that of the
MAX5974C/MAX5974D.
Soft-Start
A capacitor from SS to GND, CSS, programs the soft-start
time. VSS controls the oscillator duty cycle during startup
to provide a slow and smooth increase of the duty cycle
to its steady-state value. Calculate the value of CSS as
follows:
×
=SS-CH SS
SS
It
C
2V
where ISS-CH (10µA typ) is the current charging CSS dur-
ing soft-start and tSS is the programmed soft-start time.
A resistor can also be added from the SS pin to GND to
clamp VSS < 2V and, hence, program the maximum duty
cycle to be less than 80% (see the Duty-Cycle Clamping
section)
Figure 3. High-Voltage Logic Control of the Enable Input
Figure 4. Always-On Operation
VS
RIN
IN
EN
CIN
MAX5974
DIGITAL
CONTROL
N
REN
CIN
IN
EN
RIN
VS
MAX5974_
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
n-Channel MOSFET Gate Driver
The NDRV output drives an external n-channel MOSFET.
NDRV can source/sink in excess of 650mA/1000mA
peak current; therefore, select a MOSFET that yields
acceptable conduction and switching losses. The external
MOSFET used must be able to withstand the maximum
clamp voltage.
p-Channel MOSFET Gate Driver
The AUXDRV output drives an external p-channel
MOSFET with the aid of a level shifter. The level shifter
consists of CAUX, RAUX, and D5 as shown in the Typical
Application Circuits. When AUXDRV is high, CAUX is
recharged through D5. When AUXDRV is low, the gate of
the p-channel MOSFET is pulled below the source by the
voltage stored on CAUX, turning on the pFET.
Add a zener diode between gate to source of the external
n-channel and p-channel MOSFETs after the gate resis-
tors to protect VGS from rising above its absolute maxi-
mum rating during transient condition (see the Typical
Application Circuits).
Dead Time
Dead time between the main and AUX output edges allow
ZVS to occur, minimizing conduction losses and improv-
ing efficiency. The dead time (tDT) is applied to both lead-
ing and trailing edges of the main and AUX outputs as
shown in Figure 5. Connect a resistor between DT and
GND to set tDT to any value between 40ns and 400ns:
Ω
= ×
DT DT
10k
Rt
40ns
Oscillator/Switching Frequency
The ICs’ switching frequency is programmable between
100kHz and 600kHz with a resistor RRT connected
between RT and GND. Use the following formula to deter-
mine the appropriate value of RRT needed to generate the
desired output-switching frequency (fSW):
×
=
9
RT
SW
8.7 10
Rf
where fSW is the desired switching frequency.
Figure 5. Dead Time Between AUXDRV and NDRV
BLANKING, tBLK
NDRV
AUXDRV
DEAD TIME, tDT
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Peak Current Limit
The current-sense resistor (RCS in the Typical Application
Circuits), connected between the source of the n-channel
MOSFET and PGND, sets the current limit. The current-
limit comparator has a voltage trip level (VCS-PEAK) of
400mV. Use the following equation to calculate the value
of RCS:
=
CS
PRI
400mV
RI
where IPRI is the peak current in the primary side of the
transformer, which also flows through the MOSFET. When
the voltage produced by this current (through the current-
sense resistor) exceeds the current-limit comparator
threshold, the MOSFET driver (NDRV) terminates the
current on-cycle, within 35ns (typ).
The devices implement 115ns of leading-edge blanking
to ignore leading-edge current spikes. These spikes are
caused by reflected secondary currents, current-discharg-
ing capacitance at the FET’s drain, and gate-charging cur-
rent. Use a small RC network for additional filtering of the
leading-edge spike on the sense waveform when needed.
Set the corner frequency between 10MHz and 20MHz.
After the leading-edge blanking time, the device monitors
VCS for any breaches of the peak current limit of 400mV.
The duty cycle is terminated immediately when VCS
exceeds 400mV.
Reverse Current Limit
The devices protect the transformer against saturation
due to reverse current by monitoring the voltage across
RCS while the AUX output is low and the p-channel FET
is on.
Output Short-Circuit Protection
with Hiccup Mode
When the device detects eight consecutive peak current-
limit events, both NDRV and AUXDRV driver outputs are
turned off for a restart period, tRSTRT. After tRSTRT, the
device undergoes soft-start. The duration of the restart
period depends on the value of the capacitor at SS (CSS).
During this period, CSS is discharged with a pulldown cur-
rent of ISS-DH (2µA typ). Once its voltage reaches 0.15V,
the restart period ends and the device initiates a soft-start
sequence. An internal counter ensures that the minimum
restart period (tRSTRT-MIN) is 1024 clock cycles when the
time required for CSS to discharge to 0.15V is less than
1024 clock cycles. Figure 6 shows the behavior of the
device prior and during hiccup mode.
Frequency Foldback for High-Eciency
Light-Load Operation
The frequency foldback threshold can be programmed
from 0 to 20% of the full load current using a resistor from
FFB to GND.
Figure 6. Hiccup Mode Timing Diagram
VCSBL
(BLANKED CS
VOLTAGE)
VCS-PEAK
(400mV)
HICCUP
DISCHARGE WITH ISS-DH
VSS-DTH
SOFT-START
VOLTAGE,
VSS
VSS-HI
tRSTRT
tSS
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20
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
When VCSAVG falls below VFFB, the device folds back
the switching frequency to 1/2 the original value to reduce
switching losses and increase the converter efficiency.
Calculate the value of RFFB as follows:
××
=LOAD(LIGHT) CS
FFB
FFB
10 I R
RI
where RFFB is the resistor between FFB and GND,
ILOAD(LIGHT) is the current at light-load conditions that
triggers frequency foldback, RCS is the value of the sense
resistor connected between CS and PGND, and IFFB is
the current sourced from FFB to RFFB (30µA typ).
Duty-Cycle Clamping
The maximum duty cycle is determined by the lowest
of three voltages: 2V, the voltage at SS (VSS), and the
voltage (2.43V - VDCLMP). The maximum duty cycle is
calculated as:
=MIN
MAX
V
D
2.43V
where VMIN = minimum (2V, VSS, 2.43V - VDCLMP).
SS
By connecting a resistor between SS and ground, the
voltage at SS can be made to be lower than 2V. VSS is
calculated as follows:
= ×
SS SS SS-CH
VRI
where RSS is the resistor connected between SS and
GND, and ISS-CH is the current sourced from SS to RSS
(10µA typ).
DCLMP
To set DMAX using supply voltage feed-forward, connect
a resistive divider between the supply voltage, DCLMP,
and GND as shown in the Typical Application Circuits.
This feed-forward duty-cycle clamp ensures that the
external n-channel MOSFET is not stressed during supply
transients. VDCLMP is calculated as follows:
= ×
+
DCLMP2
DCLMP S
DCLMP1 DCLMP2
R
VV
RR
where RDCLMP1 and RDCLMP2 are the resistive divider
values shown in the Typical Application Circuits and VS is
the input supply voltage.
Oscillator Synchronization
The internal oscillator can be synchronized to an external
clock by applying the clock to DITHER/SYNC directly. The
external clock frequency can be set anywhere between
1.1x to 2x the internal clock frequency.
Using an external clock increases the maximum duty
cycle by a factor equal to fSYNC/fSW. This factor should
be accounted for in setting the maximum duty cycle using
any of the methods described in the Duty-Cycle Clamping
section. The formula below shows how the maximum duty
cycle is affected by the external clock frequency:
= × SYNC
MIN
MAX SW
f
V
D2.43V f
where VMIN is described in the Duty-Cycle Clamping sec-
tion, fSW is the switching frequency as set by the resistor
connected between RT and GND, and fSYNC is the exter-
nal clock frequency.
Frequency Dithering for Spread-
Spectrum Applications (Low EMI)
The switching frequency of the converter can be dith-
ered in a range of ±10% by connecting a capacitor from
DITHER/SYNC to GND, and a resistor from DITHER/
SYNC to RT as shown in the Typical Application Circuits.
This results in lower EMI.
A current source at DITHER/SYNC charges the capacitor
CDITHER to 2V at 50µA. Upon reaching this trip point, it
discharges CDITHER to 0.4V at 50µA. The charging and
discharging of the capacitor generates a triangular wave-
form on DITHER/SYNC with peak levels at 0.4V and 2V
and a frequency that is equal to:
=×
TRI
DITHER
50µA
fC 3.2V
Typically, fTRI should be set close to 1kHz. The resistor
RDITHER connected from DITHER/SYNC to RT deter-
mines the amount of dither as follows:
= × RT
DITHER
R
4
%DITHER 3R
where %DITHER is the amount of dither expressed as a
percentage of the switching frequency. Setting RDITHER
to 10 x RRT generates ±10% dither.
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Programmable Slope Compensation
The device generates a current ramp at CSSC such that
its peak is 50µA at 80% duty cycle of the oscillator. An
external resistor connected from CSSC to the CS then
converts this current ramp into programmable slope-
compensation amplitude, which is added to the current-
sense signal for stability of the peak current-mode control
loop. The ramp rate of the slope compensation signal is
given by:
××
=CSSC SW
R 50µA f
m
80%
where m is the ramp rate of the slope-compensation sig-
nal, RCSSC is the value of the resistor connected between
CSSC and CS used to program the ramp rate, and fSW is
the switching frequency.
Error Amplier
The MAX5974A/MAX5974B include an internal error
amplifier with a sample-and-hold input. The feedback
input of the MAX5974C/MAX5974D is continuously con-
nected. The noninverting input of the error amplifier is
connected to the internal reference and feedback is
provided at the inverting input. High open-loop gain and
unity-gain bandwidth allow good closed-loop bandwidth
and transient response. Calculate the power-supply out-
put voltage using the following equation:
+
= × FB1 FB2
OUT REF FB2
RR
VV R
where VREF = 1.52V for the MAX5974A/MAX5974B and
VREF = 1.215V for the MAX5974C/MAX5974D. The
amplifier’s noninverting input is internally connected to a
soft-start circuit that gradually increases the reference
voltage during startup. This forces the output voltage to
come up in an orderly and well-defined manner under all
load conditions.
Applications Information
Startup Time Considerations
The bypass capacitor at IN, CIN, supplies current imme-
diately after the devices wake up (see the Typical
Application Circuits). Large values of CIN increase the
startup time, but also supply gate charge for more cycles
during initial startup. If the value of CIN is too small, VIN
drops below 7V because NDRV does not have enough
time to switch and build up sufficient voltage across the
tertiary output (MAX5974C/MAX5974D) or coupled induc-
tor output (MAX5974A/MAX5974B), which powers the
device. The device goes back into UVLO and does not
start. Use a low-leakage capacitor for CIN.
Typically, offline power supplies keep startup times to less
than 500ms even in low-line conditions (85V AC input
for universal offline or 36V DC for telecom applications).
Size the startup resistor, RIN, to supply both the maxi-
mum startup bias of the device (150µA) and the charg-
ing current for CIN. CIN must be charged to 16V within
the desired 500ms time period. CIN must store enough
charge to deliver current to the device for at least the
soft-start time (tSS) set by CSS. To calculate the approxi-
mate amount of capacitance required, use the following
formula:
=
+
=
G GTOT SW
IN G SS
IN
HYST
IQ f
(I I )(t )
CV
where IIN is the ICs’ internal supply current (1.8mA) after
startup, QGTOT is the total gate charge for the n-channel
and p-channel FETs, fSW is the ICs’ switching frequency,
VHYST is the bootstrap UVLO hysteresis (9V typ), and tSS
is the soft-start time. RIN is then calculated as follows:
−
≅S(MIN) INUVR
IN
START
VV
RI
where VS(MIN) is the minimum input supply voltage for the
application (36V for telecom), VINUVR is the bootstrap
UVLO wake-up level (16V), and ISTART is the IN supply
current at startup (150µA max).
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Choose a higher value for RIN than the one calculated
above if a longer startup time can be tolerated in order to
minimize power loss on this resistor.
Active Clamp Circuit
Traditional clamp circuits prevent transformer satura-
tion by channeling the magnetizing current (IM) of the
transformer onto a dissipative RC network. To improve
efficiency, the active clamp circuit recycles IM between the
magnetizing inductance and clamp capacitor. VCLAMP is
given by:
−
=S
CLAMP
V
V
1D
where VS is the voltage of the power source and D is
the duty cycle. To select n-channel and p-channel FETs
with adequate breakdown voltages, use the maximum
value of VCLAMP. VCLAMP(MAX) occurs when the input
voltage is at its minimum and the duty cycle is at its
maximum. VCLAMP(MAX-NORMAL) during normal opera-
tion is therefore:
−
=×
×
S(MIN)
CLAMP(MAX-NORMAL) PO
S S(MIN)
V
VNV
1NV
where VS(MIN) is the minimum voltage of the power
source, NP/NS is the primary to secondary turns ratio, and
VO is the output voltage. The clamp capacitor, n-channel,
and p-channel FETs must have breakdown voltages
exceeding this level.
If feed-forward maximum duty-cycle clamp is used then:
= = −
=−×
+
DCLMP
MIN
MAX-FF
S DCLMP2
DCLMP1 DCLMP2
V
V
D1
2.43 2.43
VR
12.43 R R
Therefore, VCLAMP(MAX-FF) during feed-forward maxi-
mum duty clamp is:
( )
−
=−
×+
=
S
CLAMP(MAX-FF) MAX FF
DCLMP1 DCLMP2
DCLMP2
V
V1D
2.43 R R
R
The AUX driver controls the p-channel FET through a
level shifter. The level shifter consists of an RC network
(formed by CAUX and RAUX) and diode D5, as shown in
the Typical Application Circuits. Choose RAUX and CAUX
so that the time constant exceeds 100/fSW. Diode D5 is
a small-signal diode with a voltage rating exceeding 25V.
Additionally, CCLAMP should be chosen such that the
complex poles formed with magnetizing inductance
(LMAG) and CCLAMP are 2x to 4x away from the loop
bandwidth:
>×
π× BW
MAG CLAMP
1-D 3f
2L C
Bias Circuit
Optocoupler Feedback (MAX5974C/MAX5974D)
An in-phase tertiary winding is needed to power the bias
circuit when using optocoupler feedback. The voltage
across the tertiary VT during the on-time is:
= × T
TOUT
S
N
VV N
where VOUT is the output voltage and NT/NS is the turns
ratio from the tertiary to the secondary winding. Select the
turns ratio so that VT is above the UVLO shutdown level
(7.35V max) by a margin determined by the holdup time
needed to “ride through” a brownout.
Coupled-Inductor Feedback (MAX5974A/MAX5974B)
When using coupled-inductor feedback, the power for
the devices can be taken from the coupled inductor dur-
ing the off-time. The voltage across the coupled inductor,
VCOUPLED, during the off-time is:
= × C
COUPLED OUT
O
N
VV
N
where VOUT is the output voltage and NC/NO is the turns
ratio from the coupled output to the main output winding.
Select the turns ratio so that VCOUPLED is above the
UVLO shutdown level (7.5V max) by a margin determined
by the holdup time needed to “ride through” a brownout.
This voltage appears at the input of the devices, less
a diode drop. An RC network consisting of RSNUB and
CSNUB is for damping the reverse recovery transients of
diode D6.
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
During on-time, the coupled output is:
−=−×
SC
COUPLED-ON OUT
S
PO
NN
V (V V )
NN
where VS is the input supply voltage.
Care must be taken to ensure that the voltage at FB
(equal to VCOUPLED-ON attenuated by the feedback
resistive divider) is not more than 5V:
( )
= ×<
+
FB2
FB-ON COUPLED-ON
FB1 FB2
R
V V 5V
RR
If this condition is not met, a signal diode should be
placed from GND (anode) to FB (cathode).
Layout Recommendations
Typically, there are two sources of noise emission in a
switching power supply: high di/dt loops and high dV/dt
surfaces. For example, traces that carry the drain current
often form high di/dt loops. Similarly, the heatsink of the
main MOSFET presents a dV/dt source; therefore, mini-
mize the surface area of the MOSFET heatsink as much
as possible. Keep all PCB traces carrying switching cur-
rents as short as possible to minimize current loops. Use
a ground plane for best results.
For universal AC input design, follow all applicable safety
regulations. Offline power supplies can require UL, VDE,
and other similar agency approvals.
Refer to the MAX5974A and MAX5974C Evaluation Kit
data sheets for recommended layout and component
values.
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24
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
IN
EN
DCLMP
DT
DITHER/
SYNC
SS
CIN
1µF
25V
CF
330pF
CCOMP2
6.8pF
RIN
100kΩ
L2
6.8µH
COUT1 COUT2 COUT3 COUT4
COUT5
0.1µF
CBULK
33µF
RDCLMP1
30.1kΩ
1%
PGOOD
ROPTO2
1kΩ
1%
RDCLMP2
750Ω 1%
RDT
16.9kΩ 1%
CSS
0.1µF
D1
D2
D3
NT
L1
3.3mH
T1
VS
36V TO 57V
IN
CDITHER
10nF
FFB
FB
COMP
CS
D5
AUXDRV
CSSC
GND
RT
RFFB
10.0kΩ 1%
RG1
121kΩ 1%
RG2
200kΩ 1%
RCSSC
4.02kΩ 1%
RAUX
10kΩ
RCS
0.2Ω
RGATE3
10Ω
RGATE4
10Ω
RGATE1
10Ω
RGATE2
10Ω
RFB1
7.5kΩ
1%
5V, 5A
RFB2
2.49kΩ
1%
N3
FDS3692
N1
5i412DP
U1
FOD817CSD
N4
IRF6217
N
NPNS
D4
N
CAUX
47nF
CINT
0.1µF
U2
TLV4314AIDBVT-1.24V
CCLAMP
47nF
CCOMP1
2.2nF
ROPTO1
825Ω
1%
RBIAS
4.02kΩ
1%
RRT
14.7kΩ 1%
RF
499Ω 1%
NDRV
PGND
N2
5i412DP
N
RCOMP2
2.00kΩ
1%
P
ROPTO3
4.99kΩ
1% RCOMP2
499Ω
1%
MAX5974C
MAX5974D
(OPTOCOUPLER
FEEDBACK)
REN
100kΩ
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25
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Application Circuits
IN
EN
DCLMP
DT
DITHER/
SYNC
SS
CIN
1µF
25V
RIN
100kΩ
COUT1 COUT2 COUT3 COUT4 COUT5
0.1µF
CBULK
33µF
63V
RDCLMP1
30.1kΩ
1%
RDCLMP2
750Ω 1%
RDT
16.9kΩ 1%
CSS
0.1µF
D3
D6
TO FB
5V, 5A
4 x 47µF
6.3V
LCOUPLED
NC
NO
VS
36V TO 57V
CDITHER
10nF
CINT
47nF
CCOMP
4.7nF
FFB
FB
COMP
CS
D5
AUXDRV
CSSC
GND
RT
RFFB
10kΩ 1%
RZ
2kΩ 1%
RCSSC
4.02kΩ 1%
RAUX
10kΩ
RCS
0.2Ω
RGATE3
10Ω
RGATE4
10Ω
RGATE1
10Ω
RGATE2
10Ω
RSNUB
69.8Ω 1%
RFB1
54.9kΩ 1%
RFB2
10kΩ 1%
CSNUB
10pF
N3
FDS3692
N1
5i412DP
N4
IRF6217
N
NPNS
D4
N
CAUX
47nF
CCLAMP
47nF
RRT
14.7kΩ 1%
NDRV
PGND
N2
5i412DP
N
P
MAX5974A
MAX5974B
(COUPLED INDUCTOR
FEEDBACK)
T1
CF
330pF
RF
499Ω 1%
PGOOD
REN
100kΩ
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26
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Application Circuits (continued)
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
PART TOP MARK PIN-PACKAGE TEMP RANGE UVLO
THRESHOLD (V) FEEDBACK MODE
MAX5974AETE+ +AHY 16 TQFN-EP* -40°C to +105°C 16 Sample/Hold
MAX5974BETE+ +AHZ 16 TQFN-EP* -40°C to +85°C 8.4 Sample/Hold
MAX5974CETE+ +AIA 16 TQFN-EP* -40°C to +85°C 16 Continuously Connected
MAX5974DETE+ +AIB 16 TQFN-EP* -40°C to +85°C 8.4 Continuously Connected
MAX5974DATE+ +AIB 16 TQFN-EP* -40°C to +125°C 8.4 Continuously Connected
IN
EN
DCLMP
DT
DITHER/
SYNC
SS
CIN
RIN
COUT1 COUT2 COUT3 COUT4
CBULK
RDCLMP1
RDCLMP2
RDT
RDITHER
CSS
D3
L2
VS
CDITHER
FFB
FB
COMP
CCOMP CHF
CS
D5
AUXDRV
CSSC
GND
RT
RFFB
Rz
RCSSC
RAUX
RCS
RGATE3
RGATE4
RGATE1
RGATE2
N3
N1
N4
N
NP
T1
NS
D4
N
CAUX
CCLAMP
RRT
NDRV
PGND
N2
N
P
MAX5974C
MAX5974D
D1
D2
NT
L1
RFB1
RFB2
REN
100kΩ
PGOOD
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Application Circuits (continued)
Chip Information
PROCESS: BiCMOS
Ordering Information/Selector Guide
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 6/10 Initial release —
1 9/10
Introduced the MAX5974B/MAX5974D. Updated the Absolute Maximum
Ratings, Electrical Characteristics, Pin Description, the p-Channel MOSFET
Gate Driver, Frequency Foldback for High-Efciency Light-Load Operation
sections, and Typical Application Circuits.
1, 2, 3, 12, 15, 17,
19, 21, 23, 24, 25
2 6/11 Added internal zener diode information 1–10, 12–17, 19–25
3 10/13
Updated COMP function in Pin Description, corrected pin name in UVLO
on Power Source section, corrected Figures 1 and 2, corrected Typical
Application Circuits
11, 16, 24–26
4 10/14 Added MAX5974DATE+ option to Ordering Information, Electrical
Characteristics, and updated Typical Application Circuits 1, 2–5, 25–27
5 7/15
Removed EN from 2nd line in Absolute Maximum Ratings and changed the
1st line under Maximum Input/Output Current (continuous) from IN, NDRV,
AUXDRV to EN
2
6 7/17 Updated Absolute Maximum Ratings section, Electrical Characteristics table,
and Ordering Information table, 2–6, 27
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2017 Maxim Integrated Products, Inc.
│
28
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Revision History
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
