MDT10P21 XTALStandard crystal oscillator 1. General Description HFXTHigh frequency crystal oscillator This EPROM-Based 8-bit micro-controller uses a u 4 oscillator start-up time can be selected by fully static CMOS design technology to achieve high programming option: speed, small size, low power and high noise 150 s, 20 ms, 40 ms, 80 ms u immunity. Timer(WDT) can be operated freely On chip memory includes 0.5K words EPROM and80 u bytes static RAM. On-chip RC oscillator based Watchdog 12 I/O(for 18 pins package),14 I/O(for 20 pins Four comparator inputs with external Vref (not for 18 package),16 I/O(for 22/24 pins package) pins pin package) are also provided. with their own independent direction control 3. Applications 2. Features u Fully CMOS static design The application areas of this MDT10P21 range from u 8-bit data bus appliance motor control and high speed automotive u On chip EPROM size : 0.5 K words to low power remote transmitters/receivers, pointing u Internal RAM size : 80 bytes devices, and telecommunications processors, such (72 general purpose registers, 8 special as Remote controller, small instruments, chargers, registers) toy, automobile and PC peripheral ... etc u 36 single word instructions u 14-bit instructions u 2-level stacks u Operating voltage : 2.3V ~ 5.5 V u Operating frequency : 0 ~ 20 MHz u The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction u Addressing modes include direct, indirect and relative addressing modes u Built-in Power-on Reset u 4 Channel comparator u Power edge-detector Reset u Sleep Mode for power saving u 8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler u 4 types of oscillator can be selected by programming option: RCLow cost RC oscillator LFXTLow frequency crystal oscillator This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 1 2004/1 Ver. 1.3 MDT10P21 4. Pin Assignment A120PINS, A222PINS, A324PINS, A5 :18 PINS PPDIP,SSOP, KSKINNY A1P,A1S A3S PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 NC PA7 PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 NC PA6 PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 A2K PA7 PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 PA6 PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 A5P,A5S PA2CIC2 1 PA3/CIC3 2 RTCC 3 /MCLR 4 Vss 5 PB0 6 PB1 7 PB2 8 PB3 9 18 17 16 15 14 13 12 11 10 PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 2 2004/1 Ver. 1.3 MDT10P21 5. Block Diagram Stack Two Levels Port PB0 ~P B7 8 bits RAM 72x8 EPROM x 0.5K 14 (MDT10P21) Port B 9 bits Program Counters Instruction Register Special Register OS MC OS C1 LR C2 Oscillator Circuit Port PA 0~P A7 (22,24 pins) PA0~P A5 (20 pins) PA0~P A3 Port A (18 pins) 8 bits 14 bits 9 bits D0~D7 Instruction Decoder Control Circuit CMR0~C MR5 Comparat or mode Register Data 8-bit Power on Reset Power Down Reset Working Register Status Register ALU 8-bit Timer/Counter WDT/OST Timer Prescale RTCC This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 3 2004/1 Ver. 1.3 MDT10P21 6. Pin Function Description Pin Name I/O PA0~PA7 I/O Function Description PA0~PA3 : TTL input level or comparator input PA4 : TTL input level or comparator VREF input PA5~PA7 : TTL input level PB0~PB7 I/O Port B, TTL input level RTCC I Real Time Clock/Counter, Schmitt Trigger input levels /MCLR I Master Clear, Schmitt Trigger input levels OSC1 I Oscillator Input OSC2 O Oscillator Output Vdd Power supply Vss Ground NC Unused ,do not connect 7. Memory Map (A) Register Map Address Description 00 Indirect Addressing Register 01 RTCC 02 PC 03 STATUS 04 MSR 05 Port A 06 Port B 07 Control register for comparator 08~0F Internal RAM, General Purpose Register 10~1F Internal RAM, Memory bank 0 30~3F Internal RAM, Memory bank 1 50~5F Internal RAM, Memory bank 2 70~7F Internal RAM, memory bank 3 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 4 2004/1 Ver. 1.3 MDT10P21 (1) IAR ( Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter Register) : R1 (3) PC (Program Counter) : R2 Write PC, CALL --- always 0 LJUMP, JUMP, LCALL --- from instruction word RTIW, RET --- from STACK A8 A7~A0 Write PC --- from ALU LJUMP, JUMP, LCALL, CALL --- from instruction word RTIW, RET --- from STACK (4) STATUS (Status register) : R3 Bit Symbol Function 0 C Carry bit 1 HC Half Carry bit 2 Z Zero bit 3 PF Power loss Flag bit 4 TF Time overflow Flag bit ---- 5-7 General purpose bit (5) MSR (Memory Select Register) : R4 Memory Select Register : 00 : 10~1F 01 : 30~3F 10 : 50~5F 11 : 70~7F b7 b6 b5 b4 b3 b2 b1 b0 Read only "1" Indirect Addressing Mode (6) PORT A : R5 PA7~PA0, I/O Register for 22, 24 pins PA5~PA0, I/O Register for 20 pins PA3~PA0, I/O Register for 18 pins This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 5 2004/1 Ver. 1.3 MDT10P21 (7) PORT B : R6 PB7~PB0, I/O Register (8) CMR(Comparator Mode Register) : R7 Bit 0 Function 0: Define PA0 as TTL input 1: Define PA0 as comparator input 1 0: Define PA1 as TTL input 1: Define PA1 as comparator input 2 0: Define PA2 as TTL input 1: Define PA2 as comparator input 3 0: Define PA3 as TTL input 1: Define PA3 as comparator input 5:4 Reference Voltage select 00: 1/4 VDD 01: 1/2 VDD 10: 3/4 VDD 11: VREF (External pin and PA4 must be set to input) 7:6 Register bits (9) TMR (Time Mode Register) Bit Symbol Function Prescaler Value 2--0 PS2--0 3 PSC 4 TCE 5 TCS RTCC rate WDT rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1 : 16 1:8 1 0 0 1 : 32 1 : 16 1 0 1 1 : 64 1 : 32 1 1 0 1 : 128 1 : 64 1 1 1 1 : 256 1 : 128 Prescaler assignment bit : 0 -- RTCC 1 -- Watchdog Timer RTCC signal Edge : 0 -- Increment on low-to-high transition on RTCC pin 1 -- Increment on high-to-low transition on RTCC pin RTCC signal set : 0 -- Internal instruction cycle clock 1 -- Transition on RTCC pin This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 6 2004/1 Ver. 1.3 MDT10P21 (10) CPIO A, CPIO B (Control Port I/O Mode Register) The CPIO register is "write-only" "0", I/O pin in output mode; "1", I/O pin in input mode. (11) EPROM Option by writer programming : A. FIRST WORD Oscillator Type Oscillator Start-up Time Oscillator 150 s LFXT Oscillator 20 ms XTAL Oscillator 40 ms HFXT Oscillator 80 ms RC Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time Power Edge Detect Security bit PED Disable Security Disable PED Enable Security Enable (B) Program Memory Address Description 000- 1FF Program memory The starting address of the power on, external reset or WDT 1FF 8. Reset Condition for all Registers Register Address Power-On Reset /MCLR Reset WDT Reset CPIO A 1111 1111 1111 1111 1111 1111 CPIO B 1111 1111 1111 1111 1111 1111 TMR --11 1111 --11 1111 --11 1111 IAR 00h RTCC 01h xxxx xxxx uuuu uuuu uuuu uuuu PC 02h 1111 1111 1111 1111 1111 1111 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 7 2004/1 Ver. 1.3 MDT10P21 Register Address Power-On Reset /MCLR Reset WDT Reset STATUS 03h 0001 1xxx 000# #uuu 000# #uuu MSR 04h 100x xxxx 100u uuuu 1uuu uuuu PORT A 05h xxxx xxxx uuuuuuuu uuuu uuuu PORT B 06h xxxx xxxx uuuu uuuu uuuu uuuu CMR 07h 0000 0000 uuuu uuuu uuuu uuuu Note : uunchanged, xunknown, - unimplemented, read as "0" #value depends on the condition of the following table Condition Status: bit 4 Status: bit 3 /MCLR reset (not during SLEEP) U u /MCLR reset during SLEEP 1 0 WDT reset (not during SLEEP) 0 1 WDT reset during SLEEP 0 0 9. Instruction Set Instruction Code Mnemonic Operands Function Operating Status 010000 00000000 NOP No operation None 010000 00000001 CLRWT Clear Watchdog timer 0WT TF, PF 010000 00000010 SLEEP Sleep mode 0WT, stop OSC TF, PF 010000 00000011 TMODE Load W to TMODE register WTMODE None 010000 00000100 RET Return StackPC None 010000 00000rrr CPIO R Control I/O port register WCPIO r None 010001 1rrrrrrr STWR R Store W to register WR None 011000 trrrrrrr LDR R, t Load register Rt Z 111010 iiiiiiii LDWI I Load immediate to W IW None 010111 trrrrrrr SWAPR R, t Swap halves register [R(0~3)R(4~7)]t None 011001 trrrrrrr INCR R, t Increment register R + 1t Z 011010 trrrrrrr INCRSZ R, t Increment register, skip if zero R + 1t None 011011 trrrrrrr ADDWR R, t Add W and register W + Rt C, HC, Z 011100 trrrrrrr SUBWR R, t Subtract W from register R Wt (R+/W+1 t) C, HC, Z 011101 trrrrrrr DECR R, t Decrement register R 1t Z 011110 trrrrrrr DECRSZ R, t Decrement register, skip if zero R 1t None 010010 trrrrrrr ANDWR R, t AND W and register R Wt Z This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 8 2004/1 Ver. 1.3 MDT10P21 Instruction Code Mnemonic Operands Function Operating Status 110100 iiiiiiii ANDWI i AND W and immediate i WW Z 010011 trrrrrrr IORWR R, t Inclu. OR W and register R Wt Z 110101 iiiiiiii IORWI i Inclu. OR W and immediate i WW Z 010100 trrrrrrr XORWR R, t Exclu. OR W and register R Wt Z 110110 iiiiiiii XORWI i Exclu. OR W and immediate i WW Z 011111 trrrrrrr COMR R, t Complement register /Rt Z 010110 trrrrrrr RRR R, t Rotate right register R(n) R(n-1), C R(7), R(0)C C 010101 trrrrrrr RLR R, t Rotate left register R(n)r(n+1), C CR(0), R(7)C 010000 1xxxxxxx CLRW Clear working register 0W Z 010001 0rrrrrrr CLRR Clear register 0R Z 0000bb brrrrrrr BCR R, b Bit clear 0R(b) None 0010bb brrrrrrr BSR R, b Bit set 1R(b) None 0001bb brrrrrrr BTSC R, b Bit Test, skip if clear Skip if R(b)=0 None 0011bb brrrrrrr BTSS R, b Bit Test, skip if set Skip if R(b)=1 None 100nnn nnnnnnnn LCALL n Long CALL subroutine nPC, PC+1Stack None 101nnn nnnnnnnn LJUMP n Long JUMP to address nPC None 110000 nnnnnnnn CALL n Call subroutine nPC, PC+1Stack None 110001 iiiiiiii RTIW i Return, place immediate to W StackPC,iW None 11001n nnnnnnnn JUMP JUMP to address nPC None R n Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive `' Exclusive `' Logic AND `' b t R C HC Z / x i n : : 0 1 : : : : : : : : Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don't care Immediate data ( 8 bits ) Immediate address This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 9 2004/1 Ver. 1.3 MDT10P21 10. Electrical Characteristics (Operating temperature at 25). Sym Description Condition Vdd Operating voltage VIL Min Typ Max Unit 2.3 6.3 V Input Low Voltage PA, PB Vdd=5V -0.6 1.0 V RTCC, /MCLR Vdd=5V -0.6 1.0 V PA, PB Vdd=5V 2.0 Vdd V RTCC, /MCLR Vdd=5V 3.2 Vdd V IIL Input leakage current Vdd=5V +/-1 A VOL Output Low Voltage VIH Input high Voltage PA, PB Vdd=5V, IOL=20mA 0.4 V Vdd=5V, IOL=5mA 0.1 V Vdd=5V, IOH= -20mA 3.8 V Vdd=5V, IOH= -5mA 4.5 V 0.1 VOH Output High Voltage PA, PB A Islp Sleep current (WDT disable) Vdd2.3 ~ 6.3 V Islp Sleep current (WDT enable) Vdd2.3 V 1 A Vdd3.0 V 3 A Vdd4.0 V 8 A Vdd5.0 V 17 A Vdd6.3 V 36 A Vpr Power Edge-detector Reset Voltage Twdt The basic WDT time-out cycle time TFLT /MCLR filter Icc Comparator Supply current (one 1.0 1.1 1.3 V Vdd2.3 V 27.0 mS Vdd3.0 V 23.2 mS Vdd4.0 V 20.4 mS Vdd5.0 V 18.4 mS Vdd6.3 V 16.8 mS Vdd5.0 V 600 nS Vdd=5.0v 15 A comparator) Vref Input reference voltage --- Vdd=2.5v ~6.3v Comparator Response time Vdd=5.0v , V- = Vref V-=Vdd/4, V+=V- 0.2v V+ = (PA0~PA3) Vdd-0.8v V 8 S V-=Vdd/2, V+=V- 0.2v 8 S V-=Vdd3/4, V+=V- 0.2v 8 S V-=VDD-0.8,V+=V 0.2v 8 S This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 10 2004/1 Ver. 1.3 MDT10P21 11. Operating Current Temperature25 , the typical value as followings : 11.1 OSC TypeRC ; WDTEnable; Comparator Disable @ Vdd5.0 V Cext. (F) 3P 20P 100P 300P Rext. (Ohm) Frequency (Hz) Current (A) 4.7 K 10.5M 1.35 mA 10.0 K 5.36M 750 A 47.0 K 1.24M 250 A 100.0 K 589K 180 A 300.0 K 200K 130 A 470.0 K 126K 120 A 4.7 K 5.6M 770 A 10.0 K 2.85M 460 A 47.0 K 640K 190 A 100.0 K 300K 150 A 300.0 K 104K 125 A 470.0 K 64K 115 A 310 A 4.7 K 1.68M 10.0 K 834K 210 A 47.0 K 182K 125 A 100.0 K 87.6K 118 A 300.0 K 29.6K 110 A 470.0 K 18.6K 105 A 4.7 K 748K 200 A 10.0 K 367K 155 A 47.0 K 80K 115 A 100.0 K 38K 110 A 300.0 K 12.8K 105 A 470.0 K 8K 100 A This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 11 2004/1 Ver. 1.3 MDT10P21 11.2 OSC TypeLF (C=20 p); WDTDisable ; Comparator Disable Voltage/Frequency 32 K 455 K 1M Sleep 2.1 V 3.0uA @2.6v 32.0uA @2.2v 42.0uA 1.0 A 3.0 V 6.0uA 45uA 60uA 1.0 A 4.0 V 12.0uA 65uA 100uA 1.0 A 5.0 V 30.0uA 100uA 150uA 1.0 A 6.3 V 110uA 185uA 260uA 1.0 A 11.3 OSC TypeXT (C=10 p); WDTEnable ; Comparator Disable Voltage/Frequency 1M 4M 10 M Sleep 2.1 V 65uA 200uA 360uA 1.0 A 3.0 V 136uA 350uA 650uA 3 A 4.0 V 252uA 550uA 1.0mA 8 A 5.0 V 422uA 820uA 1.6mA 17 A 6.3 V 810uA 1.36mA 2.2mA 36 A 11.4 OSC TypeHF (C=10 p); WDTEnable ; Comparator Disable Voltage/Frequency 4M 10 M 20 M Sleep 1.0 A 2.1 V 200uA 450uA @2.2v 940uA 3.0 V 410uA 810uA 1.37mA 3 A 4.0 V 620uA 1.30mA 2.0mA 8 A 5.0 V 1mA 1.70mA 3.0mA 17 A 6.3 V 1.56mA 2.50mA 4.0mA 36 A Edge-detector Reset Voltage (Not in Sleep Mode), @ V dd5.0 V Vpr2.1~2.2 V Vpr Vdd (Power Supply) 11.5 Power This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 12 2004/1 Ver. 1.3 MDT10P21 12. Port A Equivalent Circuit PA0-PA3 D Q I/O Control Latch I/O Control C K Q B Port I/O Pin D Data O/P Latch Write G QB Input Resistor 0 Data Bus TTL input level D QB Data I/P Latch Read S G + 1 VREF comparator level Compartor Control PA4 D Q I/O Control Latch I/O Control CK QB Port I/O Pin D Data O/P Latch Write G Q B Input Resistor Data Bus Read comparator enable D QB Data I/P Latch TTL Input Level G 3 Vref S0 S1 2 3/4 VDD 1 1/2 VDD 0 1/4 VDD CMR_4 CMR_5 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 13 2004/1 Ver. 1.3 MDT10P21 PA5-PA7 D Q I/O Control Latch I/O Control QB CK Port I/O Pin D Data O/P Latch Write Q B G Data Bus D QB Input Resistor Data I/P Latch Read TTL Input Level G Port B Equivalent Circuit D Q I/O Control Latch I/O Control QB CK Port I/O Pin D Data O/P Latch Write G Q B Data Bus D QB Read Data I/P Latch Input Resistor TTL Input Level G This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 14 2004/1 Ver. 1.3 MDT10P21 13. MCLRB and RTCC Input Equivalent Circuit R1K MCLRB Schmitt Trigger R1K RTCC Schmitt Trigger This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 15 2004/1 Ver. 1.3 MDT10P21 14. External Capacitor Selection For Crystal Oscillator @ Vdd5.0 V Osc. Type Resonator Freq. Capacity Range 20 MHz 10 pF ~ 50 pF 10 MHz 20 pF ~ 50 pF 4 MHz 10 pF ~ 30 pF 10 MHz 10 pF ~ 50 pF 4 MHz 10 pF ~ 50 pF 1 MHz 20 pF ~50 pF 1 MHz 20 pF ~ 30 pF 455 K 20 pF ~30 pF 32 K 20 pF ~30 pF HF XT LF MDT10P21 OSC1 C1 OSC2 C2 To increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor are for reference only, but the higher capacitance also increases the start-up time. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 16 2004/1 Ver. 1.3