LP38503TSX-ADJ/NOPB - NATIONAL SEMICONDUCTOR

LP38501-ADJ,LP38503-ADJ

LP38501/3-ADJ, LP38501A/3A-ADJ 3A FlexCap Low Dropout Linear Regulator

for 2.7V to 5.5V Inputs

Literature Number: SNVS522G

LP38501/3-ADJ, LP38501A/

3A-ADJ

October 30, 2009

3A FlexCap Low Dropout Linear Regulator for 2.7V to 5.5V

Inputs

General Description

National's FlexCap LDO's feature unique compensation that

allows the use of any type of output capacitor with no limits

on minimum or maximum ESR. The LP38501/3 series of low-

dropout linear regulators operates from a +2.7V to +5.5V input

supply. These ultra low dropout linear regulators respond very

quickly to step changes in load, which makes them suitable

for low voltage microprocessor applications. Developed on a

CMOS process, (utilizing a PMOS pass transistor), the

LP38501/3 has low quiescent current that changes little with

load current.

Ground Pin Current: Typically 2 mA at 3A load current.

Disable Mode: Typically 25 nA quiescent current when the

Enable pin is pulled low.

Simplified Compensation: Stable with any type of output

capacitor, regardless of ESR.

Precision Output: "A" grade versions available with 1.5%

VADJ tolerance (25°C) and 3% over line, load and tempera-

ture.

Features

■FlexCap: Stable with ceramic, tantalum, or aluminum

capacitors

■Stable with 10 µF input/output capacitor

■Adjustable output voltage from 0.6V to 5V

■Low ground pin current

■25 nA quiescent current in shutdown mode

■Guaranteed output current of 3A

■Available in TO-263, TO-263 THIN packages

■Guaranteed VADJ accuracy of ±1.5% @ 25°C (A Grade)

■Guaranteed VADJ accuracy of ±3.5% @ 25°C (STD)

■Over-Temperature and Over-Current protection

■−40°C to +125°C operating TJ range

■Enable pin (LP38501)

Applications

■ASIC Power Supplies In:

Printers, Graphics Cards, DVD Players

Set Top Boxes, Copiers, Routers

■DSP and FPGA Power Supplies

■SMPS Regulator

■Conversion from 3.3V or 5V Rail

Typical Application Circuit

30028119

LP38501/3-ADJ, LP38501A/3A-ADJ 3A FlexCap Low Dropout Linear Regulator for 2.7V to 5.5V

Inputs

Connection Diagrams for TO-263 (TS) Package

30028122

Top View (LP38501TS-ADJ)

TO-263 Package

30028121

Top View (LP38503TS-ADJ)

TO-263 Package

Connection Diagrams for TO-263 THIN (TJ) Package

30028162

Top View (LP38501TJ-ADJ, LP38501ATJ-ADJ)

TO-263 THIN Package

30028163

Top View (LP38503TJ-ADJ, LP38503ATJ-ADJ)

TO-263 THIN Package

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LP38501/3-ADJ

Pin Descriptions for TO-263 (TS) and TO-263 THIN (TJ) Packages

Pin # Designation Function

EN Enable (LP38501 only). Pull high to enable the output, low to disable the output. This pin has

no internal bias and must be either tied to the input voltage, or actively driven.

N/C In the LP38503, this pin has no internal connections. It can be left floating or used for trace

routing.

2 IN Input Supply Pin

3 GND Ground

4 OUT Regulated Output Voltage Pin

5 ADJ Sets output voltage

DAP DAP

The DAP is used as a thermal connection to remove heat from the device to the circuit board

copper clad area which acts as the heatsink. The DAP is electrically connected to the

backside of the die. The DAP must be connected to ground potential, but can not be used as

the only ground connection.

Ordering Information

TABLE 1. Package Marking and Ordering Information

Output

Voltage

Order Number Package Type Package Marking Supplied As:

ADJ

LP38501TSX-ADJ

TO-263

LP38501TS-ADJ Tape and Reel of 500 Units

LP38501TS-ADJ LP38501TS-ADJ Rail of 45 Units

LP38503TSX-ADJ LP38503TS-ADJ Tape and Reel of 500 Units

LP38503TS-ADJ LP38503TS-ADJ Rail of 45 Units

ADJ

LP38501TJ-ADJ

TO-263 THIN

LP38501TJ-ADJ Tape and Reel of 1000 Units

LP38503TJ-ADJ LP38503TJ-ADJ Tape and Reel of 1000 Units

LP38501ATJ-ADJ LP38501ATJ-AD Tape and Reel of 1000 Units

LP38503ATJ-ADJ LP38503ATJ-AD Tape and Reel of 1000 Units

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LP38501/3-ADJ

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Storage Temperature Range −65°C to +150°C

Lead Temperature

(Soldering, 5 sec.) 260°C

ESD Rating (Note 2) ±2 kV

Power Dissipation(Note 3) Internally Limited

Input Pin Voltage (Survival) −0.3V to +6.0V

Enable Pin Voltage (Survival) −0.3V to +6.0V

Output Pin Voltage (Survival) −0.3V to +6.0V

IOUT(Survival) Internally Limited

Operating Ratings (Note 1)

Input Supply Voltage 2.7V to 5.5V

Enable Input Voltage 0.0V to 5.5V

Output Current (DC) 0 to 3A

Junction Temperature(Note 3) −40°C to +125°C

VOUT 0.6V to 5V

Electrical Characteristics

LP38501/3–ADJ

Unless otherwise specified: VIN = 3.3V, IOUT = 10 mA, CIN = 10 µF, COUT = 10 µF, VEN = VIN, VOUT = 1.8V. Limits in standard type

are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and

Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric

norm at TJ = 25°C, and are provided for reference purposes only.

Symbol Parameter Conditions Min Typ Max Units

VADJ Adjust Pin Voltage (Note 6)2.7V ≤ VIN ≤ 5.5V

10 mA ≤ IOUT ≤ 3A

0.584

0.575 0.605 0.626

0.635 V

VADJ

Adjust Pin Voltage (Note 6)

"A" GRADE

2.7V ≤ VIN ≤ 5.5V

10 mA ≤ IOUT ≤ 3A

0.596

0.587 0.605 0.614

0.623 V

IADJ Adjust Pin Bias Current 2.7V ≤ VIN ≤ 5.5V 50 750 nA

VDO Dropout Voltage (Note 7)IOUT = 3A 420 550

665 mV

ΔVOUT/ΔVIN

Output Voltage Line

Regulation

(Note 4, Note 6)

2.7V ≤ VIN ≤ 5.5V —0.04

0.05 —%/V

ΔVOUT/ΔIOUT

Output Voltage Load

Regulation

(Note 5, Note 6)

10 mA ≤ IOUT ≤ 3A —0.12

0.24 —%/A

IGND

Ground Pin Current In Normal

Operation Mode 10 mA ≤ IOUT ≤ 3A —24

5mA

IDISABLED Ground Pin Current VEN < VIL(EN) —0.025 0.125

15 µA

IOUT(PK) Peak Output Current VOUT ≥ VOUT(NOM) - 5% 6 A

ISC Short Circuit Current VOUT = 0V 3.5 6 A

Enable Input (LP38501 Only)

VIH(EN) Enable Logic High VOUT = ON 1.4 — — V

VIL(EN) Enable Logic Low VOUT = OFF — — 0.65

td(off) Turn-off delay

Time from VEN < VIL(EN) to VOUT =

OFF

ILOAD = 3A

—25 —

µs

td(on) Turn-on delay

Time from VEN >VIH(EN) to VOUT =

ILOAD = 3A

—25 —

IIH(EN) Enable Pin High Current VEN = VIN —35 —nA

IIL(EN) Enable Pin Low Current VEN = 0V —35 —

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LP38501/3-ADJ

Symbol Parameter Conditions Min Typ Max Units

AC Parameters

PSRR Ripple Rejection

VIN = 3.0V, IOUT = 3A

f = 120Hz —58 —

VIN = 3.0V, IOUT = 3A

f = 1 kHz —56 —

ρn(l/f) Output Noise Density f = 120Hz, COUT = 10 µF CER —1.0 —µV/√Hz

enOutput Noise Voltage BW = 100Hz – 100kHz

COUT = 10 µF CER —100 —µV (rms)

Thermal Characteristics

TSD Thermal Shutdown TJ rising —170 —°C

ΔTSD Thermal Shutdown Hysteresis TJ falling from TSD —10 —

θJ-A

Thermal Resistance

Junction to Ambient

TO-263, TO-263 THIN(Note 8)

1 sq. in. copper 37

°C/W

θJ-C

Thermal Resistance

Junction to Case TO-263, TO-263 THIN —5—

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and conditions, see the Electrical Characteristics.

Note 2: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.

Note 3: Operating junction temperature must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum

allowable operating junction temperature (TJ(MAX)), and package thermal resistance (θJA). See Application Information.

Note 4: Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the voltage at the input.

Note 5: Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in the load current at the output.

Note 6: The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the output

voltage tolerance specification.

Note 7: Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. For any output

voltage less than 2.5V, the minimum VIN operating voltage is the limiting factor.

Note 8: The value of θJA for the TO-263 (TS) package and TO-263 THIN (TJ) package can range from approximately 30 to 60°C/W depending on the amount of

PCB copper dedicated to heat transfer (See Application Information).

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LP38501/3-ADJ

Typical Performance Characteristics Unless otherwise specified: TJ = 25°C, VIN = 2.7V, VEN = VIN,

CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA, VOUT = 1.8V

Noise Density

30028110

Noise Density

30028114

IGND vs Load Current

30028111

IGND(OFF) vs Temperature

30028112

VADJ vs Temperature

30028113

Dropout Voltage vs Load Current

30028115

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LP38501/3-ADJ

VEN vs Temperature

30028116

Turn-on Characteristics

30028117

Load Regulation vs Temperature

30028118

Turn-on Time

30028155

Turn-on Time

30028156

PSRR

30028120

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LP38501/3-ADJ

Block Diagrams

LP38501-ADJ Block Diagram

30028150

LP38503-ADJ Block Diagram

30028151

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LP38501/3-ADJ

Application Information

EXTERNAL CAPACITORS

The LP3850X requires that at least 10 µF (±20%) capacitors

be used at the input and output pins located within one cm of

the IC. Larger capacitors may be used without limit on size for

both CIN and COUT. Capacitor tolerances such as temperature

variation and voltage loading effects must be considered

when selecting capacitors to ensure that they will provide the

minimum required amount of capacitance under all operating

conditions for the application.

In general, ceramic capacitors are best for noise bypassing

and transient response because of their ultra low ESR. It must

be noted that if ceramics are used, only the types with X5R

or X7R dielectric ratings should be used (never Z5U or Y5F).

Capacitors which have the Z5U or Y5F characteristics will see

a drop in capacitance of as much as 50% if their temperature

increases from 25°C to 85°C. In addition, the capacitance

drops significantly with applied voltage: a typical Z5U or Y5F

capacitor can lose as much as 60% of it’s rated capacitance

if only half of the rated voltage is applied to it. For these rea-

sons, only X5R and X7R ceramics should be used.

INPUT CAPACITOR

All linear regulators can be affected by the source impedance

of the voltage which is connected to the input. If the source

impedance is too high, the reactive component of the source

may affect the control loop’s phase margin. To ensure prop-

er loop operation, the ESR of the capacitor used for CIN

must not exceed 0.5 Ohms. Any good quality ceramic ca-

pacitor will meet this requirement, as well as many good

quality tantalums. Aluminum electrolytic capacitors may also

work, but can possibly have an ESR which increases signifi-

cantly at cold temperatures. If the ESR of the input capacitor

may exceed 0.5 Ohms, it is recommended that a 2.2 µF ce-

ramic capacitor be used in parallel, as this will assure stable

loop operation.

OUTPUT CAPACITOR

Any type of capacitor may be used for COUT, with no limita-

tions on minimum or maximum ESR, as long as the minimum

amount of capacitance is present. The amount of capacitance

can be increased without limit. Increasing the size of COUT

typically will give improved load transient response.

SETTING THE OUTPUT VOLTAGE

The output voltage of the LP38501/3-ADJ can be set to any

value between 0.6V and 5V using two external resistors

shown as R1 and R2 in Figure 1.

30028157

FIGURE 1.

The value of R2 should always be less than or equal to 10

kΩ for good loop compensation. R1 can be selected for a giv-

en VOUT using the following formula:

VOUT = VADJ (1 + R1/R2) + IADJ (R1)

Where VADJ is the adjust pin voltage and IADJ is the bias cur-

rent flowing into the adjust pin.

STABILITY AND PHASE MARGIN

Any regulator which operates using a feedback loop must be

compensated in such a way as to ensure adequate phase

margin, which is defined as the difference between the phase

shift and -180 degrees at the frequency where the loop gain

crosses unity (0 dB). For most LDO regulators, the ESR of the

output capacitor is required to create a zero to add enough

phase lead to ensure stable operation. The LP38501 has a

unique internal compensation circuit which maintains phase

margin regardless of the ESR of the output capacitor, so any

type of capacitor may be used.

Figure 2 shows the gain/phase plot of the LP38501-ADJ with

an output of 1.2V, 10 µF ceramic output capacitor, delivering

2A of load current. It can be seen that the unity-gain crossover

occurs at 300 kHz, and the phase margin is about 40° (which

is very stable).

30028153

FIGURE 2. Gain-Bandwidth Plot for 2A Load

Figure 3 shows the gain and phase with no external load. In

this case, the only load is provided by the gain setting resistors

(about 12 kΩ total in this test). It is immediately obvious that

the unity-gain frequency is significantly lower (dropping to

about 500 Hz), at which point the phase margin is 125°.

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LP38501/3-ADJ

30028154

FIGURE 3. Gain-Bandwidth Plot for No Load

The reduction in unity-gain bandwidth as load current is re-

duced is normal for any LDO regulator using a P-FET or PNP

pass transistor, because they have a pole in the loop gain

function given by:

This illustrates how the pole goes to the highest frequency

when RL is minimum value (maximum load current). In gen-

eral, LDO’s have maximum bandwidth (and lowest phase

margin) at full load current. In the case of the LP38501, it can

be seen that it has good phase margin even when using ce-

ramic capacitors with ESR values of only a few milli Ohms.

LOAD TRANSIENT RESPONSE

Load transient response is defined as the change in regulated

output voltage which occurs as a result of a change in load

current. Many applications have loads which vary, and the

control loop of the voltage regulator must adjust the current

in the pass FET transistor in response to load current

changes. For this reason, regulators with wider bandwidths

often have better transient response.

The LP38501 employs an internal feedforward design which

makes the load transient response much faster than would be

predicted simply by loop speed: this feedforward means any

voltage changes appearing on the output are coupled through

to the high-speed driver used to control the gate of the pass

FET along a signal path using very fast FET devices. Because

of this, the pass transistor’s current can change very quickly.

Figure 4 shows the output transient response resulting from

a change in load current of 0.1A – 3A, and then 3A – 0.1A

with a load current slew rate of 500 mA/µs. As shown in the

plots, the resulting change in output voltage is only about 40

mV (peak), which is just slightly over 2% for the 1.8V output

used for this test. This is excellent performance for such a

small output capacitor.

30028136

FIGURE 4. Load Transient Response: 10 µF Ceramic,

0.5A/µs di/dt

When the load current changes much more quickly, the output

voltage will show more change because the loop and internal

feedforward circuitry are not able to react as fast as the load

changes. In such cases, it is the output capacitor which must

supply load current during the transition until the loop re-

sponds and changes the pass transistor’s drive to deliver the

new value of load current. As an example, the slew rate of the

load current will be increased to 75A/µs and the same test will

be performed. In Figure 5, it can be seen that the peak ex-

cursion of the output voltage during the transient has now

increased to about 200 mV, which is just slightly over 11% for

the 1.8V output.

30028134

FIGURE 5. Load Transient Response: 10 µF Ceramic,

75A/µs di/dt

A better understanding of the load transient can be obtained

when the load’s rising edge is expanded in time scale (Figure

6).

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LP38501/3-ADJ

30028135

FIGURE 6. Rising Edge, 10 µF Ceramic, 75A/µs di/dt

It can be seen from the figure that the output voltage starts

“correcting” back upwards after less than a micro second, and

has fully reversed direction after about 1.2 µs. This very rapid

reaction is a result of the maximum loop bandwidth (full load

is being delivered) and the feedforward effect kicking on the

drive to the FET before feedback gets fully around the loop.

In cases where extremely fast load changes occur, and output

voltage regulation better than 10% is required, the output ca-

pacitance must be increased. When selecting capacitors, it

must be understood that the better performing ones usually

cost the most. For fast changing loads, the internal parasitics

of ESR (equivalent series resistance) and ESL (equivalent

series inductance) degrade the capacitor’s ability to source

current quickly to the load. The best capacitor types for tran-

sient performance are (in order):

1. Multilayer Ceramic: with the lowest values of ESR and

ESL, they can have ESR values in the range of a few milli

Ohms. Disadvantage: capacitance values above about

22 µF significantly increase in cost.

2. Low-ESR Aluminum Electrolytics: these are aluminum

types (like OSCON) with a special electrolyte which

provides extremely low ESR values, and are the closest

to ceramic performance while still providing large

amounts of capacitance. These are cheaper (by

capacitance) than ceramic.

3. Solid tantalum: can provide several hundred µF of

capacitance, transient performance is slightly worse than

OSCON type capacitors, cheaper than ceramic in large

values.

4. General purpose aluminum electrolytics: cheap and

provide a lot of capacitance, but give the worst

performance.

As a first example, larger values of ceramic capacitance will

be tried to show how much reduction can be obtained from

the 200 mV output change (Figure 6) which was seen with

only a 10 µF ceramic output capacitor. In Figure 7, the 10 µF

output capacitor is increased to 22 µF. The 200 mV transient

is reduced to about 160 mV, which is from about 11% of

VOUT down to about 9%.

30028137

FIGURE 7. 22 µF Ceramic Output Capacitor

In Figure 8, the output capacitance is increased to 47 µF ce-

ramic. It can be seen that the output transient is further

reduced down to about 120 mV, which is still about 6.6% of

the output voltage. This shows that a 5X increase in ceramic

capacitance from the original 10 µF only reduced the peak

voltage transient amplitude by about 40%.

30028138

FIGURE 8. 47 µF Ceramic Output Capacitor

In general, managing load transients is done by paralleling

ceramic capacitance with a larger bulk capacitance. In this

way, the ceramic can source current during the rapidly chang-

ing edge and the bulk capacitor can support the load current

after the first initial spike in current.

In the next test, the same 10 µF ceramic capacitor will be

paralleled with a general purpose (cheap) aluminum elec-

trolytic whose capacitance is 220 µF. As shown in Figure 9,

there is a small improvement over the 200 mV peak seen with

the 10 µF ceramic alone. By adding the 220 µF aluminum

capacitor, the peak is reduced to about 160 mV (the same

peak value as seen with a 22 µF ceramic capacitor alone).

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LP38501/3-ADJ

30028139

FIGURE 9. 10 µF Ceramic Paralleled By 220 µF Generic

Aluminum Electrolytic

A solid Tantalum should work better, so the aluminum elec-

trolytic is replaced by a 220 µF Tantalum (Figure 10). The

peak amplitude of the output transient is now reduced to about

130 mV, just slightly worse than the value of the 47 µF ceramic

alone.

30028141

FIGURE 10. 10 µF Ceramic Paralleled By 220 µF Tantalum

The OSCON (ultra low ESR) aluminum electrolytic is the best

of the electrolytics. Figure 11 shows the output voltage tran-

sient is reduced down to about 90 mV (about 5% of VOUT)

when a 220 µF OSCON is added to the 10 µF ceramic. This

indicates that some kind of ultra-low ESR aluminum elec-

trolytic used in parallel with some ceramic capacitance is

probably the best approach for extremely fast transients, but

each application must be dialed in for it’s specific load re-

quirements.

30028140

FIGURE 11. 10 µF Ceramic Paralleled By 220 µF OSCON

PRINTED CIRCUIT BOARD LAYOUT

Good layout practices will minimize voltage error and prevent

instability which can result from ground loops. The input and

output capacitors should be directly connected to the IC pins

with short traces that have no other current flowing in them

(Kelvin connect).

The best way to do this is to place the capacitors very near

the IC and make connections directly to the IC pins via short

traces on the top layer of the PCB. The regulator’s ground pin

should be connected through vias to the internal or backside

ground plane so that the regulator has a single point ground.

The external resistors which set the output voltage must also

be located very near the IC with all connections directly tied

via short traces to the pins of the IC (Kelvin connect). Do not

connect the resistive divider to the load point or DC error will

be induced.

RFI/EMI SUSCEPTIBILITY

RFI (Radio Frequency Interference) and EMI (Electro-Mag-

netic Interference) can degrade any integrated circuit's per-

formance because of the small dimensions of the geometries

inside the device. In applications where circuit sources are

present which generate signals with significant high frequen-

cy energy content (> 1 MHz), care must be taken to ensure

that this does not affect the IC regulator.

If RFI/EMI noise is present on the input side of the regulator

(such as applications where the input source comes from the

output of a switching regulator), good ceramic bypass capac-

itors must be used at the input pin of the IC to reduce the

amount of EMI conducted into the IC.

If the LP38501/3-ADJ output is connected to a load which

switches at high speed (such as a clock), the high-frequency

current pulses required by the load must be supplied by the

capacitors on the IC output. Since the bandwidth of the reg-

ulator loop is less than 300 kHz, the control circuitry cannot

respond to load changes above that frequency. This means

the effective output impedance of the IC at frequencies above

300 kHz is determined only by the output capacitor(s). Ce-

ramic capacitors provide the best performance in this type of

application.

In applications where the load is switching at high speed, the

output of the IC may need RF isolation from the load. In such

cases, it is recommended that some inductance be placed

between the output capacitor and the load, and good RF by-

pass capacitors be placed directly across the load. PCB

layout is also critical in high noise environments, since RFI/

EMI is easily radiated directly into PC traces. Noisy circuitry

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LP38501/3-ADJ

should be isolated from "clean" circuits where possible, and

grounded through a separate path. At MHz frequencies,

ground planes begin to look inductive and RFI/EMI can cause

ground bounce across the ground plane. In multi-layer PC

Board applications, care should be taken in layout so that

noisy power and ground planes do not radiate directly into

adjacent layers which carry analog power and ground.

OUTPUT NOISE

Noise is specified in two ways-

Spot Noise or Output noise density is the RMS sum of all

noise sources, measured at the regulator output, at a specific

frequency (measured with a 1Hz bandwidth). This type of

noise is usually plotted on a curve as a function of frequency.

Total output noise voltage or Broadband noise is the RMS

sum of spot noise over a specified bandwidth, usually several

decades of frequencies. Attention should be paid to the units

of measurement.

Spot noise is measured in units µV/√Hz or nV/√Hz and total

output noise is measured in µV(rms). The primary source of

noise in low-dropout regulators is the internal reference. In

CMOS regulators, noise has a low frequency component and

a high frequency component, which depend strongly on the

silicon area and quiescent current.

Noise can generally be reduced in two ways: increase the

transistor area or increase the reference current. However,

enlarging the transisitors will increase die size, and increasing

the reference current means higher total supply current

(ground pin current).

SHORT-CIRCUIT PROTECTION

The LP38501/3-ADJ contains internal current limiting which

will reduce output current to a safe value if the output is over-

loaded or shorted. Depending upon the value of VIN, thermal

limiting may also become active as the average power dissi-

pated causes the die temperature to increase to the limit value

(about 170°C). The hysteresis of the thermal shutdown cir-

cuitry can result in a “cyclic” behavior on the output as the die

temperature heats and cools.

ENABLE OPERATION (LP38501-ADJ Only)

The Enable pin (EN) must be actively terminated by either a

10 kΩ pull-up resistor to VIN, or a driver which actively pulls

high and low (such as a CMOS rail to rail comparator). If active

drive is used, the pull-up resistor is not required. This pin must

be tied to VIN if not used (it must not be left floating).

DROPOUT VOLTAGE

The dropout voltage of a regulator is defined as the input-to-

output differential required by the regulator to keep the output

voltage within 2% of the nominal value. For CMOS LDOs, the

dropout voltage is the product of the load current and the

RDS(on) of the internal MOSFET pass element.

Since the output voltage is beginning to “drop out” of regula-

tion when it drops by 2%, electrical performance of the device

will be reduced compared to the values listed in the Electrical

Characteristics table for some parameters (line and load reg-

ulation and PSRR would be affected).

REVERSE CURRENT PATH

The internal MOSFET pass element in the LP38501/3-ADJ

has an inherent parasitic diode. During normal operation, the

input voltage is higher than the output voltage and the para-

sitic diode is reverse biased. However, if the output is pulled

above the input in an application, then current flows from the

output to the input as the parasitic diode gets forward biased.

The output can be pulled above the input as long as the cur-

rent in the parasitic diode is limited to 200 mA continuous and

1A peak. The regulator output pin should not be taken below

ground potential. If the LP38501/3-ADJ is used in a dual-sup-

ply system where the regulator load is returned to a negative

supply, the output must be diode-clamped to ground.

POWER DISSIPATION/HEATSINKING

The maximum power dissipation (PD(MAX)) of the LP38501/3-

ADJ is limited by the maximum junction temperature of

125°C, along with the maximum ambient temperature (TA

(MAX)) of the application, and the thermal resistance (θJA) of

the package. Under all possible conditions, the junction tem-

perature (TJ) must be within the range specified in the Oper-

ating Ratings. The total power dissipation of the device is

given by:

PD = ( (VIN − VOUT) x IOUT) + (VIN x IGND) (1)

where IGND is the operating ground current of the device

(specified under Electrical Characteristics).

The maximum allowable junction temperature rise (ΔTJ) de-

pends on the maximum expected ambient temperature

(TA(MAX)) of the application, and the maximum allowable junc-

tion temperature (TJ(MAX)):

ΔTJ = TJ(MAX)− TA(MAX) (2)

The maximum allowable value for junction to ambient Ther-

mal Resistance, θJA, can be calculated using the formula:

θJA = ΔTJ / PD(MAX) (3)

The LP38501/3-ADJ is available in the TO-263 package. The

thermal resistance depends on the amount of copper area

allocated to heat transfer.

HEATSINKING TO-263, TO-263 THIN PACKAGES

The TO-263 package and TO-263 THIN package use the

copper plane on the PCB as a heatsink. The DAP of the pack-

age is soldered to the copper plane for heat sinking. Figure

12 shows a typical curve for the θJA of the TO-263 package

for different copper area sizes (the thermal performance of

both the TO-263 and TO-263 THIN are the same). The tests

were done using a PCB with 1 ounce copper on top side only

which were square in shape.

13 www.national.com

LP38501/3-ADJ

30028152

FIGURE 12. θJA vs Copper Area for TO-263 Package

As shown in the figure, increasing the copper area beyond 1.5

square inch produces very little improvement.

www.national.com 14

LP38501/3-ADJ

Physical Dimensions inches (millimeters) unless otherwise noted

TO-263 5-Lead, Molded, Surface Mount Package

NS Package Number TS5B

TO-263 THIN 5-Lead, Molded, Surface Mount Package

NS Package Number TJ5A

15 www.national.com

LP38501/3-ADJ

Notes

LP38501/3-ADJ, LP38501A/3A-ADJ 3A FlexCap Low Dropout Linear Regulator for 2.7V to 5.5V

Inputs

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