ADM7151ARDZ-04-R7 - Analog Devices

800 mA Ultralow Noise,

High PSRR, RF Linear Regulator

Data Sheet ADM7151

Rev. A Document Feedback

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FEATURES

Input voltage range: 4.5 V to 16 V

Maximum output current: 800 mA

Adjustable output from 1.5 V to 5.1 V

Low noise

1.0 μV rms total integrated noise from 100 Hz to 100 kHz

1.6 μV rms total integrated noise from 10 Hz to 100 kHz

Noise spectral density: 1.7 nV√Hz from 10 kHz to 1 MHz

Power supply rejection ratio (PSRR) at 400 mA load

>90 dB from 1 kHz to 100 kHz, VOUT = 5 V

>60 dB at 1 MHz, VOUT = 5 V

Dropout voltage: 0.6 V at VOUT = 5 V, 800 mA load

Initial voltage accuracy: ±1%

Voltage accuracy over line, load and temperature: ±2%

Quiescent current (IGND): 4.3 mA at no load

Low shutdown current: 0.1 μA

Stable with a 10 μF ceramic output capacitor

8-lead LFCSP package and 8-lead SOIC package

APPLICATIONS

Regulated power noise sensitive applications

RF mixers, phase-locked loops (PLLs), voltage-controlled

oscillators (VCOs), and PLLs with integrated VCOs

Clock distribution circuits

Ultrasound and other imaging applications

High speed RF transceivers

High speed, 16-bit or greater ADCs

Communications and infrastructure

Cable digital-to-analog converter (DAC) drivers

TYPICAL APPLICATION CIRCUIT

VOUT

REF

REF_SENSE

GND

VIN

BYP

VREG

BYP

REG

DM7151-04

REG

10µF

BYP

1µF

REF

1µF

OUT

= 1.5V × (R1 + R2)/R2

1kΩ < R2 < 200kΩ

10µF

OUT

10µF

OFF

= 6.2V V

OUT

= 5.0V

11480-001

Figure 1. ADM7151-04 with VOUT = 5 V

GENERAL DESCRIPTION

The ADM7151 is a low dropout (LDO) linear regulator that

operates from 4.5 V to 16 V and provides up to 800 mA of output

current. Using an advanced proprietary architecture, it provides

high power supply rejection (>90 dB from 1 kHz to 1 MHz),

ultralow noise (1.7 nV√Hz from 10 kHz to 1 MHz), and excellent

line and load transient response with a 10 μF ceramic output

capacitor. The output voltage can be set to any voltage between

1.5 V and 5.1 V with two resistors.

The ADM7151 is available in two models that optimize power

dissipation and PSRR performance as a function of input and

output voltage. See Table 6 and Table 7 for selection guides.

The ADM7151 regulator output noise is 1.0 μV rms from

100 Hz to 100 kHz, and the noise spectral density is 1.7 nV/√Hz

from 10 kHz to 1 MHz.

The ADM7151 is available in 8-lead, 3 mm × 3 mm LFCSP and

8-lead SOIC packages, making it not only a very compact solution,

but also providing excellent thermal performance for applications

requiring up to 800 mA of output current in a small, low profile

footprint.

100k

100

10k

0.1 1 10 100 1k 10k 100k 1M

NOISE SPECTRAL DENSITY (nV/

√

Hz)

FREQUENCY (Hz)

BYP

= 1µF

BYP

= 10µF

BYP

= 100µF

BYP

= 1mF

11480-002

Figure 2. Noise Spectral Density (NSD) vs. Frequency for Various CBYP

ADM7151 Data Sheet

TABLE OF CONTENTS

Features........................................................................................... 1

Applications ................................................................................... 1

Typical Application Circuit ........................................................... 1

General Description ...................................................................... 1

Revision History ............................................................................ 2

Specifications ................................................................................. 3

Input and Output Capacitor, Recommended Specifications .. 4

Absolute Maximum Ratings ......................................................... 5

Thermal Data ............................................................................. 5

Thermal Resistance ................................................................... 5

ESD Caution............................................................................... 5

Pin Configurations and Function Descriptions .......................... 6

Typical Performance Characteristics............................................ 7

Theory of Operation.................................................................... 15

Applications Information............................................................ 16

Model Selection ....................................................................... 16

Capacitor Selection.................................................................. 16

Enable (EN) and Undervoltage Lockout (UVLO) ................ 18

Start-Up Time .......................................................................... 19

REF, BYP, and VREG Pins....................................................... 19

Current-Limit and Thermal Overload Protection ................ 19

Thermal Considerations ......................................................... 19

Printed Circuit Board Layout Considerations....................... 22

Outline Dimensions .................................................................... 23

Ordering Guide........................................................................ 24

REVISION HISTORY

4/15—Rev. 0 to R ev. A

Change to Figure 4..........................................................................6

Change to Figure 39......................................................................12

9/13—Revision 0: Initial Version

Rev. A | Page 2 of 24

Data Sheet ADM7151

SPECIFICATIONS

VIN = 4.5 V, VOUT = 1.5 V, VREF = VREF_SENSE (unity gain), VEN = VIN, IOUT = 10 mA, CIN = COUT = CREG = 10 µF, CREF = CBYP = 1 µF. TA = 25°C

for typical specifications. TJ = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

INPUT VOLTAGE RANGE

VIN

4.5

OPERATING SUPPLY CURRENT IGND IOUT = 0 µA 4.3 7.0 mA

IOUT = 800 mA 8.6 12 mA

SHUTDOWN CURRENT IIN-SD VEN = GND 0.1 3 µA

OUTPUT NOISE OUTN OISE 10 Hz to 100 kHz, independent of output voltage 1.6 µV rms

100 Hz to 100 kHz, independent of output voltage 1.0 µV rms

NOISE SPECTRAL DENSITY NSD 10 kHz to 1 MHz, independent of output voltage 1.7 nV/√Hz

POWER SUPPLY REJECTION RATIO PSRR

ADM7151-04 1 kHz to 100 kHz, VIN = 6.2 V, VOUT = 5 V at 800 mA 84 dB

1 MHz, VIN = 6.2 V, VOUT = 5 V at 800 mA 53 dB

1 kHz to 100 kHz, VIN = 6.2 V, VOUT = 5 V at 400 mA 94 dB

1 MHz, VIN = 6.2 V, VOUT = 5 V at 400 mA 67 dB

ADM7151-02 1 kHz to 100 kHz, VIN = 5.2 V, VOUT = 4 V at 800 mA 91 dB

1 MHz, VIN = 5.2 V, VOUT = 4 V at 800 mA 50 dB

1 kHz to 100 kHz, VIN = 5.2 V, VOUT = 4 V at 400 mA 94 dB

1 MHz, VIN = 5.2 V, VOUT = 4 V at 400 mA 58 dB

VOUT VOLTAGE ACCURACY

VOUT = VREF

Voltage Accuracy VOUT IOUT = 10 mA −1 +1 %

1 mA < I

OUT

< 800 mA, over line, load and

temperature

−2 +2 %

VOUT RE G U L ATI ON

Line Regulation ΔVOUT/ΔVIN VIN = 4.5 V to 16 V −0.01 +0.01 %/V

Load Regulation1 ΔVOUT/ΔIOUT IOUT = 1 mA to 800 mA 0.5 1.0 %/A

CURRENT-LIMIT THRESHOLD ILIMIT

VREF Current Limit Threshold 20 mA

VOUT Current Limit Threshold2 1.0 1.3 1.6 A

DROPOUT VOLTAGE3 VDROPOUT IOUT = 400 mA, VOUT = 5 V 0.30 0.60 V

IOUT = 800 mA, VOUT = 5 V 0.60 1.20 V

PULL-DOWN RESISTANCE

VOUT Pull-Down Resistance VOUT-PULL VEN = 0 V, VOUT = 1 V 600 Ω

VREG Pull-Down Resistance VR EG -PULL VEN = 0 V, VREG = 1 V 34 kΩ

VREF Pull-Down Resistance VR EF-PU LL VEN = 0 V, VREF = 1 V 800 Ω

VBYP Pull-Down Resistance

VBYP-PULL

VEN = 0 V, VBYP = 1 V

500

START-UP TIME4 VOUT = 5 V

VOUT Start-Up Time tS TA R T -UP 2.8 ms

VREG Start-Up Time tREG -S TA R T -UP 1.0 ms

VREF Start-Up Time tREF-S TA R T -UP 1.8 ms

THERMAL SHUTDOWN

Thermal Shutdown Threshold TSSD TJ rising 155 °C

Thermal Shutdown Hysteresis TSSD -HYS 15 °C

UNDERVOLTAGE THRESHOLDS

Input Voltage Rising

UVLORISE

TJ = −40°C to +125°C

4.49

Input Voltage Falling UVLOFA L L TJ = −40°C to +125°C 3.85 V

Hysteresis UVLOHYS 240 mV

Rev. A | Page 3 of 24

ADM7151 Data Sheet

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

VREG 5 UNDERVOLTAGE THRESHOLDS

VREG Rise VREGUVLORISE TJ = −40°C to +125°C 3.1 V

VREG Fall

VREGUVLOFA L L

TJ = −40°C to +125°C

2.55

Hysteresis VREGUVLOHYS 210 mV

EN INPUT 4.5 V ≤ VIN ≤ 16 V

EN Input Logic High ENHIGH 3.2 V

EN Input Logic Low ENLOW 0.8 V

EN Input Logic Hysteresis ENHYS VIN = 5 V 225 mV

EN Input Leakage Current IEN-LKG VEN = VIN or GND 0.1 1.0 µA

1 Based on an end-point calculation using 1 mA and 800 mA loads. See Figure 6 and Figure 13 for typical load regulation performance for loads less than 1 mA.

2 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V, or 4.5 V.

3 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to achieve the nominal output voltage. Dropout applies only for

output voltages above 4.5 V.

4 Start-up time is defined as the time between the rising edge of VEN to VOUT, VREG, or VREF being at 90% of its nominal value.

5 The output voltage is turned off until the VREG UVLO rise threshold is crossed. The VREG output is turned off until the input voltage UVLO rising threshold is crossed.

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

Table 2.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

CAPACITANCE TA = −40°C to +125°C

Minimum Input1 CIN 7.0 µF

Minimum Regulator1 CREG 7.0 µF

Minimum Output1 COUT 7.0 µF

Minimum Bypass CBYP 0.1 µF

Minimum Reference CREF 0.7 µF

CAPACITOR EQUIVALENT SERIES RESISTANCE (ESR) RESR TA = −40°C to +125°C

CREG, COUT, CIN, CR EF 0.001 0.2 Ω

CBYP 0.001 2.0 Ω

1 The minimum input, regulator, and output capacitance must be greater than 7.0 µF over the full range of operating conditions. The full range of operating conditions

in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are

recommended; however, Y5V and Z5U capacitors are not recommended for use with any LDO.

Rev. A | Page 4 of 24

Data Sheet ADM7151

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VIN to GND −0.3 V to +18 V

VREG to GND −0.3 V to VIN, or +6 V

(whichever is less)

VOUT to GND

−0.3 V to VREG, or +6 V

(whichever is less)

VOUT to BYP ±0.3 V

EN to GND −0.3 V to18 V

BYP to GND −0.3 V to VREG, or +6 V

(whichever is less)

REF to GND

−0.3 V to VREG, or +6 V

(whichever is less)

REF_SENSE to GND −0.3 V to +6 V

Storage Temperature Range −65°C to +150°C

Junction Temperature 150°C

Operating Ambient Temperature Range –40°C to +125°C

Soldering Conditions JEDEC J-STD-020

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL DATA

Absolute maximum ratings apply individually only, not in

combination. The ADM7151 can be damaged when the junction

temperature limits are exceeded. Monitoring ambient temperature

does not guarantee that TJ is within the specified temperature

limits. In applications with high power dissipation and poor

thermal resistance, the maximum ambient temperature may

have to be derated.

In applications with moderate power dissipation and low

printed circuit board (PCB) thermal resistance, the maximum

ambient temperature can exceed the maximum limit as long as

the junction temperature is within specification limits. The

junction temperature (TJ) of the device is dependent on the

ambient temperature (TA), the power dissipation of the device

(PD), and the junction to ambient thermal resistance of the

package (θJA).

Maximum junction temperature (TJ) is calculated from the

ambient temperature (TA) and power dissipation (PD) using the

formula

TJ = TA + (PD × θJA)

Junction to ambient thermal resistance (θJA) of the package is

based on modeling and calculation using a 4-layer board. The

junction to ambient thermal resistance is highly dependent on

the application and board layout. In applications where high

maximum power dissipation exists, close attention to thermal

board design is required. The value of θJA may vary, depending on

PCB material, layout, and environmental conditions. The specified

values of θJA are based on a 4-layer, 4 in. × 3 in. circuit board.

See JESD51-7 and JESD51-9 for detailed information on the

board construction.

ΨJB is the junction to board thermal characterization parameter

with units of °C/W. ΨJB of the package is based on modeling and the

calculation using a 4-layer board. The JESD51-12, Guidelines for

Reporting and Using Electronic Package Thermal Information,

states that thermal characterization parameters are not the same

as thermal resistances. ΨJB measures the component power

flowing through multiple thermal paths rather than a single

path as in thermal resistance (θJB). Therefore, ΨJB thermal paths

include convection from the top of the package as well as

radiation from the package, factors that make ΨJB more useful

in real-world applications. Maximum junction temperature (TJ)

is calculated from the board temperature (TB) and power

dissipation (PD) using the formula

TJ = TB + (PD × ΨJB)

See JESD51-8 and JESD51-12 for more detailed information

about ΨJB.

THERMAL RESISTANCE

θJA, θJC, and ΨJB are specified for the worst-case conditions, that

is, a device soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type

Unit

8-Lead LFCSP 36.7 23.5 13.3 °C/W

8-Lead SOIC 36.9 27.1 18.6 °C/W

ESD CAUTION

Rev. A | Page 5 of 24

ADM7151 Data Sheet

Rev. A | Page 6 of 24

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

3BYP

4GND

1VREG

2VOUT

6REF

5 REF_SENSE

8VIN

7EN

ADM7151

TOP VIEW

(Not to Scale)

11480-003

NOTES

1. EXPOSED PAD ON THE BOTTOM OF THE PACKAGE.

EXPOSED PAD ENHANCES THERMAL PERFORMANCE AND IS

ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE.

CONNECT THE EXPOSED PAD TO THE GROUND PLANE ON

THE BOARD TO ENSURE PROPER OPERATION.

Figure 3. 8-Lead LFCSP Pin Configuration

ADM7151

TOP VIEW

(Not to Scale)

VREG

VOUT

BYP

GND

VIN

REF

REF_SENSE

11480-004

NOTES

1. EXPOSED PAD ON THE BOTTOM OF THE PACKAGE.

EXPOSED PAD ENHANCES THERMAL PERFORMANCE AND IS

ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE.

CONNECT THE EXPOSED PAD TO THE GROUND PLANE ON

THE BOARD TO ENSURE PROPER OPERATION.

Figure 4. 8-Lead SOIC Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 VREG

Regulated Input Supply to LDO Amplifier. Bypass VREG to GND with a 10 μF or greater capacitor. Do not connect a

load to ground.

2 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 10 μF or greater capacitor.

3 BYP Low Noise Bypass Capacitor. Connect a 1 μF capacitor to GND to reduce noise. Do not connect a load to ground.

4 GND Ground Connection.

5 REF_SENSE External Resistor Divider Used to Set the Output Voltage. VOUT = VREF × (R1 + R2)/R2, where VREF = 1.5 V.

6 REF Low Noise Reference Voltage Output. Bypass REF to GND with a 1 μF capacitor. Short REF_SENSE to REF for fixed

output voltages. Do not connect a load to ground.

7 EN Enable. Drive EN high to turn on the regulator and drive EN low to turn off the regulator. For automatic startup,

connect EN to VIN.

8 VIN Regulator Input Supply. Bypass VIN to GND with a 10 μF or greater capacitor.

EP EP Exposed Pad on the Bottom of the Package. Exposed pad enhances thermal performance and is electrically

connected to GND inside the package. Connect the exposed pad to the ground plane on the board to ensure

proper operation.

Data Sheet ADM7151

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = VOUT + 1.2 V or VIN = 4.5 V, whichever is greater, EN = VIN, IOUT = 10 mA, CIN = COUT = CREG = 10 µF, CREF = CBYP = 1 µF, TA = 25°C,

unless otherwise noted.

4.04

3.96

3.97

3.98

3.99

4.00

4.01

4.02

4.03

–40 –5 25 85 125

VOUT (V)

JUNCTION TEM P E RATURE (°C)

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

11480-005

Figure 5. Output Voltage (VOUT) vs. Junction Temperature (TJ), ADM7151-02,

VOUT = 4 V

4.04

3.96

3.97

3.98

3.99

4.00

4.01

4.02

4.03

110 100 1000

VOUT (V)

ILOAD (mA)

11480-006

Figure 6. Output Voltage (VOUT) vs. Load Current (ILOAD), ADM7151-02,

VOUT = 4 V

4.04

3.96

3.97

3.98

3.99

4.00

4.01

4.02

4.03

5161514131211109876

VOUT (V)

VIN (V)

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

11480-007

Figure 7. Output Voltage (VOUT) vs. Input Voltage (VIN), ADM7151-02,

VOUT = 4 V

–40 –5 25 85 125

GRO UND CURRE NT (mA)

JUNCTION TEM P E RATURE (°C)

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

11480-008

Figure 8. Ground Current vs. Junction Temperature (TJ), ADM7151-02,

VOUT = 4 V

110 100 1000

GRO UND CURRE NT (mA)

ILOAD (mA)

11480-009

Figure 9. Ground Current vs. Load Current (ILOAD ), ADM7151-02, VO UT = 4 V

5161514131211109876

GRO UND CURRE NT (mA)

VIN (V)

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

11480-010

Figure 10. Ground Current vs. Input Voltage (VIN), ADM7151-02, VOUT = 4 V

Rev. A | Page 7 of 24

ADM7151 Data Sheet

–40 –5 25 85 125

SHUT DO WN CURRENT (µ A)

TEMPERATURE (°C)

0.1

0.01

0.001

0.0001

VIN = 6.2V

VIN = 6.5V

VIN = 7.0V

VIN = 10V

VIN = 16V

11480-011

Figure 11. Shutdown Current vs. Temperature at Various Input Voltages

–40 –5 25 85 125

VOUT (V)

JUNCTION TEM P E RATURE (°C)

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

5.00

4.90

4.91

4.92

4.93

4.94

4.95

4.96

4.97

4.98

4.99

11480-012

Figure 12. Output Voltage (VOUT) vs. Junction Temperature (TJ), ADM7151-04,

VOUT = 5 V

110 100 1000

VOUT (V)

ILOAD (mA)

5.00

4.90

4.91

4.92

4.93

4.94

4.95

4.96

4.97

4.98

4.99

11480-013

Figure 13. Output Voltage (VO UT) vs. Load Current (ILOAD), ADM7151-04,

VOUT = 5 V

VOUT (V)

VIN (V) 1612 141086

4.90

4.91

4.92

4.93

4.94

4.95

4.96

4.97

4.98

4.99

5.00

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

11480-014

Figure 14. Output Voltage (VO UT) vs. Input Voltage (VIN), ADM7151-04,

VOUT = 5 V

–40 –5 25 85 125

GRO UND CURRE NT (mA)

JUNCTION TEM P E RATURE (°C)

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

11480-015

Figure 15. Ground Current vs. Junction Temperature (TJ), ADM7151-04,

VOUT = 5 V

110 100 1000

GRO UND CURRE NT (mA)

ILOAD (mA)

11480-016

Figure 16. Ground Current vs. Load Current (ILOAD ), ADM7151-04,

VOUT = 5 V

Rev. A | Page 8 of 24

Data Sheet ADM7151

11480-017

GRO UND CURRE NT (mA)

VIN (V) 1612 141086

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

Figure 17. Ground Current vs. Input Voltage (VIN), ADM7151-04, VOUT = 5 V

110 100 1000

DROPOUT VOLTAGE (mA)

ILOAD (mA)

700

100

200

300

400

500

600

11480-018

Figure 18. Dropout Voltage vs. Load Current (ILOAD), ADM7151-04, VOUT = 5 V

11480-019

OUT

(V)

(V) 6.05.85.65.45.25.04.84.6

4.0

5.2

5.0

4.8

4.6

4.4

4.2

DROPOUT

= 5mA

DROPOUT

= 10mA

DROPOUT

= 100mA

DROPOUT

= 200mA

DROPOUT

= 400mA

DROPOUT

= 800mA

Figure 19. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout,

ADM7151-04, VOUT = 5 V

11480-020

GRO UND CURRE NT (µA)

VIN (V) 6.05.85.65.45.25.04.84.6

IGND = 5mA

IGND = 10mA

IGND = 100mA

IGND = 200mA

IGND = 400mA

IGND = 800mA

Figure 20. Ground Current vs. Input Voltage (VIN) in Dropout, ADM7151-04,

VOUT = 5 V

11480-021

PSRR (dB)

FRE Q UE NCY ( Hz ) 10M1M100k10k1k100101

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0LOAD = 800mA

LOAD = 400mA

LOAD = 200mA

LOAD = 100mA

LOAD = 10mA

Figure 21. Power Supply Rejection Ratio (PSRR) vs. Frequency, ADM7151-02,

VOUT = 4 V

11480-022

PSRR (dB)

FRE Q UE NCY ( Hz ) 10M1M100k10k1k100101

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0LOAD = 800mA

LOAD = 400mA

LOAD = 200mA

LOAD = 100mA

LOAD = 10mA

Figure 22. Power Supply Rejection Ratio (PSRR) vs. Frequency, ADM7151-04,

VOUT = 5 V

Rev. A | Page 9 of 24

ADM7151 Data Sheet

11480-023

PSRR (dB)

FRE Q UE NCY ( Hz ) 10M1M100k10k1k100101

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0600mV

700mV

800mV

900mV

1.0V

1.1V

1.2V

1.3V

1.4V

Figure 23. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various

Headroom Voltages, ADM7151-02, VOUT = 4 V, 400 mA Load

11480-024

PSRR (dB)

FRE Q UE NCY ( Hz ) 10M1M100k10k1k100101

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0600mV

700mV

800mV

900mV

1.0V

1.1V

1.2V

1.4V

1.6V

1.8V

Figure 24. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various

Headroom Voltages, ADM7151-04, VOUT = 5 V, 400 mA Load

11480-025

PSRR (dB)

HEADROOM ( V ) 1.51.41.31.21.11.00.90.80.70.60.5

–120

–100

–80

–60

–40

–20

100Hz

10kHz

1MHz

10Hz

1kHz

100kHz

10MHz

Figure 25. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

ADM7151-02, VOUT = 4 V, 100 mA Load

11480-026

PSRR (dB)

HEADROOM ( V ) 1.41.31.21.11.00.90.80.70.6

–120

–100

–80

–60

–40

–20

010Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

Figure 26. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

ADM7151-02, VOUT = 4 V, 400 mA Load

11480-027

PSRR (dB)

HEADROOM ( V ) 1.61.4 1.51.31.21.11.00.90.80.7

–120

–100

–80

–60

–40

–20

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

Figure 27. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

ADM7151-02, VOUT = 4 V, 800 mA Load

11480-028

PSRR (dB)

HEADROOM ( V ) 1.50.3 0.5 0.7 0.9 1.1 1.3

–140

–120

–100

–60

–20

–80

–40

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

Figure 28. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

ADM7151-04, VOUT = 5 V, 100 mA Load

Rev. A | Page 10 of 24

Data Sheet ADM7151

11480-029

PSRR (dB)

HEADROOM ( V ) 1.81.61.41.21.00.80.6

–120

–100

–60

–20

–80

–40

010Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

Figure 29. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

ADM7151-04, VOUT = 5 V, 400 mA Load

11480-030

PSRR (dB)

HEADROOM ( V ) 1.71.51.31.10.90.7

–120

–100

–60

–20

–80

–40

010Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

Figure 30. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

ADM7151-04, VOUT = 5 V, 800 mA Load

11480-031

NOI S E ( µVrms)

LOAD CURRENT ( mA) 100010010

2.0

1.6

1.2

0.8

0.4

10Hz T O 100kHz

Figure 31. RMS Output Noise vs. Load Current (ILOAD), 10 Hz to 100 kHz,

ADM7151-04, VOUT = 5 V

11480-032

NOI S E ( µVrms)

LOAD CURRENT ( mA) 100010010

2.0

1.6

1.2

0.8

0.4

100Hz T O 100kHz

Figure 32. RMS Output Noise vs. Load Current (ILOAD), 100 Hz to 100 kHz,

ADM7151-04, VOUT = 5 V

11480-033

NOI S E ( µVrms)

LOAD CURRENT ( mA) 100010010

2.0

1.6

1.2

0.8

0.4

10Hz T O 100kHz

Figure 33. RMS Output Noise vs. Load Current (ILOAD), 10 Hz to 100 kHz,

ADM7151-02, VOUT = 4 V

11480-034

NOI S E ( µVrms)

LOAD CURRENT ( mA) 100010010

2.0

1.6

1.2

0.8

0.4

100Hz T O 100kHz

Figure 34. RMS Output Noise vs. Load Current (ILOAD), 100 Hz to 100 kHz,

ADM7151-02, VOUT = 4 V

Rev. A | Page 11 of 24

ADM7151 Data Sheet

Rev. A | Page 12 of 24

11480-035

NOISE SPECTRAL DENSITY (nV/

√

Hz)

FREQUENCY (Hz)

10M100k 1M10k1k

0.1

Figure 35. Output Noise Spectral Density, 1 kHz to 10 MHz, ILOAD = 10 mA

11480-036

NOISE SPECTRAL DENSITY (nV/

√

Hz)

FREQUENCY (Hz)

100k10k1k1001010.1

100

100k

10k

Figure 36. Output Noise Spectral Density, 0.1 Hz to 10 kHz, ILOAD = 10 mA

11480-037

NOISE SPECTRAL DENSITY (nV/

√

Hz)

FREQUENCY (Hz)

10M1M100k10k1k10010

0.1

100

LOAD = 800mA

LOAD = 400mA

LOAD = 200mA

LOAD = 100mA

LOAD = 10mA

Figure 37. Output Noise Spectral Density at Different Load Currents,

10 Hz to 10 MHz

11480-038

NOISE SPECTRAL DENSITY (nV/

√

Hz)

FREQUENCY (Hz)

1M100k10k1k1001010.1

100

100k

10k

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

Figure 38. Output Noise Spectral Density at Different Load Currents,

0.1 Hz to 1 MHz

11480-039

NOISE SPECTRAL DENSITY (nV/

√

Hz)

FREQUENCY (Hz)

1M100k10k1k1001010.1

100

100k

10k

BYP

= 1µF

BYP

= 4.7µF

BYP

= 10µF

BYP

= 22µF

BYP

= 47µF

BYP

= 100µF

BYP

= 470µF

Figure 39. Output Noise Spectral Density vs. at Different CBYP,

Load Current = 10 mA

CH1 500mA Ω

CH2 20mV

M20µs A CH1 200mA

T 10.40%

11480-040

Figure 40. Load Transient Response, ILOAD = 1 mA to 800 mA,

VOUT = 5 V, VIN = 6.2 V, CH1 = IOUT, CH2 = VOUT

Data Sheet ADM7151

Rev. A | Page 13 of 24

CH1 500mA Ω

CH2 10mV

M4µs A CH1 200mA

T 11.0%

11480-041

Figure 41. Load Transient Response, ILOAD = 10 mA to 800 mA,

VOUT = 5 V, VIN = 6.2 V, CH1 = IOUT, CH2 = VOUT

CH1 200mA Ω

CH2 10mV

M2µs A CH1 460mA

T 11.0%

11480-042

Figure 42. Load Transient Response, ILOAD = 100 mA to 600 mA,

VOUT = 5 V, VIN = 6.2 V, CH1 = IOUT, CH2 = VOUT

CH1 50.0mA Ω

CH2 2.0mV

M4µs A CH1 50.0mA

T 10.0%

11480-043

Figure 43. Load Transient Response, ILOAD = 1 mA to 100 mA,

VOUT = 5 V, VIN = 6.2 V, CH1 = IOUT, CH2 = VOUT

CH1 1.0V

CH2 2.0mV Ω

M10µs A CH1 1.14V

T 10.0%

11480-044

Figure 44. Line Transient Response, 2 V Input Step, ILOAD = 800 mA,

VOUT = 1.8 V, VIN = 4.5 V, CH1 = VIN, CH2 = VOUT

CH1 1.0V

CH2 2.0mV Ω

M10µs A CH3 1.14V

T 10.0%

11480-045

Figure 45. Line Transient Response, 2 V Input Step, ILOAD = 800 mA,

VOUT = 3.3 V, VIN = 4.5 V, CH1 = VIN, CH2 = VOUT

CH1 1.0V

CH2 2.0mV Ω

M10µs A CH3 1.14V

T 10.0%

11480-046

Figure 46. Line Transient Response, 2 V Input Step, ILOAD = 800 mA,

VOUT = 5 V, VIN = 6.2 V, CH1 = VIN, CH2 = VOUT

ADM7151 Data Sheet

VOLTS

TIME (ms) 100123456789

–0.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VEN

VREG

VREF

VOUT

11480-047

Figure 47. VOUT, VREF, VR EG Start-Up Times After VEN Rising,

VOUT = 3.3 V, VIN = 5 V

Rev. A | Page 14 of 24

Data Sheet ADM7151

Rev. A | Page 15 of 24

THEORY OF OPERATION

The ADM7151 is an adjustable, ultralow noise, high power

supply rejection ratio (PSRR) linear regulator targeting radio

frequency (RF) applications. The input voltage range is 4.5 V to

16 V, and it can deliver up to 800 mA of output current. Typical

shutdown current consumption is 0.1 μA at room temperature.

Optimized for use with 10 μF ceramic capacitors, the ADM7151

provides excellent transient performance.

VREG GND

VOUT

VIN

REF

REF_SENSE

REFERENCE

SHUTDOWN

ACTIVE

RIPPLE

FILTER SHORT CIRCUIT,

THERMAL

PROTECT

OTA

E/A

BYP

11480-048

Figure 48. Adjustable Output Voltage Internal Block Diagram

Internally, the ADM7151 consists of a reference, an error amplifier,

a feedback voltage divider, and a P-channel MOSFET pass

transistor. Output current is delivered via the PMOS pass

device, which is controlled by the error amplifier. The error

amplifier compares the reference voltage with the feedback

voltage from the output and amplifies the difference. If the

feedback voltage is lower than the reference voltage, the gate

of the PMOS device is pulled lower, allowing more current to

pass and increasing the output voltage. If the feedback voltage

is higher than the reference voltage, the gate of the PMOS

device is pulled higher, allowing less current to pass and

decreasing the output voltage.

By heavily filtering the reference voltage, the ADM7151 is able

to achieve 1.7 nV/√Hz output typical from 10 kHz to 1 MHz.

Because the error amplifier is always in unity gain, the output

noise is independent of the output voltage.

To maintain very high PSRR over a wide frequency range, the

ADM7151 architecture uses an internal active ripple filter. This

stage isolates the low output noise LDO from noise on VIN.

The result is that the ADM7151 PSRR is significantly higher

over a wider frequency range than any single stage LDO.

The ADM7151 output voltage can be adjusted between 1.5 V

and 5.1 V and is available in two models that optimize the input

voltage and output voltage ranges to keep power dissipation as

low as possible without compromising PSRR performance. The

output voltage is determined by an external voltage divider

according to the following equation:

VOUT = 1.5 V × (1 + R1/R2)

VOUT

REF

REF_SENSE

GND

VIN

BYP

VREG

BYP

REG

ADM7151-04

REG

10µF

BYP

1µF

REF

1µF

OUT

= 1.5V × (R1 + R2)/R2

1kΩ < R2 < 200kΩ

10µF

OUT

10µF

OFF

= 6.2V V

OUT

= 5.0V

11480-049

Figure 49. Typical Adjustable Output Voltage Application Schematic

The R2 value must be greater than 1 kΩ to prevent excessive

loading of the reference voltage appearing on the REF pin. To

minimize errors in the output voltage caused by the REF_SENSE

pin input current, the R2 value must be less than 200 kΩ. For

example, when R1 and R2 each equal 200 kΩ, the output

voltage is 3.0 V. The output voltage error introduced by the

REF_SENSE pin input current is 10 mV or 0.33%, assuming a

maximum REF_SENSE pin input current of 100 nA at 125°C.

The ADM7151 uses the EN pin to enable and disable the VOUT

pin under normal operating conditions. When EN is high, VOUT

turns on, and when EN is low, VOUT turns off. For automatic

startup, EN can be tied to VIN.

VREG

VIN

REF_SENSE

REF

OUT

BYP

GND

18V 6V

6V 6V

18V

11480-050

Figure 50. Simplified ESD Protection Block Diagram

The ESD protection devices are shown in the block diagram as

Zener diodes (see Figure 50).

ADM7151 Data Sheet

Rev. A | Page 16 of 24

APPLICATIONS INFORMATION

MODEL SELECTION

The ADM7151 is available in two models to allow the user to

select the best combination of power dissipation and PSRR

performance for a given application.

CAPACITOR SELECTION

Output Capacitor

The ADM7151 is designed for operation with ceramic capacitors

but functions with most commonly used capacitors as long as

care is taken with regard to the effective series resistance (ESR)

value. The ESR of the output capacitor affects the stability of the

LDO control loop. A minimum of 10 μF capacitance with an

ESR of 0.2 Ω or less is recommended to ensure the stability of

the ADM7151. Output capacitance also affects transient

response to changes in load current. Using a larger value of

output capacitance improves the transient response of the

ADM7151 to large changes in load current. Figure 51 shows the

transient responses for an output capacitance value of 10 μF.

CH1 500mA Ω

CH2 10mV

M4µs A CH1 200mA

T 11.0%

11480-051

Figure 51. Output Transient Response, VOUT = 5 V, COUT = 10 μF

Input and VREG Capacitor

Connecting a 10 μF capacitor from VIN to GND reduces the

circuit sensitivity to PCB layout, especially when long input

traces or high source impedance are encountered.

To maintain the best possible stability and PSRR performance,

connect a 10 μF capacitor from VREG to GND. When more

than 10 μF of output capacitance is required, increase the input

and VREG capacitors to match it.

REF Capacitor

The REF capacitor is necessary to stabilize the reference amplifier.

Connect a capacitor of at least 1 μF between REF and GND.

Table 6. Model Selection Guide for PSRR

Model VOUT Range (V)

PSRR (dB) at 800 mA, 1.2 V Headroom PSRR (dB) at 400 mA, 1 V Headroom

10 kHz 100 kHz 1 MHz 10 kHz 100 kHz 1 MHz

ADM7151-02 1.5 to 4.0 91 91 50 94 94 58

ADM7151-04 1.5 to 5.1 84 84 53 94 94 67

Table 7. Model Selection Guide for Input Voltage

Model VOUT Range (V)

Minimum VIN at 800 mA Load Minimum VIN at 400 mA Load

VOUT < 3.3 V VOUT < 5 V VOUT ≥ 3.3 V VOUT ≥ 5 V VOUT < 3.3 V VOUT < 5 V VOUT ≥ 3.3 V VOUT ≥ 5 V

ADM7151-02 1.5 to 4.0 4.5 V N/A1 VOUT + 1.2 V N/A1 4.5 V N/A1 V

OUT + 1.0 V N/A1

ADM7151-04 1.5 to 5.1 N/A1 6.2 V N/A1 V

OUT + 1.2 V N/A1 6 V N/A1 V

OUT + 1.0 V

1 N/A = not applicable.

Data Sheet ADM7151

BYP Capacitor

The BYP capacitor is necessary to filter the reference buffer. A

1 µF capacitor is typically connected between BYP and GND.

Capacitors as small as 0.1 µF can be used; however, the output

noise voltage of the LDO increases as a result.

In addition, the BYP capacitor can be increased to reduce the

noise below 1 kHz at the expense of increasing the start-up time

of the LDO. Very large values of CBYP significantly reduce the

noise below 10 Hz. Tantalum capacitors are recommended for

capacitors larger than about 33 µF. A 1 µF ceramic capacitor in

parallel with the larger tantalum capacitor is required to retain

good noise performance at higher frequencies.

NOISE SPECTRAL DENSITY (nV/√Hz)

FRE Q UE NCY ( Hz ) 1M0.1 110 100 1k 10k 100k

100k

100

10k

CBYP = 1µF

CBYP = 4. 7µ F

CBYP = 10µF

CBYP = 22µF

CBYP = 47µF

CBYP = 100µF

CBYP = 470µF

CBYP = 1mF

11480-052

Figure 52. Noise Spectral Density vs. Frequency, CBYP = 1 µF to 1 mF

NOISE SPECTRAL DENSITY (nV/√Hz)

CBYP (µF) 1000110 100

10k

100

1Hz

10Hz

100Hz

400Hz

3Hz

30Hz

300Hz

1kHz

11480-053

Figure 53. Noise Spectral Density vs. CBYP for Different Frequencies

Capacitor Properties

Any good quality ceramic capacitors can be used with the

ADM7151 as long as they meet the minimum capacitance

and maximum ESR requirements. Ceramic capacitors are

manufactured with a variety of dielectrics, each with different

behavior over temperature and applied voltage. Capacitors must

have a dielectric adequate to ensure the minimum capacitance

over the necessary temperature range and dc bias conditions.

X5R or X7R dielectrics with a voltage rating of 6.3 V to 50 V

are recommended. However, Y5V and Z5U dielectrics are not

recommended due to their poor temperature and dc bias

characteristics.

Figure 54 depicts the capacitance vs. dc bias voltage of a 1206,

10 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is

strongly influenced by the capacitor size and voltage rating. In

general, a capacitor in a larger package or higher voltage rating

exhibits better stability. The temperature variation of the X5R

dielectric is ~±15% over the −40°C to +85°C temperature range

and is not a function of package or voltage rating.

CAPACITANCE ( µF)

DC BIAS V OL TAG E (V) 1004826

11480-054

Figure 54. Capacitance vs. DC Bias Voltage

Use Equation 1 to determine the worst-case capacitance

accounting for capacitor variation over temperature, component

tolerance, and voltage.

CEFF = CBIA S × (1 − TEMPCO) × (1 − TOL) (1)

where:

CBIAS is the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient (TEMPCO)

over −40°C to +85°C is assumed to be 15% for an X5R dielectric.

The tolerance of the capacitor (TOL) is assumed to be 10%, and

CBIAS is 9.72 µF at 5 V, as shown in Figure 54.

Substituting these values in Equation 1 yields

CEFF = 9.72 µF × (1 − 0.15) × (1 − 0.1) = 7.44 µF

Therefore, the capacitor chosen in this example meets the

minimum capacitance requirement of the LDO over

temperature and tolerance at the chosen output voltage.

To guarantee the performance of the ADM7151, it is imperative

that the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

Rev. A | Page 17 of 24

ADM7151 Data Sheet

ENABLE (EN) AND UNDERVOLTAGE LOCKOUT

(UVLO)

The ADM7151 uses the EN pin to enable and disable the VOUT

pin under normal operating conditions. As shown in Figure 55,

when a rising voltage on EN crosses the upper threshold,

VOUT turns on. When a falling voltage on EN crosses the lower

threshold, VOUT turns off. The hysteresis varies as a function

of the input voltage. For example, the EN hysteresis is

approximately 200 mV with an input voltage of 4.5 V.

VOUT (V)

VEN (V) 1.61.51.0 1.2 1.41.1 1.3

3.5

3.0

2.5

2.0

1.5

1.0

0.5

VOUT_EN_RISE

VOUT_EN_FALL

11480-055

Figure 55. Typical VO UT Response to EN Pin Operation, VOUT = 3.3 V, VIN = 5 V

EN RISE THRESHOLD (V)

VIN (V) 16

+125°C

+25°C

–40°C

14121086

1.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

11480-056

Figure 56. Typical EN Rise Threshold vs. Input Voltage (VIN) for Various

Temperatures

EN F ALL THRES HOLD ( V )

VIN (V) 16

+125°C

+25°C

–40°C

141210

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

11480-057

Figure 57. Typical EN Fall Threshold vs. Input Voltage (VIN) for Various

Temperatures

The ADM7151 also incorporates an internal undervoltage

lockout circuit to disable the output voltage when the input

voltage is less than the minimum input voltage rating of the

regulator. The upper and lower thresholds are internally fixed

with approximately 300 mV of hysteresis.

VOUT (V)

VIN (V) 4.54.44.0 4.2 4.34.1

3.5

3.0

2.5

2.0

1.5

1.0

0.5

VOUT_VIN_RISE

VOUT_VIN_FALL

11480-058

Figure 58. Typical UVLO Hysteresis, VO UT = 3.3 V

Figure 58 shows the typical hysteresis of the UVLO function.

This hysteresis prevents on/off oscillations that can occur due to

noise on the input voltage as it passes through the threshold

points.

Rev. A | Page 18 of 24

Data Sheet ADM7151

START-UP TIME

The ADM7151 uses an internal soft start to limit the inrush

current when the output is enabled. The start-up time for a 5 V

output is approximately 3 ms from the time the EN active threshold

is crossed to when the output reaches 90% of its final value.

The rise time of the output voltage (10% to 90%) is approximately

0.0012 × CBYP seconds

where CBYP is in microfarads.

OUT

(V)

TIME (Seconds) 0.0200.01600.008 0.0120.004 0.0180.0140.006 0.0100.002

ENABLE

CBYP = 1µF

CBYP = 4. 7µ F

CBYP = 10µ F

11480-059

Figure 59. Typical Start-Up Behavior with CBYP = 1 µF to 10 µF

VOUT (V)

TIME (Seconds) 0.200.1600.08 0.120.04 0.180.140.06 0.100.02

1ENABLE

CBYP = 10µF

CBYP = 47µF

CBYP = 330µF

11480-060

Figure 60. Typical Start-Up Behavior with CBYP = 10 µF to 330 µF

REF, BYP, AND VREG PINS

REF, BYP, and VREG are internally generated voltages that

require external bypass capacitors for proper operation. Do not,

under any circumstances, connect any loads to these pins

because doing so compromises the noise and PSRR performance

of the ADM7151. Using larger values of CBYP, CREF, and CREG is

acceptable but can increase the start-up time, as described in

the Start-Up Time section.

CURRENT-LIMIT AND THERMAL OVERLOAD

PROTECTION

The ADM7151 is protected against damage due to excessive

power dissipation by current and thermal overload protection

circuits. The ADM7151 is designed to current limit when the

output load reaches 1.3 A (typical). When the output load

exceeds 1.3 A, the output voltage is reduced to maintain a

constant current limit.

Thermal overload protection is included, which limits the

junction temperature to a maximum of 155°C (typical). Under

extreme conditions (that is, high ambient temperature and/or

high power dissipation) when the junction temperature starts to

rise above 155°C, the output is turned off, reducing the output

current to zero. When the junction temperature drops below

140°C, the output is turned on again, and output current is

restored to its operating value.

Consider the case where a hard short from VOUT to GND occurs.

At first, the ADM7151 current limits, so that only 1.3 A is

conducted into the short. If self heating of the junction is great

enough to cause its temperature to rise above 155°C, thermal

shutdown activates, turning off the output and reducing the

output current to zero. As the junction temperature cools and

drops below 140°C, the output turns on and conducts 1.3 A into

the short, again causing the junction temperature to rise above

155°C. This thermal oscillation between 140°C and 155°C

causes a current oscillation between 1.3 A and 0 mA that

continues as long as the short remains at the output.

Current-limit and thermal limit protections are intended to

protect the device against accidental overload conditions. For

reliable operation, device power dissipation must be externally

limited so that the junction temperature does not exceed 150°C.

THERMAL CONSIDERATIONS

In applications with low input to output voltage differential, the

ADM7151 does not dissipate much heat. However, in applications

with high ambient temperature and/or high input voltage, the

heat dissipated in the package can become large enough that it

causes the junction temperature of the die to exceed the maximum

junction temperature of 150°C.

When the junction temperature exceeds 155°C, the converter

enters thermal shutdown. It recovers only after the junction

temperature decreases below 140°C to prevent any permanent

damage. Therefore, thermal analysis for the chosen application

is important to guarantee reliable performance over all conditions.

The junction temperature of the die is the sum of the ambient

temperature of the environment and the temperature rise of the

package due to the power dissipation, as shown in Equation 2.

To guarantee reliable operation, the junction temperature of the

ADM7151 must not exceed 150°C. To ensure that the junction

temperature stays below this maximum value, the user must be

aware of the parameters that contribute to junction temperature

changes. These parameters include ambient temperature, power

dissipation in the power device, and thermal resistances between

the junction and ambient air (θJA). The θJA number is dependent

on the package assembly compounds that are used and the amount

of copper used to solder the package GND pin and exposed pad

to the PCB.

Rev. A | Page 19 of 24

ADM7151 Data Sheet

Table 8 shows typical θJA values of the 8-lead SOIC and 8-lead

LFCSP packages for various PCB copper sizes.

Table 9 shows the typical ΨJB values of the 8-lead SOIC and

8-l e a d L F C S P.

Table 8. Typical θJA Values

θJA (°C/W)

Copper Size (mm2) 8-Lead LFCSP 8-Lead SOIC

251 165.1 165

100

125.8

126.4

500

68.1

69.8

1000 56.4 57.8

6400 42.1 43.6

1 Device soldered to minimum size pin traces.

Table 9. Typical ΨJB

Values

Package

ΨJB (°C/W)

8-Lead LFCSP 15.1

8-Lead SOIC 17.9

The junction temperature of the ADM7151 is calculated from

the following equation:

TJ = TA + (PD × θJA) (2)

where:

TA is the ambient temperature.

PD is the power dissipation in the die, given by

PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND) (3)

where:

VIN and VOUT are thinput and output voltages, respectively.

ILOAD is the load current.

IGND is the groune d current.

Power dissipation due to ground current is quite small and can

be ignored. Therefore, the junction temperature equation simplifies

to the following:

TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA} (4)

As shown in Equation 4, for a given ambient temperature, input to

output voltage differential, and continuous load current, there

exists a minimum copper size requirement for the PCB to ensure

that the junction temperature does not rise above 150°C.

The heat dissipation from the package can be improved by

increasing the amount of copper attached to the pins and exposed

pad of the ADM7151. Adding thermal planes under the package

also improves thermal performance. However, as listed in Table 8, a

point of diminishing returns is eventually reached, beyond

which an increase in the copper area does not yield significant

reduction in the junction to ambient thermal resistance.

Figure 61 to Figure 66 show junction temperature calculations for

different ambient temperatures, power dissipation, and areas of

PCB copper.

11480-061

JUNCTION TEM P E RATURE (°C)

TOTAL POWER DISSIPATION (W)

6400mm2

500mm2

25mm2

TJ MAX

105

115

125

135

145

155

00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

Figure 61. Junction Temperature vs. Total Power Dissipation for

the 8-Lead LFCSP, TA = 25°C

11480-062

JUNCTION TEM P E RATURE (°C)

TOTAL POWER DISSIPATION (W)

1.8 2.0 2.2 2.41.61.41.21.0

0.80.6

0.4

0.20

100

110

120

140

160

130

150

6400mm2

500mm2

25mm2

TJ MAX

Figure 62. Junction Temperature vs. Total Power Dissipation for

the 8-Lead LFCSP, TA = 50°C

11480-063

JUNCTION TEM P E RATURE (°C)

TOTAL POWER DISSIPATION (W) 1.50.8 0.9 1.0 1.1 1.2 1.3 1.40.70.60.50.40.3

0.20.10

105

115

125

135

155

145

6400mm2

500mm2

25mm2

TJ MAX

Figure 63. Junction Temperature vs. Total Power Dissipation for

the 8-Lead LFCSP, TA = 85°C

Rev. A | Page 20 of 24

Data Sheet ADM7151

11480-064

JUNCTION TEM P E RATURE (°C)

TOTAL POWER DISSIPATION (W) 2.82.62.4 3.02.22.01.81.61.41.21.00.80.60.40.20

155

145

125

102

135

115

6400mm2

500mm2

25mm2

TJ MAX

Figure 64. Junction Temperature vs. Total Power Dissipation for

the 8-Lead SOIC, TA = 25°C

11480-065

JUNCTION TEM P E RATURE (°C)

TOTAL POWER DISSIPATION (W)

1.8 2.0 2.2 2.41.61.41.21.0

0.80.6

0.4

0.20

100

110

120

130

160

150

140

6400mm2

500mm2

25mm2

TJ MAX

Figure 65. Junction Temperature vs. Total Power Dissipation for

the 8-Lead SOIC, TA = 50°C

11480-066

JUNCTION TEM P E RATURE (°C)

TOTAL POWER DISSIPATION (W) 2.0

1.6 1.81.41.2

1.00.80.60.40.2

105

115

125

135

155

145

6400mm2

500mm2

25mm2

TJ MAX

Figure 66. Junction Temperature vs. Total Power Dissipation for

the 8-Lead SOIC, TA = 85°C

Thermal Characterization Parameter (ΨJB)

When the board temperature is known, use the thermal

characterization parameter, ΨJB, to estimate the junction

temperature rise (see Figure 67 and Figure 68). Maximum

junction temperature (TJ) is calculated from the board

temperature (TB) and power dissipation (PD) using the following

formula:

TJ = TB + (PD × ΨJB) (5)

The typical value of ΨJB is 15.1°C/W for the 8-lead LFCSP

package and 17.9°C/W for the 8-lead SOIC package.

11480-067

JUNCTION TEM P E RATURE (°C)

TOTAL POWER DISSIPATION (W) 9.0

8.58.0

7.0

6.0 7.5

6.5

5.55.0

4.54.03.53.02.5

2.0

1.51.0

0.50

160

140

120

100

TB = 25° C

TB = 50° C

TB = 65° C

TB = 85° C

TJ MAX

Figure 67. Junction Temperature vs. Total Power Dissipation for

the 8-Lead LFCSP

11480-068

JUNCTION TEM P E RATURE (°C)

TOTAL POWER DISSIPATION (W)

5.5 7.57.06.56.05.0

4.54.03.53.0

2.52.01.5

1.00.50

160

140

120

100

TB = 25° C

TB = 50° C

TB = 65° C

TB = 85° C

TJ MAX

Figure 68. Junction Temperature vs. Total Power Dissipation for

the 8-Lead SOIC

Rev. A | Page 21 of 24

ADM7151 Data Sheet

Rev. A | Page 22 of 24

PRINTED CIRCUIT BOARD LAYOUT

CONSIDERATIONS

Place the input capacitor as close as possible to the VIN and

GND pins. Place the output capacitor as close as possible to the

VOUT and GND pins. Place the bypass capacitors for VREG,

VREF, and VBYP close to the respective pins and GND. Use of an

0805, 0603, or 0402 size capacitor achieves the smallest possible

footprint solution on boards where area is limited.

11480-069

Figure 69. Example 8-Lead LFCSP PCB Layout

11480-070

Figure 70. Example 8-Lead SOIC PCB Layout

Data Sheet ADM7151

OUTLINE DIMENSIONS

2.44

2.34

2.24

TOP VIEW

0.30

0.25

0.20

BOTTOM VIEW

PIN 1 INDEX

AREA

SEATING

PLANE

0.80

0.75

0.70

1.70

1.60

1.50

0.203 REF

0.05 M AX

0.02 NO M

0.50 BSC

EXPOSED

PAD

3.10

3.00 SQ

2.90

PIN 1

INDICATOR

(R 0. 15)

FOR PRO P E R CONNECT IO N OF

THE EXPOSED PAD, REFER TO

THE PIN CO NFI G URATI ON AND

FUNCTION DES CRIPT IO NS

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.50

0.40

0.30

COMPLIANT

JEDEC STANDARDS M O-229- WEED

11-28-2012-C

0.20 M IN

Figure 71. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Very Thin, Dual Lead

(CP-8-11)

Dimensions shown in millimeters

COMPLIANT TO JEDE C S TANDARDS MS-012-AA

06-03-2011-B

1.27

0.40

1.75

1.35

2.41

0.356

0.457

4.00

3.90

3.80

6.20

6.00

5.80

5.00

4.90

4.80

0.10 M AX

0.05 NO M

3.81 REF

0.25

0.17

8°

0°

0.50

0.25

45°

COPLANARITY

0.10

1.04 REF

1.27 BSC

SEATING

PLANE

FOR PRO P E R CONNECT IO N OF

THE EXPOSED PAD, REFER TO

THE P IN CO NFI G URATI ON AND

FUNCTION DES CRIPT IO NS

SECTION OF THIS DATA SHEET.

BOTTOM VIEW

TOP VIEW

0.51

0.31

1.65

1.25

3.098

Figure 72. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]

Narrow Body

(RD-8-2)

Dimensions shown in millimeters

Rev. A | Page 23 of 24

ADM7151 Data Sheet

ORDERING GUIDE

Model1 Temperature Range Output Voltage Range(V) Package Description Package Option Branding

ADM7151ACPZ-02-R2

−40°C to +125°C

1.5 to 4.0

8-Lead LFCSP_WD

CP-8-11

LNN

ADM7151ACPZ-02-R7

−40°C to +125°C

1.5 to 4.0

8-Lead LFCSP_WD

CP-8-11

LNN

ADM7151ARDZ-02 −40°C to +125°C 1.5 to 4.0 8-Lead SOIC_N_EP RD-8-2

ADM7151ARDZ-02-R7 −40°C to +125°C 1.5 to 4.0 8-Lead SOIC_N_EP RD-8-2

ADM7151ACPZ-04-R2 −40°C to +125°C 1.5 to 5.1 8-Lead LFCSP_WD CP-8-11 LNP

ADM7151ACPZ-04-R7 −40°C to +125°C 1.5 to 5.1 8-Lead LFCSP_WD CP-8-11 LNP

ADM7151ARDZ-04 −40°C to +125°C 1.5 to 5.1 8-Lead SOIC_N_EP RD-8-2

ADM7151ARDZ-04-R7 −40°C to +125°C 1.5 to 5.1 8-Lead SOIC_N_EP RD-8-2

ADM7151CP-02-EVALZ 1.5 to 4.0 Evaluation Board

1 Z = RoHS Compliant Part.

registered trademarks are the property of

their respective owners.

D11480-0-4/15(A)

Rev. A | Page 24 of 24

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

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ADM7151ARDZ-02 ADM7151ACPZ-04-R7 ADM7151ARDZ-04 ADM7151CP-02-EVALZ ADM7151ARDZ-02-R7

ADM7151ACPZ-02-R7 ADM7151ARDZ-04-R7