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DATA SH EET
Product data sheet
Supersedes data of 2004 May 05 2004 Jul 30
DISCRETE SEMICONDUCTORS
PDTA115E series
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩ
2004 Jul 30 2
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
FEATURES
•Built-in bias resistors
•Simplified circuit design
•Reduction of component count
•Reduced pick and place costs.
APPLICATIONS
•General purpose switc hing and amplification
•Inverter and interface c ir cu i ts
•Circuit driver.
QUICK REFERENCE DATA
DESCRIPTION
PNP resistor-equipped transistor (see “Simplified outline,
symbol and pinning” for pac kage details).
SYMBOL PARAMETER TYP. MAX. UNIT
VCEO collector-emitter
voltage − −50 V
IOoutput curr en t (DC) − −20 mA
R1 bias resistor 100 −kΩ
R2 bias resistor 100 −kΩ
PRODUCT OVERVIEW
Note
1. * = p: Made in Hong Kong.
* = t: Made in Malaysia.
* = W: Made in China.
TYPE NUMBER PACKAGE MARKING CODE NPN COMPLEMENT
PHILIPS EIAJ
PDTA115EE SOT416 SC-75 5E PDTC115EE
PDTA115EEF SOT490 SC-89 6B PDTC115EEF
PDTA115EK SOT346 SC-59 62 PDTC115EK
PDTA115EM SOT883 SC-101 F6 PDTC115EM
PDTA115ES SOT54 (TO-92) SC-43 TA115E PDTC115ES
PDTA115ET SOT23 −*AB(1) PDTC115ET
PDTA115EU SOT323 SC-70 *7C(1) PDTC115EU
2004 Jul 30 3
NXP Semiconductors Pr oduct data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
SIMPLIFIED OUTLINE, SYMBOL AND PINNING
TYPE NUMBER SIMPLIFIED OUTLINE AND SYMBOL PINNING
PIN DESCRIPTION
PDTA115ES 1base
2collector
3emitter
PDTA115EE 1base
PDTA115EEF 2emitter
PDTA115EK 3collector
PDTA115ET
PDTA115EU
PDTA115EM 1base
2emitter
3collector
handbook, halfpage
MAM338
1
2
3
R1
R2
2
3
1
handbook, halfpage
MDB271
Top view
12
3
1
2
3
R1
R2
handbook, halfpage
MDB267
2
1
3
Bottom view
1
2
3
R1
R2
2004 Jul 30 4
NXP Semiconductors Pr oduct data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
ORDERING INFORMATION
LIMITING VALUES
In accordance with th e Absolute Maximum Ratin g S ystem (IEC 60134).
Notes
1. Refer to standard mounting conditions.
2. Reflow soldering is the only recommended soldering method.
3. Refer to SOT883 standard mounting conditions; FR4 with 60 μm copper strip line.
TYPE NUMBER PACKAGE
NAME DESCRIPTION VERSION
PDTA115EE −plastic surface mounted package; 3 leads SOT416
PDTA115EEF −plastic surface mounted package; 3 leads SOT490
PDTA115EK −plastic surface mounted package; 3 leads SOT346
PDTA115EM −leadless ultra small plastic package; 3 solder lands; body
1.0 × 0.6 × 0.5 mm SOT883
PDTA115ES −pla stic single-ended leaded (through ho le) packag e; 3 leads SOT54
PDTA115ET −plastic surface mounted package; 3 leads SOT23
PDTA115EU −plastic surface mounted package; 3 leads SOT323
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCBO collector-base voltage open emitter − −50 V
VCEO collector-emitter voltage open base − −50 V
VEBO emitter-base voltage open collector − −10 V
VIinput voltage
positive −+10 V
negative − −40 V
IOoutput current (DC) − −20 mA
ICM peak collector current − −100 mA
Ptot total power dissipation Tamb ≤ 25 °C
SOT23 note 1 −250 mW
SOT54 note 1 −500 mW
SOT323 note 1 −200 mW
SOT346 note 1 −250 mW
SOT416 note 1 −150 mW
SOT490 notes 1 and 2 −250 mW
SOT883 notes 2 and 3 −250 mW
Tstg storage temperature −65 +150 °C
Tjjunction temperature −150 °C
Tamb operating ambient temperature −65 +150 °C
2004 Jul 30 5
NXP Semiconductors Pr oduct data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
THERMAL CHARACTE RISTICS
Notes
1. Refer to standard mounting conditions.
2. Reflow soldering is the only recommended soldering method.
3. Refer to SOT883 standard mounting conditions; FR4 with 60 μm copper strip line.
CHARACTERISTICS
Tamb = 25 °C unless otherwise specified.
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth(j-a) thermal resistance from junction to ambient Tamb ≤ 25 °C
SOT23 note 1 500 K/W
SOT54 note 1 250 K/W
SOT323 note 1 625 K/W
SOT346 note 1 500 K/W
SOT416 note 1 833 K/W
SOT490 notes 1 and 2 500 K/W
SOT883 notes 2 and 3 500 K/W
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
ICBO collector-base cut-off current VCB = −50 V; IE = 0 A −−−100 nA
ICEO collector-emitter cut-off current VCE = −30 V; IB = 0 A −−−1μA
VCE = −30 V; IB = 0 A;
Tj = 150 °C−−−50 μA
IEBO emitter-base cu t-off current VEB = −5 V; IC = 0 A −−−50 μA
hFE DC current gain VCE = −5 V; IC = −5 mA 80 − −
VCEsat collector-emitter saturation voltage IC = −5 mA; IB = −0.25 mA −−−150 mV
Vi(off) input-off voltage IC = −100 μA; VCE = −5 V − −1.2 −0.5 V
Vi(on) input-on voltage IC = −1 mA; VCE = −0.3 V −3−1.6 −V
R1 input resistor 70 100 130 kΩ
resistor ratio 0.8 11.2
Cccollector capacitance IE = ie = 0 A; VCB = −10 V;
f = 1 MHz −−3pF
R2
R1
--------
2004 Jul 30 6
NXP Semiconductors Pr oduct data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
PACKAGE OUTLINES
UNIT A1
max bpcDEe1HELpQw
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.1 0.30
0.15 0.25
0.10 1.8
1.4 0.9
0.7 0.5
e
11.75
1.45 0.2
v
0.2
DIMENSIONS (mm are the original dimensions)
0.45
0.15 0.23
0.13
SOT416 SC-75
wM
bp
D
e1
e
A
A1
Lp
Q
detail X
HE
EAB
B
vMA
0 0.5 1 mm
scale
A
0.95
0.60
c
X
12
3
Plastic surface-mounted package; 3 leads SOT41
6
04-11-04
06-03-16
2004 Jul 30 7
NXP Semiconductors Pr oduct data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
UNIT bpcDE e1HELpwv
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
05-07-28
06-03-16
IEC JEDEC JEITA
mm 0.33
0.23 0.2
0.1 1.7
1.5 0.95
0.75 0.5
e
1.0 1.7
1.5 0.1
0.1
DIMENSIONS (mm are the original dimensions)
0.5
0.3
SOT490 SC-89
bp
D
e1
e
A
Lp
detail X
HE
E
wM
vMA
B
AB
0 1 2 mm
scale
A
0.8
0.6
c
X
12
3
Plastic surface-mounted package; 3 leads SOT49
0
2004 Jul 30 8
NXP Semiconductors Pr oduct data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
UNIT A
1
b
p
cDE e
1
H
E
L
p
Qwv
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.50
0.35 0.26
0.10 3.1
2.7 1.7
1.3 0.95
e
1.9 3.0
2.5 0.33
0.23 0.2
0.2
DIMENSIONS (mm are the original dimensions)
0.6
0.2
SOT346 TO-236 SC-59A
bp
D
e1
e
A
A1
Lp
Q
detail X
HE
E
w
M
v
M
A
B
A
B
0 1 2 mm
scale
A
1.3
1.0 0.1
0.013
c
X
12
3
Plastic surface-mounted package; 3 leads SOT34
6
04-11-11
06-03-16
2004 Jul 30 9
NXP Semiconductors Pr oduct data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
UNIT A1
max.
A(1) bb
1e1
eLL
1
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.50
0.46 0.20
0.12 0.55
0.47
0.03 0.62
0.55 0.35 0.65
DIMENSIONS (mm are the original dimensions)
Note
1. Including plating thickness
0.30
0.22
0.30
0.22
SOT883 SC-101 03-02-05
03-04-03
DE
1.02
0.95
L
E
2
3
1
b
b1
A1
A
D
L1
0 0.5 1 mm
scale
L
eadless ultra small plastic package; 3 solder lands; body 1.0 x 0.6 x 0.5 mm SOT88
3
e
e1
2004 Jul 30 10
NXP Semiconductors Pr oduct data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
UNIT A
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 5.2
5.0
b
0.48
0.40
c
0.45
0.38
D
4.8
4.4
d
1.7
1.4
E
4.2
3.6
L
14.5
12.7
e
2.54
e1
1.27
L1(1)
max.
2.5
b1
0.66
0.55
DIMENSIONS (mm are the original dimensions)
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
SOT54 TO-92 SC-43A 04-06-28
04-11-16
A L
0 2.5 5 mm
scale
b
c
D
b1L1
d
E
Plastic single-ended leaded (through hole) package; 3 leads SOT5
4
e1e
1
2
3
2004 Jul 30 11
NXP Semiconductors Pr oduct data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
UNIT A
1
max. b
p
cDE e
1
H
E
L
p
Qwv
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
04-11-04
06-03-16
IEC JEDEC JEITA
mm 0.1 0.48
0.38 0.15
0.09 3.0
2.8 1.4
1.2 0.95
e
1.9 2.5
2.1 0.55
0.45 0.1
0.2
DIMENSIONS (mm are the original dimensions)
0.45
0.15
SOT23 TO-236AB
bp
D
e1
e
A
A1
Lp
Q
detail X
HE
E
w
M
v
M
A
B
AB
0 1 2 mm
scale
A
1.1
0.9
c
X
12
3
Plastic surface-mounted package; 3 leads SOT2
3
2004 Jul 30 12
NXP Semiconductors Pr oduct data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
UNIT A1
max bpcD Ee1HELpQwv
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.1
1.1
0.8 0.4
0.3 0.25
0.10 2.2
1.8 1.35
1.15 0.65
e
1.3 2.2
2.0 0.23
0.13 0.20.2
DIMENSIONS (mm are the original dimensions)
0.45
0.15
SOT323 SC-70
wM
bp
D
e1
e
A
B
A1
Lp
Q
detail X
c
HE
E
vMA
AB
y
0 1 2 mm
scale
A
X
12
3
Plastic surface-mounted package; 3 leads SOT32
3
04-11-04
06-03-16
2004 Jul 30 13
NXP Semiconductors Pr oduct data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
DATA SHEET STATUS
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product s ta tus of device(s ) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
DOCUMENT
STATUS(1) PRODUCT
STATUS(2) DEFINITION
Objective data sheet Development This document contains data from the objective specification for pro duct
development.
Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production T his document contains the product specification.
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values (as defined in the Absolute Maximum Ratings
System of IEC 60134) may cause permanent damage to
the device. Limiting values a re s t ress ratings only and
operation of the device at these or an y other conditions
above those given in the Characteristics sections of this
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Quick refer ence data ⎯ The Quick reference data is an
extract of th e product data given in the Limiting values and
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not complete, exhaus tive or legally binding.
NXP Semiconductors
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© NXP B.V. 2009
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
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Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimer s. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Printed in The Netherlands R75/03/pp14 Date of release: 2004 Jul 30 Document order nu mber: 9397 750 13648
