NJU6637
2003
/
04
/
18
16-CHARACTER 3-LINE DOT MATRIX LCD
CONTROLLER DRIVER
GENERAL DESCRIPTION
The NJU6637 is a 1Chip Dot Matrix LCD controller
driver for up to 16-character 3-line display.
It contains microprocessor Interface circuits, Instruction
decoder controller, character generator ROM/RAM and
common and segment drivers.
The bleeder resistance generates for LCD Bias voltage
Internally.
The CR oscillator Incorporates C and R, therefore no
external components for oscillation are required.
The microprocessor Interface circuits which operate
1MHz frequency, can be connected directly to serial I/F
microprocessor.
The character generator consists of 10,200 bits ROM
and 8 x 5 bits RAM. The standard version ROM is
coded with 255 characters including capital and small
letter fonts.
The 24-common and 80-segment drive up to
16-character 3-line LCD panel which divided two
common electrode blocks.
The rectangle outlook is very applicable to COG.
FEATURES
16-character 3-line Dot Matrix LCD Controller Driver
Serial Direct Interface with Microprocessor
Display Data RAM :48 x 8 bits : Maximum 16-character 3line Display
Character Generator ROM :10,200 bits ; 255 characters for 5 x 8 dots
Character Generator RAM :8 x 5 bits ; 1 Patterns( 5 x 8 dots)
Microprocessor direst accessing to Display Data RAM and Character Generator RAM
High Voltage LCD Driver :24-common / 80-segment
Duty Ratio :1/24 Duty
Maximum Display Characters :48 Characters
Common Driver Order Assignment by mask option
Version COM1 to COM24 (PAD Name)
NJU6637A COM1 to COM24
NJU6637B COM24 to COM1
Useful Instruction Set
Clear Display, Returns Home, Display ON/OFF Cont, Cursor ON/OFF Cont, Display Blink, Cursor Shift,
Character Shift.
Power On Reset / Hardware Reset Function
Oscillation Circuit on chip
Bleeder Resistance on chip
Low Power Consumption
Operating Voltage --- +3V
Package Outline --- Bumped Chip
C-MOS Technology
PACKAGE OUTLINE
NJU6637CH
NJU6637
PAD LOCATION
NJU6637A Mode A (SEL=”L”)
Chip Size : 5.48 x 1.68mm Bump Size : 90 x 45um
Chip Center: X=0um, Y=0um Bump Height : 25um
Chip Thickness : 400um+30um Bump Material :Au
1
DUMMY3
DUMMY2
DUMMY1
DUMMY36
DUMMY37
DUMMY38
DUMMY39
DUMMY40
DUMMY41
DUMMY42
SEG9
SEG80
DUMMY43
DUMMY44
DUMMY45
DUMMY46
DUMMY47
DUMMY48
DUMMY49
DUMMY50
OSC2
OSC1
DUMMY10
VSS
VSS
VSS
V5
V5
V5
VDD
VDD
VDD
DUMMY33
COM9
SEG8
DUMMY34
DUMMY35
COM16
SEG1
x
DUMMY32
DUMMY31
DUMMY30
DUMMY11
CS
SI
SCL
RS
RESET
SEL
TE
S
T
DUMMY53
COM1
COM24
DUMMY52
DUMMY51
COM8
COM17
y
NJU6637
NJU6637A Mode B (SEL=”H”)
1
DUMMY3
DUMMY2
DUMMY1
DUMMY36
DUMMY37
DUMMY38
DUMMY39
DUMMY40
DUMMY41
DUMMY42
SEG72
SEG1
DUMMY43
DUMMY44
DUMMY45
DUMMY46
DUMMY47
DUMMY48
DUMMY49
DUMMY50
OSC2
OSC1
DUMMY10
VSS
VSS
VSS
V5
V5
V5
VDD
VDD
VDD
DUMMY33
COM9
SEG73
DUMMY34
DUMMY35
COM16
SEG80
x
DUMMY32
DUMMY31
DUMMY30
DUMMY11
CS
SI
SCL
RS
RESET
SEL
TEST
DUMMY53
COM1
COM24
DUMMY52
DUMMY51
COM8
COM17
y
NJU6637
NJU6637B Mode A (SEL=”L”)
1
DUMMY3
DUMMY2
DUMMY1
DUMMY36
DUMMY37
DUMMY38
DUMMY39
DUMMY40
DUMMY41
DUMMY42
SEG9
SEG80
DUMMY43
DUMMY44
DUMMY45
DUMMY46
DUMMY47
DUMMY48
DUMMY49
DUMMY50
OSC2
OSC1
DUMMY10
VSS
VSS
VSS
V5
V5
V5
VDD
VDD
VDD
DUMMY33
COM16
SEG8
DUMMY34
DUMMY35
COM9
SEG1
x
DUMMY32
DUMMY31
DUMMY30
DUMMY11
CS
SI
SCL
RS
RESET
SEL
TEST
DUMMY53
COM24
COM1
DUMMY52
DUMMY51
COM17
COM8
y
NJU6637
NJU6637B Mode B (SEL=”H”)
1
DUMMY3
DUMMY2
DUMMY1
DUMMY36
DUMMY37
DUMMY38
DUMMY39
DUMMY40
DUMMY41
DUMMY42
SEG72
SEG1
DUMMY43
DUMMY44
DUMMY45
DUMMY46
DUMMY47
DUMMY48
DUMMY49
DUMMY50
OSC2
OSC1
DUMMY10
VSS
VSS
VSS
V5
V5
V5
VDD
VDD
VDD
DUMMY33
COM16
SEG73
DUMMY34
DUMMY35
COM9
SEG80
x
DUMMY32
DUMMY31
DUMMY30
DUMMY11
CS
SI
SCL
RS
RESET
SEL
TEST
DUMMY53
COM24
COM1
DUMMY52
DUMMY51
COM17
COM8
y
NJU6637
Alignment Mark size
DUMMY1
DUMMY32
DUMMY36
DUMMY50
63
10.8
14.4
10.8
12.6
14.4
63
10.8
14.4 10.8
12.6 14.4
90
10.8
14.4
10.8
39.6
14.4
63
10.8
14.4 10.8
12.6 14.4
y x
y x
NJU6637
PAD COORDINATES
Chip Size(5.4 8mm x 1.68mm)
PAD Name
PAD Name
PAD No. SEL=H SEL=L
X= µmY= µm
PAD No. SEL=H SEL=L
X= µmY= µm
1
DUMMY1 DUMMY1
-2599 -690 51
DUMMY33 DUMMY33
2599 -540
2
DUMMY2 DUMMY2
-2520 -690 52 COM9 COM9 2599 -480
3
DUMMY3 DUMMY3
-2460 -690 53 COM10 COM10 2599 -420
4
DUMMY4 DUMMY4
-2400 -690 54 COM11 COM11 2599 -360
5
DUMMY5 DUMMY5
-2340 -690 55 COM12 COM12 2599 -300
6
DUMMY6 DUMMY6
-2280 -690 56 COM13 COM13 2599 -240
7
DUMMY7 DUMMY7
-2220 -690 57 COM14 COM14 2599 -180
8
DUMMY8 DUMMY8
-2160 -690 58 COM15 COM15 2599 -120
9
DUMMY9 DUMMY9
-2100 -690 59 COM16 COM16 2599 -60
10
DUMMY10 DUMMY10
-2040 -690 60 SEG80 SEG1 2599 0
11 OSC1 OSC1 -1860 -690 61 SEG79 SEG2 2599 60
12 OSC2 OSC2 -1620 -690 62 SEG78 SEG3 2599 120
13 V5 V5 -1440 -690 63 SEG77 SEG4 2599 180
14 V5 V5 -1380 -690 64 SEG76 SEG5 2599 240
15 V5 V5 -1320 -690 65 SEG75 SEG6 2599 300
16 VSS VSS -1080 -690 66 SEG74 SEG7 2599 360
17 VSS VSS -1020 -690 67 SEG73 SEG8 2599 420
18 VSS VSS -960 -690 68
DUMMY34 DUMMY34
2599 480
19 VDD VDD -900 -690 69
DUMMY35 DUMMY35
2599 540
20 VDD VDD -840 -690 70
DUMMY36 DUMMY36
2599 698
21 VDD VDD -780 -690 71
DUMMY37 DUMMY37
2520 698
22 TEST TEST -540 -690 72
DUMMY38 DUMMY38
2460 698
23 SEL SEL -300 -690 73
DUMMY39 DUMMY39
2400 698
24 RESET RESET -60 -690 74
DUMMY40 DUMMY40
2340 698
25 RS RS 180 -690 75
DUMMY41 DUMMY41
2280 698
26 SCL SCL 420 -690 76
DUMMY42 DUMMY42
2220 698
27 SI SI 660 -690 77
SEG72 SEG9 2160 698
28 CS CS 1140 -690 78
SEG71 SEG10 2100 698
29
DUMMY11 DUMMY11
1320 -690 79 SEG70 SEG11 2040 698
30
DUMMY12 DUMMY12
1380 -690 80 SEG69 SEG12 1980 698
31
DUMMY13 DUMMY13
1440 -690 81 SEG68 SEG13 1920 698
32
DUMMY14 DUMMY14
1500 -690 82 SEG67 SEG14 1860 698
33
DUMMY15 DUMMY15
1560 -690 83 SEG66 SEG15 1800 698
34
DUMMY16 DUMMY16
1620 -690 84 SEG65 SEG16 1740 698
35
DUMMY17 DUMMY17
1680 -690 85 SEG64 SEG17 1680 698
36
DUMMY18 DUMMY18
1740 -690 86 SEG63 SEG18 1620 698
37
DUMMY19 DUMMY19
1800 -690 87 SEG62 SEG19 1560 698
38
DUMMY20 DUMMY20
1860 -690 88 SEG61 SEG20 1500 698
39
DUMMY21 DUMMY21
1920 -690 89 SEG60 SEG21 1440 698
40
DUMMY22 DUMMY22
1980 -690 90 SEG59 SEG22 1380 698
41
DUMMY23 DUMMY23
2040 -690 91 SEG58 SEG23 1320 698
42
DUMMY24 DUMMY24
2100 -690 92 SEG57 SEG24 1260 698
43
DUMMY25 DUMMY25
2160 -690 93 SEG56 SEG25 1200 698
44
DUMMY26 DUMMY26
2220 -690 94 SEG55 SEG26 1140 698
45
DUMMY27 DUMMY27
2280 -690 95 SEG54 SEG27 1080 698
46
DUMMY28 DUMMY28
2340 -690 96 SEG53 SEG28 1020 698
47
DUMMY29 DUMMY29
2400 -690 97 SEG52 SEG29 960 698
48
DUMMY30 DUMMY30
2460 -690 98 SEG51 SEG30 900 698
49
DUMMY31 DUMMY31
2520 -690 99 SEG50 SEG31 840 698
50
DUMMY32 DUMMY32
2599 -690 100 SEG49 SEG32 780 698
NJU6637
PAD Name
PAD Name
PAD No. SEL=H SEL=L
X= µmY= µm
PAD No. SEL=H SEL=L
X= µm
Y= µm
101 SEG48 SEG33 720 698 151
DUMMY45 DUMMY45
-2280 698
102 SEG47
SEG34 660 698 152
DUMMY46 DUMMY46
-2340 698
103 SEG46
SEG35 600 698 153
DUMMY47 DUMMY47
-2400 698
104 SEG45
SEG36 540 698 154
DUMMY48 DUMMY48
-2460 698
105 SEG44 SEG37 480 698 155
DUMMY49 DUMMY49
-2520 698
106 SEG43 SEG38 420 698 156
DUMMY50 DUMMY50
-2599 698
107 SEG42 SEG39 360 698 157
DUMMY51 DUMMY51
-2599 540
108 SEG41 SEG40 300 698 158
DUMMY52 DUMMY52
-2599 480
109 SEG40 SEG41 240 698 159 COM24 COM24 -2599 420
110 SEG39 SEG42 180 698 160 COM23 COM23 -2599 360
111 SEG38 SEG43 120 698 161 COM22 COM22 -2599 300
112 SEG37 SEG44 60 698 162 COM21 COM21 -2599 240
113 SEG36 SEG45 0 698 163 COM20 COM20 -2599 180
114 SEG35 SEG46 -60 698 164 COM19 COM19 -2599 120
115 SEG34 SEG47 -120 698 165 COM18 COM18 -2599 60
116 SEG33 SEG48 -180 698 166 COM17 COM17 -2599 0
117 SEG32 SEG49 -240 698 167 COM8 COM8 -2599 -60
118 SEG31 SEG50 -300 698 168 COM7 COM7 -2599 -120
119 SEG30 SEG51 -360 698 169 COM6 COM6 -2599 -180
120 SEG29 SEG52 -420 698 170 COM5 COM5 -2599 -240
121 SEG28 SEG53 -480 698 171 COM4 COM4 -2599 -300
122 SEG27 SEG54 -540 698 172 COM3 COM3 -2599 -360
123 SEG26 SEG55 -600 698 173 COM2 COM2 -2599 -420
124 SEG25 SEG56 -660 698 174 COM1 COM1 -2599 -480
125 SEG24 SEG57 -720 698 175
DUMMY53 DUMMY53
-2599 -540
126 SEG23 SEG58 -780 698
127 SEG22 SEG59 -840 698
128 SEG21 SEG60 -900 698
129 SEG20 SEG61 -960 698
130 SEG19 SEG62 -1020 698
131 SEG18 SEG63 -1080 698
132 SEG17 SEG64 -1140 698
133 SEG16 SEG65 -1200 698
134 SEG15 SEG66 -1260 698
135 SEG14 SEG67 -1320 698
136 SEG13 SEG68 -1380 698
137 SEG12 SEG69 -1440 698
138 SEG11 SEG70 -1500 698
139 SEG10 SEG71 -1560 698
140 SEG9 SEG72
-1620 698
141 SEG8 SEG73
-1680 698
142 SEG7 SEG74
-1740 698
143 SEG6 SEG75
-1800 698
144 SEG5 SEG76
-1860 698
145 SEG4 SEG77
-1920 698
146 SEG3 SEG78
-1980 698
147 SEG2 SEG79
-2040 698
148 SEG1 SEG80
-2100 698
149
DUMMY43 DUMMY43
-2160 698
150
DUMMY44 DUMMY44
-2220 698
NJU6637
BLOCK DIAGRAM
Instruction
Decoder(ID) Address
Counter
Display Data RAM (DDRAM)
48 x 8bits
Character
Generator
RAM(CGRAM)
8 x 5bits
Character
Generator
ROM(CGROM)
10,200bits
Instruction Reg.(IR) Data
Reg.(DR)
Cursor Blink Cont.
Timing
Gen.
24bit
Shift Re
g
. 80bit Latch
Common
Driver Segment
Driver
I/O Buffer
CR
OSC
Power on
Reset
80bit
Shift Reg.
OSC1
OSC2
SCL
CS
RESET
RS
S
I
SEL
COM1 to
COM24
SEG1 to
SEG80
VSS
VDD
V5 V5
V4
V3
V2
V1
Parallel to Serial Convertor
NJU6637
TERMINAL DESCRIPTION
PAD No. SYMBOL I/O FUNCTION
19-21
16-18 V
DD
V
SS
Power Source : V
DD
= +3V,
GND : V
SS
= 0V
13-15 V
5
LCD driving Power Source
11 OSC
1
I Oscillation Frequency Adjustment Terminals. Normally Open.
(Oscillation C and R are Incorporated, Osc Freq.=145kHZ)
12 OSC
2
O Oscillation Frequency Adjustment Terminals. Normally Open.
This terminal also operates as the clock frequency monitor.
25 RS I Resister selection signal Input
"0": Instruction Resister
"1":Data Register
26 SCL I Shift clock input
28 CS I Chip select signal input
27 SI I Data input terminal
23 SEL I Segment driver location order select terminal
"0": Mode A
"1": Mode B
52-59
159-174 COM
1
– COM
24
O LCD Common driving signal Terminals
60-67
77-148 SEG
1
– SEG
80
O LCD segment driving signal Terminals
24 RESET I Reset Terminal
When the “L” level Input over than 1.2ms to this terminal,
the system will be reset.(f
OSC
=145kHz)
22 TEST I Maker Test Terminal
This terminal should be connected to Vss or open.
1-9
22-51
68-76
149-158
175
DUMMY
1
DUMMY
53
– Dummy Terminal
These terminals are electrically open.
NJU6637
FUNCTIONAL DESCRIPTION
(1)Description for each blocks
(1-1)Register
The NJU6637 incorporates two 8-bit registers, an Instruction Register (IR) and a Data Register (DR).
The Register (IR) stores Instruction codes such as “Clear Display” and “Return Home”, and address
data for Display Data RAM (DD RAM) and Character Generator RAM (CG RAM).
The Register (DR) is a temporary storing register, the data in the Register (DR) is written into the
DD RAM or CG RAM.
The data in the Register (DR) written by the MPU is transferred from the Register automatically to the
DD RAM or CG RAM by Internal operation.
These two registers are selected by the selection signal RS.
(1-2) Address counter (AC)
The address Counter (AC) addresses the DD RAM and CG RAM.
When the address setting instruction is written into the Register (IR), the address information is
transferred from Register (IR) to the counter (AC). The selection of either the DD RAM or CG RAM is
also determined by this instruction.
After writing (or reading) the display data to (or from) the DD RAM or CG RAM, the counter (AC)
increments (or decrements) “1” automatically.
(1-3)Display Data RAM (DD RAM)
The display data RAM (DD RAM) consisting of 48 x 8 bits stores up to 48-character display data
represented in 8-bit code.
The DD RAM address data set in the address Counter (AC) is represented in hexadecimal.
Higher order bit Lower order bit (Example) DD RAM address “ 08 ”
AC AC
6
AC
5
AC
4
AC
3
AC
2
AC
1
AC
0
0 0 0 1 0 0 0
16-character 2-line Display
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Display position
1
st
line 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F DD RAMaddress(Hex.)
2
nd
line 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
3
rd
line 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F
The relation between DD RAM address and display position on the LCD shown below.
[ Left Shift Display ]
(00) 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00
(10) 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 10
(20) 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 20
[ Right Sift Display ]
0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E (0F)
1F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E (1F)
2F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E (2F)
0
Hexadecimal 8
Hexadecimal
NJU6637
(1-4)Character Generator ROM(CG ROM)
The Character Generator ROM (CG ROM) generates 5 x 8 dots character pattern represented in 8-bit
character codes.
The s torage capacity is up to 255 k inds of 5 x 8 dots character pattern. The cor respondenc e between
character code and standard character pattern is shown in Table 2.
User-defined character pattern ( Custom Font ) are also available by mask option.
Table 2. CG ROM Character Pattern ( ROM version –02 )
Lower 4 bit
(
Hexadecimal
)
U
pp
er 4 bit
(
Hexadecimal
)
NJU6637
(1-5)Character Generator RAM
The character generator RAM (CG RAM) stores any kinds of character pattern in 5 x 8 dots written by
the user program to d ispla y user’s orig inal c harac ter pattern. T he CG R AM stor es 1 k inds of char acter
in 5 x 8 dots mode.
To display user’s original character pattern stored in the CG RAM, the address data (00)
H
should be
written to the DD RAM as shown in Table 2.
Table 3. shows the correspondence among the character pattern, CG RAM address and data.
Table 3. Correspondence of CG RAM address, DD RAM character code
and CG RAM character pattern (5 x 8 dots)
Character Code
(DD RAM data) CG RAM address Character pattern
(CG RAM data)
7 6 5 4 3 2 1 0
Upper bit Lower bit
7 6 5 4 3 2 1 0
Upper bit Lower bit
4 3 2 1 0
Upperbit Lowerbit
0 0 0 0 0 0 0 0
0 1 0 0 0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1 1 1 1 0
1 0 0 0 1
1 0 0 0 1
1 1 1 1 0
1 0 1 0 0
1 0 0 1 0
1 0 0 0 1
0 0 0 0 0
Character
Pattern
Example
Cursor Position
Notes: 1. Character code bits 0 and 1 correspond to the CG RAM address 3 and 4.
2. CG RAM address 0, 1 and 2 designate a character pattern line position.
The 8th line is the cursor position and the display is performed by logical OR with cursor.
Therefore, in case of the cursor display, the data of 8th line should be “0”.
If there is “1” in the 8th line, the bit “1” is always displayed on the cursor position regardless of
cursor existence.
3. Character pattern row position corresponding to the CG RAM data bits 0 to 4 are all shown above.
4. ”1” for CG RAM data corresponds to display On and “0” to display Off.
(1-6)Timing Generator
The timing generator generates a timing signals for the DD RAM, CG RAM, CG ROM and other internal
circuit operation.
RAM read t iming for the displa y and i nter n al op er ati on timing for MP U acc es s ar e s eparatel y ge nerat ed ,
so that they may not interfere with each other.
Theref ore, when the d ata write to th e DD RAM f or exam ple, ther e will b e undes irable I nfluenc e, such a s
flickering, in areas other than the display area.
(1-7) LCD Driver
LCD driver consists of 24-common driver and 80-segment driver.
The 80 bits of character pattern data are shifted in the shift-register and latched when the 40 bits shift
performed completely. This latched data controls display driver to output LCD driving waveform.
(1-8) Common Driver Assignment
The scanning order can be assigned by mask option as shown as follows:
COM Outputs Terminals
PAD No. 174 167 166 159 59 52
Pin name COM1 COM8 COM17 COM24 COM16 COM9
Ver. A COM1 COM8 COM17 COM24 COM16 COM9
Ver. B COM24 COM17 COM8 COM1 COM9 COM16
NJU6637
(1-9) Cursor Blinking Control Circuit
This circuits controls cursor On/Off and cursor position character blinks. The cursor or blinks
appears in the digit position at the DD RAM address set in the address counter(AC).
When the address counter is (08)
H
, a cursor position is shown as follows:
AC
6
AC
5
AC
4
AC
3
AC
2
AC
1
AC
0
AC 0 0 0 1 0 0 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Display Position
1
st
line 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F DD RAM Address
2
nd
line 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F (Hexadecimal)
3
rd
line 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F
Note) The cursor or blinks appears when the address counter (AC) selects the CG RAM.
But the displayed cursor and blink are meaningless.
If the AC stores the CG RAM address data, the cursor and blink are displayed in the meaningless position.
(2)Power on Initialization by internal circuits
(2-1) Initializati on By internal Reset circuits
The NJU6637 is initiali zed automaticall y by the in ter na l p o wer on in itializat ion c irc uits wh en the p o wer i s
turned on. In the internal power on initialization, following instructions are executed.
During the internal power on initialization is kept 4ms after V
DD
= 2.4V. (fosc=145KHz)
Initialization flow is shown below:
Display On/Off
Control
Entry Mode Set
Clear Display
Note) If the condition of po wer supply rise tim e described in the Electrical Chara cteristics is not satisfied, the
internal Po wer on init ial i zati on Cir c uits will not oper ate and in iti al i zation wil l not be perf ormed.
In this case, the initialization by MPU software is required.
(2-2) Initialization By Hardware
The NJU6637 incorporates RESET terminal to initialize the all system. When the “L” level input over
than 1.2m s to the RESET term inal, the reset sequenc e is executed. In t his time, the in itialization d uring
4ms after RESET terminal goes to “H”.
Operation timing
Over 1.2ms Initializat ion set tim e
4ms
External Reset
Si
nal
Cursor Position
D=0 :Display Off
C=0 :Cursor Off
B=0 :Cursor Blink Off
I/D=1 :Increment by 1
S=0 :No Shift
NJU6637
(3)Instructions
The NJU6637 incorporates two resisters, which are Instruction Register (IR) and a Data Register (DR).
These two registers store control information temporarily to allow interface between NJU6637 and MPU or
peripheral ICs operating different cycles. The operation of NJU6637 is determined by this control signal
from MPU. The control information includes register selection signals (RS) and data bus signals (DB
0
to
DB
7
). Table 5. Shows each instruction and its operating time.
Note) The execution time mentioned in Table 5. is based on or f
OSC
=145kHz.
If the oscillation frequency is changed, the execution time is also changed.
Table 5. Table of Instruction
C O D E
INSTRUCTION
RS DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
DESCRIPTION EXEC TIME
(f
OSC
=145kHz)*
Maker Test 0 000 00 000
All “0” code is using for maker
testing.
Clear Display 0 000 00 001
Display clear and sets DD RAM
address 0 in AC.
2ms
Return Home
0 000 00 01
Sets DD RAM address 00H In AC
and returns display being shifted to
original positi on.
DD RAM contents remain
unchanged.
0µs
Entry Mode Set
0 000 00 1I/D S
Sets cursor move direction and
species shift of display are
perform ed In data write.
I/D=1:Increment,
I/D=D:Decrement,
S=1:Accopani es displ a y shift.
0µs
Display ON/OFF
Control 0 000 01 DC B
Sets of display On/Off(D), cursor
On/Off(C) and blink of cursor
positi on charact er(B )
0µs
Cursor or Display
Shift
0 0 0 0 1 S/C R/L
Move cursor and shifts display
without changing DD RAM
contents.
S/C=1 : Display shift
S/C=0 : Cursor shift
R/L=1 : Shift to right
R/L=0 : Shift to the left
0µs
Set RAM Address 0 1 RAM address
Sets RAM address. After this
instruction, the data is transferred
to RAM.
0µs
Write Data(DD RAM)
Write Data to
CG or DD RAM 1 (CG RAM)
W rites data into CG or DD RAM.
55µs
Explanat ion of
Abbreviation
DD RAM : Display data RA M, CG RAM : Character generat or RAM
ACG : CG RAM address, ADD : DD RAM address, Corresponds to cursor address
AC : Address count er used for both DD and CG RAM
*:Don't care
Note : The time of between instruction and next instruction is needed to consider PWcs .
PWcs is decided by sum of PWcs(500ns) and instruction execution time.
It is possible that instruction execution time is changes in same as oscillation frequency ratio.
NJU6637
(3-1)Description of instruction
a) Maker Test
RS DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Code 0 0 0 0 0 0 0 0 0
All “0” code is using device testing mode ( only for maker ).
b) Clear Display
RS DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Code 0 0 0 0 0 0 0 0 1
Clear display instruction is executed when the code “1” is written into DB
0
.
when this instructi on is ex ecuted, th e space code (2 0)
H
is written into every DD RAM address, the
DD RAM address 0 is set into the address counter and entry mode is set an increment. If the
cursor or blink are displayed, they are returned to the left end of the 1
st
line on the LCD.
The S of entry mode and CG RAM data does not change.
Note: The character pattern for character code (20)
H
must be blank code in the user-defined
character pattern( Custom font ).
c) Return Home
RS DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Code 0 0 0 0 0 0 0 1
Return hom e instruction is executed when the code “1” is written Into DB
1
. When this Instruction
is executed, the DD RAM address 0 is set to address counter. Displa y is returned to the original
position if s hifted, the cur sor or blink is retur ned to the left end of the L CD. If t he c urs or or b link ar e
on the display, the DD RAM contents are not changed.
d) Entry Mode Set
RS DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Code 0 0 0 0 0 0 1 I/D S
Entr y mode set instruc tion which sets c ursor m oving direct ion and displa y shift On/O ff, is execut ed
when the code “1” is written into D B
2
and the codes of (I/D) and (S) are written into DB
1
(I/D) and
DB
0
(S) as shown below.
(I/D) sets the address increment or decrement, and the (S) sets the entire display shift in the DD
RAM writing.
I/D FUNCTION
1 Address increm ent : T he addres s of the DD RAM incr em ent ( +1) when
the write, and the cursor or blink moves to the right.
0 Address decrement : The address of the DD or CG RAM decrement
( -1) when the write, and the cursor or blink move to the left.
S FUNCTION
1 Entire display shift.
The s hift direc tion is det er mined by I/D: shift to the left at I/D= 1 an d s hift
to the right a t the I/ D=0. The shift is oper ate d with on l y the c harac ter, so
that it looks as if the cursor stands still and the display moves. The
display does not shift when reading from the DD RAM and writing into
CG RAM.
0 The display does not shifting
=Don’t Care
NJU6637
e) Display ON/OFF Control
RS DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Code 0 0 0 0 0 1 D C B
Display On/Off control instruction which controls the display On/Off, the cursor On/Off and the
cursor position character blink, is executed when the code “1” is writte n into DB
3
and the codes of
(D), (C) and (B) are written into DB
2
(D), DB
1
(C) and DB0(B) as shown below.
D FUNCTION
1 Display On.
0 Display Off . In this m ode, the dis pla y data remains in the DD RAM s o
that it is retrieved immediately on the display when the D change to 1.
C FUNCTION
1 Cursor On. The cursor is displayed by 5 dots on the 8th line.
0 Cursor Off. Even if the display data write, the I/D etc does not change.
B FUNCTION
1 The cursor position character is blinking. Blinking rate is 600ms at
f
OSC
=145kH z. The blink is displayed alternatively with all on (it means
all black) and characters display. The cursor and the blink can be
displayed simultaneously.
0 The character does not blink.
f) Cursor Display Shift
RS DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Code 0 0 0 0 1 S/C R/L
The Cursor/Display shift instruction shifts the cursor position or display the right or left without
writing reading display data. This function is used to correct or search the display. The cursor
moves to the 2nd line when it passes the 16th digit of the 1st line. Notice that the ever y 1st to 3rd
line displays shift at the same time. When the displayed data are shifted repeatedly, each line
moves only horizontally.
The 2nd and 3rd line display does not shift into the 1st and 2nd line.
The contents of address counter (AC) is not changed by operation of display shift only.
This instructio n is ex ecuted when t he code “1” is writte n into D B
4
and th e codes of (S/C) an d (R/L )
are written int o DB
3
(S/C) and DB
2
(R/L) as shown below.
S/C R/L FUNCTION
0 0 Shifts the cursor position to the left ((AC) is decrement by 1)
0 1 Shifts the cursor position to the right ((AC) is incremented by 1)
1 0 Shifts the entire display to the left and the cursor follows it.
1 1 Shifts the entire display to the right and the cursor follows it.
=Don’t Care
! " " " !
" ! ! ! "
" ! ! ! "
" ! ! ! "
" " " " "
" ! ! ! "
" ! ! ! "
" " " " "
Character Font 5 x 7dots
(1) Cursor display example
! " " " !
" ! ! ! "
" ! ! ! "
" ! ! ! "
" " " " "
" ! ! ! "
" ! ! ! "
! ! ! ! !
Alternating displa y
(2) Blink display example
" " " " "
" " " " "
" " " " "
" " " " "
" " " " "
" " " " "
" " " " "
" " " " "
NJU6637
g) Set RAM Address
RS DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Code 0 1 A A A A A A A
Higher order bit Lower order bit
The RAM address set instruction is executed when the code "1" is written into DB7 and the
address is written into DB6 to DB0 as shown above.
The address data (DB6 to DB0) is written into the address counter (AC) by this instruction.
After this instruction execution, the data writing is performed into the addressed RAM.
The RAM includes DD RAM and CG RAM, and these RAMs are shared by address as shown
below.
DD RAM address
DD RAM 1-Line : (00)
H
– (0F)
H
DD RAM 2-Line : (10)
H
– (1F)
H
DD RAM 3-Line : (20)
H
– (2F)
H
CG RAM 1character : (40)
H
– (47)
H
h) Write Data to CG or DD RAM
Write data to DD RAM
RS DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Code 1 D D D D D D D D
Higher order bit Lower order bit
Write data to CG RAM
RS DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Code 1 D D D D D
Higher order bit Lower order bit
Write Data to CG RA M or DD RAM instructi on is exe cuted when the code ” 1” is written into (R S)
and code “0” is writte n into (R/W).
By the execution of this instruction, the b inary 5-bit data “DDDDD” are written into the CG RAM,
and the binary 8-bit data “DDDDDDDD” are written into the DD RAM. The selection of the CG
RAM or DD RAM is determ ined b y the previo us instruc t ion.
After this instruction execution, the address increment(+1) or decrement(-1) is performed
autom atically accord ing to t he entry m ode set. And the dis pla y shift is also exec uted accord ing to
the previous entry mode set.
=Don’t Care
NJU6637
(3-2) Initialization by instruction
If the po wer supply con ditions for the correct operation of the internal res et circuits are no t method, t he
NJU6637 must be initialized by the instruction.
Power On
Wait more than 4 ms
after V
DD
rises to 2.4V
RS DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Display Off 0 0 0 0 0 1 0 0 0
RS DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Display Clear 0 0 0 0 0 0 0 0 1
RS DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Entry Mode Set 0 0 0 0 0 0 1 1 0
Write data to the CG or DD RAM
and set the instruction.
Initialized.
No display appears.
Example for set address
in crem en t and c urs o r righ t sh ift
when the data write to the DD
RAM.
NJU6637
(4) Bleeder Resistance
Each LCD driving voltage ( V1, V2, V3, V4 ) is generated by the high impedance bleeder resistance
buffered by voltage follower OP-AMP to get a enough display characteristics with low operating current.
The bleeder resistance is set 1/6.3 bias suitable for 1/24 duty ratio and 6M resistance in total.
The capacitor connected between V5 and VDD is needed for stabilizing V5. The determination of the
each capacitance of C1, C2 and C3 generating for LCD operating voltage, is required to operate with
the LCD panel actually. The capacitance for the typical application is shown below :
LCD Driving Voltage vs. Duty Ratio
Duty Ratio 1/24
Power
Supply Bias 1/6.3
V
5
V
DD
-V
LCD
The V
LCD
is maximum swing of LCD waveform.
LCD Driving Voltage example
952k
V
5
V
DD
V
LCD
V
5
V
4
V
3
V
2
V
1
2192k
952k
952k
952k
NJU6637
NJU6637
(5) Relation between oscillation frequency and LCD frame frequency.
As the NJU6637 incorporate oscillation capacitor and resistor for CR oscillation, 145kHz oscillation is
availab le with out any exter nal com ponents.
The LCD frame frequency example mentioned below is based on 145kHz oscillation.(1clock =6.875
µ
s)
1/24 duty
1 frame = 6.875 (µs) x 96 x 24 = 15.84 (ms)
Frame frequency = 1 / 15.84 (ms) = 63.1 (Hz)
(6) Interface with MPU
Serial interface circuit is activated when the chip select terminal (CS) goes to "L" level. The data
input is MSB first like as the order of DB7, DB6 ---- DB0.
The input data is entered into the shift register synchronized at the rise edge of the serial clock SCL.
The shift register converted to parallel data at the CS rise edge input.
In case of entering over than 8-bit data, valid data is last 8-bit data.
The time chart for the serial interface is shown below.
Note : The level ("L" or "H") of RS terminals should be set before CS terminal goes to "L" level.
CS
RS
SCL
SI DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 2 3
96 clock
2 3 4 24 • • • • • • • • • • • • 1 2 3 4 24 1
V
DD
V
1
V
2
V
4
V
5
1 frame 1 frame
V
3
NJU6637
ABSOLUTE MAXIMUM RATINGS
(Ta=25°C)
P A R A M E T E R SYMBOL R A T I N G S UNIT NOTE
Supply Voltage (1) V
DD
-0.3 – +7.0 V
Supply Voltage (2) V
LCD
VDD-7.0 – VDD+0.3 V V5 Terminal
Input Voltage V
IN
-0.3 – V
DD
+0.3 V
Operating Temperature T
opr
-30 – +80 °C
Storage Temperature T
stg
-55 +125 °C
Note 1.) If the LSI is used on condition above the absolute maximum ratings, the LSI may be destroyed.
Using the LSI within electrical characteristics is strongly recommended for normal operation. Use
beyond the electric characteristics conditions will cause malfunction and poor reliability.
Note 2.) Decoupling capacitor should be connected between V
DD
and V
SS
, V
DD
and V
5
due to the stabilized
operation for the LSI.
Note 3.) All voltage values are specified as V
SS
=0V
Note 4.) The relation V
DD
>V
SS
V
5
, V
SS
=0V must be maintained.
ELECTRICAL CHARACT ERI STICS
(VDD=2.4 – 3.6V, VSS= 0V, Ta=25 °C)
PARAMETER SYMBOL SYMBOL MIN TYP MAX UNIT NOTE
Operating Volt. V
DD
V
DD
2.4 3.0 3.6 V
V
IH1
0.8 V
DD
– V
DD
V
Input Voltage 1 V
IL1
All Input / Output Terminals except
OSC1 Terminals V
SS
0.2 V
DD
V
V
IH2
V
DD
-0.5 – V
DD
V
Input Voltage 2 V
IL2
OSC1 Terminal V
SS
0.5 V
V
OH
-I
OH
=0.205mA, V
DD
=3V 2.0 V
Output Voltage V
OL
I
OL
=1.6mA, V
DD
=3V – 0.5 V
5
Driver
On-resist.(COM) R
COM1
±I
d
=1µA, Vo= V
DD
,V5 – – 20
k
Driver
On-resist.(SEG) R
SEG1
±I
d
=1µA, Vo= V
DD
,V5 – – 30
k
Driver
On-resist.(COM) R
COM2
±I
d
=1µA, Vo= V1,V4 – – 40
k
Driver
On-resist.(SEG) R
SEG2
±I
d
=1µA, Vo= V2,V3 – – 50
k
Input Leakage
Current I
LI
V
IN
=0 to V
DD
-1 1
µA 6
I
DD1
VDD=3V fOSC=Internal Osc.
V5=-2V,during display 80 290
µA
Operating Current I
DD2
VDD=3V fOSC=Internal Osc.
during access,
TCYCE=5us
, V5=-2V 500
µA 7
V
1
2.08 2.21 2.34
V
2
1.28 1.41 1.54
V
3
-0.54 -0.41 -0.28
LCD Driving
Voltage V
4
V
DD
=3V, Ta=25°C, V5=-2V
-1.34 -1.21 -1.08
V
Oscillation
Frequency f
OSC
V
DD
=3V, Ta=25°C 110 145 180 kHz
LCD Driving
Voltage V
LCD
V
DD
=3V, V
5
Terminal
V
DD
-3
V
DD
-6
V
V5 Terminal
Current I5 V
DD
=3V, V5=-2V
50
µA
Note 5.) App l y to the OSC2 Terminals.
Note 6.) Except pull-down resistance current. (All input terminal except OSC1 terminal)
Note 7.) Except Input / Output current but including the current flow on bleeder resistance.
If the input level is medium, current consumption will increase due to the penetration current. Therefore,
the input level must be fixed to “H” or “L”.
NJU6637
Bus timing characteristics
(V
DD
=2.4 – 3.6V,
V
SS
=0V, Ta=25 °C)
Serial Interface Sequence
PARAMETER SYMBOL MIN MAX UNIT CONDITION
Serial clock cycle time t
CYCE
1 µs
“High” level t
SCH
300 ns
Serial clock w idth Low” level t
SCL
700 ns
Serial clock rise and fall Time t
SCr
, t
SCf
20 *1
Chip select pulse width PW
CS
500+tins *2
Chip select set up time t
CSU
200 ns
Chip select hold time t
CH
200 ns
Chip Select rise and fall Time t
CSr
, t
CSf
20 ns
Address set up time t
AS
200 ns
Address hold time t
AH
200 ns
Serial input data set up time t
SISU
200 ns
Serial input data hold time t
SIH
200 – ns
Fig.1
Note*1) t
scr
and t
scf
is declared between VIH and VIL.
Note*2) tins: instruction execution time. refer to (3) Instrctions.
Serial Interfac e timin g
Fig.1
External clock input
PARAMETER SYMBOL MIN MAX UNIT CONDITION
External clo ck oper atio n Frequency f
CP
110 180 KHz
External clo ck Duty Duty 45 55 %
External clock rise Time t
CPr
0.2 µs
External clock fall Time t
CPf
0.2 µs
Fig.2
Fig.2
t
CYCE
SI
SCL
CS
RS
V
IH
V
IL
V
IH
V
IL
V
IL
t
AS
t
AH
t
CSU
V
IH
PW
CS
t
CH
t
SCH
t
SCL
t
SISU
t
SIH
OSC1 0.5V
DD
Tk Ti
T
fcp
Duty=
Tfcp=1/fcp
Tk
Tk+Ti
V
IH
V
IL
NJU6637
The Input Condition when using the Hardware Reset Circuit
PARAMETER SYMBOL CONDITION MIN TYP MAX UNIT
RESET input
”Low” level width t
RSL
f
OSC
=145kHz 1.2 ms
Input timing
Power supply condition when using the internal initialization circuit
PARAMETER SYMBOL CONDITION MIN TYP MAX UNIT
Power supply rise time t
rDD
0.1 5 ms
Power supply OFF time t
OFF
1 ms
0.1ms<t
rDD
<10ms t
OFF
>1ms
Note.) Since the internal initialization circuits will not operate normally unless the above conditions are met, in
such a case initialize by instruction(Refer to initialization by the instruction).
*t
OFF
specifies the power OFF
time in a short period OFF o
r
cyclical ON/OFF
RESET
V
RSL
V
IL
0.2V 0.2V
2.4V 3V
V
DD
t
rDD
t
OFF
NJU6637
LCD DRIVING WAVE FROM
NJU6637 1/24 Duty driving
V5
V4
V3
V2
V1
VDD
-V1
-V2
-V3
-V4
-V5
-V1
-V2
-V3
-V4
-V5
V5
V4
V3
V2
V1
VDD
COM5
COM4
COM3
COM2
COM1
COM15
COM7
COM6
COM13
COM12
COM11
COM10
COM9
COM8
COM14
SEG3
SEG4
SEG2
SEG1
SEG5
COM2
COM1-SEG2
COM1-SEG1
SEG2
SEG1
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
COM1
COM3
VDD
V1
V2
V3
V4
V5
1 2 3 4 1 2 3 4 22 23 24 22 23 24
COM16
• • • • • • • • • • • •
NJU6637
APPLICATION CIRCUI TS
16-character 3-line Display Example
(The terminal description is “Mode A”.)
NJU6637A
BOTTOM VIEW
SEG80
SEG1
COM16
CO
M
9
COM1
COM24
LCD Panel
(
16-character 3-line
)
NJU6637
16-character 3-line Display Example
(The terminal description is “Mode B”.)
NJU6637A
TOP VIEW
COM9
COM16
SEG80
SEG1
COM24
COM1
LCD Panel
(
16-character 3-line
)
NJU6637
MEMO
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.