ANALOG LC2Mos DEVICES 8-Bit DAC with Output Amplifier AD7224 REV. A 1.1 Scope. This specification covers the detail requirements for a monolithic CMOS 8-bit, voltage output, digital-to- analog converter with output amplifier and double-buffered interface logic. No external trims are required to achieve full specified performance for the part. 1.2 Part Number. The complete part numbers per Tables 1 and 2 of this specification are as follows: Device Part Number! -] AD7224T(X)/883B -2 AD7224U(X)/883B NOTE 1See paragraph 1.2.3 for package identifier. 1.2.3 Case Outline. See Appendix 1 of General Specification ADI-M-1000: package outline: (X) Package Description Q Q-18 18-Pin Cerdip E E-20A 20-Contact LCC 1.3 Absolute Maximum Ratings. (T, = + 25C unless otherwise noted) Vpp to AGND .. 0... te ee te ens 0.3V, +17V Vpp t0oDGND .... 1... ee ee ee ees 0.3V, +17V Vss tooAGND . 0... ee ee ee es -7V, Vop Vss toDGND... 0... ee ee ee ee -T7V, Vop Vpp to Vss Be he hw hw we ee ee ee 0.3V, +24V AGND toDGND ... 2... ee -0.3V, +Vpp Digital Input Voltageto DGND .. 1... 0. ee ee ee et ee 0.3V, Vop Vrer tOAGND .. 0... ee ne ~-0.3V, Vop Vout toAGND .. 0. 0. ee ee ek ee Vss> Vop Power Dissipation Upto +75 2. ee ee ee 450m WV Derates above +75... ee ee ee ees 6mW/C Operating Temperature Range ........ Le et 55C to +125C Storage Temperature 2... ee ee es 65C to + 150C Lead Temperature (Soldering 10sec) 2... ee te ees + 300C 1.5 Thermal Characteristics. Thermal Resistance @;- = 35C/W for Q-18 and E-20A 8s, = 120C/W for Q-18 and E-20A DIGITAL-TO-ANALOG CONVERTERS 8-65 DIGITAL-TO-ANALOG CONVERTERS a AD7224 SPECIFICATIONS Table 1. Design Sub [Sub [Sub Limit Group} Group| Group) Test Symbol} Device | Tria-Tmax| 1 2,3 |4 Test Condition! Units Resolution RES -1,2 |8 Bits Relative Accuracy RA -1 1 1 1 Vop= + 14V; Vss= -5V; Vaer= + 10V | + LSB max -2 V2 1 1/2 V2 Total Unadjusted Error Er -1 2 2 2 Vpp= + 14V; Vss= 5V; Varr = +10V | + LSBmax -2 1 2 ! Differential Nonlinearity DNL | -1,2 [1 1 1 Guaranteed Monotonic to 8-Bits + LSB max Full-Scale Error Ag -1 3/2 3/2 3/2 Vpp= + 14V; Vss = 5V; Vase = + 10V | + LSB max -2 1 3/2 1 1 Zero Code Error Azce -1 30 30 30 Vpp = 16.5V, 1k.4V and 14V; Vss = 5V;] +mV max -2 |20 30 [20 [20 |Vaer=Von-4 Full-Scale Temp Coefficient dAs/dT| -1,2 | 20 Von = 14V to 16.5V, Veer = + 10V + ppm/C max Voltage Output Settling Time? ts. -1,2]5 Positive Full-Scale Change ps max 7 Negative Full-Scale Change Voltage Output Slew Rate tse -1,2 | 2.5 V/s min Minimum Load Resistance RLaiw | - 1,2 | 2 Vour = + 10V; Vpn = + 14V kOQ min Reference Voltage Range VreF -1,2 | 2to Vminto (Vpp - 4) V max Reference Input Resistance R, -1,2 | 8 8 8 Vpn= K4V kN min Reference Input Capacitance Cc 1,2 } 100 Occurs When DAC Is Loaded with All Is_ | pF min Digital Input High Voltage Vin -1,2 | 2.4 2.4 2.4 Vpn = 11.4V3 Vrer = Von - 4 Vmin Digital Input Low Voltage Vi. -1,2 | 0.8 0.8 0.8 Von = 11.4V; Veer = Vop-4 V max Digital Input Leakage Current lin -1,2 ] 1 t I Vin = OVor Vion; Von = 11.4V + pA max Digital Input Capacitance CQ -1,2 /8 pF max Chip Select/Load DAC Pulse Width] tp -1,2 | 200 ns min Write/Reset Pulse Width twr -1,2 | 200 ns min Chip Select/Load DAC to Write Setup Time lcs -1,2 | 0 ns min Chip Select/Load DAC to Write HoldTime tcH -1,2 | 0 ns min Data Valid to Write Setup Time tps -1,2 | 100 ns min Data Valid to Write Ho!d Time tpx -1,2 | 10 ns min Power Supply Voltage Range Von -1,2 | 11.4 For Specified Performance +Vmin 16.5 +Vmax | Vs -1,2 | 4.5 For Specified Performance -Vmin 5.5 Vmax Power Supply Current Ipp -1,2] 6 4 6 Output Unloaded: V py = Vir.or Vin mA max Vpp= 16.58V; Vgs= 5-5V; Vane 12.5V Iss -1,2]5 3 5 NOTE: DUAL SUPPLY OPERATION Vop = + 11.4V t0 16.5V; Vcg = - SV + 10%; AGND = DGND = 0V; Vere = + 2V10(Vpp 4V) unless otherwise stated. Vane = + 10V; settling time to + 1/2LSB. 8-66 DIGITAL-TO-ANALOG CONVERTERS REV. A AD7224 Vpp = 15.75V Table 2. Design Sub [Sub | Sub Limit Group] Group | Group Test Symbol | Device | Tain-Tauax| 1 2,3 4 Test Condition! Units Resolution RES -1,2 |8 Bits Total Unadjusted Error Ey -1,2 | 2 2 2 Vpn= +14V + LSB max Differential Nonlinearity DNL |-1,2 | 1 1 1 Vop= + 14V; + LSB max Guaranteed Monotonic to 8-Bits Voltage Output Settling Time? tst. -1,2 |5 Positive Full-Scale Change us max 20 Negative Full-Scale Change Voltage Output Slew Rate tsp -1,2 [2 Vips min Minimum Load Resistance RLain | 1,2 | 2 2 2 Vout = + 10V; Vpp= + 1I5SV kOQ min Reference Input Resistance R, ~1,2 18 Vpn= 14.25V kO min Reference Input Capacitance Cc, -1,2 | 100 Occurs When DAC Is Loaded with All 1's | pF max Digital Input High Voltage Vin -1,2 [2.4 2.4 2.4 Vpp = 14.25V Vmin Digital Input Low Voltage Vin -1,2 | 0.8 0.8 0.8 Vpp= 14.25V Vmax Digital Input Leakage Current lin -4,2 ]1 Vin = OV or Vpp; Vpn = 14.25V +pAmax Digital Input Capacitance Cq -1,2 [8 pF max Chip Select/Load DAC Pulse Width | tp -1,2 | 200 ns min Write/Reset Pulse Width twr -1,2 | 200 ns min Chip SelecULoad DAC to Write Setup Time tes -1,2 70 ns min Chip SelecULoad DAC to Write HoldTime tcn -1,2 ]0 ns min Data Valid to Write Setup Time tps ~1,2 | 100 ns min Data Valid to Write Hold Time ton -1,2 | 10 ns min Power Supply Voltage Range Vop 1,2 | 14.25 For Specified Performance +Vmin 15.75 +Vmax Power Supply Current Ipp -1,2 | 6 Outputs Unloaded; Vyy = Vir or Vin mA max NOTE: SINGLE SUPPLY OPERATION Vpp = + 15V + 5%; Vss = AGND = DGND = OV; Veer = + 10V unless otherwise stated. ?Settling time to + L/2LSB. DIGITAL-TO-ANALOG CONVERTERS 8-67 DIGITAL-TO-ANALOG CONVERTERS A AD7224 3.2.1 Functional Block Diagram and Terminal Assignments. (3) {18) E Package (LCC) 1 3 3 2 @ MsB (6) }_N +N > > 3 > x DATA INPUT DAC eam) ' TrecisTer REGISTER bac 2) 3 2 A 20 19 use (13) 7) out L_ Vaee 4 vs 1g OAC AGND 5 17 Wi cs AD7224 _ ae DGND 6 TOP VIEW 16 cS Wr GS) CONTROL DB? (mse) 7 (Not to Scale} 15 ppo ise) tac Gs) bocie AD7224 RESET (17) oss 8 14 pes O) }_) Ves AGNO DGND 9 10 11 12 13 Py o x 28 2 228 3.2.4 Microcircuit Technology Group. This microcircuit is covered by technology group (80). 4.2.1 Life Test/Burn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). + 15V Vout Vner AGND DGND AD7224 DB? (MSB) DBO (LSB) oB6 081 OBS DB2 OB4 0B3 100k92 NOTE: Vop IS TURNED ON FIRST, THEN Vs5 FOLLOWED BY Vrer. 8-68 DIGITAL-TO-ANALOG CONVERTERS REV. A AD7224 al RESET REV. A Table 3. AD7224 Truth Table a 5 5 a = whe bee lg Function Both Registers are Transparent Both Registers are Latched Both Registers are Latched Input Register Transparent Input Register Latched DAC Register Transparent DAC Register Latched Both Registers Loaded With All Zeros Both Register Latched With All Zeros and Output Remains at Zero FOL L __L_| BothRegisters are Transparent and Output Follows Input Data rm mmm mm me aren momese xR m rom a m1 by H = High State, L = Low State, X = Dont Care -== t, p se} cs tsa] [ton torr] twee] P DAC REGISTER wr o tes 9] ee ~~ ton as s iDAc tos [toe 1s INPUT REGISTER a Figure 1. Input Control Logic DATA DATA IN VALID 4 NOTES 1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% of Voo. t, = t) = 20ns OVER Von RANGE 2. TIMING MEASUREMENT REFERENCE LEVEL iS Ven + Ve = INPUT DATA Figure 2. Write Cycle Timing Diagram DIGITAL-TO-ANALOG CONVERTERS 8-69 DIGITAL-TO-ANALOG CONVERTERS a