AD9430CMOSPCB - Analog Devices

12-Bit, 170/210 MSPS

3.3 V A/D Converter

AD9430

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

SNR = 65 dB @ fIN = 70 MHz @ 210 MSPS

ENOB of 10.6 @ fIN = 70 MHz @ 210 MSPS (–0.5 dBFS)

SFDR = 80 dBc @ fIN = 70 MHz @ 210 MSPS (–0.5 dBFS)

Excellent linearity:

DNL = ±0.3 LSB (typical)

INL = ±0.5 LSB (typical)

2 output data options:

Demultiplexed 3.3 V CMOS outputs each @ 105 MSPS

Interleaved or parallel data output option

LVDS at 210 MSPS

700 MHz full-power analog bandwidth

On-chip reference and track-and-hold

Power dissipation = 1.3 W typical @ 210 MSPS

1.5 V input voltage range

3.3 V supply operation

Output data format option

Data sync input and data clock output provided

Clock duty cycle stabilizer

GENERAL DESCRIPTION

The AD9430 is a 12-bit, monolithic, sampling analog-to-digital

converter (ADC) optimized for high performance, low power,

and ease of use. The product operates up to a 210 MSPS

conversion rate and is optimized for outstanding dynamic

performance in wideband carrier and broadband systems. All

necessary functions, including a track-and-hold (T/H) and

reference, are included on the chip to provide a complete

conversion solution.

The ADC requires a 3.3 V power supply and a differential

ENCODE clock for full performance operation. The digital

outputs are TTL/CMOS or LVDS compatible and support either

twos complement or offset binary format. Separate output

power supply pins support interfacing with 3.3 V or 2.5 V

CMOS logic.

Two output buses support demultiplexed data up to 105 MSPS

rates in CMOS mode. A data sync input is supported for proper

output data port alignment in CMOS mode, and a data clock

output is available for proper output data timing. In LVDS

mode, the chip provides data at the ENCODE clock rate.

Fabricated on an advanced BiCMOS process, the AD9430 is

available in a 100-lead, surface-mount plastic package

(100 e-PAD TQFP) specified over the industrial temperature

range (–40°C to +85°C).

FUNCTIONAL BLOCK DIAGRAM

TRACK-

AND-HOLD

SCALABLE

REFERENCE

ADC

12-BIT

PIPELINE

CORE

LVDS

OUTPUTS

CLOCK

MANAGEMENT

SENSE VREF AGND DRGND DRVDD AVDD

DATA,

OVERRANGE

IN LVDS OR

2-PORT CMOS

DCO–

S5S4S2S1

CLK+

DS+

VIN+

AD9430

12

VIN–

DS–

CLK–

DCO+

SELECT CMOS

OR LVDS

CMOS

OUTPUTS

02607-001

Figure 1.

APPLICATIONS

Wireless and wired broadband communications

Cable reverse path

Communications test equipment

Radar and satellite subsystems

Power amplifier linearization

PRODUCT HIGHLIGHTS

1. High performance.

Maintains 65 dB SNR @ 210 MSPS with a 65 MHz input.

2. Low power.

Consumes only 1.3 W @ 210 MSPS.

3. Ease of use.

LVDS output data and output clock signal allow interface

to current FPGA technology. The on-chip reference and

sample-and-hold provide flexibility in system design. Use

of a single 3.3 V supply simplifies system power supply

design.

4. Out of range (OR) feature.

The OR output bit indicates when the input signal is

beyond the selected input range.

5. Pin compatible with 10-bit AD9411 (LVDS only).

.

AD9430

Rev. D | Page 2 of 44

TABLE OF CONTENTS

DC Specifications ............................................................................. 4

AC Specifications.............................................................................. 6

Digital Specifications........................................................................ 7

Switching Specifications .................................................................. 8

Timing Diagrams.............................................................................. 9

Absolute Maximum Ratings.......................................................... 10

Explanation of Test Levels......................................................... 10

ESD Caution................................................................................ 10

Pin Configurations and Function Descriptions ......................... 11

Equivalent Circuits ......................................................................... 15

Typical Performance Characteristics ........................................... 16

Term in ol og y .................................................................................... 23

Application Notes ........................................................................... 25

Theory of Operation .................................................................. 25

Encode Input............................................................................... 25

Analog Input ............................................................................... 26

DS Inputs (DS+, DS–)................................................................ 26

CMOS Outputs ........................................................................... 26

LVDS Outputs ............................................................................. 27

Voltage Reference ....................................................................... 27

Noise Power Ratio Testing (NPR)............................................ 27

Evaluation Board, CMOS Mode................................................... 28

Power Connector........................................................................ 28

Analog Inputs ............................................................................. 28

Gain.............................................................................................. 28

ENCODE..................................................................................... 28

Voltage Reference ....................................................................... 28

Data Format Select..................................................................... 28

I/P Timing Select........................................................................ 28

Timing Controls ......................................................................... 28

CMOS Data Outputs.................................................................. 29

Crystal Oscillator........................................................................ 29

Optional Amplifier..................................................................... 29

Troubleshooting.......................................................................... 30

Evaluation Board, LVDS Mode .................................................... 36

Power Connector........................................................................ 36

Analog Inputs ............................................................................. 36

Gain.............................................................................................. 36

Clock ............................................................................................ 36

Voltage Reference ....................................................................... 36

Data Format Select..................................................................... 36

Data Outputs............................................................................... 36

Crystal Oscillator........................................................................ 36

Outline Dimensions ....................................................................... 42

Ordering Guide .......................................................................... 42

AD9430

Rev. D | Page 3 of 44

REVISION HISTORY

8/05—Rev. C to Rev. D

Change to IVREF Spec Units ...............................................................4

Changes to Minimum ENOB Specification...................................6

Added Footnote for Pin 33 in LVDS Mode ...................................7

Change to LVDS Output Section ..................................................27

Added New Evaluation Board, CMOS Mode Section................32

Updated Outline Dimensions........................................................42

11/04—Rev. B to Rev. C

Changes to Specifications ................................................................4

Changes to Figure 60 .................................................................... 31

Changes to LVDS PCB BOM ....................................................... 35

Changes to Figure 68 (Evaluation Board—LVDS Mode) ......... 36

Updated Outline Dimensions ...................................................... 40

7/03—Rev. A to Rev. B

Changed order of Figure 1 and Figure 2 ...................................... 5

Updated TPC 13 .............................................................................14

Changes to LVDS OUTPUTS section..........................................20

Add New AD9430 EVALUATION BOARD, LVDS MODE

Section ......................................................................................... 27

Updated OUTLINE DIMENSIONS ........................................... 32

3/03—Rev. 0 to Rev. A

Upgraded for AD9430-210 .............................................. Universal

Changes to FEATURES ................................................................. 1

Changes to PRODUCT HIGHLIGHTS ...................................... 1

Changes to SPECIFICATIONS ..................................................... 2

Changes to Figure 2 ........................................................................ 5

Changes to ORDERING GUIDE .................................................. 6

Change to PIN FUNCTION DESCRIPTIONS .......................... 7

Edits to Output Propagation Delay section. .............................. 10

Added TPCs 5–8, 10–12, 14, 16, 18, 20, 22, 27, 31–32, 34 ...... 12

Changes to TPCs............................................. 17, 19, 26, 35–36, 38

Added text to ENCODE INPUT section ................................... 18

Added DS INPUTS section ..........................................................19

Change to Table I ..........................................................................19

Changes to LVDS Outputs section.............................................. 20

Changes to Voltage Reference section .........................................20

Replaced Figure 12......................................................................... 20

Change to Troubleshooting section .............................................22

Updated OUTLINE DIMENSIONS.............................................27

5/02—Revision 0: Initial Version

AD9430

Rev. D | Page 4 of 44

DC SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, LVDS output mode,

unless otherwise noted.

Table 1.

AD9430-170 AD9430-210

Parameter

Temp

Test

Level

Min

Typ

Max

Min

Typ

Max

Unit

RESOLUTION 12 Bits

ACCURACY

No Missing Codes Full VI Guaranteed Guaranteed

Offset Error 25°C I –3 +3 –3 +3 mV

Gain Error 25°C I –5 +5 –5 +5 % FS

Differential Nonlinearity (DNL) 25°C I –1 ± 0.3 +1 –1 ± 0.3 +1 LSB

Full VI –1 ± 0.3 +1.5 –1 ± 0.3 +1.5 LSB

Integral Nonlinearity (INL) 25°C I –1.5 ± 0.5 +1.5 –1.75 ± 0.3 +1.75 LSB

Full VI –2.25 ± 0.5 +2.25 –2.5 ± 0.3 +2.5 LSB

TEMPERATURE DRIFT

Offset Error Full V 58 58 μV/°C

Gain Error Full V 0.02 0.02 %/°C

Reference Out (VREF) Full V +0.12/–0.24 +0.12/–0.24 mV/°C

REFERENCE

Reference Out (VREF) 25°C I 1.15 1.235 1.3 1.15 1.235 1.3 V

Output Current125°C IV 3.0 3.0 mA

IVREF Input Current2 25°C I 20 20 μA

ISENSE Input Current225°C I 1.6 5.0 1.6 5.0 mA

ANALOG INPUTS (VIN+, VIN–)3

Differential Input Voltage Range

(S5 = GND)

Full V 1.536 1.536 V

Differential Input Voltage Range

(S5 = AVDD)

Full V 0.766 0.766 V

Input Common-Mode Voltage Full VI 2.65 2.8 2.9 2.65 2.8 2.9 V

Input Resistance Full VI 2.2 3 3.8 2.2 3 3.8 kΩ

Input Capacitance 25°C V 5 5 pF

POWER SUPPLY (LVDS Mode)

AVDD Full IV 3.1 3.3 3.6 3.2 3.3 3.6 V

DRVDD Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V

Supply Currents

IANALOG (AVDD = 3.3 V)4Full VI 335 372 390 450 mA

IDIGITAL (DRVDD = 3.3 V)4 Full VI 55 62 55 62 mA

Power Dissipation4 Full VI 1.29 1.43 1.5 1.7 W

Power Supply Rejection 25°C V –7.5 –7.5 mV/V

AD9430

Rev. D | Page 5 of 44

AD9430-170 AD9430-210

Parameter

Temp

Test

Level

Min

Typ

Max

Min

Typ

Max

Unit

POWER SUPPLY (CMOS Mode)

AVDD Full IV 3.1 3.3 3.6 3.2 3.3 3.6 V

DRVDD Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V

Supply Currents

IAVDD (AVDD = 3.3 V)5Full IV 335 372 390 450 mA

IDRVDD (DRVDD = 3.3 V)5 Full IV 24 30 30 30 mA

Power Dissipation5Full IV 1.1 1.3 W

Power Supply Rejection 25°C V –7.5 –7.5 mV/V

1 Internal reference mode; SENSE = Floats.

2 External reference mode; SENSE = DRVDD, VREF driven by external 1.23 V reference.

3 S5 (Pin 1) = GND. See the Analog Input section. S5 = GND in all dc and ac tests, unless otherwise noted.

4 IAVDD and IDRVDD are measured with an analog input of 10.3 MHz, –0.5 dBFS, sine wave, rated ENCODE rate, and in LVDS output mode. See Typical Performance

Characteristics and Application Notes sections for IDRVDD. Power consumption is measured with a dc input at rated ENCODE rate in LVDS output mode.

5 IAVDD and IDRVDD are measured with an analog input of 10.3 MHz, –0.5 dBFS, sine wave, rated ENCODE rate, and in CMOS output mode. See Typical Performance

Characteristics and Application Notes sections for IDRVDD. Power consumption is measured with a dc input at rated ENCODE rate in CMOS output mode.

AD9430

Rev. D | Page 6 of 44

AC SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, LVDS output mode,

unless otherwise noted.1

Table 2.

AD9430-170 AD9430-210

Parameter Temp Test Level Min Typ Max Min Typ Max Unit

SNR

Analog Input @ –0.5 dBFS 10 MHz 25°C I 63.5 65 62.5 64.5 dB

70 MHz 25°C I 63 65 62.5 64.5 dB

100 MHz 25°C V 65 64.5 dB

240 MHz 25°C V 61 61 dB

SINAD

Analog Input @ –0.5 dBFS 10 MHz 25°C I 63.5 65 62.5 64.5 dB

70 MHz 25°C I 63 65 62.5 64.5 dB

100 MHz 25°C V 65 64.5 dB

240 MHz 25°C V 60 60 dB

EFFECTIVE NUMBER OF BITS (ENOB)

10 MHz 25°C I 10.3 10.6 10.2 10.5 Bits

70 MHz 25°C I 10.3 10.6 10.2 10.5 Bits

100 MHz 25°C V 10.6 10.5 Bits

240 MHz 25°C V 9.8 9.8 Bits

WORST HARMONIC (2nd or 3rd)

Analog Input @ –0.5 dBFS, 10 MHz 10 MHz 25°C I –85 –75 –84 –74 dBc

70 MHz 25°C I –85 –75 –84 –74 dBc

100 MHz 25°C V –77 –77 dBc

240 MHz 25°C V –63 –63 dBc

WORST HARMONIC (4th or Higher)

Analog Input @ –0.5 dBFS, 10 MHz 10 MHz 25°C I –87 –78 –87 –77 dBc

70 MHz 25°C I –87 –78 –87 –77 dBc

100 MHz 25°C V –77 –77 dBc

240 MHz 25°C V –63 –63 dBc

TWO-TONE IMD2

F1, F2 @ −7 dBFS 25°C V –75 –75 dBc

ANALOG INPUT BANDWIDTH 25°C V 700 700 MHz

1 All ac specifications tested by differentially driving CLK+ and CLK−.

2 F1 = 28.3 MHz, F2 = 29.3 MHz.

AD9430

Rev. D | Page 7 of 44

DIGITAL SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.

Table 3.

Test AD9430-170 AD9430-210

Parameter Temp Level Min Typ Max Min Typ Max Unit

ENCODE AND DS INPUTS

(CLK+, CLK–, DS+, DS–)1

Differential Input Voltage2 Full IV 0.2 0.2 V

Common-Mode Voltage3 Full VI 1.375 1.5 1.575 1.375 1.5 1.575 V

Input Resistance Full VI 3.2 5.5 6.5 3.2 5.5 6.5 kΩ

Input Capacitance 25°C V 4 4 pF

LOGIC INPUTS (S1, S2, S4, S5)

Logic 1 Voltage Full IV 2.0 2.0 V

Logic 0 Voltage Full IV 0.8 0.8 V

Logic 1 Input Current Full VI 190 190 μA

Logic 0 Input Current Full VI 10 10 μA

Input Resistance 25°C V 30 30 kΩ

Input Capacitance 25°C V 4 4 pF

LOGIC OUTPUTS (CMOS Mode)

Logic 1 Voltage4 Full IV DRVDD DRVDD V

–0.05 –0.05

Logic 0 Voltage4 Full IV 0.05 0.05 V

LOGIC OUTPUTS (LVDS Mode)4, 5

VOD Differential Output Voltage Full VI 247 454 247 454 mV

VOS Output Offset Voltage Full VI 1.125 1.375 1.125 1.375 V

Output Coding Twos complement or binary Twos complement or binary

1 ENCODE (Clock) and DS inputs identical on the chip. See the Equivalent Circuits section.

2 All ac specifications tested by driving CLK+ and CLK– differentially, |(CLK+) – (CLK–)| > 200 mV.

3 ENCODE (Clock) inputs’ common-mode can be externally set, such that 0.9 V < (CLK+ or CLK−) < 2.6 V.

4 Digital output logic levels: DRVDD = 3.3 V, CLOAD = 5 pF.

5 LVDS RTERM = 100 Ω, LVDS output current set resistor (RSET) = 3.74 kΩ (1% tolerance).

AD9430

Rev. D | Page 8 of 44

SWITCHING SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.

Table 4.

Test AD9430-170 AD9430-210

Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Unit

Maximum Conversion Rate1 Full VI 170

210 MSPS

Minimum Conversion Rate1Full V 40 40 MSPS

CLK+ Pulse Width High (tEH)1 Full IV 2 12.5 2 12.5 ns

CLK+ Pulse Width Low (tEL)1 Full IV 2 12.5 2 12.5 ns

DS Input Setup Time (tSDS)2 Full IV –0.5 –0.5 ns

DS Input Hold Time (tHDS)2 Full IV 1.75 1.75 ns

OUTPUT (CMOS Mode)

Valid Time (tV) Full IV 2 2 ns

Propagation Delay (tPD) Full IV 3.8 5 3.8 5 ns

Rise Time (tR) (20% to 80%) 25°C V 1 1 ns

Fall Time (tF) (20% to 80%) 25°C V 1 1 ns

DCO Propagation Delay (tCPD) Full IV 3.8 5 3.8 5 ns

Data to DCO Skew (tPD to tCPD) Full IV –0.5 0 +0.5 –0.5 0 +0.5 ns

Interleaved Mode (A, B Latency) Full IV 14, 14 14, 14 Cycles

Parallel Mode (A, B Latency) Full IV 15, 14 15, 14 Cycles

OUTPUT (LVDS Mode)

Valid Time (tV) Full VI 2.0 2.0 ns

Propagation Delay (tPD) Full VI 3.2 4.3 3.2 4.3 ns

Rise Time (tR) (20% to 80%) 25°C V 0.5 0.5 ns

Fall Time (tF) (20% to 80%) 25°C V 0.5 0.5 ns

DCO Propagation Delay (tCPD) Full VI 1.8 2.7 3.8 1.8 2.7 3.8 ns

Data to DCO Skew (tPD – tCPD) Full IV 0.2 0.5 0.8 0.2 0.5 0.8 ns

Latency Full IV 14 14 Cycles

APERTURE DELAY (tA) 25°C V 1.2 1.2 ns

APERTURE UNCERTAINTY (Jitter, tJ) 25°C V 0.25 0.25 ps rms

OUT OF RANGE RECOVERY TIME (CMOS and LVDS) 25°C V 1 1 Cycles

1 All ac specifications tested by differentially driving CLK+ and CLK−.

2 DS inputs used in CMOS mode only.

AD9430

Rev. D | Page 9 of 44

TIMING DIAGRAMS

PORT A

DA11–DA0

PORT B

DB11–DB0

PARALLEL DATA OUT

PORT A

DA11–DA0

PORT B

DB11–DB0

CLK+

CLK–

DS+

DS–

INTERLEAVED DATA OUT

STATIC

INVALID

t

SDS

14 CYCLES

t

PD

t

V

N N+2

N+3

N+1

N N+2

N+1 N+3

t

CPD

t

HDS

DCO+

DCO–

02607-002

Figure 2. CMOS Timing Diagram

N–14 N–13 NN+1

A

IN

CLK+

CLK–

DATA OUT

DCO+

DCO–

N

N+1

N

–

1

tEH

tEL

1/f

S

tPD

14 CYCLES

tCPD

02607-003

Figure 3. LVDS Timing Diagram

AD9430

Rev. D | Page 10 of 44

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

AVDD, DRVDD 4 V

Analog Inputs –0.5 V to AVDD + 0.5 V

Digital Inputs –0.5 V to DRVDD + 0.5 V

REFIN Inputs –0.5 V to AVDD + 0.5 V

Digital Output Current 20 mA

Operating Temperature –55°C to +125°C

Storage Temperature –65°C to +150°C

Maximum Junction Temperature 150°C

Maximum Case Temperature 150°C

θJA125°C/W, 32°C/W

1 Typical θJA = 32°C/W (heat slug not soldered); typical θJA = 25°C/W (heat slug

soldered) for multilayer board in still air with solid ground plane.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational section

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

EXPLANATION OF TEST LEVELS

Table 6.

Level Description

I 100% production tested.

II 100% production tested at 25°C and sample tested at

specified temperatures.

III Sample tested only.

IV Parameter is guaranteed by design and

characterization testing.

V Parameter is a typical value only.

VI 100% production tested at 25°C; guaranteed by

design and characterization testing for industrial

temperature range; 100% production tested at

temperature extremes for military devices.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

AD9430

Rev. D | Page 11 of 44

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

26

27

28

29

30

55

54

53

52

51

CMO S P INO UT

TOP VIEW

(Not t o S cal e)

AD9430

AGND

AVDD

AGND

5

4

3

2

7

6

9

8

1

11

10

16

15

14

13

18

17

20

19

22

21

12

24

23

25

32

33

34

35

36

38

39

40

41

42

43

44

45

46

47

48

49

50

31

37

AGND

DS+

DS–

AVDD

AGND

CLK+

CLK–

AGND

AVDD

AGND

DNC

DB0

DB1

DB2

DRVDD

DRGND

DB3

DB4

80 DA9

79 DA8

78 DA7

77 DA6

76 DA5

75 DRVDD

74 DRGND

73 DA4

72 DA3

71 DA2

70 DA1

69 DA0

68 DNC

67 DRGND

66 DNC

65 DNC

64 DCO+

63 DCO–

62 DRVDD

61 DRGND

60 OR_B

59 DB11

58 DB10

57 DB9

56 DB8

DB7

DRVDD

DRGND

DB6

DB5

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

AGND

AVDD

AGND

AVDD

AGND

AVDD

AGND

OR_A

DA11

DRVDD

DRGND

DA10

S5

DNC

S4

AGND

S2

S1

DNC

AVDD

AGND

SENSE

VREF

AGND

AVDD

AGND

AVDD

AGND

VIN+

VIN–

AGND

AVDD

AGND

02607-004

Figure 4. CMOS Dual-Mode Pin Configuration

Table 7. CMOS Mode Pin Function Descriptions

Pin Number Mnemonic Description

1 S5 Full-Scale Adjust Pin. AVDD sets fS = 0.768 V p-p differential,

GND sets fS = 1.536 V p-p differential.

2, 7, 42, 43, 65, 66, 68 DNC Do Not Connect.

3 S4 Interleaved, Parallel Select Pin. High = interleaved.

4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86,

87, 91, 92, 93, 96, 97, 100

AGND1 Analog Ground.

5 S2 Output Mode Select. Low = dual-port CMOS, high = LVDS.

6 S1 Data Format Select. Low = binary, high = twos complement for

both CMOS and LVDS modes.

8, 14, 15, 18, 19, 24, 27, 28, 29, 34, 39, 40, 88, 89, 90, 94,

95, 98, 99

AVDD 3.3 V Analog Supply.

10 SENSE Reference Mode Select Pin. Float for internal reference operation.

11 VREF 1.235 V Reference I/O—Function Dependent on SENSE.

21 VIN+ Analog Input—True.

22 VIN– Analog Input—Complement.

32 DS+ Data Sync (Input)—True. Tie low if not used.

33 DS–2 Data Sync (Input)—Complement. Tie high if not used.

36 CLK+ Clock Input—True.

37 CLK– Clock Input—Complement.

44 DB0 B Port Output Data Bit (LSB).

45 DB1 B Port Output Data Bit.

AD9430

Rev. D | Page 12 of 44

Pin Number Mnemonic Description

46 DB2 B Port Output Data Bit.

47, 54, 62, 75, 83 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).

48, 53, 61, 67, 74, 82 DRGND1 Digital Output Ground.

49 DB3 B Port Output Data Bit.

50 DB4 B Port Output Data Bit.

51 DB5 B Port Output Data Bit.

52 DB6 B Port Output Data Bit.

55 DB7 B Port Output Data Bit.

56 DB8 B Port Output Data Bit.

57 DB9 B Port Output Data Bit.

58 DB10 B Port Output Data Bit.

59 DB11 B Port Output Data Bit (MSB).

60 OR_B B Port Overrange.

63 DCO– Data Clock Output—Complement.

64 DCO+ Data Clock Output—True.

69 DA0 A Port Output Data Bit (LSB).

70 DA1 A Port Output Data Bit.

71 DA2 A Port Output Data Bit.

72 DA3 A Port Output Data Bit.

73 DA4 A Port Output Data Bit.

76 DA5 A Port Output Data Bit.

77 DA6 A Port Output Data Bit.

78 DA7 A Port Output Data Bit.

79 DA8 A Port Output Data Bit.

80 DA9 A Port Output Data Bit.

81 DA10 A Port Output Data Bit.

84 DA11 A Port Output Data Bit (MSB).

85 OR_A A Port Overrange.

1 AGND and DRGND should be tied together to a common ground plane.

2 DS Complement (DS−); can be tied to AVDD (as recommended) or left floating with no ill effects.

AD9430

Rev. D | Page 13 of 44

26

27

28

29

30

55

54

53

52

51

LVDS PINOUT

TOP VIEW

(Not to Scale)

AD9430

AGND

AVDD

AGND

5

4

3

2

7

6

9

8

1

11

10

16

15

14

13

18

17

20

19

22

21

12

24

23

25

32

33

34

35

36

38

39

40

41

42

43

44

45

46

47

48

49

50

31

37

AGND

GND

AVDD

AGND

CLK+

CLK–

AGND

AVDD

AGND

DNC

DRVDD

DRGND

D0–

D0+

80 D11–

79 D10+

78 D10–

77 D9+

76 D9–

75 DRVDD

74 DRGND

73 D8+

72 D8–

71 D7+

70 D7–

69 D6+

68 D6–

67 DRGND

66 D5+

65 D5–

64 DCO+

63 DCO–

62 DRVDD

61 DRGND

60 D4+

59 D4–

58 D3+

57 D3–

56 D2+

D2–

DRVDD

DRGND

D1+

D1–

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

AGND

AVDD

AGND

AVDD

AGND

AVDD

AGND

OR+

OR–

DRVDD

DRGND

D11+

S5

DNC

S4

AGND

S2

S1

LVDSBIAS

AVDD

AGND

SENSE

VREF

AGND

AVDD

AGND

AVDD

AGND

VIN+

VIN–

AGND

AVDD

AGND

02607-005

Figure 5. LVDS Mode Pin Configuration

Table 8. LVDS Mode Pin Function Descriptions

Pin Number Mnemonic Description

1 S5 Full-Scale Adjust Pin. AVDD sets fS = 0.768 V p-p differential,

GND sets fS = 1.536 V p-p differential.

2, 42 to 46 DNC Do Not Connect.

3 S4 Control Pin for CMOS Mode. Tie low when operating in LVDS

mode.

4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86, 87, 91,

92, 93, 96, 97, 100

AGND1 Analog Ground.

5 S2 Output Mode Select. GND = dual-port CMOS; AVDD = LVDS.

6 S1

Data Format Select. GND = binary, AVDD = twos complement.

7 LVDSBIAS Set Pin for LVDS Output Current. Place 3.74 kW resistor

terminated to ground.

8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34, 39, 40, 88, 89, 90, 94, 95,

AVDD2 3.3 V Analog Supply.

98, 99

10 SENSE Reference Mode Select Pin. Float for internal reference

operation.

11 VREF 1.235 V Reference I/O—Function Dependent on SENSE.

21 VIN+ Analog Input—True.

22 VIN– Analog Input—Complement.

32 GND Data Sync (Input)—Not Used in LVDS Mode. Tie to GND.

36 CLK+ Clock Input—True (LVPECL Levels).

37 CLK– Clock Input—Complement (LVPECL Levels).

AD9430

Rev. D | Page 14 of 44

Pin Number Mnemonic Description

47, 54, 62, 75, 83 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).

48, 53, 61, 67, 74, 82 DRGND1 Digital Output Ground.

49 D0– D0 Complement Output Bit (LSB).

50 D0+ D0 True Output Bit (LSB).

51 D1– D1 Complement Output Bit.

52 D1+ D1 True Output Bit.

55 D2– D2 Complement Output Bit.

56 D2+ D2 True Output Bit.

57 D3– D3 Complement Output Bit.

58 D3+ D3 True Output Bit.

59 D4– D4 Complement Output Bit.

60 D4+ D4 True Output Bit.

63 DCO– Data Clock Output—Complement.

64 DCO+ Data Clock Output—True.

65 D5– D5 Complement Output Bit.

66 D5+ D5 True Output Bit.

68 D6– D6 Complement Output Bit.

69 D6+ D6 True Output Bit.

70 D7– D7 Complement Output Bit.

71 D7+ D7 True Output Bit.

72 D8– D8 Complement Output Bit.

73 D8+ D8 True Output Bit.

76 D9– D9 Complement Output Bit.

77 D9+ D9 True Output Bit.

78 D10– D10 Complement Output Bit.

79 D10+ D10 True Output Bit.

80 D11– D11 Complement Output Bit.

81 D11+ D11 True Output Bit.

84 OR– Overrange Complement Output Bit.

85 OR+ Overrange True Output Bit.

1 AGND and DRGND should be tied together to a common ground plane.

2 Pin 33 can be tied to AVDD (as recommended) or left floating with no ill effects

AD9430

Rev. D | Page 15 of 44

EQUIVALENT CIRCUITS

CLK+

OR

DS+

12kΩ

10kΩ

150Ω150Ω

12kΩ

10kΩ

AVDD

CLK–

OR

DS–

02607-080

Figure 6. ENCODE and DS Input

VIN+

3.5k

Ω

20k

Ω

3.5k

Ω

20k

Ω

AVDD

VIN–

02607-007

Figure 7. Analog Inputs

S1, S2,

S4, S5

VDD

30k

Ω

02607-008

Figure 8. S1 to S5 Inputs

A1

VREF

1k

Ω

SENSE

200

Ω

0.1

μ

F

DISABLE

A1 VDD

KFULL

SCALE

S5 = 0 —> K = 1.24

S5 = 1 —> K = 0.62

–+

1V

02607-009

Figure 9. VREF, SENSE I/O

DX

DR

V

DD

02607-010

Figure 10. Data Outputs (CMOS Mode)

DRVDD

DX– DX+

V

02607-011

Figure 11. Data Outputs (LVDS Mode)

AD9430

Rev. D | Page 16 of 44

85

TYPICAL PERFORMANCE CHARACTERISTICS

Charts at 170 MSPS, 210 MSPS for –170, –210 grades, respectively. AVDD, DRVDD = 3.3 V, T = 25°C, AIN differential drive, full

scale = 1.536 V, internal reference unless otherwise noted.

MHz

04010 20 30 50 60 70 80

dB

0

–100

–10

–20

–80

–30

–40

–50

–60

–70

–90

SNR = 65.2dB

SINAD = 65.1dB

H2 = –88.8dBc

H3 = –88.1dBc

SFDR = 87dBc

02607-012

Figure 12. FFT: fs = 170 MSPS, AIN = 10.3 MHz @ −0.5 dBFS, LVDS Mode

MHz

04010 20 30 50 60 70 80

dB

0

–100

–10

–20

–80

–30

–40

–50

–60

–70

–90

85

SNR = 65.1dB

SINAD = 64.9dB

FUND = –0.50dBFS

H2 = –88.6dBc

H3 = –94.6dBc

SFDR = 85.9dBc

02607-013

Figure 13. FFT: fs = 170 MSPS, AIN = 65 MHz @ –0.5 dBFS, LVDS Mode

MHz

04010 20 30 50 60 70 80

dB

0

–100

–10

–20

–80

–30

–40

–50

–60

–70

–90

85

SNR = 64.93dB

SINAD = 64.85dB

FUND = –0.44dBFS

H2 = –92.1dBc

H3 = –90.1dBc

SFDR = 75.6dBc

02607-015

Figure 14. FFT: fs = 170 MSPS, AIN = 65 MHz @ –0.5 dBFS, CMOS Mode

MHz

04010 20 30 50 60 70 80

dB

0

–100

–10

–20

–80

–30

–40

–50

–60

–70

–90

85

SNR = 62.99dBFS

SINAD = 61.45dBFS

H2 = –66.8dBc

H3 = –82.5dBc

SFDR = 66.1dBc

02607-015

Figure 15. FFT: fs = 170 MSPS, AIN = 10.3 MHz @ –0.5 dBFS,

Single-Ended Input, Full Scale = 0.76 V, LVDS Mode

dB

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100 0 153045607590105

SNR = 63.6dB

SINAD = 62.9dB

H2 = –82.5dBc

H3 = –78.6dBc

SFDR = 77.7dBc

MHz

02607-016

Figure 16. FFT: fs = 210 MSPS, AIN = 10.3 MHZ @ –0.5 dBFS, LVDS Mode

dB

0

–20

–10

–30

–40

–60

–70

–50

–80

–90

–100 0 15 30 45 60 75 90 105

SNR = 63.1dB

SINAD = 62.8dB

H2 = –81.1dBc

H3 = –76dBc

SFDR = –76dBc

MHz

02607-017

Figure 17. FFT: fs = 210 MSPS, AIN = 65 MHz @ –0.5 dBFS, CMOS Mode

AD9430

Rev. D | Page 17 of 44

dB

0

–10

–20

–30

–40

–60

–70

–80

–90

–50

–100 0 15 30 45 60 75 90 105

MHz

SNR = 63.5dB

SINAD = 62.6dB

H2 = –79dBc

H3 = –76.1dBc

SFDR = 75.2dBc

02607-018

Figure 18. FFT: fs = 210 MSPS, AIN = 65 MHz @ –0.5 dBFS, LVDS Mode

A

IN

(MHz)

dB

85

80

75

70

65

60

55

50

45

40 0 100 150 250 35050 200 300 400

SFDR

SNR

SINAD

FULL SCALE = 1.5

02607-019

Figure 19. SNR, SINAD, and SFDR vs. AIN Frequency, fS = 210 MSPS,

AIN @ –0.5 dBFS, LVDS Mode

A

IN

(MHz)

0 200 40050 100 150 250 300 350

dB

100

40

90

50

80

70

60

SECOND

THIRD

SFDR

02607-020

Figure 20. Harmonic Distortion (2nd and 3rd)

and SFDR vs. AIN Frequency

0 153045607590105

dB

0

–60

–90

–40

–20

–70

–30

–10

–50

MHz

–80

–100

SNR = 63.3dB

SINAD = 63.1dB

H2 = –80.38dBc

H3 = –81.8dBc

SFDR = 80.8dBc

02607-021

Figure 21. FFT: fs = 213 MSP, AIN = 100 MHz @ –0.5 dBFS, LVDS Mode

A

IN

(MHz)

dB

85

80

75

70

65

60

55

50

45

40 0 100 150 250 35050 200 300 400

SINAD

SNR

FULL SCALE = 0.75

02607-022

Figure 22. SNR and SINAD vs. AIN Frequency, fs = 210 MSPS,

AIN @ –0.5 dBFS, LVDS Mode, Full Scale = 0.76 V

A

IN

(MHz)

0 200 40050 100 150 250 300 350

dB

100

40

90

50

80

70

60

SECOND

THIRD

SFDR

02607-023

Figure 23. Harmonic Distortion (2nd and 3rd) and

SFDR vs. AIN Frequency, fs = 170 MSPS, CMOS Mode

AD9430

Rev. D | Page 18 of 44

AIN (MHz)

dB

70

66

68

60

62

64

58

56

54

52

500 100 15050 200 250 300 350 400

–170 SINAD

–210 SINAD

–210 SNR

–170 SNR

02607-024

Figure 24. SNR and SINAD vs. AIN Frequency, fs = 170 MSPS/210 MSPS,

AIN @ –0.5 dBFS, LVDS Mode

A

IN

(MHz)

dB

85

80

75

70

65

60

55

50

45

40 0 100 150 250 35050 200 300 400

SINAD

SNR

SFDR

02607-025

Figure 25. SNR and SINAD, SFDR vs. AIN Frequency,

fs = 210 MSPS, AIN @ –0.5 dBFS, CMOS Mode

MHz

04010 20 30 50 60 70 80

dB

0

–100

–10

–20

–80

–30

–40

–50

–60

–70

–90

85

SFDR = 75dBc

02607-026

Figure 26. Two-Tone Intermodulation Distortion

(28.3 MHz and 29.3 MHz, LVDS Mode, fs = 170 MSPS)

dB

0

–30

–60

–90

–120 0 102030405060 809010070

MHz

SFDR = 63dBc

02607-027

Figure 27. Two-Tone Intermodulation Distortion (59 MHz and 60 MHz),

LVDS Mode, fs = 210 MSPS

MHz

0 25050 100 150 200

dB

95

50

90

55

80

75

65

85

70

60 SINAD

SFDR

02607-028

Figure 28. SINAD and SFDR vs. Clock Rate

(AIN = 10.3 MHz @ –0.5 dBFS, LVDS Mode), –170 Grade

MHz

dB

85

80

75

70

65

60

55

50

45

40 0 100 150 25050 200

SINAD

SNR

SFDR

02607-029

Figure 29. SNR and SINAD, SFDR vs. Clock Rate

(AIN = 10.3 MHz, @ –0.5 dBFS), LVDS Mode, –210 Grade

AD9430

Rev. D | Page 19 of 44

ANALOG SUPPLY

CURRENT CMOS

MODE

ANALOG SUPPLY

CURRENT LVDS

MODE

OUTPUT SUPPLY

CURRENT LVDS

MODE

OUTPUT SUPPLY

CURRENT CMOS

MODE

ENCODE (MSPS)

100 220140 160 180 200120

I

AVDD

(ANALOG SUPPLY CURRENT) (mA)

400

0

350

50

250

150

300

200

100

I

DRVDD

(OUTPUT SUPPLY CURRENT) (mA)

80

60

40

20

0

02607-030

Figure 30. IAVDD and IDRVDD vs. Clock Rate (AIN = 10.3 MHz @ –0.5 dBFS)

170 MSPS Grade, CLOAD = 5 pF

ENCODE (MSPS)

I

AVDD

(ANALOG SUPPLY CURRENT) (mA)

I

DRVDD

(OUTPUT SUPPLY CURRENT) (mA)

450

400

350

300

250

200

150

100

50

0

90

80

70

60

50

40

30

20

10

0

100 140 160 200 220 240

120 180

ANALOG SUPPLY

CURRENT LVDS MODE

OUTPUT SUPPLY

CURRENT LVDS MODE

OUTPUT SUPPLY

CURRENT CMOS MODE

ANALOG SUPPLY

CURRENT CMOS MODE

02607-031

Figure 31. IAVDD and IDRVDD vs. Clock Rate

(AIN = 10.3 MHz @ –0.5 dBFS), 210 MSPS Grade, CLOAD = 5 pF

SINAD

SNR

SFDR

ENCODE POSITIVE DUTY CYCLE (%)

10 60 9020 40 50 70 8030

dB

85

50

80

75

70

65

60

55

02607-032

Figure 32. SINAD and SFDR vs. Clock Pulse Width High

(AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS, LVDS)

ENCODE POSITIVE DUTY CYCLE (%)

dB

80

75

70

65

60

55

5020 40 50 7030 60 80

SINAD

SNR

SFDR

02607-033

Figure 33. SNR, SINAD, and SFDR vs. ENCODE Pulse Width High,

(AIN = 10.3 MHz @ –0.5 dBFS, 210 MSPS, LVDS)

I

LOAD

(mA)

081472

V

REFOUT

(V)

1.4

0

1.2

1.0

0.8

0.6

0.4

0.2

R

O

= 13

Ω

TYP

02607-034

536

Figure 34. VREFOUT vs. ILOAD

TEMPERATURE (°C)

–50 10 95–30 –10 30 50 70 90

GAIN ERROR (%)

–2.0

1.5

–1.0

1.0

0.5

0

–0.5

–1.5

% GAIN ERROR

USING EXT REF

2.0

02607-035

Figure 35. Full-Scale Gain Error vs. Temperature

(AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS/210 MSPS, LVDS)

AD9430

Rev. D | Page 20 of 44

AVDD (V)

2.5 3.12.7 2.9 3.3 3.5 3.7 3.9

V

REF

(V)

1.250

1.225

1.230

1.245

1.240

1.235

02607-036

Figure 36. VREF Output Voltage vs. AVDD

TEMPERATURE (°C)

–50 10–30 –10 30 50 70 90

dB

95

60

90

70

85

80

75

65

THIRD

SECOND

SFDR

SNR

SINAD

02607-037

Figure 37. SNR, SINAD, and SFDR vs. Temperature

(AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS)

TEMPERATURE (°C)

dB

65

64

63

62

61

60

59

58

57

56

55

–45 –5 15 55–25 35 75

AVDD = 3.6

AVDD = 3.3

AVDD = 3.135

AVDD = 3.0

02607-038

Figure 38. SINAD vs. Temperature, AVDD

(AIN = 70 MHz @ –0.5 dB, 210 MSPS, LVDS Mode)

CODE

0 4000500 1500 2500 30001000 2000 3500

LSB

1.00

–1.00

0.75

–0.75

0.25

–0.25

0.50

0

–0.50

02607-039

Figure 39. Typical INL Plot (AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS, LVDS)

CODE

0 4000500 1500 2500 30001000 2000 3500

LSB

1.00

–1.00

0.75

–0.75

0.25

–0.25

0.50

0

–0.50

02607-040

Figure 40. Typical DNL Plot (AIN = 10.3 MHz @ –0.5 dBFS)

ANALOG INPUT LEVEL (dBFS)

–100 0–70 –50 –30 –20–60 –40 –10–80–90

dB

100

0

70

10

50

30

60

40

20

80

90 SFDR –dBFS

SFDR –dBc

80dB

REFERENCE LINE

02607-041

Figure 41. SFDR vs. AIN Input Level ,

AIN @ 10.3 MHz, 170 MSPS, LVDS Mode

AD9430

Rev. D | Page 21 of 44

dB

90

80

70

60

50

40

30

20

10

0

–90 –70 –60 –40 –20–80 –50 –30 –10 0

SFDR dBc

LVDS MODE

FULL SCALE = 1.5

SFDR dBc

CMOS MODE

FULL SCALE = 1.5

80dB REFERENCE LINE

02607-042

Figure 42. SFDR vs. AIN Input Level, AIN @ 10.3 MHz, 210 MSPS,

LVDS/CMOS Modes

dB

90

80

70

60

50

40

30

20

10

0

–90 –70 –60 –40 –20–80 –50 –30 –10 0

SFDR dBc

LVDS MODE

FULL SCALE = 1.5

SFDR dBc

LVDS MODE

FULL SCALE = 0.75

80dB REFERENCE LINE

02607-043

Figure 43. SFDR vs. AIN Input Level, AIN @ 10.3 MHz, 210 MSPS, LVDS Mode,

Full Scale = 0.76 V/1.536 V

MHz

2.65 42.521.25

NOISE INPUT LEVEL (dB)

0

–140

–40

–120

–100

–60

–80

–20 NPR = 56.95dB

ENCODE = 170MSPS

NOTCH @ 19MHz

02607-044

Figure 44. Noise Power Ratio Plot

MHz

dB

0

–20

–40

–60

–80

–100

19.2 38.4

19.2

47.6

02607-045

Figure 45. W-CDMA Four Channels Centered at 38.4 MHz,

fs = 153.6 MHz, LVDS Mode

FULL-SCALE RANGE (V)

0 2.52.01.0 1.50.5

dB

90

0

70

10

50

30

60

40

20

80

SINAD

SNR

SFDR

02607-046

Figure 46. SNR, SINAD, and SFDR vs. Full-Scale Range, S5 = 0,

Full-Scale Range Varied by Adjusting VREF, 170 MSPS

TEMPERATURE (°C)

–40 1006020 40–20 0 80

ns

4.5

2.5

4.0

3.5

3.0

TPD

TCPD

02607-047

Figure 47. Propagation Delay vs. Temperature, LVDS Mode,

170 MSPS/210 MSPS

AD9430

Rev. D | Page 22 of 44

TCPD (CLOCKOUT RISING)

TEMPERATURE (°C)

–40 1006020 40–20 0 80

ns

4.5

2.5

4.0

3.5

3.0

TPDF (DATA FALLING)

TPDR (DATA RISING)

02607-048

RSET (kΩ)

0110621

V

DIF

(mV)

900

0

700

500

300

800

600

400

200

100

1.4

0.5

1.2

1.0

0.8

1.3

1.1

0.9

0.7

0.6

V

OS

(V)

V

OS

V

OD

02607-049

84 42

Figure 48. Propagation Delay vs. Temperature,

CMOS Mode, 170 MSPS/210 MSPS

Figure 49. LVDS Output Swing, Common-Mode Voltage vs. RSET,

Placed at LVDSBIAS, 170 MSPS/210 MSPS

AD9430

Rev. D | Page 23 of 44

TERMINOLOGY

Analog Bandwidth

The analog input frequency at which the spectral power of the

fundamental frequency (as determined by the FFT analysis) is

reduced by 3 dB.

Aperture Delay

The delay between the 50% point of the rising edge of the

ENCODE command and the instant at which the analog input

is sampled.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Crosstalk

Coupling onto one channel being driven by a low level

(–40 dBFS) signal when the adjacent interfering channel is

driven by a full-scale signal.

Differential Analog Input Resistance, Differential Analog

Input Capacitance, and Differential Analog Input Impedance

The real and complex impedances measured at each analog

input port. The resistance is measured statically and the

capacitance and differential input impedances are measured

with a network analyzer.

Differential Analog Input Voltage Range

The peak-to-peak differential voltage that must be applied to

the converter to generate a full-scale response. Peak differential

voltage is computed by observing the voltage on a single pin

and subtracting the voltage from the other pin, which is

180° out of phase. Peak-to-peak differential is computed by

rotating the input phase 180° and again taking the peak

measurement. The difference is then computed between both

peak measurements.

Differential Nonlinearity

The deviation of any code width from an ideal 1 LSB step.

Effective Number of Bits (ENOB)

Calculated from the measured SNR based on the equation

6.02

dB1.76−

=MEASURED

SNR

ENOB

ENCODE Pulse Width/Duty Cycle

Pulse width high is the minimum amount of time the ENCODE

pulse (clock pulse) should be left in a Logic 1 state to achieve

rated performance; pulse width low is the minimum time the

ENCODE pulse should be left in a low state. See the timing

implications of changing tEH in the Encode Input section. At

a given clock rate, these specifications define an acceptable

ENCODE duty cycle.

Full-Scale Input Power

Expressed in dBm. Computed using the following equation:

⎟

⎠

⎞

⎜

⎝

⎛

=

001.0

log10

2

INPUT

rmsSCALEFULL

SCALEFULL Z

V

Power

Gain Error

The difference between the measured and ideal full-scale input

voltage range of the ADC.

Harmonic Distortion, Second

The ratio of the rms signal amplitude to the rms value of the

second harmonic component, reported in dBc.

Harmonic Distortion, Third

The ratio of the rms signal amplitude to the rms value of the

third harmonic component, reported in dBc.

Integral Nonlinearity

The deviation of the transfer function from a reference line

measured in fractions of 1 LSB using a best straight line

determined by a least square curve fit.

Minimum Conversion Rate

The ENCODE rate at which the SNR of the lowest analog

signal

frequency drops by no more than 3 dB below the

guaranteed limit.

Maximum Conversion Rate

The ENCODE rate at which parametric testing is performed.

Output Propagation Delay

The delay between a differential crossing of CLK+ and CLK– and

the time when all output data bits are within valid logic levels.

Noise (for Any Range Within the ADC)

Calculated as follows:

⎟

⎠

⎞

⎜

⎝

⎛−−

××= 10

10001.0 dBFSdBcdBM

NOISE

SignalSNRFS

ZV

where:

Z is the input impedance.

FS is the full scale of the device for the frequency in question.

SNR is the value of the particular input level.

Signal is the signal level within the ADC, reported in dB below

full scale. This value includes input levels both thermal and

quantization noise.

AD9430

Rev. D | Page 24 of 44

Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in

power supply voltage.

Signal-to-Noise and Distortion (SINAD)

The ratio of the rms signal amplitude (set 1 dB below full scale)

to the rms value of the sum of all other spectral components,

including harmonics but excluding dc.

Signal-to-Noise Ratio (Without Harmonics)

The ratio of the rms signal amplitude (set at 1 dB below full

scale) to the rms value of the sum of all other spectral

components, excluding the first five harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the

peak spurious spectral component. The peak spurious

component may or may not be a harmonic. Reported in dBc

(degrades as signal level is lowered) or dBFS (always related

back to converter full scale).

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms

value of the worst third-order intermodulation product

;

reported in dBc.

Two-Tone SFDR

The ratio of the rms value of either input tone to the rms value

of the peak spurious component. The peak spurious component

may or may not be an IMD product. Reported in dBc (degrades

as signal level is lowered) or in dBFS (always related back to

converter full scale).

Worst Other Spur

The ratio of the rms signal amplitude to the rms value of the

worst spurious component (excluding the second and third

harmonic) reported in dBc.

Transient Resp onse Time

The time it takes for the ADC to reacquire the analog input

after a transient from 10% above negative full scale to

10% below positive full scale.

Out-of-Range Recovery Time

The time it takes for the ADC to reacquire the analog input

after a transient from 10% above positive full scale to 10% above

negative full scale, or from 10% below negative full scale to

10% below positive full scale.

AD9430

Rev. D | Page 25 of 44

APPLICATION NOTES

THEORY OF OPERATION

The AD9430 architecture is optimized for high speed and ease

of use. The analog inputs drive an integrated high bandwidth

track-and-hold circuit that samples the signal prior to

quantization by the 12-bit core. For ease of use, the part

includes an on-board reference and input logic that accepts

TTL, CMOS, or LVPECL levels. The digital output logic levels

are user selectable as standard 3 V CMOS or LVDS (ANSI-644

compatible) via Pin S2.

ENCODE INPUT

Any high speed ADC is extremely sensitive to the quality of the

sampling clock provided by the user. A track-and-hold circuit is

essentially a mixer, and any noise, distortion, or timing jitter on

the clock is combined with the desired signal at the A/D output.

For that reason, considerable care has been taken in the design

of the clock inputs of the AD9430, and the user is advised to

give careful thought to the clock source.

The AD9430 has an internal clock duty cycle stabilization

circuit that locks to the rising edge of CLK+ and optimizes

timing internally. This allows for a wide range of input duty

cycles at the input without degrading performance. Jitter in

the

rising edge of the input is still of paramount concern and

is

not reduced by the internal stabilization circuit. The duty

cycle control loop does not function for clock rates less than

30 MHz nominally. The loop has a time constant associated

with it that needs to be considered in applications where the

clock rate can change dynamically, requiring a wait time of

1.5 µs to 5 µs after a dynamic clock frequency increase before

valid data is available. This circuit is always on and cannot be

disabled by the user.

The clock inputs are internally biased to 1.5 V (nominal) and

support either differential or single-ended signals. For best

dynamic performance, a differential signal is recommended. An

MC100LVEL16 performs well in the circuit to drive the clock

inputs, as illustrated in Figure 50. (For trace lengths >2 inches, a

standard LVPECL termination is recommended rather than the

simple pull-down as shown.) Note that for this low voltage

PECL device, the ac coupling is optional.

PECL

GATE

510Ω

0.1μF

CLK–

AD9430

CLK+

02607-050

Figure 50. Driving Clock Inputs with LVEL16

In interleaved mode, output data on Port A is offset from output

data changes on Port B by one-half output clock cycle, as shown

in Figure 51.

INTERLEAVED MODE PARALLEL MODE

02607-051

Figure 51.

Table 9. Output Select Coding

S11S21 S41 S51

(Data Format Select) (LVDS/CMOS Mode Select)2 (I/P Select) (Full-Scale Select)3 Mode

1 X X X Twos complement

0 X X X Offset binary

X 0 1 X Dual-mode CMOS interleaved

X 0 0 X Dual-mode CMOS parallel

X 1 X X LVDS mode

X X X 1 Full scale = 0.768 V

X X X 0 Full scale = 1.536 V

1 X = don’t care.

2 S4 used in CMOS mode only (S2 = 0). S1 to S5 all have 30 kΩ resistive pull-downs on chip.

3 S5 full-scale adjust (see the Analog Input section).

AD9430

Rev. D | Page 26 of 44

ANALOG INPUT

The analog input to the AD9430 is a differential buffer. For

best dynamic performance, impedances at VIN+ and VIN

–

should match. The analog input is optimized to provide

superior

wideband performance and requires that the analog

inputs be driven differentially. SNR and SINAD performance

degrades significantly if the analog input is driven with a single-

ended signal.

A wideband transformer such as the Mini-Circuit® ADT1-1WT

can provide the differential analog inputs for applications that

require a single-ended-to-differential conversion. Both analog

inputs are self-biased by an on-chip resistor divider to a

nominal 2.8 V. (See the Equivalent Circuits section.)

Special care was taken in the design of the analog input section

of the AD9430 to prevent damage and corruption of data when

the input is overdriven. The nominal differential input range is

approximately 1.5 V p-p ~ (768 mV × 2). Note that the best

SNR performance is achieved with S5 = 0 (full scale = 1.5).

2.8V 2.8V

VIN+

VIN–

768mV

S5 = GND

DIGITALOUT = ALL 1s DIGITALOUT = ALL 0s

02607-052

Figure 52. Differential Analog Input Range

2.8V

S5 = AVDD

768mV

VIN+

VIN– = 2.8V

2.8V

02607-053

Figure 53. Single-Ended Analog Input Range

DS INPUTS (DS+, DS–)

In CMOS output mode, the data sync inputs (DS+, DS–) can be

used in applications that require a given sample to appear at a

specific output port (A or B) relative to a given external timing

signal. The DS inputs can also be used to synchronize two or

more ADCs in a system to maintain phasing between Port A

and Port B on separate ADCs (in effect, synchronizing multiple

DCO outputs). When DS+ is held high (DS– low), the ADC

data outputs and clock do not switch and are held static.

Synchronization is accomplished by the assertion (falling edge)

of DS+ within the timing constraints tSDS and tHDS, relative to a

clock rising edge. (On initial synchronization, tHDS is not

relevant.) If DS+ falls within the required setup time (tSDS)

before a given clock rising edge, N, the analog value at that

point in time is digitized and available at Port A, 14 cycles later

in interleaved mode.

The very next sample, N + 1, is sampled by the next rising clock

edge and available at Port B, 14 cycles after that clock edge. In

dual-parallel mode, Port A has a 15-cycle latency and Port B

has a 14-cycle latency, but data is available at the same time.

Driving the DS inputs of each ADC by the same sync signal

accomplishes this. An easy way to accomplish synchronization

is by a one-time sync at power-on reset. Note that when

running the AD9430 in LVDS mode, set DS+ to ground and

DS– to 3.3 V, as the DS inputs are relevant only in CMOS

output mode, simplifying the design for some applications as

well as affording superior SNR/SINAD performance at higher

encode/analog frequencies.

CMOS OUTPUTS

The off-chip drivers on the chip can be configured to provide

CMOS-compatible output levels via Pin S2. The CMOS digital

outputs (S2 = 0) are TTL/CMOS compatible for lower power

consumption. The outputs are biased from a separate supply

(DRVDD), allowing easy interface to external logic. The outputs

are CMOS devices that swing from ground to DRVDD (with no

dc load). It is recommended to minimize the capacitive load the

ADC drives by keeping the output traces short (<1 inch, for a

total CLOAD < 5 pF). When operating in CMOS mode, it is also

recommended to place low value (20 Ω) series damping

resistors on the data lines to reduce switching transient effects

on performance.

AD9430

Rev. D | Page 27 of 44

LVDS OUTPUTS

The off-chip drivers on the chip can be configured to provide

LVDS-compatible output levels via Pin S2. LVDS outputs are

available when S2 = VDD and a 3.74 kΩ RSET resistor is placed

at Pin 7 (LVDSBIAS) to ground. The RSET resistor current is

ratioed on-chip, setting the output current at each output equal

to a nominal 3.5 mA (11 × IRSET). A 100 Ω differential

termination resistor placed at the LVDS receiver inputs results

in a nominal 350 mV swing at the receiver. LVDS mode

facilitates interfacing with LVDS receivers in custom ASICs and

FPGAs that have LVDS capability for superior switching

performance in noisy environments. Single point-to-point net

topologies are recommended with a 100 Ω termination resistor

as close to the receiver as possible. It is recommended to keep

the trace length three to four inches maximum and to keep

differential output trace lengths as equal as possible.

CLOCK OUTPUTS (DCO+, DCO–)

The input ENCODE is divided by two (in CMOS mode) and

available off chip at DCO+ and DCO–. These clocks can

facilitate latching off chip, providing a low skew clocking

solution (see Figure 2). The on-chip clock buffers should not

drive more than 5 pF of capacitance to limit switching transient

effects on performance. Note that the output clocks are CMOS

levels when CMOS mode is selected (S2 = 0) and are LVDS

levels when in LVDS mode (S2 = VDD), requiring a 100 Ω

differential termination at receiver in LVDS mode. The output

clock in LVDS mode switches at the ENCODE rate.

VOLTAGE REFERENCE

A stable and accurate 1.23 V voltage reference is built into the

AD9430 (VREF). The analog input full-scale range is linearly

proportional to the voltage at VREF. Note that an external

reference can be used by connecting the SENSE pin to VDD

(disabling internal reference) and driving VREF with the

external reference source. No appreciable degradation in

performance occurs when VREF is adjusted ±5%. A 0.1 µF

capacitor to ground is recommended at the VREF pin in

internal and external reference applications. Float the SENSE

pin for internal reference operation.

A1

VREF

1kΩSENSE

200Ω

0.1μF

DISABLE

A1 V

DD

KFULL

SCALE

+

1V

3.3V

EXTERNAL 1.23V

REFERENCE +

+

S5 = 0 —> K = 1.24

S5 = 1 —> K = 0.62

02607-054

Figure 54. Using an External Reference

NOISE POWER RATIO TESTING (NPR)

NPR is a test that is commonly used to characterize the return

path of cable systems where the signals are typically QAM

signals with a noise-like frequency spectrum. NPR performance

of the AD9430 was characterized in the lab yielding an effective

NPR = 56.9 dB at an analog input of 19 MHz. This agrees with

a theoretical maximum NPR of 57.1 dB for an 11-bit ADC at

13.6 dB backoff. The rms noise power of the signal inside the

notch is compared with the rms noise level outside the notch

using an FFT. Sufficiently long record lengths to guarantee a

sufficient number of samples inside the notch are a

requirement, as well as a high order band-stop filter that

provides the required notch depth for testing.

AD9430

Rev. D | Page 28 of 44

EVALUATION BOARD, CMOS MODE

The AD9430 evaluation board offers an easy way to test the

AD9430 in CMOS mode. It requires a clock source, an analog

input signal, and a 3.3 V power supply. The clock source is

buffered on the board to provide the clocks for the ADC,

latches, and data ready signals. The digital outputs and output

clocks are available at two 40-pin connectors, P3 and P23. The

PCB interfaces directly with ADI standard dual-channel data

capture board (HSC-ADC-EVAL-DC) which, together with

ADI ADC Analyzer software, allows for quick ADC evaluation.

The board has several different modes of operation and is

shipped in the following configurations:

• Offset binary

• Internal voltage reference

• CMOS parallel timing

• Full-scale adjust = low

POWER CONNECTOR

Power is supplied to the board via a detachable 12-lead power

strip (three 4-pin blocks). AVDD, DRVDD, and VDL are the

minimum required power connections.

Table 10. Power Connector, CMOS Mode

AVDD 3.3 V Analog supply for ADC (350 mA)

DRVDD 3.3 V Output supply for ADC (28 mA)

VDL 3.3 V Supply for support logic and DAC (350 mA)

EXT_VREF Optional external reference input

VCLK/V_XTAL Supply for clock buffer/optional CRYSTAL

VAMP Supply for optional amp

ANALOG INPUTS

The evaluation board accepts a 1.3 V p-p analog input signal

centered at ground at SMB connector J4. This signal is

terminated to ground through 50 Ω by R16. The input can be

alternatively terminated at the transformer T1 secondary by

R13 and R14. T1 is a wideband RF transformer providing the

single-ended-to-differential conversion, allowing the ADC to be

driven differentially and minimizing even-order harmonics.

An optional second transformer, T2, can be placed following

T1 if desired. This provides some performance advantage

(~1 dB to 2 dB) for high analog input frequencies (>100 MHz).

If T2 is placed, two shorting traces at the pads need to be cut.

The analog signal is low-pass filtered by R41, C12 and R42, and

C13 at the ADC input.

GAIN

Full scale is set at E17, E18, and E19. Connecting E17 to E18

sets S5 low, full scale = 1.5 V differential; connecting E17 to E19

sets S5 high, full scale = 0.75 V differential.

ENCODE

The ENCODE clock is terminated to ground through 50  at

SMB Connector J5. The input is ac coupled to a high speed

differential receiver (LVEL16) that provides the required

low jitter, fast edge rates needed for optimum performance.

J5 input should be >0.5 V p-p. Power to the EL16 is set at

Jumper E47. Connecting E47 to E45 powers the buffer from

AVDD; connecting E47 to E46 powers the buffer from

VCLK/V_XTAL.

VOLTAGE REFERENCE

The AD9430 has an internal 1.23 V voltage reference. The ADC

uses the internal reference as the default when jumpers E24 to

E27 and E25 to E26 are left open. The full scale can be increased

by placing optional Resistor R3. The required value varies with

the process and needs to be tuned for the specific application.

Full scale can similarly be reduced by placing R4; tuning is

required here as well. An external reference can be used by

shorting the SENSE pin to 3.3 V (place Jumper E26 to E25).

The E27 to E24 jumper connects the ADC VREF pin to the

EXT_VREF pin at the power connector.

DATA FORMAT SELECT

Data format select sets the output data format of the ADC.

Setting DFS (E1 to E2) low sets the output format to be offset

binary; setting DFS high (E1 to E3) sets the output to twos

complement.

I/P TIMING SELECT

Output timing is set at E11, E12 and E13. E12 to E11 sets S4

low for parallel output timing mode. E11 to E13 sets S4 high

for interleaved timing mode.

TIMING CONTROLS

Flexibility in latch clocking and output timing is accomplished

by allowing for clock inversion at the timing controls section of

the PCB. Each buffered clock is buffered by an XOR and can be

inverted by moving the appropriate jumper for that clock.

AD9430

Rev. D | Page 29 of 44

CMOS DATA OUTPUTS

The ADC CMOS digital outputs are latched on the board by

four LVT574s; the latch outputs are available at the two 40-pin

connectors at Pin 11 through Pin 33 on P23 (Channel A) and

Pin 11 through Pin 33 on P3 (Channel B). The latch output

clocks (data ready) are available at Pin 37 on P23 (Channel A)

and Pin 37 on P3 (Channel B). The data-ready clocks can be

inverted at the timing controls section if needed.

CH1 CH2CH2 M 5.00ns

1

2

Δ

4.6ns

C1 FREQ

84.65608MHz

2.00V 2.00V

02607-055

Figure 55. Data Output and Clock @ 80-Pin Connector

CRYSTAL OSCILLATOR

An optional crystal oscillator can be placed on the board to

serve as a clock source for the PCB. Power to the oscillator is

through the VCLK pin at the power connector (also called

VCLK/V_XTAL). If an oscillator is used, ensure proper

termination for best results. The board has been tested with a

Valpey Fisher VF561 and a Vectron JN00158-163.84. Test

results for the VF561 are shown in Figure 56.

MHz

0

–30

0820

dB

40 60 0

–60

–80

–20

–10

–50

–40

–100

–90

–70

ENCODE 163.84MHz

ANALOG 65.02MHz

SNR 63.93dB

SINAD 63.87dB

FUND –0.45dBFS

2ND –85.62dBc

3RD –91.31dBc

4TH –90.54dBc

5TH –90.56dBc

6TH –91.12dBc

THD –82.21dBc

SFDR 83.93dBc

SAMPLES 8k

NOISEFLR –100.44dBFS

WORSTSP –83.93dBc

02607-057

Figure 56. FFT—Using VF561 Crystal as Clock Source

OPTIONAL AMPLIFIER

The evaluation board as shipped uses a wideband RF

transformer in its analog path. A user can modify the board to

use the AD8351 op amp for ac- or dc-coupled applications

(see Figure 59 and Figure 60). Figure 60 shows the AD8351 in

an ac-coupled topology, while Figure 57 shows the AD8351 in

a dc-coupled application. Optimum performance is obtained

with the AD8351 ac coupled.

SINGLE-

ENDED

50Ω

SOURCE

R1 100nF

100nF

AD8351

INHI

INLO

R

G

OPHI

OPLO

VOCM

DIGITAL

OUT

AD9430

AIN+

AIN–

100nF

R

F

5pF

2.8V

25Ω

50Ω

25Ω

02607-078

Figure 57. Using the AD8351 on the AD9430 PCB

AD9430

Rev. D | Page 30 of 44

TROUBLESHOOTING

If the board does not seem to be working correctly, try the

following:

• Verify power at IC pins.

• Check that all jumpers are in the correct position for the

desired mode of operation.

• Verify that VREF is at 1.23 V.

• Run the clock and analog inputs at low speeds (10 MSPS/

1 MHz) and monitor latch and ADC for toggling.

The AD9430 evaluation board is provided as a design

example for customers of Analog Devices, Inc. ADI makes

no warranties, express, statutory, or implied, regarding

merchantability or fitness for a particular purpose.

SIGNAL

GENERATOR

SIGNAL

GENERATOR

REFIN

10MHz

REFOUT

BAND-PASS

FILTER ANALOG

J4

CLOCK

J5

AD9430 EVALUATION BOARD

AVDD GND DRVDDGND VDL GND

3.3V 3.3V 3.3V

+

DATA

CAPTURE

AND

PROCESSING

02607-059

–

+–

Figure 58. Evaluation Board Connections

AD9430

Rev. D | Page 31 of 44

Table 11. CMOS PCB Evaluation Board Bill of Material

No. Quantity Reference Designator Device Package Value Comments

1 47 C1, C3–C11, C15–C44,

C47, C48, C58–C62

Capacitor 0402 0.1 μF C11, C18, C30, C33,

C34, C39, C40, C48

Not placed

2 1 C2 Capacitor 0402 10 pF Not placed

3 1 C12 Capacitor 0402 20 pF Not placed

4 29 C13, C14, C45, C46, C50–C57,

C68-C84

Capacitor 0402 0.01 μF All .01uF caps not

placed

5 6 C49, C63–C67 Capacitor CAPL 10 μF

6 8 (E3, E1, E2),( E19, E17, E18),

(E13, E11, E12),( E46, E47, E45),

(E35, E33, E34),( E32, E30, E31),

(E29, E23, E28),( E22, E16, E21)

3-pin

header/jumper

7 1 E26, E25, E27, E24 4-pin

header/jumper

8 4 J1, J2, J4, J5 SMA SMA J2 not placed

9 2 P3, P231 Connector

10 3 P4, P21, P22 4-pin power

connector

Post Z5.531.3425.0 Wieland

11 3 P4, P21, P22 4-pin power

connector

Detachable

connector

25.602.5453.0 Wieland

12 4 R1, R5, R16, R27 Resistor 0402 50 Ω R1 not placed

13 3 R2, R3, R4 Resistor 0402 3.8K Ω R3, R4 not placed

14 8 R6–R8, R10, R33–R36 Resistor 0603 100 Ω R34 not placed

15 2 R9, R11 Resistor 0402 0 Ω

16 17 R12, R15, R21–R26, R28–R31, R37,

R38, R43, R46, R47

Resistor 0402 User selected All 17 not placed

17 6 R13, R14, R41, R42, R44, R45 Resistor 0402 25 Ω R13, R14, R44, R45 not

placed

18 2 R17, R18

Resistor 0402 510 Ω

19 2 R19, R20 Resistor 0402 150 Ω

20 2 R39, R40

Resistor 0402 1 kΩ

21 8 RZ1, RZ2, RZ3, RZ4, RZ5, RZ6, RZ7,

RZ8

Resistor pack 220 Ω

SO16RES 742C163221JTR CTS

22 1 L1 Inductor 0603 User selected Not placed

23 2 T1,T4 Transformer CD542 Mini-Circuits

ADT1–1WT

T4 not placed

24 2 T2,T3 Optional Macom

Transformer

SM-22 ETC1–1–13 Not placed

25 1 U1 AD9430BSV (−210) TQFP100 ADC

26 1 U2 MC100LVEL16D SO8NB Clock buffer

27 1 U3 VCX86 SO14NB XOR

28 4 U4, U5, U6, U7 LVT574 SO20

29 1 U8 JN00158 Optional XTAL Not placed

30 1 U9 AD8351 Amp

1 P3 and P23 are implemented as one physical 80-pin connector, the SAMTEC TSW-140-08-L-D-RA.

AD9430

Rev. D | Page 32 of 44

VCC

VEE

DQ

DN QN

VBB

GND

E45

E46

VCC

VCLK

E47 C36

0.1μF

J5

GND

R27

50Ω

C5

0.1μF

ENCODE 2

3

4

5

6

7

8

C8

0.1μF

R18

510Ω

R17

510Ω

MC100L

10EL16 U2

GND

R20

150ΩR19

150Ω

GND

OUT_EN

D0

D1

D2

D3

D4

D5

D6

D7

GND

VCC

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

CLOCK

U7

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11 CLKLATB

VDL

GND

GND R1

R2

R3

R4

R5

R6

R7

R8

RZ5 220

RSO16ISO

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

DY4

DY3

DY2

DY1

DY0

DYA

DYB

R1

R2

R3

R4

R5

R6

R7

R8

RZ4 220

RSO16ISO

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

OUT_EN

D0

D1

D2

D3

D4

D5

D6

D7

GND

VCC

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

CLOCK

U6

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11 CLKLATA

VDL

GND

GND R1

R2

R3

R4

R5

R6

R7

R8

RZ6 220

RSO16ISO

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

ORY

DY11

DY10

DY9

DY8

DY7

DY6

DY5

R1

R2

R3

R4

R5

R6

R7

R8

RZ3 220

RSO16ISO

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

C4OMS

P3

P40

P38

P36

P34

P32

P30

P28

P26

P24

P22

P20

P18

P16

P14

P12

P10

P8

P6

P4

P2

P39

P37

P35

P33

P31

P29

P27

P25

P23

P21

P19

P17

P15

P13

P11

P9

P7

P5

P3

P1

GND

DRB

GND

DY11

DY10

DY9

DY8

DY7

DY6

DY5

DY4

DY3

DY2

DY1

DY0

DYA

DYB

ORY

GND

OUT_EN

D0

D1

D2

D3

D4

D5

D6

D7

GND

VCC

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

CLOCK

U4

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

DM8

DM7

DM6

DM5

CLKLATA

VDL

GND

GND R1

R2

R3

R4

R5

R6

R7

R8

RZ8 220

RSO 16ISO

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

ORX

DX11

DX10

DX9

DX8

DX7

DX6

DX5

R1

R2

R3

R4

R5

R6

R7

R8

RZ1 220

RSO16ISO

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

C4OMS

P23

P40

P38

P36

P34

P32

P30

P28

P26

P24

P22

P20

P18

P16

P14

P12

P10

P8

P6

P4

P2

P39

P37

P35

P33

P31

P29

P27

P25

P23

P21

P19

P17

P15

P13

P11

P9

P7

P5

P3

P1

GND

DRA

GND

DX11

DX10

DX9

DX8

DX7

DX6

DX5

DX4

DX3

DX2

DX1

DX0

DXA

DXB

ORX

GND

OUT_EN

D0

D1

D2

D3

D4

D5

D6

D7

GND

VCC

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

CLOCK

74AC574M

U5

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11 CLKLATA

VDL

GND

GND R1

R2

R3

R4

R5

R6

R7

R8

RZ7 220

RSO16ISO

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

DX4

DX3

DX2

DX1

DX0

DXA

DXB

R1

R2

R3

R4

R5

R6

R7

R8

RZ2 220

RSO16ISO

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

P1

P2

P3

P4

1

2

3

4GNDAMP

VAMP

P4

PTMICA04

P1

P2

P3

P4

1

2

3

4GND

VDL

VCLK

VREF

P21

PTMICA04

P1

P2

P3

P4

1

2

3

4GND

VCC

GND

DRVDD

P22

PTMICA04

E20VDL

E7

DRVDD

COUTA

COUT R9

0Ω

COUTAB

COUTB R11

0Ω

H4

MTHOLES

H3

MTHOLES

H2

MTHOLES

H1

MTHOLES

GND

U3 3

74AVC86

CLKLATA

R33

100Ω

COUTA

R10

100Ω

E35

E34

VDL

GND

E33

1

2

U3 6

74AVC86

DRA

R34

100Ω

R8

100Ω

E32

E31

VDL

GND

E30

4

5

U3 8

74AVC86

CLKLATB

R35

100Ω

R7

100Ω

E29

E28

VDL

GND

E23

9

10

U3 11

74AVC86

DRB

R36

100Ω

R6

100Ω

E22

E21

VDL

GND

E16

12

13

P16 GND

GROUND PAD UNDER PART

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

U1

AD9430

DR VDD

GND

COUT

COUTB

DRVDD

GND

DRVDD

GND

DRVDD

GND

VCC

GND

VCC

GND

VCC

GND

DR VDD

GND

VCC

GND

VCC

GND

VCC

GND

C4

0.1μF

VCC

GND

E14

GND

R5

50Ω

J1

GND

R1

50Ω

J2

NOTES

1. TO USE SINGLE ENDED ANALOG INPUT,

REMOVE C6, C43, AND C47

PLACE C33, C34, R44 AND R45

E1 E3VCC

E2GND

–ENC

GND

VCC

GND

VCC

GND

VCC

GND

VCC

E11 E13VCC

E12GND

E8 E10VCC

E9GND

R40

1kΩ

GND

E4 E6VCC

E5GND

R39

1kΩ

GND

C13

0.01μF

GND

E27

E26VCC

E24VREF

E25

R4

3.8KΩ

R3

3.8KΩ

GND GND

E17 E19VCC

E18GND

C10

0.1μF

C9

0.1μF

COUTA

COUTAB

02607-060

74AC574M

GND

EL OUTB

EL OUT

GND

R2

3.8kΩ

C1

0.1μF

GND

C2

10pF

GND

J4

GND

R16

50Ω

ANALOG

OPTIN C6

0.1μF

C7

0.1μF

GND

E15

INX

T1

6

4

5

1

3

2

GND

6

4

5

1

3

2

T4

R44

25ΩC34

0.1μF

C12

20pF

R42

25Ω

R41

25Ω

AMPIN

AMPINB

C3

0.1μF

C43

0.1μF

C47

0.1μF

R14

25Ω

R13

25Ω

OPIN

OPINB

C33

0.1μF

R45

25Ω

SEE NOTE 1 FOR

SINGLE ENDED INPUT

Q

SEE NOTE 1 FOR

SINGLE ENDED INPUT

Figure 59. Evaluation Board Schematic—CMOS

AD9430

Rev. D | Page 33 of 44

02607-077

C68

0.01μF

VCC

GND

PLACE R30 OR R31

(POWER DOWN)

E/D

1

NC

2

GND

3

VCC

OUTPUTB

OUTPUT

6

5

4

JN00158

U8

GND

R15

100Ω

R38

100ΩGND

VCLK

GND

R21

100Ω

R22

100Ω

VCLK

GND

R23

100Ω

R24

100Ω

P1

P2

+

C64

10μFC16

0.1μFC17

0.1μFC19

0.1μFC21

0.1μFC20

0.1μFC23

0.1μFC22

0.1μFC25

0.1μFC24

0.1μFC27

0.1μFC26

0.1μFC29

0.1μFC28

0.1μFC31

0.1μFC32

0.1μFC35

0.1μF

VCC

GND

C38

0.1μF

C69

0.01μFC70

0.01μFC71

0.01μFC72

0.01μFC73

0.01μFC74

0.01μFC75

0.01μFC76

0.01μFC77

0.01μFC78

0.01μFC79

0.01μFC80

0.01μFC81

0.01μFC82

0.01μFC83

0.01μFC84

0.01μF

C67

10μF

VDL

GND

C46

0.01μFC50

0.01μFC51

0.01μFC52

0.01μFC45

0.01μFC44

0.1μFC42

0.1μFC41

0.1μFC15

0.1μFC37

0.1μF

C65

10μF

DRVDD

GND

C62

0.1μFC60

0.1μFC59

0.1μFC58

0.1μFC53

0.01μFC54

0.01μFC55

0.01μFC56

0.01μFC57

0.01μF

C66

10μFC14

0.01μF

VCLK

GND

+C63

10μF

VREF

GND

+C49

10μFC48

0.1μF

VAMP

GND

+

VOCM

VPOS

OPHI

OPLO

COMM

PWDN

RGP1

INHI

INLO

RGP2

GND

RGP1 VAMP

GND

RGP1 R12

25ΩR25

1.2kΩ

R31

1kΩR30

1kΩ

R43

25Ω

C11

0.1μF

R29

0Ω

GND

OPTIN

R37

25Ω

VAMP

AMPINB

AMPIN

C39

0.1μF

C40

0.1μF

R47

25Ω

R46

25Ω

GND

INX

OPIN

OPINB

T3

ETC1-1-13

T2

ETC1-1-13 1515

22

3434

PR SEC PR SEC

GND VAMP

TO USE VF561C CRYSTAL

L1

X

L IS OPTIONAL

C18

0.1μF

C30

0.1μF1

2

3

4

5

10

9

8

7

6

R26

1kΩR28

1kΩ

+

+C61

0.1μF

AD8351

U9

Figure 60. Evaluation Board Schematic—CMOS (continued)

AD9430

Rev. D | Page 34 of 44

02607-081

Figure 61. PCB Top-Side Silkscreen

02607-082

Figure 62. PCB Top-Side Copper

02607-083

Figure 63. PCB Ground Layer

02607-084

Figure 64. PCB Split Power Plane

AD9430

Rev. D | Page 35 of 44

02607-085

Figure 65. PCB Bottom-Side Copper

02607-086

Figure 66. PCB Bottom-Side Silkscreen

AD9430

Rev. D | Page 36 of 44

EVALUATION BOARD, LVDS MODE

The AD9430 evaluation board offers an easy way to test the

AD9430 in LVDS mode. (The board is also compatible with the

AD9411.) It requires a clock source, an analog input signal, and

a 3.3 V power supply. The clock source is buffered on the board

to provide the clocks for the ADC, latches, and a data-ready

signal. The digital outputs and output clocks are available at a

40-pin connector, P23. The board has several different modes of

operation and is shipped in the following configurations:

• Offset binary

• Internal voltage reference

• Full-scale adjust = low

Note that the AD9430 LVDS evaluation board does not

interface directly with the standard Analog Devices dual-

channel data capture board (HSC-ADC-EVAL-DC). An LVDS-

to-CMOS translation board is required and is available from

Analog Devices. (No translation board is required for the

AD9430 CMOS evaluation board.)

POWER CONNECTOR

Power is supplied to the board via a detachable 8-lead power

strip (two 4-pin blocks). In Table 12, VCC, DRVDD, and VDL

are the minimum required power connections, and the

LVEL16 clock buffer can be powered from VCC or VDL at

the E47 jumper.

Table 12. Power Connector, LVDS Mode

VCC 3.3 V Analog supply for ADC (350 mA)

DRVDD 3.3 V Output supply for ADC (50 mA)

VDL 3.3 V Supply for support logic

EXT_VREF Optional external reference input

ANALOG INPUTS

The evaluation board accepts a 1.3 V p-p analog input signal

centered at ground at SMB Connector J4. This signal is

terminated to ground through 50 Ω by R16. The input can be

alternatively terminated at the T1 transformer secondary by

R13 and R14.

T1 is a wideband RF transformer providing the

single-

ended-to-differential conversion, allowing the ADC to

be driven differentially and minimizing even-order harmonics.

An o

ptional second transformer, T2, can be placed following

T1

if desired. This provides some performance advantage

(~1 to 2 dB) for high analog input frequencies (>100 MHz). If

T2 is placed, two shorting traces at the pads need to be cut. The

analog signal can be low-pass filtered by R41, C12 and R42, and

C13 at the ADC input. A wideband differential amplifier

(AD8351) can be configured on the PCB for dc-coupled

applications. Remove C6, C15, and C30 to prevent transformer

loading of the amp. See Figure 67, Figure 68, and Figure 69 for

more information.

GAIN

Full scale is set at E17 to E19, E17 to E18 sets S5 low, full scale =

1.5 V differential; E17 to E19 sets S5 high, full scale = 0.75 V

differential. Best performance is obtained at 1.5 V full scale.

CLOCK

The CLOCK input is terminated to ground through a 50 Ω

resistor at SMB connector J5. The input is ac coupled to a high

speed differential receiver (LVEL16) that provides the required

low jitter, fast edge rates needed for optimum performance.

J5 input should be >0.5 V p-p. Power to the LVEL16 is set at

Jumper E47. E47 to E45 powers the buffer from AVDD; E47 to

E46 powers the buffer from VCLK/V_XTAL (not in Table 11).

VOLTAGE REFERENCE

The AD9430 has an internal 1.23 V voltage reference. The ADC

uses the internal reference as the default when jumpers E24 to

E27 and E25 to E26 are left open. The full scale can be increased

by placing optional resistor R3. The required value varies with

the process and needs to be tuned for the specific application.

Full scale can similarly be reduced by placing R4; tuning is

required here as well. An external reference can be used by

shorting the SENSE pin to 3.3 V (place jumper E26 to E25).

Jumper E27 to E24 connects the ADC VREF pin to the

EXT_VREF pin at the power connector.

DATA FORMAT SELECT

Data format select (DFS) sets the output data format of the ADC.

Setting DFS low (E1

to

E2) sets the output format to be offset

binary;

setting DFS high (E1

to

E3) sets the output to twos

complement.

DATA OUTPUTS

The ADC LVDS digital outputs are routed directly to the

connector at the card edge. Resistor pads have been placed at

the output connector to allow for termination if the connector

receiving logic does not have the required differential

termination for the data bits and DCO. Each output trace pair

should be terminated differentially at the far end of the line

with a single 100  resistor.

CRYSTAL OSCILLATOR

An optional crystal oscillator can be placed on the board to

serve as a clock source for the PCB. Power to the oscillator is

through the VDL pin at the power connector. If an oscillator is

used, ensure proper termination for best results. The board has

been tested with a Valpey Fisher VF561 and a Vectron JN00158-

163.84.

AD9430

Rev. D | Page 37 of 44

Table 13. LVDS PCB Evaluation Board Bill of Material

No. Quantity Reference Designator Device Package Value Comment

1 33 C1, C4–C11, C15–C17, C19–C32,

C35, C36, C58–C62

C3, C18, C39, C40

Capacitors 0603 0.1 μF C3, C18, C39, C40 not

placed

2 4 C33, C34, C37, C38 Capacitor 0402 0.1 μF C33, C34, C37, C38 not

placed

3 4 C63–C66 Capacitor TAJD CAPL 10 uF

4 1 C2 Capacitor 0603 10 pF C2 not placed

5 2 C12, C13 Capacitor 0603 20 pF C12, C13 not placed

6 2 J4, J5 Jacks SMB

7 2 P21, P22 Power connectors

Top

25.602.5453.0

Wieland

8 2 P21, P22 Power connectors

Posts

Z5.531.3425.0

Wieland

9 1 P23 40-pin right-angle

connector

Digi-Key

S2131-20-ND

10 16 R1, R6–R12, R15, R31–R37 Resistor 0402 100 Ω R1, R6–R12, R15, R31–37

Not placed

11 1 R2 Resistor 0603 3.8 kΩ

12 3 R5, R16, R27 Resistor 0603 50 Ω

13 2 R17, R18 Resistor 0603 510 Ω

14 2 R19, R20 Resistor 0603 150 Ω

15 2 R29, R30 Resistor 0603 1 kΩ

16 2 R41, R42 Resistor 0603 25 Ω

17 2 R3, R4 Resistor 0603 3.8 kΩ

18 2 R13, R14 Resistor 0603 25 Ω R13, R14 not placed

19 6 R22, R23, R24, R25, R26, R28 Resistor 0603 100 Ω R22, R23, R24, R25, R26,

R28 not placed

20 4 R39, R40, R45, R47 Resistor 0402 25 Ω R39, R40, R45, R47

not placed

21 2 R43, R44 Resistor 0402 10 kΩ R43, R44 not placed

22 1 R46 Resistor 0402 1.2 kΩ R46 not placed

23 3 R38, R48, R49 Resistor 0402 25 Ω R38, R48, R49 not placed

24 2 R50, R51 Resistor 0402 1 kΩ R50, R51 not placed

25 1 T1

T2

RF transformer Mini-Circuits

ADT1-1WT

T2 not placed

26 1 U2 RF amp AD8351

27 1 U9 Optional crystal

oscillator

JN00158 or

VF561

28 1 U1 AD9430 TQFP-100

29 1 U3 MC100LVEL16 SO8NB

AD9430

Rev. D | Page 38 of 44

GND

40

DRB

38

GND

36

D11B

34

D10B

32

GND

DR

GND

D11

D10

39

37

35

33

31

D9B

30

D8B

28

D7B

26

D6B

24

D5B

22

D9

D8

D7

D6

D5

29

27

25

23

21

D4B

20

D3B

18

D2B

16

D1B

14

D0B

12

D4

D3

D2

D1

D0

19

17

15

13

11

D1FB

10

D2FB

8

DORB

6

4

GND

2

D1F

D2F

DO

R

GND

9

7

5

3

1

P40

P38

P36

P34

P32

P30

P28

P26

P24

P22

P20

P18

P16

P14

P12

P10

P8

P6

P4

P2

P39

P37

P35

P33

P31

P29

P27

P25

P23

P21

P19

P17

P15

P13

P11

P9

P7

P5

P3

P1

U1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

R1

100Ω

DOR

DORB

R6

100Ω

D11

D11B

R7

100Ω

D10

D10B

R8

100Ω

D9

D9B

R15

100Ω

D1

D1B

R36

100Ω

D0

D0B

R35

100Ω

D1F

D1FB

R34

100Ω

D2F

D2FB

R31

100Ω

D2

D2B

R10

100Ω

D6

D6B

R37

100Ω

DR

DRB

R32

100Ω

D3

D3B

R11

100Ω

D7

D7B

R9

100Ω

D5

D5B

R33

100Ω

D4

D4B

R12

100Ω

D8

D8B

GND

VCC

GND

VCC

GND

VCC

GND

DRVDD

GND

DRVDD

GND

VCC

GND

DRVDD

GND

~ENC

VCC

C4

0.1μFGND

GND

R5

50Ω

C10

0.1μF

C9

0.1μF

ELOUT

ELOUTB

GND

R19

150Ω

R20

150Ω

GND

C36

0.1μF

VCC

VEE

VBB

DN

DQ

QN

2

3

4

5

6

7

8

GND

R18

510Ω

R17

510ΩC8

0.1μF

VCC E46

E47

VDL E45

10EL16

U3

J5

GND

C5

0.1μF

ENCODE

R27

50Ω

C13

20pF

GND

VCC

GND

VCC

GND

VCC

GND

VCC

C12

20pF

C15

0.1μF

C3

0.1μF

C2

10pF

C30

0.1μF

C7

0.1μFC11

0.1μF

C6

0.1μF

J4

GND

R16

50Ω

R14

25Ω

R42

25Ω

T2 OPTIONAL

GND

R13

25Ω

GND

AMPINB

AMPIN

R41

25Ω

T1

ADT1-1WT

1

5

3

4

2

6

T2

ADT1-1WT

1

5

3

4

2

6

NC NC

PRI SEC PRI SEC

GND

AMP

ANALOG

VCC E19

VCC E3

E17

GND

E18

R30

1kΩ

VCC

R29

1kΩ

E1

GND E2

R2

3.8kΩ

GND

R3

3.8kΩ

R4

3.8kΩ

VCC E26

VREF E24

E25

E27

GND

C1

0.1μF

P16 GND

GROUND PAD UNDER PART

P1

P2

1

2

GND

VREF

P3

P4

3

4

GND

VDL

P1

P2

1

2

GND

DRVDD

P3

P4

3

4

GND

VCC

P21

PTM1CRO4

P22

PTM1CRO4

H4

MTHOLE6

H3

MTHOLE6

H2

MTHOLE6

H1

MTHOLE6

GND

CONNECTOR

02607-068

Figure 67. Evaluation Board Schematic—LVDS

AD9430

Rev. D | Page 39 of 44

02607-069

+

C64

10μFC16

0.1μFC17

0.1μFC19

0.1μFC21

0.1μFC20

0.1μFC23

0.1μFC22

0.1μFC25

0.1μFC24

0.1μFC27

0.1μFC26

0.1μFC29

0.1μFC28

0.1μFC31

0.1μFC32

0.1μFC35

0.1μF

VCC

GND

+

C65

10μFC61

0.1μFC62

0.1μFC60

0.1μFC59

0.1μFC58

0.1μF

DRVDD

GND

C66

10μFC18

0.1μF

VDL

GND

+C63

10μF

VREF

GND

+

TO USE VF561 CRYSTAL

E/D

1

NC

2

GND

3

VCC

OUTPUTB

OUTPUT

6

5

4

JN00158

U9

GND

R28

100Ω

R22

100ΩGND

VDL

GND

R23

100Ω

R25

100Ω

VDL

GND

R24

100Ω

R26

100Ω

P4

P5

Figure 68. Evaluation Board Schematic—LVDS (continued)

VDL

VDL GND

GND

AMP IN

AMP

POWER DOWN

USE R43 OR R44

U2

AD8351

R44

R39

25Ω

R38

R40

25Ω

R46

R45

25Ω

R43

C33

0.1μF

C34

0.1μF

VDL

GNDGND

R51

1kΩR50

1kΩ

C38

0.1μFC37

0.1μF

R49 C39

0.1μF

R48 C40

0.1μF

AMPINB

AMPIN

GND

R47

PWUP1

RGP1

2INHI

3INLO

4

RPG2

5

VOCM

VPOS

OPHI

OPLO

COMM

10

9

8

7

625Ω

25Ω

1.2kΩ

0Ω

10kΩ

02607-079

Figure 69. Evaluation Board Schematic—LVDS (continued)

AD9430

Rev. D | Page 40 of 44

F

02607-071

Figure 70. PCB Top-Side Silkscreen—LVDS

02607-072

Figure 71. PCB Top-Side Copper—LVDS

02607-073

Figure 72. PCB Ground Layer—LVDS

02607-074

Figure 73. PCB Split Power Plane—LVDS

AD9430

Rev. D | Page 41 of 44

02607-075

Figure 74. PCB Bottom-Side Copper—LVDS

02607-076

Figure 75. PCB Bottom-Side Silkscreen—LVDS

AD9430

Rev. D | Page 42 of 44

OUTLINE DIMENSIONS

NOTES

1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.

2

. THE AD9430 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION O

F

THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF

THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNA

L

TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIV

E

SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE

DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.

COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD

1

2526 50

76100 75

51

14.00 BSC SQ

16.00 BSC SQ

0.27

0.22

0.17

0.50 BSC

1.05

1.00

0.95

0.15

0.05

0.75

0.60

0.45

SEATING

PLANE

1.20

MAX

1

25

2650

76 100

75

51

6.50

NOM

7°

3.5°

0°

COPLANARITY

0.08

0.20

0.09

TOP VIEW

(PINS DOWN)

BOTTOM VIEW

(PINS UP)

CONDUCTIVE

HEAT SINK

PIN 1

Figure 76.100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

(SV-100-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9430BSV-170 –40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP) SV-100-1

AD9430BSVZ-1701 –40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP) SV-100-1

AD9430BSV-210 –40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP) SV-100-1

AD9430BSVZ-2101 –40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP) SV-100-1

AD9430-CMOS/PCB Evaluation Board (CMOS Mode) Shipped with –210 Grade

AD9430-LVDS/PCB Evaluation Board (LVDS Mode) Shipped with –210 Grade

1 Z = Pb-free part.

AD9430

Rev. D | Page 43 of 44

NOTES

AD9430

Rev. D | Page 44 of 44

NOTES

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C02607-0-8/05(D)