+
–
GTL2014
B0
B1
B2
B3
VREF DIR
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SN74GTL2014
SCLS746A –FEBRUARY 2014–REVISED OCTOBER 2014
SN74GTL2014 4-Channel LVTTL to GTL Transceiver
1 Features 2 Applications
1• Operates as a GTL–/GTL/GTL+ to LVTTL or • Server
LVTTL to GTL–/GTL/GTL+ Translator • Base Station
• The LVTTL Inputs are Tolerant up to 5.5 V • Wireline Communication
Allowing Direct Access to TTL or 5 V CMOS 3 Description
• The GTL Input/Output Operate up to 3.6 V,
Allowing the Device to be Used in High Voltage The SN74GTL2014 is a 4-channel translator to
Open-Drain Applications interface between 3.3-V LVTTL chip set I/O and Xeon
processor GTL–/GTL/GTL+ I/O.
• VREF Goes Down to 0.5 V for Low Voltage CPU
Usage The SN74GTL2014 integrates ESD protection cells
on all terminals and is available in a TSSOP package
• Partial Power-Down Permitted (5.0 mm × 4.4 mm). The device is characterized over
• Latch-up Protection Exceed 500 mA per JESD78 the free air temperature range of –40°C to 85°C.
• Package Option: TSSOP14 Device Information(1)
• –40°C to 85°C Operating Temperature Range PART NUMBER PACKAGE BODY SIZE (NOM)
• ESD Protection on All Terminals SN74GTL2014 TSSOP (14) 5.00 mm × 4.40 mm
– 2000 V HBM, JESD22-A114 (1) For all available packages, see the orderable addendum at
– 1000 V CDM, IEC61000-4-2 the end of the data sheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74GTL2014
SCLS746A –FEBRUARY 2014–REVISED OCTOBER 2014
www.ti.com
Table of Contents
8.2 Functional Block Diagram......................................... 8
1 Features.................................................................. 18.3 Feature Description................................................... 8
2 Applications ........................................................... 18.4 Device Functional Modes.......................................... 8
3 Description............................................................. 19 Application and Implementation .......................... 9
4 Revision History..................................................... 29.1 Application Information.............................................. 9
5 Pin Configuration and Functions......................... 39.2 Typical Application.................................................... 9
6 Specifications......................................................... 410 Power Supply Recommendations ..................... 12
6.1 Absolute Maximum Ratings ...................................... 411 Layout................................................................... 12
6.2 Handling Ratings....................................................... 411.1 Layout Guidelines ................................................. 12
6.3 Recommended Operating Conditions....................... 411.2 Layout Example .................................................... 12
6.4 Thermal Information.................................................. 512 Device and Documentation Support................. 13
6.5 Electrical Characteristics........................................... 512.1 Trademarks........................................................... 13
6.6 Dynamic Electrical Characteristics............................ 612.2 Electrostatic Discharge Caution............................ 13
6.7 Typical Characteristics.............................................. 612.3 Glossary................................................................ 13
7 Parameter Measurement Information .................. 713 Mechanical, Packaging, and Orderable
8 Detailed Description.............................................. 8Information ........................................................... 13
8.1 Overview................................................................... 8
4 Revision History
Changes from Original (February 2014) to Revision A Page
• Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section. .............................................................. 1
• Updated Specifications section .............................................................................................................................................. 4
• Updated LVTTL/TTL to GTL–/GTL/GTL+ application schematic. ......................................................................................... 9
• Updated LVTTL/TTL to GTL–/GTL/GTL+ application schematic. ....................................................................................... 11
• Added Power Supply Recommendations ............................................................................................................................ 12
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GTL2014
DIR
B0
B1
VREF
B2
GND
VCC
A0
A1
GND
A2
A3
GND
1
2
3
4
5
6
78
9
10
11
12
13
14
B3
SN74GTL2014
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SCLS746A –FEBRUARY 2014–REVISED OCTOBER 2014
5 Pin Configuration and Functions
TSSOP Package (14 Pin)
(Top View)
Pin Functions
PIN DESCRIPTION
NAME NUMBER
A0 13
A01 12 LVTTL data input/output
A02 10
A03 9
B0 2
B01 3 GTL data input/output
B02 5
B03 6
DIR 1 Direction control input (LVTTL)
7
GND 8 Ground
11
VCC 14 Supply voltage
VREF 4 GTL reference voltage
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6 Specifications
6.1 Absolute Maximum Ratings
Specified at TA= –40°C to 85°C unless otherwise noted(1)
MIN MAX UNIT
VCC Supply voltage –0.5 4.6 V
IIK Input clamping current, VI < 0 V –50 mA
VSEL Input control voltages SEL(2)(3) –0.5 6 V
A port –0.5 7
VIInput voltage V
B port –0.5 4.6
IOK Control input clamp current, VO< 0 V –50 mA
A port –0.5 7
VOOutput voltage V
B port –0.5 4.6
A port 40
IOL Current into any output in the low state mA
B port 80
IOH Current into any output in the high state –40 mA
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified
(3) VIand VOare used to denote specific conditions for VI/O
6.2 Handling Ratings MIN MAX UNIT
Tstg Storage temperature range –55 150 °C
Human Body Model (HBM), JEDEC: JESD22-A114(2) All pins 0 2
VESD(1) kV
IEC61000-4-2 contact discharge(3) All pins 0 1
(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by assembly line electrostatic discharges into
the device.
(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe
manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
GTL– 0.85 0.9 0.95
VTT Termination voltage GTL 1.14 1.2 1.26 V
GTL+ 1.35 1.5 1.65
Overall 0.5 2 / 3 VTT VCC / 2
GTL– 0.5 0.6 0.63
VREF Reference voltage V
GTL 0.76 0.8 0.84
GTL+ 0.87 1 1.1
A port 0 3.3 5.5(2)
VIInput voltage V
B port 0 VTT 3.6
A port and DIR 2
VIH High-level input voltage V
B port VREF + 50 mV
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) The VI(max) of LVTTL port is 3.6 V if configured as output (DIR=L)
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
A port and DIR 0.8
VIL Low-level input voltage V
B port VREF – 50 mV
IOH High-level input current A port –20 mA
A port 20
IOL Low-level output current mA
B port 50
6.4 Thermal Information SN74GTL2014
THERMAL METRIC(1) PW UNIT
14 PINS
RθJA Junction-to-ambient thermal resistance 136.8
RθJC(top) Junction-to-case (top) thermal resistance 63.0
RθJB Junction-to-board thermal resistance 78.6 °C/W
ψJT Junction-to-top characterization parameter 11.9
ψJB Junction-to-board characterization parameter 77.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
Specified at TA= –40°C to 85°C (unless otherwise noted) –40°C TO 85°C
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX
VCC = 3 to 3.6 V, IOH = –100 µA VCC – 0.2
VOH A port V
VCC = 3 V, IOH = –16 mA 2
A port VCC = 3 V, IOL = 8 mA 0.28 0.4
VOL A port VCC = 3 V, IOL = 16 mA 0.55 0.8 V
B port VCC = 3 V, IOL = 40 mA 0.23 0.4
VCC = 3.6 V, VI= VCC ±1
A port VCC = 3.6, VI= 0 V ±1 µA
IIVCC = 3.6, VI= 5.5 V 5
B port VCC = 3.6 V, VI= VTT or GND ±1 µA
Control pin VCC = 3.6 V, VI= VCC or 0 V ±1 µA
OFF-state output current on A port VCC = 0 V, VIO = 0 to 3.6 V ±10
Ioff OFF-state output current on A port VCC = 0 V, VIO 3.6 to 5.5V ±100 µA
OFF-state output current on B port VCC = 0 V, VIO = 0 to 3.6 V ±10
A port VCC = 3.6 V, VI= VCC or GND, IO= 0 3 10 mA
ICC B port VCC = 3.6 V, VI= VTT or GND, IO= 0 3 10 mA
∆ICC A port or control input VCC = 3.6 V, VI= VCC – 0.6 V 500 µA
CIInput capacitance of control pin VI= 3.0 V or 0 V 2 2.5 pF
A port VO= 3 V or 0 4 6
CIO pF
B port VO= VTT or 0 5.46 5.55
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0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2
Vth+/Vth-
VREF (V)
VREF
VTH+
VTH-
C003
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2
Vth+/Vth-
VREF (V)
VREF
VTH+
VTH-
C001
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2
Vth+/Vth-
VREF (V)
VREF
VTH+
VTH-
C002
SN74GTL2014
SCLS746A –FEBRUARY 2014–REVISED OCTOBER 2014
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6.6 Dynamic Electrical Characteristics
over operating range, TA= –40°C to 85°C, VCC = 1.65 to 4.6 V, GND = 0 V for GTL (see Functional Block Diagram)
GTL−GTL GTL+
VCC = 3.3 V ± 0.3 V VCC = 3.3 V ± 0.3 V VCC = 3.3 V ± 0.3 V
PARAMETER VREF = 0.6 V VREF = 0.8 V VREF = 1 V UNIT
VTT = 0.9 V VTT = 1.2 V VTT = 1.5 V
MIN TYP MAX MIN TYP MAX MIN TYP MAX
tPLH (low to high propagation delay) 2.8 5 2.8 5 2.8 5
An to Bn ns
tPHL(high to low propagation delay) 3.3 7 3.4 7 3.4 7
tPLH (low to high propagation delay) 5.3 8 5.2 8 5.1 8
Bn to An ns
tPHL (high to low propagation delay) 5.2 8 4.9 7.16 4.7 7.16
6.7 Typical Characteristics
Figure 1. GTL Vth+ and Vth– vs VREF (25°C) Figure 2. GTL Vth+ and Vth– vs VREF (–40°C)
Figure 3. GTL Vth+ and Vth– vs VREF (125°C)
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7 Parameter Measurement Information
VTT = 1.2 V, VREF = 0.8 V for GTL and VTT = 1.5 V, VREF = 1 V FOR GTL+
Figure 4. Load Circuits and Voltage Waveforms
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+
–
GTL2014
B0
B1
B2
B3
VREF DIR
002aab139
A3
A2
A1
A0
+
–
+
–
+
–
SN74GTL2014
SCLS746A –FEBRUARY 2014–REVISED OCTOBER 2014
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8 Detailed Description
8.1 Overview
The GTL2014 is a 4-channel translating transceiver designed for 3.3-V LVTTL system interface with a
GTL–/GTL/GTL+ bus, where GTL–/GTL/GTL+ refers to the reference voltage of the GTL bus and the
input/output voltage thresholds associated with it.
The direction pin allows the part to function as either a GTL-to-LVTTL sampling receiver or as a LVTTL-to-GTL
interface.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 5 V tolerance on LVTTL input
The GTL2014 LVTTL inputs (only) are tolerant up to 5.5 V and allows direct access to TTL or 5 V CMOS inputs.
The LVTTL outputs are not 5.5 V tolerant.
8.3.2 3.6 V tolerance on GTL Input/Output
The GTL2014 GTL inputs and outputs operate up to 3.6 V, allowing the device to be used in higher voltage
open-drain output applications.
8.3.3 Ultra-Low VREF and High Bandwidth
GTL2014’s VREF tracks down to 0.5 V for low voltage CPUs with excellent propagation delay performance. This
feature allows the GTL2014 to support high data rates with the GTL– bus.
8.4 Device Functional Modes
The GTL2014 performs translation in two directions. One direction is GTL–/GTL/GTL+ to LVTTL when DIR is tied
to GND. With appropriate VREF set up, the GTL input can be compliant with GTL–/GTL/GTL+. Another direction
is LVTTL to GTL–/GTL/GTL+ when DIR is tied to VCC. 3.6 V tolerance on the GTL output allows the GTL
outputs to pull up to any voltage level under 3.6 V.
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FPGA
GTL2014PW
LVTTL
GTL
Chipset
R2
R1
VTT
R
1
2
3
4
5
6
78
9
10
11
12
13
14
DIR
B0
B1
VREF
B2
B3
GND GND
A3
A2
GND
A1
A0
VCC
3.3 V
Port_B to Port_A
GTL to LVTTL
3.3 V
2*VTT/3
1.0 V
GND
75 Ω
49.9 Ω
100 Ω
VCC
Vref
VTT
DIR
R
R1
R2
SN74GTL2014
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SCLS746A –FEBRUARY 2014–REVISED OCTOBER 2014
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
GTL2014 is the voltage translator for GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+. Please find the
reference schematic and recommend value for passive component in the Typical Application.
9.2 Typical Application
9.2.1 GTL–/GTL/GTL+ to LVTTL
Select appropriate VTT/VREF based upon GTL–/GTL/GTL+. The parameters in Recommended Operating
Conditions are compliant to the GTL specification.
Figure 5. Application Diagram for GTL to LVTTL
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±0.20
0.30
0.80
1.30
1.80
2.30
2.80
3.30
0 1.25 2.5 3.75 5 6.25 7.5 8.75
Amplitude (V)
Time (ns)
Input
Output
C005
SN74GTL2014
SCLS746A –FEBRUARY 2014–REVISED OCTOBER 2014
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Typical Application (continued)
9.2.1.1 Design Requirements
The GTL2014 requires industrial standard LVTTL and GTL inputs. The design example in Application Information
show standard voltage level and typical resistor values.
NOTE
Only LVTTL terminals (A1/A2/A3/A4) are tolerant to 5 V.
9.2.1.2 Detailed Design Procedure
To begin the design process, determine the following:
1. Select direction base upon application (GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+).
2. Set up appropriate DIR pin and VREF/VTT.
3. Choose correct pullup resistor value base upon data rate and driving current requirement (for LVTTL to
GTL–/GTL/GTL+).
9.2.1.3 Application Curve
Figure 6. GTL-to-LVTTL, VREF = 1 V, VIN = 1.5 V, 100 MHz
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LVTTL
GTL
Chipset
VTT
R
1
2
3
4
5
6
78
9
10
11
12
13
14
DIR
B0
B1
VREF
B2
B3
GND GND
A3
A2
GND
A1
A0
VCC
3.3 V
Port_A to Port_B
LVTTL to GTL
3.3 V
GND
1.0 V
3.3 V
75 Ω
Not Avaliable
Not Avaliable
VCC
Vref
VTT
DIR
R
R1
R2
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Typical Application (continued)
9.2.2 LVTTL/TTL to GTL–/GTL/GTL+
Because GTL is an open-drain interface, the selection of pullup resistor depends on the application requirement
(for example, data rate) and PCB trace capacitance.
Figure 7. Application Diagram for LVTTL to GTL
9.2.2.1 Design Requirements
The GTL2014 requires industrial standard LVTTL and GTL inputs. The design example in the Application
Information section show standard voltage level and typical resistor values.
NOTE
Only LVTTL terminals (A1/A2/A3/A4) are tolerant to 5 V.
9.2.2.2 Detailed Design Procedure
To begin the design process, determine the following:
1. Select direction based upon application (GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+).
2. Set up appropriate DIR pin and VREF/VTT.
3. Choose correct pullup resistor value base upon data rate and driving current requirement (for LVTTL to
GTL–/GTL/GTL+).
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Short Signal Trace as possible
Minimize Stub as possible
GTL2014
DIR
B0
B1
VREF
B2
GND
VCC
A0
A1
GND
A2
A3
GND
1
2
3
4
5
6
78
9
10
11
12
13
14
B3
-2.00E-01
3.00E-01
8.00E-01
1.30E+00
1.80E+00
2.30E+00
2.80E+00
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
Amplitude (V)
Time (ns)
Input (V)
Output (V)
C001
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SCLS746A –FEBRUARY 2014–REVISED OCTOBER 2014
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Typical Application (continued)
9.2.2.3 Application Curve
Figure 8. LVTTL-to-GTL, VREF = 1 V, VTT = 1.5 V, 10 MHz
10 Power Supply Recommendations
Because GTL is a low voltage interface, TI recommends a 0.1-µF decoupling capacitor for VREF.
11 Layout
11.1 Layout Guidelines
Typically, GTL/LVTTL is running at a low data rate; however, the GTL2014 is optimized for excellent propagation
delay, slew rate, bandwidth, and is able support 100-MHz frequencies.
11.2 Layout Example
Figure 9. Layout Example for GTL Trace
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12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.3 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74GTL2014PWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 GT14
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Sep-2014
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74GTL2014PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74GTL2014PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Sep-2014
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74GTL2014PWR TSSOP PW 14 2000 367.0 367.0 35.0
SN74GTL2014PWR TSSOP PW 14 2000 364.0 364.0 27.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Sep-2014
Pack Materials-Page 2
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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